Integrated circuit package and method of forming the same

Abstract

In one embodiment, an integrated circuit package includes: a processor die including a circuit block, the circuit block including an active device having a first technology node; a power gate die including a power semiconductor device having a second technology node, the second technology node being greater than the first technology node; and a first redistribution structure including a first metallization pattern, the first metallization pattern including a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks are electrically coupled to the power supply source line and the power supply ground line via the power semiconductor device, and a second subset of the circuit blocks are permanently electrically coupled to the power supply source line and the power supply ground line.

Description

Technical Field

[0001] The present invention relates to an integrated circuit package and a method for forming the same. Background Art

[0002] As semiconductor technology continues to evolve, integrated circuit dies have become smaller and smaller. In addition, more functions are being integrated into the die. As a result, the number of input / output (I / O) pads required for the die has increased, while the area available for I / O pads has decreased. The density of I / O pads has increased rapidly over time, which has increased the difficulty of die packaging. Some applications require integrated circuit dies to have more powerful parallel processing capabilities. Packaging technology can be used to integrate multiple dies, thereby achieving a greater degree of parallel processing capabilities.

[0003] In some packaging techniques, the integrated circuit die is singulated from the wafer before being packaged. An advantageous feature of such packaging techniques is that a fan-out package can be formed, which enables the I / O pads on the die to be rerouted to a larger area. Thus, the number of I / O pads on the die surface can be increased. Summary of the invention

[0004] In one embodiment, an integrated circuit package includes: a processor die, including a circuit block, wherein the circuit block includes an active device having a first technology node; a power gating die, including a power semiconductor device having a second technology node, the second technology node being greater than the first technology node; and a first redistribution structure, including a first metallization pattern, the first metallization pattern including a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks is electrically coupled to the power supply source line and the power supply ground line via the power semiconductor device, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source line and the power supply ground line.

[0005] In one embodiment, an integrated circuit package includes: a processor die, including a circuit block, the circuit block including an active device having a first technology node; a power gating die, directly bonded to the processor die by dielectric-to-dielectric bonding and by metal-to-metal bonding, the power gating die including a power semiconductor device having a second technology node, the second technology node being greater than the first technology node, the power semiconductor device being electrically coupled to a first subset of the circuit blocks; a dielectric layer, surrounding the power gating die; a first via, extending through the dielectric layer, the first via being electrically coupled to a second subset of the circuit blocks; and a first rewiring structure, including a first metallization pattern, the first metallization pattern including a power supply source line connected to the first via and the power gating die; a packaging substrate; and a first conductive connector, connecting the packaging substrate to the first metallization pattern of the first rewiring structure.

[0006] In one embodiment, a method for forming an integrated circuit package includes: bonding a power gating die to a wafer, the wafer including a processor die, the power gating die and the processor die including active devices with different pitches, the power gating die including a first via; forming a dielectric layer around the power gating die and on the wafer; patterning an opening in the first dielectric layer, the opening exposing a die connector of the processor die; plating a conductive material in the opening and on the die connector; planarizing the conductive material to form a second via in the opening, the planarization exposing the first via of the power gating die; and sawing the dielectric layer and the wafer to singulate the processor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 , Figure 2 and Figure 3 are various views of intermediate steps during a process for forming an integrated circuit package in accordance with some embodiments.

[0009] Figure 4 , Figure 5 and Figure 6 are cross-sectional views of intermediate steps during a process for forming a system for implementing integrated circuit packaging in accordance with some embodiments.

[0010] Figure 7is a cross-sectional view of an integrated circuit package and a system implementing the integrated circuit package according to some other embodiments.

[0011] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 are cross-sectional views of intermediate steps during a process for forming a system for implementing integrated circuit packaging in accordance with some embodiments.

[0012] Fig.17 is a cross-sectional view of an integrated circuit package and a system implementing the integrated circuit package according to some other embodiments.

[0013] Fig.18 is a cross-sectional view of an integrated circuit package and a system implementing the integrated circuit package according to some other embodiments.

[0014] Fig.19 is a cross-sectional view of an integrated circuit package and a system implementing the integrated circuit package according to some other embodiments.

[0015] Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package in accordance with some embodiments.

[0016] Fig.25 , Fig.26 , Fig. 27 and Fig.28 are cross-sectional views of intermediate steps during a process for forming a system for implementing integrated circuit packaging in accordance with some embodiments.

[0017] Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 and Fig.34 are cross-sectional views of intermediate steps during a process for forming a system for implementing integrated circuit packaging according to some other embodiments.

[0018] Fig.35 , Fig.36 , Fig.37 , Fig.38 , Fig.39 and Fig.40 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package according to some other embodiments.

[0019] Fig.41 is a cross-sectional view of an integrated circuit package according to some other embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed "on" or formed "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] According to some embodiments, an integrated circuit package is formed having a processor device and a power gating device, the processor device and the power gating device being separate semiconductor devices. The power gating device is formed with larger active devices than the processor device and includes a power semiconductor device that provides power gating for the processor device. Thus, a switching transistor having a large technology node can be used for power delivery, thereby allowing the power consumption of the resulting integrated circuit package to be reduced.

[0023] Figure 1 , Figure 2 and Figure 31 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package 100 according to some embodiments. The integrated circuit package 100 is formed by stacking semiconductor devices on a wafer 102. The stacking of the devices in one device area 102A of the wafer 102 is illustrated, but it should be understood that the wafer 102 may have any number of device areas and semiconductor devices may be stacked in each device area to form an integrated circuit package. The semiconductor devices may be bare integrated circuit dies or packaged dies. In the illustrated embodiment, each semiconductor device is a bare integrated circuit die. In other embodiments, one or more of the illustrated semiconductor devices may be encapsulated packaged dies.

[0024] exist Figure 1 , a wafer 102 is obtained. The wafer 102 includes a processor device 10 located in a device area 102A. The processor device 10 will be singulated in a subsequent process to be included in the integrated circuit package 100. The processor device 10 can be any acceptable processor or logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), an arithmetic logic unit (ALU), a system-on-a-chip (SoC), an application processor (AP), an image signal processor (ISP), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller, an artificial intelligence (AI) accelerometer, etc. As further discussed below, the processor device 10 is formed to not include a power gating feature.

[0025] The processor device 10 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the processor device 10 includes a doped or undoped semiconductor substrate 12 (e.g., silicon) or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 12 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates. The semiconductor substrate 12 has an active surface 12A and an inactive surface 12N.

[0026] Devices may be formed at the active surface 12A of the semiconductor substrate 12. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The non-active surface 12N may not have devices. An interlayer dielectric (ILD) is located above the active surface 12A of the semiconductor substrate 12. The ILD surrounds and may cover the device. The ILD may include one or more dielectric layers formed of materials such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc.

[0027] The interconnect structure 14 is located on the active surface 12A of the semiconductor substrate 12. The interconnect structure 14 interconnects the devices at the active surface 12A of the semiconductor substrate 12 to form an integrated circuit. The interconnect structure 14 can be formed by, for example, a metallization pattern in a dielectric layer. The metallization pattern includes metal lines and vias formed in one or more dielectric layers. The metallization pattern of the interconnect structure 14 is electrically coupled to the devices at the active surface 12A of the semiconductor substrate 12.

[0028] The die connector 16 is located at the front side 10F of the processor device 10. The die connector 16 may be a conductive post, pad, etc. for external connection. The die connector 16 is located in and / or on the interconnect structure 14. The die connector 16 may be formed of a metal (e.g., copper, aluminum, etc.) and may be formed by, for example, plating.

[0029] The dielectric layer 18 is located at the front side 10F of the processor device 10. The dielectric layer 18 is located in and / or on the interconnect structure 14. The dielectric layer 18 laterally encapsulates the die connector 16, and the dielectric layer 18 is laterally coterminous with the sidewalls of the processor device 10. First, the dielectric layer 18 can bury the die connector 16 so that the topmost surface of the dielectric layer 18 is located above the topmost surface of the die connector 16. The dielectric layer 18 can be: a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) based polymer, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; the like or a combination thereof. The dielectric layer 18 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. After formation, the die connector 16 and the dielectric layer 18 may be planarized using, for example, a chemical-mechanical polish (CMP) process, an etch-back process, or a combination thereof. After planarization, the surface of the die connector 16 and the surface of the dielectric layer 18 are planar and exposed at the front side 10F of the processor device 10.

[0030] Processor device 10 includes a plurality of circuit blocks. A circuit block is a logical block or logic unit of the circuitry of processor device 10. In other words, a circuit block includes a subset of the circuitry of processor device 10, wherein the circuits in a circuit block are all associated with the same domain. Examples of circuit blocks include arithmetic circuit blocks, memory circuit blocks, DSP circuit blocks, etc.

[0031] A power gating device 20 is also obtained. The power gating device 20 is part of the power delivery network of the processor device 10. Specifically, the power gating device 20 provides power gating for some or all of the circuit blocks of the processor device 10. The power gating device 20 can operate at run time to receive a control signal and turn the circuit blocks of the processor device 10 on or off in response to the control signal. For example, the circuit blocks of the processor device 10 can be turned on when needed and can be turned off when not in use, thereby reducing the power leakage of unused circuit blocks. Therefore, the power consumption of the processor device 10 can be reduced. In addition, forming the processor device 10 that does not include a power gating feature enables the area of ​​the processor device 10 to be reduced. For example, moving the power gating feature to a dedicated power gating device 20 enables the area of ​​the processor device 10 to be reduced by up to 20%.

[0032] The power gating device 20 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the power gating device 20 includes a semiconductor substrate 22, an interconnect structure 24, a die connector 26, and a dielectric layer 28, which may be similar to the semiconductor substrate 12, the interconnect structure 14, the die connector 16, and the dielectric layer 18, respectively. The die connector 26 and the dielectric layer 28 are exposed at the front side 20F of the power gating device 20. The power gating device 20 also includes a via 30 formed to extend into the semiconductor substrate 22. The via 30 is electrically coupled to the metallization pattern of the interconnect structure 24.

[0033] Taking the formation of via 30 as an example, a recess may be formed in interconnect structure 24 and / or semiconductor substrate 22 by, for example, etching, milling, laser technology, combinations thereof, etc. A thin dielectric material may be formed in the recess, for example, by using an oxidation technique. A thin barrier layer may be conformally deposited in the opening, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer may be formed of an oxide, nitride, or oxynitride (e.g., titanium nitride, titanium oxynitride, tantalum nitride, tungsten oxynitride, combinations thereof, etc.). A conductive material may be deposited over the barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layer are removed from the surface of interconnect structure 24 and / or the surface of semiconductor substrate 22 by, for example, CMP. The remaining portion of barrier layer and the remaining portion of conductive material form via 30.

[0034] In the illustrated embodiment, the via 30 is not yet exposed at the back side 20B of the power gating device 20. Instead, the via 30 is buried in the semiconductor substrate 22. As discussed further below, the via 30 will be exposed at the back side 20B of the power gating device 20 through a planarization process in subsequent processing. After exposure, the via 30 may be referred to as a through-substrate via or through-silicon via (TSV).

[0035] The power gate control device 20 includes a power semiconductor device (e.g., a semiconductor device used for power electronic devices) for providing power gate control for the processor device 10. Specifically, the power gate control device 20 may include a switch transistor, a power gate control controller, and a power gate control network structure. The power semiconductor device of the power gate control device 20 may be a bipolar device, such as an insulated-gate bipolar transistor (IGBT) device, or a power metal oxide semiconductor field effect transistor (MOSFET) device, such as a complementary metal oxide semiconductor (CMOS) device, a double diffused metal oxide semiconductor (DMOS) device, etc. In some embodiments, the processor device 10 and the power gate control device 20 are formed by different semiconductor process technologies and have devices with different pitches (e.g., active devices). For example, the processor device 10 may include a CMOS device, and the power gate control device 20 may include an IGBT device or a DMOS device. The active surface of the semiconductor substrate 22 includes a switching device region 22S, which includes a switching transistor. The switching transistor of the switching device region 22S is connected to a power supply source (V DD ) line (discussed further below), and when activated, V DD The interconnect structure 24 may be electrically coupled to a circuit block of the processor device 10. Similarly, the metallization pattern of the interconnect structure 24 may form some or all of the power gating network structures. For example, the interconnect structure 24 may include a circuit block for connecting V DD The wires are routed from the switch transistors to the metal lines and vias of the circuit blocks of the processor device 10 .

[0036] The metallization pattern of the interconnect structure 24 may form some of the power gating network structures, all of the power gating network structures, or no power gating network structures. In some embodiments, the interconnect structure 24 of the power gating device 20 includes all of the power gating network structures. In some embodiments, the interconnect structure 24 of the power gating device 20 includes some of the power gating network structures, and the interconnect structure 14 of the processor device 10 includes some of the power gating network structures. In some embodiments, the interconnect structure 24 of the power gating device 20 does not include a power gating network structure, and the interconnect structure 14 of the processor device 10 includes all of the power gating network structures.

[0037] The power delivery performance of the switch transistor may significantly affect the overall power delivery performance of the power gating device 20. Specifically, the switch transistor with a large technology node may accommodate a larger inrush current and have a smaller voltage drop (e.g., voltage potential drop (IR drop)) when the circuit block of the processor device 10 is turned on. Similarly, the switch transistor with a large technology node may have a larger threshold voltage, which enables the switch transistor to reduce power leakage. According to some embodiments, the processor device 10 has active devices with a smaller technology node (e.g., a smaller device pitch or spacing), which are not suitable for switch transistors but are suitable for logic devices, and the power gating device 20 has active devices with a larger technology node (e.g., a larger device pitch or spacing), which are not suitable for logic devices but are suitable for switch transistors. For example, the processor device 10 may have active devices (e.g., forming circuit blocks) having a technology node in the range of about 2 nanometers to about 28 nanometers, and the power gating device 20 may have active devices (e.g., power semiconductor devices) having a technology node in the range of about 3 nanometers to about 90 nanometers. Forming the power gating device 20 with larger active devices than the processor device 10 enables the processor device 10 to be scaled down to a smaller technology node that provides improved logic device performance while still enabling the power gating device 20 to provide sufficient power delivery performance. In addition, forming the power gating device 20 with larger active devices enables the manufacturing cost of the power gating device 20 to be reduced.

[0038] exist Figure 2In the embodiment of the present invention, the power gating device 20 is bonded to the processor device 10 (e.g., the wafer 102). The processor device 10 and the power gating device 20 are directly bonded in a face-to-face manner by hybrid bonding, so that the front side 10F of the processor device 10 is bonded to the front side 20F of the power gating device 20. Specifically, the dielectric layer 18 of the processor device 10 is bonded to the dielectric layer 28 of the power gating device 20 via dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film), and a subset of the die connections 16A of the processor device 10 is bonded to the die connections 26 of the power gating device 20 via metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and tempering. During the pre-bonding, a small pressing force is applied to press the power gating device 20 against the processor device 10 (e.g., the wafer 102). Pre-bonding is performed at a low temperature, and after pre-bonding, the dielectric layer 18 and the dielectric layer 28 are bonded to each other. The bonding strength is then increased in a subsequent annealing step, in which the dielectric layers 18 and 28 are annealed at a high temperature. After annealing, a bond (e.g., a fusion bond) is formed, thereby bonding the dielectric layer 18 to the dielectric layer 28. For example, the bond may be a covalent bond between the material of the dielectric layer 18 and the material of the dielectric layer 28. The die connector 16A and the die connector 26 are connected to each other in a one-to-one correspondence. The die connector 16A and the die connector 26 may be in physical contact after pre-bonding, or may expand during annealing to reach physical contact. In addition, during annealing, the material of the die connector 16A is intermixed with the material (e.g., copper) of the die connector 26, so that a metal-to-metal bond is also formed. Therefore, the resulting bond between the processor device 10 and the power gating device 20 is a hybrid bond including both a dielectric-to-dielectric bond and a metal-to-metal bond.

[0039] After hybrid bonding, the processor device 10 is electrically coupled to the power gating device 20 by direct bonding, and control communication and power / ground communication are performed via the direct bonding. Specifically, the processor device 10 can send control signals to the power gating device 20 via the direct bonding, and can receive power / ground signals from the power gating device 20 via the direct bonding. Communication delay and interconnect bandwidth between the processor device 10 and the power gating device 20 can be improved by using direct bonding. In addition, the impedance of the interconnection can also be reduced and thus the power consumption of the interconnection can be reduced. As described above, the metallization pattern of the interconnection structure 24 can form some or all of the power gating network structures in the power gating network structure. In these embodiments, the power gating network structure is thus connected to the processor device 10 by direct bonding, which can make the wiring simpler than other types of interconnections. In the embodiment shown, one power gating device 20 is bonded to the processor device 10. In another embodiment, multiple power gating devices 20 are bonded to the processor device 10.

[0040] exist Figure 3 In the embodiment of the present invention, a dielectric layer 104 is formed around the power gate device 20. The dielectric layer 104 may be formed after the power gate device 20 is placed but before annealing to complete the hybrid bonding, or the dielectric layer 104 may be formed after annealing. The dielectric layer 104 fills the gap between the power gate device 20 and other devices in the adjacent device area (not shown) of the wafer 102, thereby protecting the semiconductor device. The dielectric layer 104 may be: an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; a nitride, such as silicon nitride, etc.; a polymer, such as PBO, polyimide, BCB series polymer, etc.; an encapsulant, such as a molding compound, epoxy resin, etc.; the like or a combination thereof. In some embodiments, the dielectric layer 104 is an oxide, such as silicon oxide. In some embodiments, the dielectric layer 104 is deposited using a CVD process, etc.

[0041] Then, a via 106 extending through the dielectric layer 104 is formed. Taking the formation of the via 106 as an example, an opening is patterned in the dielectric layer 104. The patterning may be performed by an acceptable process, such as by exposing the dielectric layer 104 to light when the dielectric layer 104 is a photosensitive material, or by etching the dielectric layer 104 using, for example, anisotropic etching. The opening exposes a subset of the die connectors 16B of the processor device 10. A seed layer is formed on the dielectric layer 104 and on the portions of the die connectors 16B exposed by the opening. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer located on the titanium layer. The seed layer may be formed using, for example, PVD. A conductive material is formed on the seed layer. The conductive material may be formed by plating (e.g., electroplating or electroless plating). The conductive material may include metals, such as copper, titanium, tungsten, aluminum, etc. Then, the excess portion of the seed layer and the excess portion of the conductive material are removed, wherein the excess portion is the portion overlying the dielectric layer 104. The removal may be performed by a planarization process. The seed layer, the conductive material, the dielectric layer 104, and the power gate control device 20 are subjected to a planarization process. The removal simultaneously removes the excess portion of the seed layer and the excess portion of the conductive material and exposes the via 30. The planarization process may be, for example, a CMP process, a grinding process, an etch-back process, a similar process, or a combination thereof. The remaining portion of the seed layer and the conductive material in the opening forms the via 106. After the planarization process, the top surface of the dielectric layer 104, the top surface of the via 106, the top surface of the semiconductor substrate 22, and the top surface of the via 30 are flat.

[0042] Figure 4 , Figure 5 and Figure 6is a cross-sectional view of an intermediate step during a process according to some embodiments for forming a system implementing the integrated circuit package 100. In this embodiment, the integrated circuit package 100 is further processed to include a redistribution structure and is mounted directly to a package substrate.

[0043] exist Figure 4 In the embodiment of the present invention, a redistribution structure 108 is formed on the dielectric layer 104, the via 106, and the power gate device 20. The redistribution structure 108 includes a dielectric layer 110 and a metallization pattern 112 (sometimes referred to as a redistribution layer or a redistribution line) located in the dielectric layer 110. For example, the redistribution structure 108 may include a plurality of metallization patterns 112 separated from each other by corresponding dielectric layers 110. The metallization pattern 112 of the redistribution structure 108 is connected to the via 106 and the power gate device 20 (e.g., to the via 30).

[0044] In some embodiments, dielectric layer 110 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, BCB-based polymers, etc. In other embodiments, dielectric layer 110 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc. The dielectric layer 110 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After each dielectric layer 110 is formed, the dielectric layer 110 is then patterned to expose underlying conductive features, such as portions of the underlying metallization pattern 112. Patterning may be performed by an acceptable process, such as by exposing the dielectric layer to light when the dielectric layer 110 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 110 is a photosensitive material, the dielectric layer 110 may be developed after exposure.

[0045] The metallization patterns 112 each include a via and / or a conductive line. The via extends through the dielectric layer 110, and the conductive line extends along the dielectric layer 110. Taking the formation of the metallization pattern as an example, a seed layer (not shown) is formed on the corresponding underlying feature. For example, when forming the bottom layer of the rewiring structure 108, the seed layer can be formed on the dielectric layer 104, the via 106, the semiconductor substrate 22 and the via 30, or when forming the middle layer / top layer of the rewiring structure 108, the seed layer can be formed on the corresponding dielectric layer 110 and through the opening of the corresponding dielectric layer 110. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located on the titanium layer. The seed layer can be formed using a deposition process such as PVD. Then, a photoresist is formed on the seed layer and the photoresist is patterned. Photoresist can be formed by spin coating, etc. and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. Conductive material can be formed by plating (e.g., electroplating or electroless plating, etc.). The conductive material may include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc. or a combination thereof. Then, the portion of the photoresist and the seed layer on which the conductive material is not formed is removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, by using an acceptable etching process (e.g., by wet etching or dry etching). The remainder of the seed layer and the conductive material form a metallization pattern of a layer in the rewiring structure 108.

[0046] The redistribution structure 108 is described as an example. More or fewer dielectric layers 110 and metallization patterns 112 than described may be formed in the redistribution structure 108 by repeating or omitting the steps described above.

[0047] The metallization pattern 112 of the redistribution structure 108 includes a power supply source (V DD ) line and power supply ground (V SS ) line. V DD Line and V SS The line is connected to the vias 30 and 106. Therefore, the switch device area 22S of the power gate control device 20 is electrically coupled to V through the via 30. DD Line and V SS A first subset of the circuit blocks of the processor device 10 is electrically coupled to V via the power gating device 20. DD Line and V SSTherefore, the power gating device 20 can turn on and off the first subset of circuit blocks. The second subset of circuit blocks of the processor device 10 bypasses the power gating device 20 and is electrically coupled to V DD Line and V SS Therefore, the second subset of circuit blocks is permanently electrically coupled to power and ground. The circuit blocks that are permanently electrically coupled to power and ground are always turned on and are not power gated.

[0048] The metallization pattern 112 of the rewiring structure 108 also includes data signal lines that are electrically coupled to the processor device 10 through the vias 106. For example, some of the vias 106 couple input / output (I / O) connections of the processor device 10 to the rewiring structure 108. Thus, the processor device 10 can be coupled to an external device.

[0049] exist Figure 5 In the embodiment of the present invention, a conductive connector 114 connected to the metallization pattern 112 of the redistribution structure 108 is formed. The top dielectric layer 110 of the redistribution structure 108 can be patterned to expose some portions of the underlying metallization pattern 112. In some embodiments, under bump metallurgies (UBM) can be formed in the opening. The conductive connector 114 is formed on the UBM. The conductive connector 114 can be a ball grid array (BGA) connector, a solder column, a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), etc. The conductive connector 114 can be formed of a metal or a metal alloy, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 114 is first formed by forming a solder layer via some common method (e.g., evaporation, electroplating, printing, solder transfer, ball planting, etc.). Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 114 is a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may not have solder and have substantially vertical sidewalls.

[0050] exist Figure 6In the embodiment of the present invention, the singulation process is performed by sawing along the scribe line area (e.g., around the device area 102A). The singulation process includes sawing the redistribution structure 108, the dielectric layer 104, and the wafer 102. The singulation process separates the device area 102A (including the processor device 10) from the adjacent device area (not shown) of the wafer 102 to form the integrated circuit package 100 including the processor device 10. As described above, the power gating device 20 is directly bonded to the processor device 10 in a face-to-face manner without using solder. Therefore, the resulting integrated circuit package 100 does not have solder. After singulation, the redistribution structure 108 (e.g., the dielectric layer 110), the dielectric layer 104, and the processor device 10 are laterally adjacent.

[0051] The integrated circuit package 100 is then inverted and attached to the package substrate 200 using the conductive connector 114. The package substrate 200 may be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these materials, etc. may also be used. In addition, the package substrate 200 may be an SOI substrate. Typically, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the package substrate 200 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively include other printed circuit board (PCB) materials or films. A build-up film (eg, Ajinomoto build-up film (ABF)) or other laminates may be used for the package substrate 200 .

[0052] The package substrate 200 may include active devices and passive devices (not shown). Devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements of the design of the system. The devices may be formed using any suitable method.

[0053] The package substrate 200 may also include metallization layers and vias (not shown) and bonding pads 202 located on the metallization layers and vias. The metallization layers may be formed on active and passive devices and are designed to connect various devices to form functional circuit systems. The metallization layers may be formed of alternating layers of dielectrics (e.g., low-k dielectric materials) and conductive materials (e.g., copper) and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.), wherein the vias interconnect the conductive material layers. In some embodiments, the package substrate 200 is substantially free of active and passive devices.

[0054] The conductive connectors 114 are reflowed to bond the UBM of the redistribution structure 108 to the bonding pads 202. The conductive connectors 114 connect the package substrate 200 (including the metallization layers in the package substrate 200) to the integrated circuit package 100 (including the metallization patterns 112 of the redistribution structure 108). In some embodiments, a passive device (e.g., a surface mount device (SMD), not shown) may be bonded to the integrated circuit package 100 (e.g., bonded to the bonding pads 202) before being mounted on the package substrate 200. In these embodiments, the passive device may be bonded to the same surface of the integrated circuit package 100 as the conductive connectors 114. In some embodiments, the passive device (e.g., an SMD, not shown) may be bonded to the package substrate 200, for example, bonded to the bonding pads 202.

[0055] The conductive connector 114 may have an epoxy flux (not shown) formed thereon before being reflowed, wherein at least some of the epoxy portion of the epoxy flux remains after the integrated circuit package 100 is attached to the package substrate 200. This remaining epoxy portion may be used as an underfill to reduce stress and protect the joint resulting from the reflow of the conductive connector 114. In some embodiments, an underfill (not shown) may be formed between the integrated circuit package 100 and the package substrate 200, thereby surrounding the conductive connector 114. The underfill may be formed by a capillary flow process after the integrated circuit package 100 is attached, or may be formed by a suitable deposition method before the integrated circuit package 100 is attached.

[0056] Figure 7 1 is a cross-sectional view of an integrated circuit package 100 and a system implementing the integrated circuit package 100 according to some other embodiments. Figure 6 In the embodiment described above, the processor device 10 and the power gating device 20 are directly combined in a face-to-back manner. Therefore, the metallization pattern 112 (e.g., VDD line and VSS line) of the redistribution structure 108 is connected to the die connection 26 and electrically coupled to the processor device 10 through the via 30.

[0057] The processor device 10 and the power gating device 20 are directly bonded in a face-to-back manner by hybrid bonding, such that the front side 10F of the processor device 10 is bonded to the back side 20B of the power gating device 20. Specifically, the dielectric layer 18 of the processor device 10 is bonded to the semiconductor substrate 22 of the power gating device 20 via dielectric-to-dielectric bonding without using any adhesive material (e.g., die attach film), and a subset of the die connections 16A of the processor device 10 are bonded to the vias 30 of the power gating device 20 via metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding may include pre-bonding and tempering. During the pre-bonding, a small pressing force is applied to press the power gating device 20 against the processor device 10. The pre-bonding is performed at a low temperature, and after the pre-bonding, the dielectric layer 18 and the semiconductor substrate 22 are bonded to each other. In some embodiments, an oxide (e.g., native oxide, thermal oxide, etc.) is formed at the back side 20B of the power gating device 20 (e.g., on the semiconductor substrate 22), and the oxide is used for bonding. The bonding strength is then improved in a subsequent tempering step, in which the dielectric layer 18 and the semiconductor substrate 22 are tempered at a high temperature. After tempering, a bond (e.g., a fusion bond) is formed, thereby bonding the dielectric layer 18 and the semiconductor substrate 22. For example, the bond can be a covalent bond between the material of the dielectric layer 18 and the material of the semiconductor substrate 22. The die connector 16A and the via 30 are connected to each other in a one-to-one correspondence. The die connector 16A and the via 30 can be in physical contact after pre-bonding, or can expand during tempering to achieve physical contact. In addition, during tempering, the material of the die connector 16A is intermixed with the material of the via 30 (e.g., copper) so that a metal-to-metal bond is also formed. Therefore, the resulting bond between the processor device 10 and the power gating device 20 is a hybrid bond including both dielectric-to-dielectric bonding and metal-to-metal bonding.

[0058] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.161 is a cross-sectional view of an intermediate step during a process for forming a system implementing an integrated circuit package 100 according to some other embodiments. In this embodiment, the integrated circuit package 100 is singulated and included in a package assembly. The device is illustrated as being packaged in one package region 302A, but it should be understood that any number of package regions may be formed simultaneously. The package region 302A will be singulated in subsequent processing. The singulated package assembly may be a fan-out package, such as an integrated fan-out (InFO) package. The fan-out package is then mounted to a package substrate.

[0059] exist Figure 8 In the embodiment of the present invention, a carrier substrate 302 is provided, and a release layer 304 is formed on the carrier substrate 302. The carrier substrate 302 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 302 may be a wafer so that a plurality of packages may be formed on the carrier substrate 302 at the same time. The release layer 304 may be formed of a polymer material, and the release layer 304 may be removed from the overlying structure to be formed in a subsequent step together with the carrier substrate 302. In some embodiments, the release layer 304 is an epoxy resin-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 304 may be a UV glue that loses its adhesive properties when exposed to ultraviolet (UV) light. The release layer 304 may be dispensed in the form of a liquid and cured, and the release layer 304 may be a laminated film laminated to the carrier substrate 302, or may be a similar material. The top surface of the release layer 304 may be flush and may have a high degree of flatness.

[0060] exist Fig. 9 In the embodiment, a redistribution structure 306 may be formed on the release layer 304. The redistribution structure 306 may be formed on the release layer 304. Figure 4 The rewiring structure 108 is formed in a similar manner and from similar materials. Rewiring structure 306 includes a dielectric layer 308 and a metallization pattern 310 (sometimes referred to as a rewiring layer or rewiring line). More or fewer dielectric layers 308 and metallization patterns 310 than illustrated may be formed in rewiring structure 306. Rewiring structure 306 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on release layer 304 in place of rewiring structure 306.

[0061] exist Fig.10In the embodiment, a via 312 is formed extending through the topmost dielectric layer 308 of the redistribution structure 306. Thus, the via 312 is connected to the metallization pattern 310 of the redistribution structure 306. The via 312 is optional and may be omitted. For example, the via 312 may (or may not) be omitted in an embodiment in which the redistribution structure 306 is omitted.

[0062] Taking the formation of vias 312 as an example, an opening can be formed in the topmost dielectric layer 308 of the rewiring structure 306. Then, a seed layer is formed on the rewiring structure 306 (e.g., on the topmost dielectric layer 308 and on the portion of the metallization pattern 310 exposed by the opening in the topmost dielectric layer 308). In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating and the photoresist is exposed to light for patterning. The pattern of the photoresist corresponds to the via. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating (e.g., electroplating or electroless plating, etc.). The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, by using an acceptable etching process (e.g., by wet etching or dry etching). The remaining portion of the seed layer and the conductive material form the via 312.

[0063] exist Fig.11 In the embodiment of the present invention, the singulated integrated circuit package 100 is placed on the redistribution structure 306 (eg, the topmost dielectric layer 308). To form the singulated integrated circuit package 100, the Figure 3 The intermediate structure is similar to the intermediate structure described above. By cutting along the scribe line area (for example, in the device area 102A (see Figure 3 ) is sawed around the wafer 102 to perform the singulation process. The singulation process includes sawing the dielectric layer 104 and the wafer 102. The singulation process separates the device area 102A (including the processor device 10) from the adjacent device area (not shown) of the wafer 102 to form the integrated circuit package 100 including the processor device 10. As described above, the power gating device 20 is directly bonded to the processor device 10 in a face-to-face manner without using solder. Therefore, the resulting integrated circuit package 100 does not have solder. After singulation, the dielectric layer 104 is laterally adjacent to the processor device 10.

[0064] exist Fig.12 In the embodiment of the present invention, an encapsulant 314 is formed on and around the via 312 and the integrated circuit package 100. After being formed, the encapsulant 314 encapsulates the via 312 and the integrated circuit package 100. The encapsulant 314 may be a molding compound, an epoxy resin, etc. The encapsulant 314 may be applied by compression molding, transfer molding, etc., and the encapsulant 314 may be formed on the carrier substrate 302 so as to bury or cover the integrated circuit package 100 and / or the via 312. The encapsulant 314 may be applied in a liquid or semi-liquid form and then subsequently cured. In some embodiments, the encapsulant 314 is different from the dielectric layer 104 and includes a different material than the dielectric layer 104. Then, a planarization process may be performed on the encapsulant 314 to expose the via 312 and the integrated circuit package 100. The planarization process may remove material of the via 312, material of the encapsulation 314, material of the dielectric layer 104, material of the via 106, material of the semiconductor substrate 22, and / or material of the via 30 until the vias 30, 106, 312 are exposed. After the planarization process, the top surface of the planarized component is coplanar. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etch back, etc. In some embodiments, for example, if the vias 30, 106, 312 are already exposed, the planarization may be omitted.

[0065] exist Fig.13 In the embodiment, a redistribution structure 316 is formed on the encapsulation body 314, the via 312 and the integrated circuit package 100. Figure 4 The rewiring structure 316 is formed in a similar manner and from similar materials as the rewiring structure 108 described above. The rewiring structure 316 includes a dielectric layer 318 and a metallization pattern 320 (sometimes referred to as a rewiring layer or a rewiring line). More or fewer dielectric layers 318 and metallization patterns 320 than illustrated may be formed in the rewiring structure 316. The metallization pattern 320 of the rewiring structure 316 is connected to the vias 30, 106, 312. The metallization pattern 320 of the rewiring structure 316 includes a power supply source (V DD ) line, power supply ground (V SS ) lines and data signal lines, power supply source (V DD ) line, power supply ground (V SS ) lines and data signal lines with respect to Figure 4 The aforementioned method is electrically coupled to the processor device 10 and the power gating device 20 in a similar manner.

[0066] exist Fig.14 In the embodiment, a conductive connector 322 is formed to be connected to the metallization pattern 320 of the redistribution structure 316. Figure 5The conductive connector 322 is formed in a similar manner and from a similar material as the conductive connector 114 . For example, the conductive connector 322 can be formed on the UBM of the redistribution structure 316 .

[0067] exist Fig.15 In the embodiment, carrier substrate peeling is performed to peel (strip) carrier substrate 302 from rewiring structure 306 (e.g., bottom-most dielectric layer 308). According to some embodiments, peeling includes projecting light (e.g., laser or UV light) onto release layer 304 so that release layer 304 decomposes under the heat of the light and carrier substrate 302 can be removed. Then, the structure can be turned upside down and placed on, for example, a tape.

[0068] In addition, a conductive connector 324 is formed through the bottommost dielectric layer 308 of the redistribution structure 306. An opening may be formed through the bottommost dielectric layer 308 of the redistribution structure 306 to expose a portion of the metallization pattern 310. The opening may be formed, for example, using laser drilling, etching, etc. The conductive connector 324 is formed in the opening and is connected to the exposed portion of the metallization pattern 310. Figure 5 Conductive connector 324 is formed in a similar manner and from similar materials as conductive connector 114 described above.

[0069] exist Fig.16 , a singulation process is performed by sawing along the scribe line regions (e.g., around the package region 302A). The singulation process includes sawing the redistribution structures 306, 316 and the encapsulation body 314. The singulation process separates the package region 302A from adjacent package regions (not shown) to form the integrated circuit package 300. After singulation, the redistribution structures 306, 316 (e.g., dielectric layers 308, 318) are laterally adjacent to the encapsulation body 314.

[0070] Another integrated circuit package 400 may be attached to the integrated circuit package 300 to form a package-on-package structure. The integrated circuit package 400 may be a memory package. The integrated circuit package 400 may be attached to the integrated circuit package 300 before or after the integrated circuit package 300 is singulated. The integrated circuit package 400 includes a substrate 402 and one or more dies 404 connected to the substrate 402. In some embodiments (not shown), one or more stacks of dies 404 are connected to the substrate 402. The substrate 402 may be made of a semiconductor material such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these materials, etc. may also be used. In addition, the substrate 402 may be a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In an alternative embodiment, the substrate 402 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. A constituent film (e.g., Ajinomoto constituent film (ABF)) or other laminates can be used for the substrate 402.

[0071] The substrate 402 may include active devices and passive devices (not shown). Those skilled in the art will recognize that a variety of devices (e.g., transistors, capacitors, resistors, combinations of these, etc.) may be used to generate the structural and functional requirements of the design of the integrated circuit package 400. The devices may be formed using any suitable method. The substrate 402 may also include metallization layers (not shown) and through-holes. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form a functional circuit system. The metallization layers may be formed of alternating layers of dielectrics (e.g., low-k dielectric materials) and conductive materials (e.g., copper) and may be formed via any suitable process (e.g., deposition, damascene, dual damascene, etc.), wherein the through-holes interconnect the conductive material layers. In some embodiments, the substrate 402 is substantially free of active and passive devices.

[0072] The substrate 402 may have a bonding pad 406 on one side of the substrate 402 to connect to the conductive connector 324. In some embodiments, the bonding pad 406 is formed by forming a recess (not shown) in a dielectric layer (not shown) on the side of the substrate 402. The recess may be formed so that the bonding pad 406 can be embedded in the dielectric layer. In other embodiments, when the bonding pad 406 can be formed on the dielectric layer, the recess is omitted. In some embodiments, the bonding pad 406 includes a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc. or a combination thereof. The conductive material of the bonding pad 406 can be deposited on the thin seed layer. The conductive material can be formed by an electrochemical plating process, an electroless plating process, CVD, ALD, PVD, etc. or a combination thereof. In one embodiment, the conductive material of the bonding pad 406 is copper, tungsten, aluminum, silver, gold, etc. or a combination thereof.

[0073] In one embodiment, bonding pad 406 is a UBM including three conductive material layers, such as a titanium layer, a copper layer, and a nickel layer. For example, bonding pad 406 may be formed of copper, may be formed on a titanium layer (not shown) and have a nickel finish, which may extend the shelf life of integrated circuit package 400, which may be particularly advantageous when integrated circuit package 400 is a memory device, such as a dynamic random access memory (DRAM) module. However, those skilled in the art will recognize that there are many suitable materials and layer arrangements suitable for forming bonding pad 406, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold. Any suitable material or material layer that may be used for bonding pad 406 is fully intended to be included within the scope of the present application.

[0074] In the illustrated embodiment, die 404 is connected to substrate 402 by conductive bumps, but other connections, such as wire bonding, may be used. In one embodiment, die 404 is a stacked memory die. For example, die 404 may be a memory die, such as a low-power (LP) double data rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc.

[0075] The die 404 and the wire bonds (when present) may be encapsulated by a molding material 410. The molding material 410 may be molded over the die 404 and the wire bonds, for example, using compression molding. In some embodiments, the molding material 410 is a molding compound, a polymer, an epoxy, a silica filler material, or the like, or a combination thereof. A curing process may be performed to cure the molding material 410; the curing process may be a thermal cure, a UV cure, or the like, or a combination thereof. In some embodiments, the die 404 is buried in the molding material 410, and after curing the molding material 410, a planarization step (e.g., grinding) is performed to remove excess portions of the molding material 410 and provide a substantially planar surface for the integrated circuit package 400.

[0076] After the integrated circuit package 400 is formed, the integrated circuit package 400 is attached to the integrated circuit package 300 via the conductive connector 324. The conductive connector 324 can be connected to the bonding pad 406 by reflowing the conductive connector 324. Therefore, the die 404 can be electrically coupled to the integrated circuit package 100 via the conductive connector 324, the via 312 and the redistribution structures 306 and 316.

[0077] In some embodiments, a solder resist (not shown) is formed on a side of substrate 402 opposite die 404. Conductive connectors 324 may be disposed in openings in the solder resist to connect to conductive features (e.g., bonding pads 406) in substrate 402. The solder resist may be used to protect some areas of substrate 402 from external damage.

[0078] In some embodiments, the conductive connectors 324 have epoxy flux (not shown) formed thereon before being reflowed, wherein at least some of the epoxy portion of the epoxy flux remains after attaching the integrated circuit package 400 to the redistribution structure 306 .

[0079] In some embodiments, an underfill (not shown) is formed between the redistribution structure 306 and the substrate 402, thereby surrounding the conductive connector 324. The underfill can reduce stress and protect the joints resulting from reflow of the conductive connector 324. The underfill can be formed by a capillary flow process after the integrated circuit package 400 is attached, or can be formed by a suitable deposition method before the integrated circuit package 400 is attached. In embodiments where epoxy flux is formed, the epoxy flux can be used as the underfill.

[0080] Then, the stacked package structure is inverted and attached to the package substrate 200 using the conductive connector 322. The package substrate 200 may be similar to the Figure 6 The package substrate 200 , for example, can include a bonding pad 202 connected to a conductive connector 322 .

[0081] Fig.17 1 is a cross-sectional view of an integrated circuit package 100 and a system implementing the integrated circuit package 100 according to some other embodiments. Fig.16 In the embodiment described above, the processor device 10 and the power gate control device 20 are directly combined in a face-to-back manner, which is similar to the embodiment described above. Figure 7 Thus, the metallization pattern 320 (eg, V DD Line and V SS The chip is connected to the die connection 26 by a conductive line and is electrically coupled to the processor device 10 by a conductive via 30.

[0082] Fig.18 1 is a cross-sectional view of an integrated circuit package 100 and a system implementing the integrated circuit package 100 according to some other embodiments. Fig.16 In the embodiment described above, however, the redistribution structure 306, the via 312 and the integrated circuit package 400 are omitted.

[0083] Fig.19 1 is a cross-sectional view of an integrated circuit package 100 and a system implementing the integrated circuit package 100 according to some other embodiments. Fig.17 In the embodiment described above, however, the redistribution structure 306, the via 312 and the integrated circuit package 400 are omitted.

[0084] Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 5 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package 500 according to some embodiments. The integrated circuit package 500 is formed by stacking a plurality of semiconductor device layers each encapsulated in an encapsulation material. The devices are illustrated as being encapsulated in one packaging region 502A, but it should be understood that any number of packaging regions may be formed simultaneously. The packaging regions 502A will be singulated in subsequent processing. The singulated package assembly may be a multi-stacked (MUST) package. The MUST package is then mounted to a packaging substrate.

[0085] exist Fig. 20 In the embodiment, a carrier substrate 502 is provided, and a release layer 504 is formed on the carrier substrate 502. Figure 8 The carrier substrate 502 may be formed in a similar manner and from similar materials as described above with respect to the carrier substrate 302. Figure 8 The release layer 504 is formed in a similar manner and from similar materials as the release layer 304 described above. Figure 1A processor device 10 similar to the processor device described above (eg, including semiconductor substrate 12 , interconnect structure 14 , die connector 16 , and dielectric layer 18 ) is placed on release layer 504 .

[0086] exist Fig.21 In the embodiment, an encapsulation body 506 is formed on and around the processor device 10. Fig.12 The encapsulation 506 is formed in a similar manner and from a similar material as the encapsulation 314. If necessary, the encapsulation 506 may be planarized to expose the die connector 16.

[0087] exist Fig. 22 In the embodiment, a rewiring structure 510 is formed on the encapsulation body 506 and the processor device 10. Figure 4 The rewiring structure 510 is formed in a similar manner and from similar materials as the rewiring structure 108 described above. The rewiring structure 510 includes a dielectric layer 512 and a metallization pattern 514 (sometimes referred to as a rewiring layer or a rewiring line). More or fewer dielectric layers 512 and metallization patterns 514 than illustrated may be formed in the rewiring structure 510. The metallization patterns 514 of the rewiring structure 510 are connected to the die connector 16 of the processor device 10.

[0088] exist Fig.23 In the embodiment, a via 516 is formed extending through the topmost dielectric layer 512 of the redistribution structure 510. Fig.10 The via 516 is formed in a similar manner and from similar materials as the via 312 .

[0089] One or more power gating devices 20 are placed on the redistribution structure 510 (e.g., the topmost dielectric layer 512). Each power gating device 20 may be similar to the Figure 1 The power gating device (e.g., including semiconductor substrate 22, interconnect structure 24, die connector 26, and dielectric layer 28) is electrically coupled to processor device 10 via the redistribution structure of the MUST package, and thus, vias 30 do not need to be formed (see Figure 1 ). Therefore, the manufacturing cost of the power gate control device 20 can be reduced.

[0090] exist Fig.24 In the embodiment, an encapsulation body 518 is formed on and around the power gate control device 20 and the via 516. The encapsulation body 518 may be Fig.12 The encapsulant 314 is formed in a similar manner and from similar materials. If necessary, the encapsulant 518 may be planarized to expose the vias 516 and the die connectors 26 .

[0091] Fig.25 , Fig.26 , Fig. 27 and Fig.28 is a cross-sectional view of an intermediate step during a process according to some embodiments for forming a system implementing an integrated circuit package 500. In this embodiment, the integrated circuit package 500 is further processed to include a redistribution structure and is mounted directly to a package substrate.

[0092] exist Fig.25 In the embodiment, a redistribution structure 520 is formed on the encapsulation body 518 and the power gate control device 20. Figure 4 The rewiring structure 520 is formed in a similar manner and from similar materials as the rewiring structure 108 described above. The rewiring structure 520 includes a dielectric layer 522 and a metallization pattern 524 (sometimes referred to as a rewiring layer or a rewiring line). More or fewer dielectric layers 522 and metallization patterns 524 than illustrated may be formed in the rewiring structure 520. The metallization pattern 524 of the rewiring structure 520 is connected to the via 516 and the die connection 26 of the power gating device 20. Thus, the processor device 10 is electrically coupled to the metallization pattern 524 of the rewiring structure 520 via the via 514 and the metallization pattern 524 of the rewiring structure 510.

[0093] The metallization pattern 524 of the redistribution structure 520 includes a power supply source (V DD ) line, power supply ground (V SS ) lines and data signal lines. The metallization pattern 524 of the redistribution structure 520 also includes lines that electrically couple the vias 516 to the output terminals of the power gating device 20. Thus, the first subset of the circuit blocks of the processor device 10 are electrically coupled to the V DD Line and V SS Therefore, the first subset of circuit blocks can be turned on and off by the power gate control device 20. The second subset of circuit blocks of the processor device 10 bypasses the power gate control device 20 and is electrically coupled to V DD Line and V SS The second subset of circuit blocks is permanently electrically coupled to power and ground. The second subset of circuit blocks may be essential circuit blocks that are always on. The data signal line is electrically coupled to the processor device 10 and the power gating device 20. The processor device 10 may send a control signal to the power gating device 20 via the data signal line, and may receive a power / ground signal from the power gating device 20 via the data signal line.

[0094] exist Fig.26 In the embodiment, a conductive connection 526 is formed to be connected to the metallization pattern 524 of the redistribution structure 520. Figure 5Conductive connector 526 is formed in a similar manner and from similar materials as conductive connector 114 described above.

[0095] exist Fig. 27 In the embodiment, carrier substrate peeling is performed to peel (strip) carrier substrate 502 from rewiring structure 510 (e.g., bottom-most dielectric layer 512). According to some embodiments, peeling includes projecting light (e.g., laser or UV light) onto release layer 504 so that release layer 504 decomposes under the heat of the light and carrier substrate 502 can be removed. Then, the structure can be turned upside down and placed on, for example, a tape.

[0096] exist Fig.28 , a singulation process is performed by sawing along the scribe line regions (e.g., around the package region 502A). The singulation process includes sawing the redistribution structures 510, 520 and the encapsulation bodies 506, 518. The singulation process separates the package region 502A from adjacent package regions (not shown) to form the integrated circuit package 500. After singulation, the redistribution structures 510, 520 (e.g., dielectric layers 512, 522) are laterally adjacent to the encapsulation bodies 506, 518.

[0097] Then, the integrated circuit package 500 is attached to the package substrate 200 using the conductive connector 526. The package substrate 200 may be similar to the Figure 6 The package substrate 200 , for example, can include a bonding pad 202 connected to a conductive connector 526 .

[0098] Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 and Fig.34 6 is a cross-sectional view of an intermediate step during a process for forming a system implementing an integrated circuit package 500 according to some embodiments. In this embodiment, the integrated circuit package 500 is singulated and included in a package assembly. The device is illustrated as being packaged in one package region 602A, but it should be understood that any number of package regions may be formed simultaneously. The package regions 602A will be singulated in subsequent processing. The singulated package assembly may be a fan-out package, such as an integrated fan-out (InFO) package. The fan-out package is then mounted to a package substrate.

[0099] exist Fig.29 In the embodiment, a carrier substrate 602 is provided, and a release layer 604 is formed on the carrier substrate 602. Figure 8 The carrier substrate 602 may be formed in a similar manner and from similar materials as described above with respect to the carrier substrate 302. Figure 8 Release layer 604 is formed in a similar manner and from similar materials as release layer 304 described above.

[0100] A redistribution structure 606 may be formed on the release layer 604. Figure 4 Rewiring structure 606 is formed in a similar manner and from similar materials as rewiring structure 108 described above. Rewiring structure 606 includes dielectric layer 608 and metallization pattern 610 (sometimes referred to as rewiring layer or rewiring line). More or fewer dielectric layers 608 and metallization patterns 610 than illustrated may be formed in rewiring structure 606. Rewiring structure 606 is optional. In some embodiments, a dielectric layer that does not include a metallization pattern is formed on release layer 604 in place of rewiring structure 606.

[0101] exist Fig.30 In the embodiment, a via 612 is formed extending through the topmost dielectric layer 608 of the rewiring structure 606. Thus, the via 612 is connected to the metallization pattern 610 of the rewiring structure 606. Fig.10 The via 612 is formed in a similar manner and from a similar material as the via 312 described above. The via 612 is optional and may be omitted. For example, the via 612 may (or may not) be omitted in an embodiment where the redistribution structure 606 is omitted.

[0102] The singulated integrated circuit package 500 is placed on the redistribution structure 606 (eg, the topmost dielectric layer 608) adjacent to the via 612. To form the singulated integrated circuit package 500, the Fig.24 The intermediate structure described above is similar to the intermediate structure. Carrier substrate peeling is performed to separate the intermediate structure from the carrier substrate 502 (see Fig.24 ) is peeled off (stripped off). Then, by cutting along the scribe line area (for example, in the packaging area 502A (see Fig.24 ) is sawed around the package 502A to perform a singulation process. The singulation process includes sawing the redistribution structure 510 and the encapsulation bodies 506, 518. The singulation process separates the package area 502A from the adjacent package area (not shown) to form the integrated circuit package 500. After singulation, the redistribution structure 510 (e.g., the dielectric layer 512) is laterally adjacent to the encapsulation bodies 506, 518.

[0103] exist Fig.31 In the embodiment, an encapsulation body 614 is formed on and around the via 612 and the integrated circuit package 500. Fig.12 Encapsulation 614 is formed in a similar manner and from similar materials as encapsulation 314. In some embodiments, encapsulation 614 is different from and includes different materials than encapsulation 506, 518. If desired, encapsulation 614 may be planarized to expose die connectors 26 and vias 516, 612.

[0104] exist Fig.32 In the embodiment, a redistribution structure 616 is formed on the encapsulation body 614, the via 612 and the integrated circuit package 500. Figure 4 The rewiring structure 616 is formed in a similar manner and from similar materials as the rewiring structure 108 described above. The rewiring structure 616 includes a dielectric layer 618 and a metallization pattern 620 (sometimes referred to as a rewiring layer or rewiring line). More or fewer dielectric layers 618 and metallization patterns 620 than illustrated may be formed in the rewiring structure 616. The metallization pattern 620 of the rewiring structure 616 is connected to the die connector 26 and the vias 516, 612. The metallization pattern 620 of the rewiring structure 616 includes a power supply source (V DD ) line, power supply ground (V SS ) lines and data signal lines, power supply source (V DD ) line, power supply ground (V SS ) lines and data signal lines with respect to Figure 4 The aforementioned method is electrically coupled to the processor device 10 and the power gating device 20 in a similar manner.

[0105] Conductive connectors 622 are formed to connect to the metallization pattern 620 of the redistribution structure 616. Figure 5 The conductive connector 622 is formed in a similar manner and from a similar material as the conductive connector 114 . For example, the conductive connector 622 can be formed on the UBM of the redistribution structure 616 .

[0106] exist Fig.33 In the embodiment, carrier substrate peeling is performed to peel (strip) carrier substrate 602 from rewiring structure 606 (e.g., bottom-most dielectric layer 608). According to some embodiments, peeling includes projecting light (e.g., laser or UV light) onto release layer 604 so that release layer 604 decomposes under the heat of the light and carrier substrate 602 can be removed. Then, the structure can be turned upside down and placed on, for example, a tape.

[0107] In addition, a conductive connector 624 is formed at the bottommost dielectric layer 608 of the redistribution structure 606. An opening may be formed through the bottommost dielectric layer 608 of the redistribution structure 606, thereby exposing a portion of the metallization pattern 610. The opening may be formed, for example, using laser drilling, etching, etc. The conductive connector 624 is formed in the opening and connected to the exposed portion of the metallization pattern 610. Figure 5 Conductive connector 624 is formed in a similar manner and from similar materials as conductive connector 114 described above.

[0108] exist Fig.34, a singulation process is performed by sawing along the scribe line regions (e.g., around the encapsulation region 602A). The singulation process includes sawing the redistribution structures 606, 616 and the encapsulation body 614. The singulation process separates the encapsulation region 602A from adjacent encapsulation regions (not shown) to form the integrated circuit package 600. After singulation, the redistribution structures 606, 616 (e.g., dielectric layers 608, 618) are laterally adjacent to the encapsulation body 614.

[0109] Another integrated circuit package 400 may be attached to the integrated circuit package 600 to form a stacked package structure. The integrated circuit package 400 may be attached to the integrated circuit package 600 before or after the integrated circuit package 600 is singulated. The integrated circuit package 400 may be similar to the integrated circuit package 600 described above. Fig.16 The integrated circuit package 400 is shown. For example, the integrated circuit package 400 can include a bonding pad 406 connected to the conductive connector 624 .

[0110] Then, the stacked package structure is inverted and attached to the package substrate 200 using the conductive connector 622. The package substrate 200 may be similar to the Figure 6 The package substrate 200 , for example, can include a bonding pad 202 connected to a conductive connector 622 .

[0111] Fig.35 , Fig.36 , Fig.37 , Fig.38 , Fig.39 and Fig.40 7 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package 700 according to some other embodiments. The integrated circuit package 700 is formed by singulating the processor device 10 and the power gating device 20 and including the processor device 10 and the power gating device 20 in a package assembly. The device is illustrated as being packaged in one package region 702A, but it should be understood that any number of package regions may be formed simultaneously. The package regions 702A will be singulated in subsequent processing. The singulated package assembly may be a fan-out package, such as an integrated fan-out (InFO) package. The fan-out package is then mounted to a package substrate.

[0112] exist Fig.35 In the embodiment, a carrier substrate 702 is provided, and a release layer 704 is formed on the carrier substrate 702. Figure 8 The carrier substrate 702 may be formed in a similar manner and from similar materials as described above with respect to the carrier substrate 302. Figure 8 The release layer 704 is formed in a similar manner and from a similar material as the release layer 304 described above. Then, a via hole 706 is formed on the release layer 704, and the via hole 706 extends away from the release layer 704. Fig.10 The via 706 is formed in a similar manner and from similar materials as the via 312 described above.

[0113] Then, the Figure 1 A processor device 10 similar to the processor device described above (e.g., including semiconductor substrate 12, interconnect structure 14, die connector 16, and dielectric layer 18) is placed on release layer 704 adjacent to via 706. In this embodiment, processor device 10 also includes via 708 formed to extend through semiconductor substrate 12. Via 708 is electrically coupled to the metallization pattern of interconnect structure 14.

[0114] exist Fig.36 In the embodiment, an encapsulation body 710 is formed on and around the via 706 and the processor device 10. Fig.12 The encapsulation 710 is formed in a similar manner and from similar materials as the encapsulation 314. If necessary, the encapsulation 710 may be planarized to expose the die connectors 16 and the vias 706.

[0115] exist Fig.37 In the embodiment, a rewiring structure 712 is formed on the encapsulation body 710, the via 706 and the processor device 10. Figure 4 The redistribution structure 712 is formed in a similar manner and from similar materials as the redistribution structure 108 described above. The redistribution structure 712 includes a dielectric layer 714 and a metallization pattern 716 (sometimes referred to as a redistribution layer or redistribution line). More or fewer dielectric layers 714 and metallization patterns 716 than illustrated may be formed in the redistribution structure 712. The metallization patterns 716 of the redistribution structure 712 are connected to the die connector 16 and the via 706.

[0116] Conductive connectors 718 are formed to connect to the metallization pattern 716 of the redistribution structure 712. Figure 5 The conductive connector 718 is formed in a similar manner and from a similar material as the conductive connector 114 . For example, the conductive connector 718 can be formed on the UBM of the redistribution structure 712 .

[0117] exist Fig.38 In the embodiment, carrier substrate peeling is performed to peel (peel) carrier substrate 702 from processor device 10. According to some embodiments, peeling includes projecting light (e.g., laser or UV light) onto release layer 704 so that release layer 704 decomposes under the heat of the light and carrier substrate 702 can be removed. Then, the structure can be inverted and placed on, for example, a tape.

[0118] A rewiring structure 720 is formed on the encapsulation 710, the via 706 and the processor device 10. Figure 4 The redistribution structure 720 is formed in a similar manner and from similar materials as the redistribution structure 108 described above. The redistribution structure 720 includes a dielectric layer 722 and a metallization pattern 724 (sometimes referred to as a redistribution layer or redistribution line). More or fewer dielectric layers 722 and metallization patterns 724 than illustrated may be formed in the redistribution structure 720. The metallization patterns 724 of the redistribution structure 720 are connected to the vias 706, 708.

[0119] exist Fig.39 In the embodiment, the conductive connecting member 726 is used to connect the Figure 1 The power gating device 20 (e.g., including the semiconductor substrate 22, the interconnect structure 24, and the die connector 26) similar to the power gating device described above is attached to the redistribution structure 720. The power gating device 20 is electrically coupled to the processor device 10 via the redistribution structures 712, 720 (e.g., the metallization patterns 716, 724), and therefore, there is no need to form the via 30 (see Figure 1 In addition, the dielectric layer 28 may be omitted in the power gate control device 20 (see Figure 1 ). Therefore, the manufacturing cost of the power gate control device 20 can be reduced.

[0120] In some embodiments, the power gating device 20 is attached to a conductive bump, such as a micro bump. For example, the grain connector 728 can be formed to extend through the bottommost dielectric layer 722 of the redistribution structure 720. Taking the formation of the grain connector 728 as an example, an opening can be formed through the bottommost dielectric layer 722 of the redistribution structure 720 to expose a portion of the metallization pattern 724. The opening can be formed, for example, using laser drilling, etching, etc. The grain connector 728 can be plated or deposited in the opening, and the grain connector 728 is connected to the exposed portion of the metallization pattern 724. Conductive connectors 726 are formed to connect corresponding pairs of grain connectors 26, 728. It can be related to Figure 5 The conductive connector 726 is formed in a similar manner and from a similar material as the conductive connector 114 . In this embodiment, the rear side of the processor device 10 faces the front side of the power gating device 20 .

[0121] The metallization pattern 716 of the redistribution structure 712 includes a power supply source (V DD ) line, power supply ground (V SS ) lines and data signal lines. V DD Line and V SS The first subset of lines are connected to the die connection 16 of the processor device 10. Therefore, the first subset of circuit blocks of the processor device 10 bypasses the power gating device 20 and is electrically connected to the V pin of the rewiring structure 712. DD Line and V SSTherefore, the first subset of circuit blocks is permanently electrically coupled to power and ground. The first subset of circuit blocks may be necessary circuit blocks that are always turned on. DD Line and V SS The second subset of lines is electrically coupled to the input terminal of the power gating device 20 via the vias 706 and the metallization pattern 724 of the rewiring structure 720. The metallization pattern 724 of the rewiring structure 720 also includes lines that electrically couple the processor device 10 to the output terminal of the power gating device 20. Therefore, the second subset of circuit blocks of the processor device 10 is electrically coupled to V via the power gating device 20, the rewiring structure 720, and the vias 706, 708. DD Line and V SS Therefore, the power gate control device 20 can turn on and off the second subset of circuit blocks. In some embodiments, some of the vias 708 are connected to data signal lines of the rewiring structure 720. The data signal lines are electrically coupled to the processor device 10 and the power gate control device 20. The processor device 10 can send control signals to the power gate control device 20 via the data signal lines, and can receive power / ground signals from the power gate control device 20 via the data signal lines.

[0122] Then, an underfill 730 is formed between the power gate device 20 and the redistribution structure 720 to surround the conductive connection 726. The underfill 730 may be formed by a capillary flow process after the power gate device 20 is attached, or may be formed by a suitable deposition method before the power gate device 20 is attached.

[0123] An encapsulation body 732 is formed on and around the power gate control device 20 and the bottom filling glue 730. Fig.12 The encapsulation 732 is formed in a similar manner and with similar materials as the encapsulation 314. If necessary, the encapsulation 710 may be planarized to expose the power gate device 20.

[0124] exist Fig.40 , a singulation process is performed by sawing along the scribe line areas (e.g., around the package area 702A). The singulation process includes sawing the redistribution structures 712, 720 and the encapsulation bodies 710, 732. The singulation process separates the package area 702A from the adjacent package areas (not shown) to form the integrated circuit package 700. After singulation, the redistribution structures 712, 720 (e.g., dielectric layers 714, 722) are laterally adjacent to the encapsulation bodies 710, 732.

[0125] The integrated circuit package 700 is then attached to the package substrate 200 using conductive connectors 718. The package substrate 200 may be similar to that described with reference to FIG. Figure 6The package substrate 200 , for example, can include bonding pads 202 connected to the conductive connector 718 .

[0126] Fig.41 is a cross-sectional view of an integrated circuit package 700 according to some other embodiments. This embodiment is similar to the embodiment of Fig.40 In the embodiment described above, the front side of the processor device 10 faces the front side of the power gating device 20. Therefore, the metallization pattern 724 (eg, V DD Line and V SS The vias 706 and 708 are directly connected to the die connection 16. Therefore, the vias 706 and 708 are used for data signal lines.

[0127] Embodiments can achieve many advantages. Forming an integrated circuit package in which the power gating device 20 is separated from the processor device 10 enables the power gating device 20 to be formed with larger active devices than the processor device 10. Therefore, a switching transistor with a large technology node can be used for power delivery. The switching transistor with a large technology node can accommodate larger inrush currents and have smaller voltage drops (e.g., IR drops) when the circuit blocks of the processor device 10 are turned on, and also have smaller power leakage. Therefore, the power consumption of the resulting integrated circuit package can be reduced.

[0128] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate to enable testing of the 3D package or 3DIC device, using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce cost.

[0129] In one embodiment, a device includes: a processor die including circuit blocks, wherein the circuit blocks include active devices having a first technology node; a power gating die including power semiconductor devices having a second technology node, wherein the second technology node is greater than the first technology node; and a first redistribution structure including a first metallization pattern, wherein the first metallization pattern includes a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks are electrically coupled to the power supply source line and the power supply ground line via the power semiconductor devices, and a second subset of the circuit blocks are permanently electrically coupled to the power supply source line and the power supply ground line.

[0130] In some embodiments, the device further comprises: a package substrate; and a conductive connector connected to the package substrate and the first metallization pattern of the first rewiring structure. In some embodiments of the device, the processor die and the power gating die are directly bonded by dielectric-to-dielectric bonding and by metal-to-metal bonding, and the device further comprises: a via connected to the processor die and the first metallization pattern of the first rewiring structure; and a dielectric layer surrounding the via and the power gating die, the dielectric layer and the power gating die are each disposed between the first rewiring structure and the processor die, the first rewiring structure, the dielectric layer and the processor die being laterally adjacent. In some embodiments of the device, the processor die and the power gating die are directly bonded by dielectric-to-dielectric bonding and by metal-to-metal bonding, and the device also includes: a via connected to the processor die and the first metallization pattern of the first rewiring structure; a dielectric layer surrounding the via and the power gating die, the dielectric layer and the power gating die are each arranged between the first rewiring structure and the processor die, the dielectric layer and the processor die are laterally adjacent to each other; and an encapsulation surrounding the processor die and the dielectric layer, the encapsulation is laterally adjacent to the first rewiring structure. In some embodiments of the device, the first metallization pattern of the first rewiring structure is connected to the power gating die, and the device further includes: a second rewiring structure disposed between the processor die and the power gating die, the second rewiring structure including a second metallization pattern, the processor die being connected to the second metallization pattern; a first encapsulation surrounding the power gating die; a via extending through the first encapsulation, the via being connected to the first metallization pattern of the first rewiring structure and the second metallization pattern of the second rewiring structure; and a second encapsulation surrounding the processor die, the second encapsulation, the second rewiring structure, the first encapsulation and the first rewiring structure being laterally adjacent.In some embodiments of the device, the first metallization pattern of the first rewiring structure is connected to the power gating die, and the device further includes: a second rewiring structure disposed between the processor die and the power gating die, the second rewiring structure including a second metallization pattern, the processor die being connected to the second metallization pattern; a first encapsulation surrounding the power gating die; a via extending through the first encapsulation, the via being connected to the first metallization pattern of the first rewiring structure and the second metallization pattern of the second rewiring structure; a second encapsulation surrounding the processor die, the second encapsulation, the second rewiring structure and the first encapsulation being laterally adjacent to each other; and a third encapsulation surrounding the second encapsulation, the second rewiring structure and the first encapsulation, the third encapsulation being laterally adjacent to the first rewiring structure. In some embodiments of the device, the first metallization pattern of the first rewiring structure is connected to the processor die, and the device further includes: a second rewiring structure disposed between the processor die and the power gating die, the second rewiring structure including a second metallization pattern, the second metallization pattern being connected to the processor die and the power gating die; a first encapsulation surrounding the processor die; a via extending through the first encapsulation, the via being connected to the first metallization pattern of the first rewiring structure and the second metallization pattern of the second rewiring structure; and a second encapsulation surrounding the power gating die, the second encapsulation, the first encapsulation, the second rewiring structure, and the first rewiring structure being laterally adjacent. In some embodiments of the device, the power gating die is operable at run time to receive a control signal from the processor die and to turn on or off the first subset of the circuit blocks of the processor die in response to the control signal. In some embodiments of the apparatus, the active devices of the processor die are complementary metal oxide semiconductor devices, and the power semiconductor devices of the power gating die are insulated gate bipolar transistor devices or double diffused metal oxide semiconductor devices.

[0131] In one embodiment, a device includes: a processor die including a circuit block, the circuit block including an active device having a first technology node; a power gating die directly bonded to the processor die by dielectric-to-dielectric bonding and by metal-to-metal bonding, the power gating die including a power semiconductor device having a second technology node, the second technology node being greater than the first technology node, the power semiconductor device being electrically coupled to a first subset of the circuit blocks; a dielectric layer surrounding the power gating die; a first via extending through the dielectric layer, the first via being electrically coupled to a second subset of the circuit blocks; and a first rewiring structure including a first metallization pattern, the first metallization pattern including a power supply source line connected to the first via and the power gating die; a packaging substrate; and a first conductive connector connecting the packaging substrate to the first metallization pattern of the first rewiring structure.

[0132] In some embodiments of the device, the processor die, the dielectric layer, and the first rewiring structure are laterally adjacent. In some embodiments of the device, the processor die is laterally adjacent to the dielectric layer, and the device further comprises: an encapsulation surrounding the processor die and the dielectric layer, the encapsulation being laterally adjacent to the first rewiring structure. In some embodiments, the device further comprises: a second rewiring structure comprising a second metallization pattern, the encapsulation being disposed between the first rewiring structure and the second rewiring structure; a second via extending through the encapsulation, the second via being connected to the second metallization pattern of the second rewiring structure and the first metallization pattern of the first rewiring structure; a memory package; and a second conductive connector connecting the memory package to the second metallization pattern of the second rewiring structure. In some embodiments of the device, the active device of the processor die is a complementary metal oxide semiconductor device, and the power semiconductor device of the power gating die is an insulated gate bipolar transistor device or a double diffused metal oxide semiconductor device. In some embodiments of the device, the processor die and the power gating die are directly bonded in a face-to-face manner. In some embodiments of the device, the processor die and the power gating die are directly coupled in a face-to-back manner.

[0133] In one embodiment, a method includes: bonding a power gating die to a wafer, the wafer including a processor die, the power gating die and the processor die including active devices having different pitches, the power gating die including a first via; forming a dielectric layer around the power gating die and on the wafer; patterning openings in the first dielectric layer, the openings exposing a die connector of the processor die; plating a conductive material in the openings and on the die connectors; planarizing the conductive material to form a second via in the openings, the planarization exposing the first via of the power gating die; and sawing the dielectric layer and the wafer to singulate the processor die.

[0134] In some embodiments, before the sawing, the method further comprises: forming a redistribution structure on the power gating die, the dielectric layer, and the second via, and the sawing comprises sawing the redistribution structure. In some embodiments, after the sawing, the method further comprises: encapsulating the power gating die and the dielectric layer with an encapsulant; and forming a redistribution structure on the encapsulant, the power gating die, the dielectric layer, and the second via. In some embodiments of the method, the power gating die comprises an active device having a larger technology node than the processor die.

[0135] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit package, characterized in that include: A processor die including a circuit block including an active device; A power gate die including a power semiconductor device having a device pitch greater than a device pitch of the active device; as well as a first rewiring structure comprising a first metallization pattern, the first metallization pattern comprising a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks are electrically coupled to the power supply source line and the power supply ground line via the power semiconductor device, and a second subset of the circuit blocks are permanently electrically coupled to the power supply source line and the power supply ground line, The processor die and the power gate die are directly bonded by dielectric-to-dielectric bonding and metal-to-metal bonding, and the integrated circuit package further comprises: a via connected to the processor die and the first metallization pattern of the first rewiring structure; a dielectric layer surrounding the via and the power gate die, wherein the dielectric layer and the power gate die are respectively disposed between the first redistribution structure and the processor die, and the dielectric layer and the processor die are adjacent in a lateral direction; and An encapsulation body surrounds the processor die and the dielectric layer, and the encapsulation body is adjacent to the first redistribution structure in a lateral direction.

2. The integrated circuit package of claim 1 , further comprising: Package substrate; as well as A conductive connector is connected to the package substrate and the first metallization pattern of the first redistribution structure.

3. The integrated circuit package of claim 1 , wherein the processor die and the power gating die are directly bonded by dielectric-to-dielectric bonding and by metal-to-metal bonding, and the integrated circuit package further comprises: a via connected to the processor die and the first metallization pattern of the first rewiring structure; as well as The dielectric layer surrounds the via and the power gate die. The dielectric layer and the power gate die are respectively disposed between the first redistribution structure and the processor die. The first redistribution structure, the dielectric layer and the processor die are adjacent to each other in a lateral direction.

4. The integrated circuit package of claim 1, wherein the power gating die comprises active devices having a larger device pitch than the processor die.

5. An integrated circuit package, characterized in that include: A processor die including a circuit block including an active device; A power gate die including a power semiconductor device having a device pitch greater than a device pitch of the active device; as well as a first rewiring structure comprising a first metallization pattern, the first metallization pattern comprising a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks are electrically coupled to the power supply source line and the power supply ground line via the power semiconductor device, and a second subset of the circuit blocks are permanently electrically coupled to the power supply source line and the power supply ground line, The first metallization pattern of the first redistribution structure is connected to the power gating die, and the integrated circuit package further comprises: A second rewiring structure disposed between the processor die and the power gating die, the second rewiring structure comprising a second metallization pattern, the processor die being connected to the second metallization pattern; A first encapsulation body surrounding the power gate control die; a via extending through the first encapsulation body, the via being connected to the first metallization pattern of the first rewiring structure and the second metallization pattern of the second rewiring structure; and The second encapsulation body surrounds the processor die, and the second encapsulation body, the second redistribution structure, the first encapsulation body and the first redistribution structure are adjacent in a lateral direction.

6. An integrated circuit package, characterized in that include: A processor die including a circuit block including an active device; A power gate die including a power semiconductor device having a device pitch greater than a device pitch of the active device; as well as a first rewiring structure comprising a first metallization pattern, the first metallization pattern comprising a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks are electrically coupled to the power supply source line and the power supply ground line via the power semiconductor device, and a second subset of the circuit blocks are permanently electrically coupled to the power supply source line and the power supply ground line, The first metallization pattern of the first redistribution structure is connected to the power gating die, and the integrated circuit package further comprises: A second rewiring structure disposed between the processor die and the power gating die, the second rewiring structure comprising a second metallization pattern, the processor die being connected to the second metallization pattern; A first encapsulation body surrounding the power gate control die; a via extending through the first encapsulation body, the via being connected to the first metallization pattern of the first rewiring structure and the second metallization pattern of the second rewiring structure; A second encapsulation body surrounds the processor die, the second encapsulation body, the second redistribution structure and the first encapsulation body being adjacent in a lateral direction; and The third encapsulation body surrounds the second encapsulation body, the second redistribution structure and the first encapsulation body, and the third encapsulation body is adjacent to the first redistribution structure in a lateral direction.

7. An integrated circuit package, characterized in that include: A processor die including a circuit block including an active device; A power gate die including a power semiconductor device having a device pitch greater than a device pitch of the active device; as well as a first rewiring structure comprising a first metallization pattern, the first metallization pattern comprising a power supply source line and a power supply ground line, wherein a first subset of the circuit blocks are electrically coupled to the power supply source line and the power supply ground line via the power semiconductor device, and a second subset of the circuit blocks are permanently electrically coupled to the power supply source line and the power supply ground line, The first metallization pattern of the first redistribution structure is connected to the processor die, and the integrated circuit package further comprises: A second rewiring structure disposed between the processor die and the power gating die, the second rewiring structure comprising a second metallization pattern connected to the processor die and the power gating die; A first package surrounding the processor die; a via extending through the first encapsulation body, the via being connected to the first metallization pattern of the first rewiring structure and the second metallization pattern of the second rewiring structure; and The second encapsulation surrounds the power gate die, and the second encapsulation, the first encapsulation, the second redistribution structure and the first redistribution structure are adjacent to each other in a lateral direction.

8. The integrated circuit package of claim 7, wherein the power gating die is operable at run time to receive a control signal from the processor die and to turn on or off the first subset of the circuit blocks of the processor die in response to the control signal.

9. The integrated circuit package of claim 7, wherein the active devices of the processor die are complementary metal oxide semiconductor devices and the power semiconductor devices of the power gating die are insulated gate bipolar transistor devices or double diffused metal oxide semiconductor devices.

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