Lateral DMOS devices with stepped profiles to reduce surface electric field and drift structure

Abstract

The present invention is entitled "Lateral DMOS Device with Stepped Profile and Reduced Surface Electric Field and Drift Structure". The present invention discloses a method for manufacturing a MOSFET, the method comprising forming a source region and a drain region, forming a gate region, forming a bulk diffusion region, forming a metal structure, and forming a drift region comprising an n-type drift structure having a stepped dopant concentration distribution, wherein the dopant concentration increases laterally from the drain region to the source region of the device.

Description

Technical Field

[0001] This description relates to metal-oxide-semiconductor field-effect transistors (MOSFETs) used in power supply applications. Background Technology

[0002] Laterally diffused MOS transistors (LDMOS) are likely the preferred devices for high-voltage and smart power applications. Whether discrete or embedded in a BCD (BIPOLAR-CMOS-DMOS) technology platform, the key performance metric for LDMOS devices is their specific on-state resistance (Rsp) at a given breakdown voltage (BVdss). In fact, lower Rsp devices can produce smaller devices, which in turn allows for the fabrication of more devices on a single wafer. Summary of the Invention

[0003] Laterally diffused MOS devices (LDMOS) fabricated on semiconductor substrates have drift diffusion regions comprising a stepped profile drift structure and a stepped profile reduced surface electric field (RESURF) structure. In n-type LDMOS devices, the stepped profile drift structure is n-type, and the reduced surface electric field structure is p-type.

[0004] In an example implementation of an n-type LDMOS device, the stepped profile drift structure has an increasing doping concentration along a lateral or horizontal line from the drain side to the source side of the device.

[0005] In some example implementations of n-type LDMOS devices, the p-type stepped profile reduces the surface electric field structure to have an increased doping concentration along the transverse line from the drain side to the source side of the device.

[0006] In some example implementations of n-type LDMOS devices, the p-type stepped profile reduces the surface electric field structure to a reduced depth in the semiconductor substrate along a transverse line from the drain side to the source side of the device.

[0007] In an example implementation, the doping distribution of the stepped profile drift structure and the stepped profile reduced surface electric field structure can be optimized to minimize the on-state resistance (Rsp) of the device at a given breakdown voltage (BVdss). Attached Figure Description

[0008] Figure 1 The half-pitch cross-section of a device cell in an example n-type LDMOS device is shown.

[0009] Figure 2 An example n-type LDMOS device with different numbers of nDrift diffusion regions and pResurf diffusion regions is shown.

[0010] Figure 3An example n-type LDMOS device is shown, including an n-type stepped profile drift structure and a p-type stepped profile reduced surface electric field structure.

[0011] Figure 4 An example n-type LDMOS device fabricated on a substrate having an n-type buried layer (nBL) is shown.

[0012] Figure 5 Cross-sectional views of the impact electrical line and equipotential line of the test device are shown.

[0013] Figure 6 It is shown Figure 5 The graph shows the Rsp and BVdss values ​​of the doping concentration for various groups of the test device.

[0014] Figures 7 to 15 A schematic diagram of the substrate is shown as it is processed through multiple steps of an example nLDMOS device fabrication process.

[0015] Figure 16 An example method for manufacturing nLDMOS devices is shown. Detailed Implementation

[0016] High-voltage MOSFET devices can include thick and lightly doped epitaxial layers, which makes integration with low-voltage circuitry difficult. Due to the high resistivity of the thick and lightly doped epitaxial layers, such devices exhibit high on-state resistance. To achieve lower Rsp, a reduced surface field (RESURF) structure can be used in the device during the blocking state to obtain a fully depleted area in the drift region. A RESURF structure utilizes a lightly doped substrate (e.g., a p-doped substrate) and a thin epitaxial layer (e.g., an n-type epitaxial layer) to block high voltages in the device. A lateral diode formed from a thin n-type epitaxial layer on a lightly doped p-substrate can have a higher breakdown voltage than a conventional lateral diode without a RESURF structure.

[0017] The example LDMOS devices disclosed herein include surface electric field reduction structures and drift structures, which can significantly improve device performance (e.g., lower Rsp and higher BVdss). Surface electric field reduction structures or drift structures (or both) can include a stepped dopant concentration distribution. LDMOS devices can be n-type (nLDMOS) or p-type (pLDMOS) devices. For simplicity, this document describes only the n-type version of the device, but it should be understood that n-type and p-type dopants can be used interchangeably to describe the p-type version of the device.

[0018] An example LDMOS device can have four terminals, such as a drain terminal, a gate terminal, a source terminal, and a body terminal. If the source terminal and the body terminal are electrically connected together to form a single terminal (often called the source), the device may have three terminals: a drain terminal, a gate terminal, and a source terminal.

[0019] Example LDMOS devices may have a drift diffusion region comprising a reduced surface electric field structure (stepped profile reduced surface electric field structure) with a stepped dopant concentration distribution and a drift structure (stepped profile drift structure) with a stepped dopant concentration distribution.

[0020] A stepped profile surface electric field reduction structure can have an increased dopant concentration along a horizontal or lateral line from the drain side to the source side of the device, or a decreased diffusion depth along the same line, or a combination of both (i.e., increased dopant concentration and decreased diffusion depth along the lateral line). A stepped profile drift structure can have an increased dopant concentration along a horizontal or lateral line from the drain side to the source side of the device. In example embodiments, the dopant distribution of the surface electric field reduction and drift structure can be designed to maximize the breakdown voltage and minimize the device resistance.

[0021] In an example implementation, nLDMOS devices can be fabricated on the BCD technology platform.

[0022] In the example implementation, the nLDMOS device may include one or more of the following structures:

[0023] a. Reduced surface electric field oxides between polysilicon gate and drift region

[0024] b. A self-aligned bulk diffusion region with a linked diffusion region on the source side of the device.

[0025] c. The docking source host connected to the silicide

[0026] d. Using a substrate separated from the source by field oxide (Shallow Trench Isolation (STI), Localized Oxidation of Silicon (LOCOS), etc.)

[0027] e. Provide a buried layer (BL) diffusion region that vertically isolates the device body from the substrate beneath the entire device.

[0028] The diffusion region (i.e., the doped region) described herein can be formed, for example, by ion implantation followed by thermal diffusion.

[0029] In the example, when an nLDMOS device has a BL diffusion region (e.g., an n-type BL (NBL)), the device can be further laterally isolated by an additional annular n-type diffusion region around the device. This additional n-type diffusion region can be deep enough to physically contact the BL diffusion region and shallow enough to physically contact the standard metal contact / silicide / source-drain (SD) structure at the substrate surface.

[0030] In some embodiments, an nLDMOS device can be fabricated on the surface of a p-type doped layer (e.g., a pEpi layer) of silicon grown or deposited on a semiconductor substrate. Two active regions (AAs) – a source active region (AA) and a drain AA – can be formed on the surface of the semiconductor substrate. The two AAs can be laterally separated by growing or depositing a relatively thin (e.g., <20 nm) dielectric layer (e.g., a gate oxide layer) on the pEpi layer. Alternatively, the two AAs can be laterally separated by a surface-field reducing oxide layer formed on the surface of the semiconductor substrate as a thicker (e.g., >30 nm) dielectric (e.g., silicon dioxide) layer. In some embodiments, the gate oxide layer can have the same thickness as the surface-field reducing oxide layer, and the source AA and drain AA can be merged into a single AA.

[0031] Furthermore, in device fabrication, a gate (e.g., a heavily doped n-type polysilicon polygon) can be formed that overlaps with a portion (but not all) of the source AA and a portion of the surface-reducing oxide layer. Spacers (e.g., dielectric structures) can be formed around the entire gate. Heavily doped n-type diffusion regions (often referred to as nLink or nLDD) can be formed at the surface of the source AA and below the spacers.

[0032] In an example implementation, nLDD can be provided by a CMOS technology component of a BCD platform on which devices are fabricated, while nLink can be dedicated to nLDMOS.

[0033] Furthermore, in device fabrication, a source diffusion region (e.g., a heavily doped n-type diffusion region) can be formed on the surface of the source AA and along the spacer, and a body tap diffusion region (e.g., a heavily doped p-type diffusion region) can be formed on the surface of the source AA and along the source diffusion region. In some embodiments, the body tap region may contact the source diffusion region. In some embodiments, the body tap region may be separated from the source diffusion region by an additional isolation dielectric (e.g., a field oxide such as LOCOS or STI) that divides the source AA into two AAs (source AA and body AA).

[0034] Furthermore, in device fabrication, a drain diffusion region (e.g., a heavily doped n-type diffusion region) can be formed on the surface of the drain AA.

[0035] In device fabrication, metallization structures can be fabricated on the surfaces of both the semiconductor substrate and the gate in the following regions: gate polygon, drain diffusion region, source diffusion region, and body tap region. The metallization structure may include silicide contacts (e.g., metal contacts + silicide, etc.). The metal structure can define the gate terminal, drain terminal, source terminal, and body terminal of the nLDMOS device.

[0036] In an example implementation where the body tap region and the source diffusion region are in contact, the source terminal and the body terminal can be connected together as a single source terminal.

[0037] Furthermore, in device fabrication, a host diffusion region (e.g., a lightly doped p-type diffusion region) can be formed on the surface of a semiconductor substrate. The host diffusion region can extend vertically from the surface of the semiconductor substrate to reach a greater depth than the nLink / nLDD, source diffusion region, and host tap region, and can extend horizontally (laterally) to surround the gate-covered portions of the host tap region, source diffusion region, nLink / nLDD, and source AA. The portion of the host diffusion region overlapping the gate can form the device channel. This channel can have a channel length (Lg). The nLink / nLDD can provide electrical continuity between the channel and the source diffusion region, which in turn provides electrical continuity for the source terminals.

[0038] The host diffusion region can be formed by using a sequence of p-type ion implants through a single mask (e.g., a CMOS pWell mask) or through multiple masks (e.g., a CMOS pWell + self-aligned pBody mask).

[0039] Furthermore, in device fabrication, a drift diffusion region (nDrift diffusion region) (e.g., a lightly doped n-type diffusion region) can be formed on the surface of the substrate. The nDrift diffusion region can extend vertically from the surface of the substrate to reach deeper than the drain diffusion region and the reduced surface electric field oxide layer, and can extend horizontally to surround at least a portion of the drain diffusion region, the reduced surface electric field oxide layer, and the source AA.

[0040] In some implementations, the nDrift diffusion region and the main diffusion region may be in contact. In some implementations, the nDrift diffusion region and the main diffusion region may be separate. In some implementations, the nDrift diffusion region and the main diffusion region may overlap.

[0041] The nDrift diffusion region can have a stepped dopant concentration distribution, for example, its dopant concentration gradually increases in the horizontal (lateral) direction from the edge of the drain diffusion region toward the junction of the drain diffusion region and the main diffusion region.

[0042] In an example implementation, a sequence or chain of n-type injectors passing through partially overlapping masks (e.g., at least two partially overlapping masks) can be used to generate a stepped profile of the nDrift diffusion region. Each nDrift diffusion region can have a width (step) corresponding to an opening in the corresponding mask.

[0043] Furthermore, in device fabrication, a reduced surface electric field diffusion region (pResurf diffusion region) (e.g., a lightly doped p-type diffusion region) can be formed at a depth below the surface of the substrate through the substrate surface. The pResurf diffusion region can be confined to a region deeper than the nDrift diffusion region and does not need to extend vertically to the surface of the semiconductor substrate. However, in some embodiments, the pResurf diffusion region may be locally trimmed to resemble the nDrift diffusion region. The pResurf can extend horizontally to surround the nDrift diffusion region. However, in some embodiments, the pResurf diffusion region overlaps with the main diffusion region.

[0044] The pResurf diffusion region can have a stepped profile; for example, its doping concentration gradually increases horizontally from the drain diffusion region toward the bulk diffusion region. The depth of the pResurf diffusion region in the semiconductor substrate can decrease horizontally from the drain diffusion region toward the bulk diffusion region.

[0045] In an example implementation, a sequence or chain of p-type injectors passing through a single mask can be used to generate the stepped profile of the pResurf diffusion region. However, in some implementations, a sequence or chain of p-type injectors passing through multiple masks can be used to generate the stepped profile of the pResurf diffusion region. In some implementations, the mask used to generate the stepped profile of the pResurf diffusion region can be the same as the mask used to generate the nDrift diffusion region.

[0046] Furthermore, in device fabrication, nLDMOS devices can be vertically electrically isolated from pEpi / pSubstrate via an n-type buried layer (nBL) (e.g., a lightly doped buried n-type layer). The nBL can be confined to a region deeper than the pResurf diffusion region and can extend non-vertically toward the surface of the semiconductor substrate.

[0047] In some embodiments, the nBL can extend horizontally across the entire device. In such cases, device fabrication may include additional lateral isolation surrounding the entire device. In some embodiments, additional lateral isolation can be achieved using annular n-type diffusion regions (e.g., nSinker diffusion regions) surrounding the device. The nSinker diffusion region can extend vertically from the surface of a semiconductor substrate in which the nSinker diffusion region can be contacted (e.g., metal contacts and silicides, etc.) to the nBL. In some embodiments, additional lateral isolation can be achieved using deep trench isolation (DTI) structures. In some embodiments, additional lateral isolation can be achieved by combining DTI and nSinker diffusion region structures.

[0048] Figure 1 A half-pitch cross section of a device cell of an example n-type LDMOS device 100 with a p-type stepped profile reduced surface electric field structure 120 and an n-type stepped profile drift structure 110 is shown.

[0049] For ease of description, this article may refer to, for example, in Figure 1 The X and Y axes shown on the page describe the relative orientation or coordinates of the features of device 100. The direction parallel to the X-axis can be referred to as the horizontal or lateral direction. The direction parallel to the Y-axis can be referred to as the vertical or depth direction. Furthermore, for visual clarity, on... Figure 1 Only half of the device cells of device 100 are shown in the image. A real LDMOS device can include dozens or hundreds of device cells, which can be represented, for example, by mapping and repeating (e.g., in the X direction). Figure 1 The finite half-unit structure shown is used to obtain it.

[0050] Device 100 can be fabricated on a BCD technology platform. Device 100 may have a drain structure 130, a gate structure 140, and a source-body structure 150. Device 100 may have three or four terminals (e.g., a drain terminal, a gate terminal, a source terminal, and a body terminal). The source terminal and the body terminal may be connected together. Figure 1 A device 100 is shown, for example, having the following terminals: a drain terminal 131, a gate terminal 141, and a source-body terminal 151 connected together.

[0051] In the example implementation, device 100 may be constructed on a p-type substrate / p-epi / n buried layer (nBL) substrate (e.g., substrate 101). Although nBL may be optional, nBL is useful for high-voltage switching applications of device 100.

[0052] In an example implementation, the source-body structure 150 (e.g., a low-voltage (LV) source) may have a body comprising a p-type well (e.g., pWell 154), a p-type body (e.g., pBody 153), and a p-type source-drain diffusion region (e.g., pSD 152). In an example implementation, the source-body structure 150 may include an n-type source-drain diffusion region (e.g., nSD 155). In some implementations, the body of the source-body structure 150 may comprise only a p-type well (e.g., pWell 154) and a p-type source diffusion region (e.g., pSD 152).

[0053] In an example embodiment, the gate structure 140 of device 100 may include an n-type polysilicon gate (e.g., nPoly 143) and a gate oxide 144 deposited or grown on a silicon surface 102 of substrate 101. Further, spacers 145 (e.g., dielectric structures) may be formed around the entire gate polysilicon. In some embodiments, a channel is formed at the silicon surface 102 below the gate structure 140.

[0054] In an example implementation, the source-body structure 150 (e.g., a low-voltage LV source) may have a source coupled to an n-type source-drain diffusion region (e.g., nSD 155) via an n-type chain structure (e.g., nLink 154 below spacer 145) for a gate region transition. In some implementations, the source of the source structure 150 may be coupled to the n-type source-drain diffusion region (e.g., nSD 155) via a lightly doped drain diffusion structure (e.g., nLDD) for a gate region transition. The nLDD can be implemented using CMOS components of a BCD technology platform.

[0055] In an example embodiment, device 100 may include a resurf oxide structure (e.g., resurf oxide 160) at surface 102 between drain structure 130 and gate structure 140 to reduce surface electric field effects in device 100. The resurf oxide 160 may extend at least partially beneath gate structure 140. In an example embodiment, the resurf oxide layer (e.g., resurf oxide 160) is disposed on the surface (e.g., surface 102) of the substrate beneath the gate (e.g., gate structure 140) of the device.

[0056] In device 100, drain structure 130 may include an n-type source-drain diffusion region (e.g., nSD 132) that makes a low-resistance contact with drain terminal 131. Drain structure 130 further includes one or both of a stepped profile surface electric field reduction structure 120 and an n-type stepped profile drift structure 110. In the example embodiment, the surface electric field reduction effect in device 100 is obtained from one or both of the p-type stepped profile surface electric field reduction structure 120 and the n-type stepped profile drift structure 110 included in the device.

[0057] An n-type stepped profile drift structure 110, fabricated by n-doped implantation through an overlapping mask, may include a series of M nDrift diffusion regions (e.g., region 110-1, region 110-2, region 110-i, ..., and region 110-M, where M is an integer and i is an integer less than M). In example embodiments, M may be two or larger. Figure 1 As shown, the nDrift diffusion regions (e.g., Ndrift diffusion regions 110-1, 110-2, 110-i, ..., and 110-M) can have increasing dopant concentrations along a lateral or horizontal line from the drain side to the source side of the device in a series of M steps (e.g., step 1, step 2, step i, ..., and step M). For example, the dopant concentration in region 110-2 at step 2 can be greater than the dopant concentration at step 1 in region 110-1, the dopant concentration in region 110-i at step i can be greater than the dopant concentration in region 110-2 at step 2, the dopant concentration in region 110-M at step M can be greater than the dopant concentration in region 110-i at step i, and so on. The nDrift diffusion region steps (e.g., step 1, step 2, step i, and step M) can have horizontal widths (e.g., X1, X2, Xi, ..., XM, respectively).

[0058] In an example implementation, the nDrift diffusion regions can extend to different vertical depths in the substrate. For example, the nDrift diffusion region 110-1 at step 1 can extend to a depth d1 below surface 102, region 110-2 at step 2 can extend to a depth d2 below surface 102, region 110-i at step i can extend to a depth di below surface 102, and region 110-M at step M can extend to a depth dm below surface 102. In an example implementation, the depth of each diffusion region in the nDrift diffusion regions below surface 102 (e.g., nDrift diffusion regions 110-1, 110-2, 110-i, ... and 110-M) can decrease in the lateral direction (e.g., stepwise) from the drain diffusion region toward the body diffusion region (e.g., d1>d2>di>dm).

[0059] The nDrift diffusion regions may overlap and extend horizontally below or beneath one another. For example, region 110-1 (having width X1 and depth d1) may extend horizontally below region 110-2 (having width X2 < X1 and depth d2 < d1) and region 110-i (having width Xi < X2 and depth di < d2), etc. Thus, a portion of region 110-2 may be disposed between a portion of region 110-i and region 110-1. Similarly, a portion of region 110-i may be disposed between a portion of region 110-M and region 110-2.

[0060] The n-type stepped-profile drift structure 110 may be fabricated by n-dopant implantation through one or more masks. In an exemplary embodiment, a sequence or chain of n-type implants through partially overlapping masks (e.g., at least two partially overlapping masks) may be used to produce a stepped profile having an increasing doping concentration along a lateral or horizontal line from the drain side to the source side of the device. The nDrift diffusion regions (e.g., Ndrift diffusion regions 110-1, region 110-2, region 110-i,..., and region 110-M) may have horizontal widths (e.g., X1, X2, Xi,..., XM, respectively), which correspond to the openings of the overlapping masks (not shown) through which the n-dopant implantations are performed.

[0061] The p-type stepped-profile reduced surface field structure 120, which may be fabricated by p-dopant implantation through one or more masks, may include a series of m pResurf diffusion regions (e.g., pResurf diffusion regions 120-1, region 120-2, region 120-j,..., and region 120-m, where m is an integer and j is an integer less than m). In an exemplary embodiment, the number m of pResurf diffusion regions in the p-type stepped-profile reduced surface field structure 120 in device 100 may be the same as the number M of nDrift diffusion regions in the n-type stepped-profile drift structure 110 (i.e., m = M). Each pResurf diffusion region may be located at a corresponding depth in the substrate. For example, as Figure 1As shown, the pResurf diffusion region 120-1 at step 1 can be at a depth D1 below surface 102, region 120-2 at step 2 can be at a depth D2 below surface 102, region 120-j at step i can be at a depth Dj below surface 102, and region 120-m at step M can be at a depth Dm below surface 102. In the example embodiment, a sequence or chain of p-type implants passing through one or more masks can be used to generate a stepped profile along a lateral line from the drain side to the source side of the device. The depth of each diffusion region in the pResurf diffusion regions (e.g., pResurf diffusion regions 120-1, 120-2, 120-j, ... and 120-m) below the n-type stepped profile drift region structure 110 can decrease in the lateral direction from the drain diffusion region toward the main diffusion region (e.g., D1 at step 1 > D2 at step 2 > Dj at step i > Dm at step M).

[0062] The reduced surface electric field effect in device 100 caused by the n-type stepped profile drift region structure 110 and the p-type stepped profile reduced surface electric field structure 120 can result in lower Rsp and higher BVdss.

[0063] although Figure 1 An n-type LDMOS is shown, but it should be understood that a p-type LDMOS can be obtained by swapping the n-dopant type and the p-dopant type.

[0064] exist Figure 1 In the example device 100 shown, an n-type stepped profile drift region structure 110 and a p-type stepped profile reduced surface electric field structure 120 can be obtained by injection using a common set of overlapping masks. Further, the number M of nDrift diffusion regions can be the same as the number m of pResurf diffusion regions. In other words, each nDrift diffusion region (e.g., ndrift region 110-1, region 110-2, region 110-i, ... or region 110-M) can have a corresponding or associated pResurf diffusion region (e.g., pResurf region 120-1, region 120-2, region 120-j, ... or region 120-m). The corresponding or related pResurf diffusion regions (e.g., pResurf region 120-1, region 120-2, region 120-j, ... or region 120-m) may have the same width (e.g., X1, X2, Xi, XM) as the nDrift diffusion regions (e.g., Ndrift region 110-1, region 110-2, region 110-i, ... and region 110-M).

[0065] Figure 2An example device 200 is shown, wherein the number M of nDrift diffusion regions differs from the number m of pResurf diffusion regions (e.g., M = m + 1). In example device 200, for example, the first nDrift diffusion region 110-1 does not have a corresponding pResurf diffusion region (i.e., in...). Figure 2 The stepped profile reduced surface electric field structure 120 shown does not have a pResurf diffusion region 120-1. For example, when injection is performed through a common set of overlapping masks, by setting the p-type injectant dose for the pResurf diffusion region 120-1 to zero to obtain the n-type stepped profile drift structure 110 and the p-type reduced surface electric field structure 120, a stepped profile reduced surface electric field structure 120 without the pResurf diffusion region 120-1 can be obtained.

[0066] In some implementations, it may not be necessary to inject through a common set of overlapping masks to obtain the n-type stepped profile drift structure 110 and the p-type stepped profile reduced surface electric field structure 120. Different numbers or geometries of Ndrift and pResurf diffusion regions can be obtained in the n-type stepped profile drift structure 110 and the p-type stepped profile reduced surface electric field structure 120 respectively by injecting through different sets of masks. This geometric flexibility can provide additional control parameters for designing LDMOS device characteristics such as Rsp and BVdss.

[0067] Figure 3 An example device 300 is shown, in which injection through different sets of masks not only yields a number M (e.g., M = 4) of nDrift diffusion regions different from the number m (e.g., m = 3) of pResurf diffusion regions, but also yields an n-type stepped profile drift structure 110 and a p-type stepped profile reduced surface electric field structure 120. For example, Figure 3 An example device 300 is shown with four nDrift regions (regions 110-1, 110-2, 110-I, and 110-M) and only three pResurf2 regions (regions 120-2, 120-j, and 120-m). Figure 3In the example device 300 shown, only the pResurf2 region 120-2 can be injected through the same mask as its corresponding nDrift region 110-2. pResurf2 regions 120-j and 120-m can be injected through masks different from any of the masks used in the four nDrift regions. The pResurf2 region 120-2 injected through the same mask (opening) and the corresponding nDrift region 110-2 can have the same horizontal width (e.g., X2). However, the horizontal widths (e.g., Xrm, Xrj) of pResurf2 regions 120-m and 120-j (injected through masks different from any of the masks used in the four nDrift regions) may differ from the widths (Xm, Xi) of the corresponding nDrift regions 110-M and 110-i.

[0068] Figure 4 An example device 400 is shown, wherein a substrate 101 includes a buried n-type buried layer (nBL) 170. The nBL 170 may be located below the device and is larger than pResurf1 (e.g., Figure 1 The n-type diffusion regions 120-1 and pWell 154 are deeper n-type diffusion regions. In example device 400, the nBL diffusion regions can form barriers that separate the p-type regions of the device (e.g., pBody 153, pWell 154 and the reduced surface electric field structure 120) from the underlying pEpi / pSubstrate 101, thereby allowing the body of the device to be biased independently of pEpi / pSubstrate 101.

[0069] Figure 5 Cross-sectional views of the collision voltage line and equipotential line of the test nLDMOS device, obtained through a technical computer-aided design (TCAD) simulation, are shown. The test nLDMOS device has, for example, two pairs of Ndrift diffusion regions and pResurf diffusion regions (i.e., Figure 1 (nDRift1 / pResurf1 and nDrift2 / pResurf2). Different configurations of injectable dosage for the nDrift1, nDrift2, Presurf1, and Presurf2 regions were considered.

[0070] Figure 6 This is a graph showing the Rsp and BVdss values ​​obtained for various groups of doping concentration values ​​(i.e., dopant concentration group 610) for the implantation doses of the pResurf1, pResurf2, nDRift1, and nDrift2 regions used as test nLDMOS devices. Figure 6 The Rsp and BVdss values ​​obtained for a conventional device (labeled WFR620) are also shown. From Figure 6The results shown indicate that the tested nLDMOS device (labeled WFR 630) exhibits an approximately 21% reduction in Rsp value compared to the conventional device POR WFR620, and also possesses a higher BVdss value (e.g., an increase of approximately 1V). The optimal results for the target WFR 630 correspond, for example, to dopant concentration groups 610 for D11;D32;D33 and D11;D42;D43 in the pResurf2, nDRift1, and nDrift2 regions.

[0071] Figures 7 to 15 This illustrates the fabrication of an example nLDMOS device (e.g., Figure 1 A schematic diagram of the substrate 101 during the processing of multiple steps in an example manufacturing process of the device 100.

[0072] Figure 7 A starting p-type substrate 101 is shown, which may have a sacrificial oxide layer 701 grown on the substrate after pEpi growth, pad oxide growth and STI formation.

[0073] Figure 8 A reduced surface electric field oxide layer 801 grown on substrate 101 is shown. The growth of the reduced surface electric field oxide layer may involve pad nitride layer deposition, reduced surface electric field oxide photolithographic pattern mask, nitride etching, resist stripping, reduced surface electric field oxide growth, and nitride stripping.

[0074] The n-type drift structure 110 and the p-type reduced surface electric field structure 120 can be formed in the substrate 101 by ion implantation through one or more sequences of resist masks (not shown). In an example embodiment, a sequence or chain of n-type implants through partially overlapping masks can be used to form the n-type drift structure 110. A sequence or chain of p-type implants through the same partially overlapping masks can be used to form the p-type reduced surface electric field structure 120. For example, a first resist mask can be placed on the substrate 101, and n-type ions can be implanted through the mask to form a first Ndrift region of the n-type drift structure 110, and p-type ions can be implanted through the same mask to form a first pResurf region of the p-type reduced surface electric field structure 120. Next, a second resist mask (overlapping with the first mask) can be placed on the substrate 101. N-type ions can be implanted through a second resist mask to form a second Ndrift region of the n-type drift structure 110, and p-type ions can be implanted through the same mask to form a second pResurf region of the p-type reduced surface electric field structure 120. Furthermore, the implantation of n-type and p-type ions can be repeated through additional overlapping resist masks placed on the substrate to form additional Ndrift and pResurf regions. N-type ions can be implanted through each of the resist masks placed on the substrate 101 before or after the implantation of p-type ions.

[0075] Figure 9 An n-type drift structure 110 and a p-type surface electric field reduction structure 120 formed in a substrate 101 are shown. The n-type drift structure 110 may include multiple ndrift diffusion regions (e.g., Ndrift1, Ndrift2, Ndrift, ..., and NdriftN). The p-type surface electric field reduction structure 120 may include multiple surface electric field reduction diffusion regions (e.g., pResurf1, pResurf2, pResurf, ..., and pResurfN). The formation of these structures may involve: an nDrift1 mask, an nDrift1 implant chain, a resurf1 implant chain, and resist stripping; ...; an nDriftN mask, an nDriftN implant chain, a pResurfN implant chain, and resist stripping, etc.

[0076] Figure 10 A p-type well 1001 formed in a substrate 101 is shown. The formation of the p-well may involve: a p-well mask, p-well implantation, and resist stripping.

[0077] Figure 11 The diagram shows the formation of gate oxide 1101 on the top surface of substrate 101 (after the sacrificial oxide layer is stripped).

[0078] Figure 12The image shows a substrate 101 after forming a precursor structure 1201 for a gate (e.g., nPoly), a structure 1202 for a p-body, and a structure 1203 for an nLink. The formation of these structures may involve: polysilicon deposition, a self-aligned pBody mask, polysilicon etching, nLink implantation, pBody implantation, and resist stripping.

[0079] Figure 13 The substrate 101 is shown after the gate structure 1301 has been formed in the substrate 101. The formation of this structure may involve: polysilicon masking, polysilicon etching, and resist stripping.

[0080] Figure 14 The substrate 101 is shown after the source and drain structures (e.g., spacer 1401, pSD 12P, and nSD 13N) have been formed in the substrate 101. The formation of these structures may involve: spacer formation, nSD mask, nSD implant, resist stripping, pSD mask, pSD implant, and resist stripping.

[0081] Figure 15 The substrate 101 is shown after a back-end metallization process, including a silicide layer 1504, has been used to form device terminals (e.g., source terminal 1501, gate terminal 1502, and drain terminal 1503). The back-end process may involve silicide formation, interlayer dielectric (ILD) layer formation, ILD formation, and the formation of conductive material or metal contacts.

[0082] Figure 16 An example method 1600 is shown for manufacturing a MOSFET device (e.g., an n-type LDMOS) with reduced on-state resistance (Rsp) at a given breakdown voltage (BVdss).

[0083] Method 1600 includes forming a source region and a drain region (1610) on the surface of a semiconductor substrate; forming a gate region (1620); forming a bulk diffusion region (1630); forming a metal structure (1640); and forming a drift region (1650). The semiconductor substrate may be, for example, a p-type substrate (e.g., pEpi / pSubstrate) having a p-type doped silicon epitaxial layer.

[0084] The formation of source and drain regions 1610 may include forming a dielectric layer (e.g., a gate oxide layer less than about 20 nm) at the surface of the semiconductor substrate and forming a surface-reducing oxide layer (e.g., a dielectric layer greater than about 30 nm) at the semiconductor surface to separate the source and drain regions.

[0085] Forming the gate region 1620 may include forming a gate polygon (e.g., a heavily doped n-type polysilicon layer) to overlap with a portion, but not all, of the source region and a portion of the surface-field reducing oxide layer. Forming the gate region 1620 may further include forming spacers (i.e., dielectric structures) around the gate polygon.

[0086] The formation of the source and drain regions 1610 may further include: forming a first heavily doped n-type diffusion (commonly referred to as nLink or nLDD) on the surface of the source region and below the spacer, forming a second heavily doped n-type diffusion (source diffusion) on the surface of the source region and along the spacer, and forming a heavily doped p-type diffusion (body tap) on the surface of the source region and along the source diffusion.

[0087] In some example implementations, the body tap diffusion can contact the source diffusion. In some example implementations, the body tap can be separated from the source diffusion by an additional isolation dielectric (e.g., field oxide, LOCOS, STI, etc.). The additional isolation dielectric can divide the source region into two parts: the source region and the body region.

[0088] The formation of source and drain regions 1610 may further include forming heavily doped n-type diffusion (drain diffusion) at the surface of drain AA.

[0089] Forming the host diffusion region 1630 may include forming a lightly doped p-type diffusion (host diffusion) by using a sequence of p-type ion implants through a single mask (e.g., a CMOS pWell mask) or through multiple masks (e.g., a CMOS pWell mask + a self-aligned pBody mask). The host diffusion region may extend vertically from the surface of the semiconductor substrate deeper than the nLink / nLDD, source diffusion, and host tap. Further, the host diffusion may extend horizontally to surround the host tap, source diffusion, nLink / nLDD, and the portion of the source region covered by the gate region. The portion of the host diffusion region that overlaps with the gate region is typically referred to as a channel, and its length (Lg) is typically referred to as the gate length. In an example embodiment, the nLink / nLDD may provide electrical continuity between the channel and the source diffusion.

[0090] Forming the metal structure 1640 may include forming a metal structure on the surfaces of both the semiconductor substrate and the gate region (e.g., above the gate polygon, drain diffusion, source diffusion, and body tap). The metal structure may include a silicide layer and metal or conductive contacts. The metal structure defines terminals of the device (e.g., gate terminal, drain terminal, source terminal, and body terminal). In an example embodiment, where the source diffusion and body diffusion contacts are in place in the device, the source terminal and body terminal may be connected to a single terminal (i.e., the source terminal).

[0091] Forming the drift region 1650 may include forming an n-type drift structure with a stepped dopant concentration distribution, wherein the dopant concentration increases along the lateral direction from the drain region to the source region of the device (1652).

[0092] Forming an n-type drift structure 1652 may include surface implantation of two or more lightly doped drift diffusion regions (nDrift diffusion regions) through a semiconductor substrate. In an example embodiment, surface implantation of two or more lightly doped drift diffusion regions through a semiconductor substrate includes implanting n-type ions through multiple overlapping masks. In an example embodiment, a MOSFET device may have an n-type drift structure having two implanted overlapping drift diffusion regions.

[0093] The nDrift diffusion region can extend vertically from the surface of the semiconductor substrate to reach a greater depth than the drain diffusion and the reducing surface electric field oxide. Furthermore, the nDrift diffusion region can extend horizontally to surround at least a portion of the drain diffusion, the reducing surface electric field oxide, and the source region.

[0094] In some example implementations, the nDrift diffusion region and the main diffusion region may be in contact. In some example implementations, the nDrift diffusion region and the main diffusion region may be separate, and in some example implementations, the nDrift diffusion region and the main diffusion region may overlap.

[0095] In an example implementation, the nDrift diffusion region may have a stepped dopant concentration distribution in which the dopant concentration in the nDrift diffusion region increases horizontally in steps from the edge of the drain diffusion region to the junction with the body diffusion region. The stepped dopant concentration distribution can be formed by a sequence of n-type ion implants passing through multiple overlapping masks. In an example implementation, a minimum of two partially overlapping masks can be used to form the stepped dopant concentration distribution (e.g., a dopant concentration distribution with an intermediate dopant concentration step over two nDrift diffusion regions).

[0096] Forming the drift region 1650 may further include forming a p-type reduced surface electric field structure with a stepped dopant concentration distribution, wherein the dopant concentration increases along the lateral direction from the drain region to the source region of the device (1654).

[0097] p-type reduced surface electric field structures may include one or more pResurf diffusion regions. These pResurf diffusion regions may be confined to areas deeper than the nDrift diffusion regions and may not extend vertically to the surface of the semiconductor substrate. In some embodiments, the pResurf diffusion regions may be locally tailored to nDrift diffusion.

[0098] Furthermore, the pResurf diffusion region can extend horizontally to surround the nDrift diffusion region. In some implementations, the pResurf diffusion region can overlap with the main diffusion region.

[0099] In an example implementation, the pResurf diffusion region may have a dopant concentration distribution in which the dopant concentration increases stepwise in the horizontal direction from below the drain diffusion toward the bulk. In some implementations, the depth of the pResurf diffusion region may decrease stepwise in the horizontal direction from below the drain diffusion toward the bulk diffusion.

[0100] In some example implementations, the stepped dopant concentration distribution in the pResurf diffusion region can be formed by a sequence of p-type ion implants passing through a single mask or multiple masks.

[0101] In some example implementations, the stepped dopant concentration distribution of the pResurf diffusion region can be formed by a p-type ion implantation sequence passing through the same overlapping mask of the n-type ion implantation sequence used for the stepped dopant concentration distribution of the nDrift diffusion region.

[0102] In the example implementation, the number of overlapping masks can be two. Injection through two overlapping masks can produce a stepped dopant concentration distribution in the nDrift diffusion region with two diffusion regions (the dopant concentration between the two diffusion regions has a step).

[0103] Method 1600 may further include forming an isolation structure to electrically isolate the device from the substrate (1660). In an example embodiment, forming the isolation structure 1660 may include forming a lightly doped buried n-type diffusion (nBL). For example, nBL can vertically electrically isolate an nLDMOS device from a pEpi / pSubstrate.

[0104] The nBL can extend horizontally to surround the entire device. In example embodiments, the nBL is confined to a region deeper than the pResurf diffusion region and does not extend vertically to the surface of the semiconductor substrate. In some example embodiments, the pResurf diffusion region can be locally trimmed into the nBL.

[0105] Furthermore, forming the isolation structure 1660 may include forming additional lateral isolation surrounding the entire device. Forming the additional lateral isolation may include forming an n-type diffusion region (nSinker). The nSinker may be a ring-shaped diffusion region that surrounds the device and extends vertically from the substrate surface to nBL. The nSinker may be contacted at the surface of the substrate by a metal structure (e.g., metal contacts, silicide layer, etc.).

[0106] In some example implementations, forming additional lateral isolation may include forming a deep trench structure (DTI) or combining a DTI with an nSinker for lateral isolation.

[0107] It should also be understood that when an element (such as a transistor or resistor) is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of this application (if included) may be amended to describe the exemplary relationships described in the specification or shown in the drawings.

[0108] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatial relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, term proximity may include lateral proximity or horizontal proximity.

[0109] Specific implementations of the various techniques described herein may be implemented (e.g., included therein) in digital electronic circuits, computer hardware, firmware, software, or combinations thereof. Parts of the methods may also be implemented using dedicated logic circuits such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), and the apparatus may be implemented as such dedicated logic circuits.

[0110] The implementation can be implemented in a computing system that includes industrial motor drives, solar inverters, ballasts, general-purpose half-bridge topologies, auxiliary and / or traction motor inverter drives, switch-mode power supplies, on-board chargers, uninterruptible power supplies (UPS), back-end components (e.g., as data servers), or middleware components (e.g., application servers), or front-end components (e.g., client computers with graphical user interfaces or web browsers through which users can interact with the implementation), or any combination of such back-end, middleware, or front-end components. Components can be interconnected via digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (LANs) and wide area networks (WANs), such as the Internet.

[0111] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and so on.

[0112] While certain features of the described embodiments have been illustrated herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the particular embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or methods described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A lateral MOSFET, the lateral MOSFET comprising: Substrate; Source region; Gate region; Drain region; and A drift region is disposed between the gate region and the drain region. The drift region includes a drift structure comprising a series of overlapping drift diffusion regions formed along a lateral direction from the drain region to the source region. The series of overlapping drift diffusion regions has a stepped dopant concentration distribution, wherein the dopant concentration increases along the lateral direction from the drain region to the source region.

2. The MOSFET of claim 1, wherein the series of overlapping drift diffusion regions comprises a plurality of overlapping drift diffusion regions extending along the lateral direction from the drain region to the source region to a reduced depth.

3. The MOSFET of claim 1, further comprising: A reduced surface electric field (RESURF) structure is disposed below the drift structure in the drift region, the reduced surface electric field structure including a plurality of reduced surface electric field diffusion regions formed along the lateral direction from the drain region to the source region.

4. The MOSFET of claim 3, wherein each of the plurality of reduced surface electric field diffusion regions is formed at a corresponding depth in the substrate, and wherein the depth of the plurality of reduced surface electric field diffusion regions decreases along the lateral direction from the drain region to the source region.

5. The MOSFET of claim 3, wherein each of the plurality of reduced surface electric field diffusion regions has a corresponding dopant concentration, and wherein the dopant concentration of the plurality of reduced surface electric field diffusion regions increases in a stepwise manner along the lateral direction from the drain region to the source region.

6. The MOSFET of claim 5, wherein each of the series of overlapping drift diffusion regions has a width in the lateral direction and is associated with one of the plurality of reduced surface electric field diffusion regions having the same width or different widths in the lateral direction.

7. The MOSFET of claim 5, wherein at least one of the series of overlapping drift diffusion regions is not associated with any surface electric field reduction diffusion region.

8. A method for manufacturing a MOSFET, the method comprising: Source and drain regions are formed on the surface of a semiconductor substrate; Forming the gate region; Formation of the main diffusion zone; Forming a metallic structure; as well as A drift region is formed, the drift region including an n-type drift structure, the n-type drift structure including a series of n-type overlapping drift diffusion regions formed along a lateral direction from the drain region to the source region, the series of n-type overlapping drift diffusion regions having a stepped dopant concentration distribution, wherein the dopant concentration increases along the lateral direction from the drain region to the source region.

9. The method of claim 8, wherein forming the n-type drift structure comprises implanting two or more lightly doped drift diffusion regions through the surface of the semiconductor substrate, and wherein the two or more lightly doped drift diffusion regions have a stepped dopant concentration distribution, wherein the dopant concentration in the two or more lightly doped drift diffusion regions increases stepwise in a horizontal direction from the edge of the drain region to the main diffusion region.

10. The method of claim 8, wherein forming the drift region further comprises forming a p-type reduced surface electric field (RESURF) structure having a stepped dopant concentration distribution, wherein the dopant concentration increases along a lateral direction from the drain region to the source region.

11. The method of claim 10, wherein forming the p-type reduced surface electric field structure comprises forming one or more lightly doped p-type diffusion regions, the one or more lightly doped p-type diffusion regions being confined in a region deeper than the n-type drift structure.

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