Gate driver stage, bootstrap circuit and gate driver integrated device

Abstract

This application relates to a gate driver stage, a bootstrap circuit, and a gate driver integrated device. A gate driver bootstrap circuit and related methods are disclosed. An example gate driver stage (202) includes a first terminal (302) to be coupled to a capacitor (234), the capacitor and a second terminal (304) to be coupled to a gate terminal (322) of a power transistor (120A); a gate driver (334) coupled to the first terminal and the second terminal; and a bootstrap circuit (232) coupled to the first terminal, the second terminal, and the gate driver, the bootstrap circuit including a control stage circuit (408) having an output, and a first transistor (410) having a first gate terminal (410G) coupled to the output and a first current terminal (410S) coupled to the first terminal.

Description

[0001] Related applications

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 62 / 923,343, filed October 18, 2019. U.S. Provisional Patent Application No. 62 / 923,343 is hereby incorporated herein by reference in its entirety. Priority is claimed in U.S. Provisional Patent Application No. 62 / 923,343. Technical Field

[0003] This invention generally relates to gate drivers, and more specifically to gate driver bootstrap circuits and related methods. Background Technology

[0004] High-voltage and / or high-current applications require power electronics capable of operating efficiently and effectively under various operating conditions. In such applications, power modules utilize power devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), etc.) to deliver power. Drivers are used to control the power devices acting as power delivery systems to support the delivery of power to the load. Summary of the Invention

[0005] One embodiment of the present invention provides a gate driver stage, the gate driver stage comprising: a first terminal and a second terminal, the first terminal being coupled to a capacitor, the capacitor and the second terminal being coupled to a gate terminal of a power transistor; a gate driver coupled to the first terminal and the second terminal; and a bootstrap circuit coupled to the first terminal, the second terminal and the gate driver, the bootstrap circuit comprising: a control stage circuit having an output; and a first transistor having a first gate terminal and a first current terminal, the first gate terminal being coupled to the output and the first current terminal being coupled to the first terminal.

[0006] Another embodiment of the present invention provides a bootstrap circuit, the bootstrap circuit comprising: a first current limiting circuit having a first output; a second current limiting circuit having a second output; a control stage circuit having a first input, a second input, and a third output, the first input being coupled to the first output and the second output; a voltage regulation loop having a third input, a fourth input, and a fourth output, the fourth output being coupled to the first input; and a transistor having a gate terminal and a current terminal, the gate terminal being coupled to the third output, and the current terminal being coupled to the third input.

[0007] Another embodiment of the present invention provides a gate driver stage, the gate driver stage comprising: a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal, the second terminal, and the third terminal being coupled to a gate terminal of a transistor, and the fourth terminal being coupled to a current terminal of the transistor; a first gate driver coupled to the first terminal and the second terminal, the first gate driver being configured to turn on the transistor; a second gate driver coupled to the third terminal and the fourth terminal, the second gate driver being configured to turn off the transistor; and a bootstrap circuit coupled to the first terminal, the second terminal, and the first gate driver.

[0008] Another embodiment of the present invention provides a gate driver integrated device, the gate driver integrated device comprising: a first terminal coupled to a capacitor; a second terminal coupled to a gate terminal of a transistor; a gate driver stage coupled to the first terminal and the second terminal, the gate driver stage comprising: a gate driver configured to turn on the transistor; and a bootstrap circuit coupled to the first terminal, the second terminal and the gate driver. Attached Figure Description

[0009] Figure 1 This is a schematic illustration of a typical electric or hybrid vehicle high-voltage power electronic device system that includes a typical controller and a typical gate driver integrated device.

[0010] Figure 2 It includes an instanced gate driver stage and an instanced bootstrap circuit. Figure 1 A schematic illustration of an implementation scheme for an example gate driver integrated device.

[0011] Figure 3 yes Figure 2 A schematic illustration of an example gate driver stage and an example bootstrap circuit.

[0012] Figure 4 It includes an instanced control stage circuit, a first instanced current limiting circuit, and a second instanced current limiting circuit. Figures 2 to 3 A schematic diagram illustrating an example of a bootstrap circuit.

[0013] Figure 5 It includes Figure 4 The implementation schemes of the instanced control stage circuit, the first instanced current limiting circuit, and the second instanced current limiting circuit. Figures 2 to 4 A schematic diagram illustrating an example of a bootstrap circuit.

[0014] Figure 6 Is with Figure 2 , 3Timing diagrams corresponding to the instance operations of instance bootstrap circuits 4 and / or 5.

[0015] Figure 7 This is a schematic illustration of an implementation of an instance gate driver integrated device that includes an instance gate driver stage and an instance bootstrap circuit.

[0016] Figure 8 Is with Figure 7 The timing diagram corresponding to the instance operation of the instance bootstrap circuit.

[0017] Figure 9A Is with Figure 2 , 3 Timing diagrams corresponding to the instance operations of instance bootstrap circuits 4 and / or 5 during the charging operation.

[0018] Figure 9B Is with Figure 7 The timing diagram corresponding to the instance operation of the instance bootstrap circuit during the charging operation.

[0019] Figure 10A It is related to short-circuit conditions. Figure 2 , 3 Timing diagrams corresponding to the instance operations of instance bootstrap circuits 4 and / or 5.

[0020] Figure 10B It is related to short-circuit conditions. Figure 7 The timing diagram corresponding to the instance operation of the instance bootstrap circuit.

[0021] Figure 11A It is related to the output undershoot condition of the gate driver. Figure 2 , 3 Timing diagrams corresponding to the instance operations of instance bootstrap circuits 4 and / or 5.

[0022] Figure 11B It is related to the output undershoot condition of the gate driver. Figure 7 The timing diagram corresponding to the instance operation of the instance bootstrap circuit.

[0023] Figure 12 This means that it can be implemented using executable instance machine-readable instructions and / or configured to perform... Figure 2 , 3 4 and / or 5 example bootstrap circuits Figure 2 Instance gate driver stages and / or more generally Figure 1 The flowchart illustrates the process performed when the hardware of the instance gate driver integrated device is invoked from the instance gate driver contained in the instance gate driver stage. Detailed Implementation

[0024] The figures are not to scale. Generally, the same element symbols will be used in all figures and accompanying written description to refer to the same or similar parts. As used herein, connection references (e.g., attachment, coupling, connection, and combination) will be interpreted in accordance with the language of the description and, where applicable, the surrounding claims. Connection references in this application should be constructed in accordance with the language of the claims and the context of the description which describes the purpose of connecting or coupling various elements. Thus, connection references do not necessarily imply that two elements are directly connected or directly coupled to each other and have a fixed relationship.

[0025] The term "coupled" is used throughout this specification. This term may encompass connection, communication, or signaling paths that achieve a functional relationship consistent with the description of this invention. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B via a direct connection, or in a second instance, device A is coupled to device B via an intervening component C (if the intervening component C does not alter the functional relationship between device A and device B), such that control signals generated by device A via device A control device B.

[0026] The descriptors “first,” “second,” “third,” etc., are used herein when identifying multiple elements or components that can be individually mentioned. Unless otherwise specified or understood based on their context of use, such descriptors are not intended to assign any meaning regarding priority, physical order or arrangement in a list, or chronological sequence, but are merely labels to individually mention multiple elements or components for ease of understanding of the disclosed instance. In some instances, the descriptor “first” may be used to refer to an element in a detailed description, while the same element may be referred to in the claims using different descriptors such as “second” or “third.” In such examples, it should be understood that such descriptors are used merely for ease of mentioning multiple elements or components.

[0027] Consistent with this invention, the term "configured to" is intended to describe the structural and functional characteristics of one or more tangible, non-transitory components. For example, the term "configured to" can be understood as having a specific configuration designed or specifically intended to perform a certain function. Within this understanding, if a device includes tangible, non-transitory components that can be enabled, activated, or powered to perform a certain function, then the device is "configured to" perform said function. While the term "configured to" may encompass the concept of configurability, it should not be limited to this narrow definition. Therefore, when used to describe a device, the term "configured to" does not require that the described device be configurable at any given point in time.

[0028] Furthermore, the term "example" is used herein to mean something used as an example, illustration, etc., and is not necessarily advantageous. Moreover, although the invention has been shown and described with respect to one or more embodiments, equivalent changes and modifications will become apparent upon reading and understanding this specification and the accompanying drawings. The invention includes all such modifications and modifications and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), the terminology used to describe such components is intended to correspond (unless otherwise indicated) to any component that performs the specified function of the described component (e.g., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure. Additionally, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, this feature may be combined with one or more other features of other embodiments, which may be desirable and advantageous for any given or particular application.

[0029] While this specification contains numerous details, these details should not be construed as limiting the scope of what can be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of a single embodiment may also be implemented in combination in that single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a certain combination and even initially claimed, in some cases one or more features from said combination may be removed from said combination, and said combination may be for sub-combinations or variations thereof.

[0030] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring the execution of such operations in the shown specific order or sequential order, or the execution of all illustrated operations, to achieve the desired result, unless such order is stated in one or more claims. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be construed as requiring such separation in all embodiments.

[0031] The automotive traction market is poised for rapid growth in the coming years due to increasingly stringent global government regulations on carbon dioxide (CO2) emissions. For example, California, France, and the UK have announced plans to phase out the sale of internal combustion engine (ICE) vehicles by 2040.

[0032] High-voltage and / or high-current isolated-gate driver environments and applications (such as traction inverters in electric vehicles (EVs), hybrid electric vehicles (HEVs), etc.) require power electronics capable of efficient and effective operation at high temperatures. Power delivery and / or management modules can deliver power using low-impedance insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), etc., made of silicon carbide (SiC) or any other material. For example, power silicon carbide transistors can be used to deliver tens or hundreds of amperes to a load during normal operation.

[0033] In traction applications (e.g., in traction inverters for EV or HEV vehicles), gate drivers with high output current are used to drive high-power devices. There are technical constraints for designing high-current output drivers. For example, P-type devices (e.g., P-channel field-effect transistors (FETs) (e.g., P-channel MOSFETs), IGBTs, etc.) consume large die areas. In such examples, N-type devices (e.g., N-channel FETs (e.g., N-channel MOSFETs), IGBTs, etc.) can be used instead of P-type devices by driving the gate of an N-type device with a charge pump or bootstrap procedure (e.g., a bootstrap circuit). Another technical constraint is to reduce the die area of ​​said power devices while improving the power efficiency, reliability, and safety of high-voltage and / or high-current power devices.

[0034] In some examples, the gate driver (e.g., a gate driver operating in a traction application) may include a conventional bootstrap circuit that does not generate sufficient current in response to a short or narrow negative pulse produced by the gate driver. For example, the gate driver output (e.g., a high-side (HS) gate driver output) may not drop to a reference voltage (e.g., it may not drop all the way down to 0 volts (V)). In such examples, the peak current delivered to the gate driver by the bootstrap circuit may be lower than desired because the peak current is based on the HS gate driver output. Accordingly, a lower HS gate driver voltage output may result in a lower peak current.

[0035] In some examples, the gate driver (e.g., a gate driver operating in a traction application) may include a conventional bootstrap circuit that is not configured to reduce the current generated by the bootstrap circuit in response to a short-circuit condition. For example, integrated circuit (IC) terminals (e.g., electrical connections, legs, pins, etc.) may be shorted to ground (e.g., ground rail, reference rail, etc.). In such examples, the bootstrap circuit may generate current at a relatively high level for a period of time, which can lead to damage to the gate driver or other associated electrical components.

[0036] In some examples, the gate driver (e.g., a gate driver operating in a traction application) may include a conventional bootstrap circuit that generates a current that can cause an overcharge condition in a capacitor associated with the bootstrap circuit. The capacitor can be used to boost the voltage at the input of the gate driver. For example, the gate driver may produce a gate driver output (e.g., an HS gate driver output) that is less than a reference voltage (e.g., less than 0V). In such examples, the bootstrap circuit can overcharge the capacitor, which can lead to damage to the gate driver or other associated electrical components.

[0037] The examples disclosed herein include exemplary bootstrap circuits to improve the operation of exemplary gate drivers. In some of the disclosed examples, the bootstrap circuit is coupled to the HS output of the gate driver. For example, the bootstrap circuit may be an HS output reference bootstrap circuit. In such examples, the bootstrap circuit may be configured to use a reference voltage of the HS output. In some of the disclosed examples, the bootstrap circuit includes a voltage regulation loop to reduce and / or otherwise eliminate overcharging of the capacitors associated with the bootstrap circuit. In such disclosed examples, the voltage regulation loop reduces the power consumption of the bootstrap circuit when it is not necessary to bootstrap the gate driver to a specified output.

[0038] In some of the disclosed embodiments, the bootstrap circuit includes a control stage circuit and a first current-limiting circuit configured to protect the control stage circuit from exceeding a predetermined current density (e.g., maximum current density, peak current density, etc.) and / or safe operating area (SOA) of the components included in the gate driver and / or more generally the gate driver. In some of the disclosed embodiments, the bootstrap circuit includes a second current-limiting circuit configured to be triggered and / or otherwise invoked after a predefined or predetermined time delay to protect the components included in the gate driver and / or more generally the gate driver during short-circuit conditions. Advantageously, the exemplary bootstrap circuits disclosed herein can improve the reliability, safety, and / or operational life of electrical components included in safety-related applications (e.g., gate drivers or other integrated circuits included in traction inverters or other electrical or electronic assemblies contained in EVs, HEVs, etc.).

[0039] Figure 1 This is a schematic illustration of an exemplary high-voltage power electronic device system 100 including exemplary gate driver integrated devices 102A to F. Figure 1In the examples, gate driver integrated devices 102A to F include a first exemplary gate driver integrated device 102A, a second exemplary gate driver integrated device 102B, a third exemplary gate driver integrated device 102C, a fourth exemplary gate driver integrated device 102D, a fifth exemplary gate driver integrated device 102E, and a sixth exemplary gate driver integrated device 102F. Alternatively, the high-voltage power electronic device system 100 may include more than Figure 1 The gate driver integrated devices 102A to F depicted herein are few or more gate driver integrated devices.

[0040] exist Figure 1 In the illustrated example, the high-voltage power electronics system 100 is a vehicle high-voltage power electronics system included in EVs, HEVs, etc. Alternatively, the high-voltage power electronics system 100 can be used in any other high-voltage application (e.g., 200-volt (V) power delivery applications, 400-V power delivery applications, 650-V power delivery applications, etc.).

[0041] exist Figure 1 In the illustrated example, the high-voltage power electronic device system 100 includes an exemplary three-phase battery charger 104 to convert alternating current (AC) power into direct current (DC) power to charge an exemplary battery source 106. Figure 1 In this example, a three-phase battery charger 104 is coupled to a battery power source 106. Figure 1 In this example, the three-phase battery charger 104 is a three-phase rectifier that converts AC power from the exemplary trunk transmission network 108 into DC power to charge one or more high-voltage batteries of the battery source 106. Alternatively, the three-phase battery charger 104 can be replaced with a battery charger having two or fewer phases or more than three phases. Figure 1 In this embodiment, battery source 106 includes one or more lithium-ion batteries. Alternatively, battery source 106 may include different types of batteries or a combination of different battery types.

[0042] exist Figure 1 In the illustrated example, the three-phase battery charger 104 has a two-stage architecture. Figure 1In one example, the two-stage architecture includes an exemplary first stage 110 corresponding to a front-end power factor correction (PFC) stage and a second exemplary stage 112 corresponding to an isolated DC / DC converter. For example, the first stage 110 may be an active PFC circuit comprising a multiphase rectifier, control circuitry, and power transistors. In such an example, the first stage 110 may be configured to convert AC power from the mains transmission network 108 into DC power. The control circuitry may be configured to measure the DC input voltage and / or current, and then adjust the switching time, duty cycle, etc., to ensure that the DC input voltage and / or current are in phase, reduce switching losses, reduce switching noise, and / or combinations thereof. In other examples, the second stage 112 may be a converter (e.g., a flyback converter, a boost converter, etc.) configured to perform soft switching and reduce electromagnetic interference (EMI).

[0043] exist Figure 1 In the illustrated example, battery source 106 is coupled to exemplary power converter 114. Figure 1 In one example, power converter 114 is a high-voltage boost converter. For instance, in an example where the voltage of battery source 106 is relatively low (e.g., 12V, 24V, etc.), power converter 114 can be configured to boost the voltage of battery source 106 to several hundred volts (e.g., 200V, 400V, 600V, etc.). Alternatively, Figure 1 The power converter 114 may include one or more of the following: power converter 114 and / or different types of power converters (e.g., buck converter, buck-boost converter, etc.).

[0044] exist Figure 1 In the illustrated example, power converter 114 is coupled to an exemplary traction inverter 116. Figure 1 In this example, traction inverter 116 is a high-voltage traction inverter configured to convert DC current from power converter 114 into AC current to control the rotation of exemplary motor 118 by generating a rotating magnetic field. Figure 1 In this context, motor 118 is a three-phase motor. For example, motor 118 may be a three-phase motor configured to be included in EVs, HEVs, etc. Alternatively, motor 118 may be configured to be controlled using fewer or more than three phases.

[0045] exist Figure 1 In the illustrated example, the traction inverter 116 includes gate driver integrations 102A to F to perform switching and / or other operations on exemplary transistors (e.g., power transistors) 120A to F. Figure 1In the example, transistors 120A to F include a first exemplary transistor 120A, a second exemplary transistor 120B, a third exemplary transistor 120C, a fourth exemplary transistor 120D, a fifth exemplary transistor 120E, and a sixth exemplary transistor 120F. Alternatively, there may be a transistor with the following characteristics: Figure 1 The examples depict transistors ranging from 120A to F, with fewer or more transistors.

[0046] exist Figure 1 In the illustrated example, transistors 120A to F are N-channel transistors (e.g., N-channel field-effect transistors (FETs), N-channel IGBTs, etc.). For example, one or more of transistors 120A to F may be silicon carbide (SiC) N-channel transistors, silicon (Si) N-channel transistors, etc., and / or combinations thereof. Alternatively, P-channel transistors (e.g., P-channel FETs, P-channel IGBTs, etc.) may be used to implement the traction inverter 116. For example, one or more of transistors 120A to F may be SiC P-channel transistors, Si P-channel transistors, etc., and / or combinations thereof.

[0047] exist Figure 1 In the illustrated example, transistors 120A to F are IGBTs. For example, one or more of transistors 120A to F may be SiC N-channel IGBTs, SiN-channel IGBTs, and / or combinations thereof. Alternatively, alternatives and / or other than these may be used. Figure 1 The traction inverter 116 is implemented using FETs (e.g., power FETs, MOSFETs, power MOSFETs, etc.) of the IGBTs depicted in the examples. For example, one or more of transistors 120A to F may be SiC N-channel FETs (e.g., SiC N-channel MOSFETs), SiC P-channel FETs (e.g., SiC P-channel MOSFETs), Si N-channel FETs (e.g., Si N-channel MOSFETs), Si P-channel FETs (e.g., Si P-channel MOSFETs), and / or combinations thereof. In such examples, one or more of transistors 120A to F may be SiC FETs, Si FETs, etc.

[0048] exist Figure 1 In the illustrated example, the first gate driver integrated device 102A is coupled to the first transistor 120A. Figure 1 In this configuration, the second gate driver integrated device 102B is coupled to the second transistor 120B. Figure 1 In this configuration, the third gate driver integrated device 102C is coupled to the third transistor 120C. Figure 1 In the middle, the fourth gate driver integrated device 102D is coupled to the fourth transistor 120D. In Figure 1In the process, the fifth gate driver integrated device 102E is coupled to the fifth transistor 120E. Figure 1 In the middle, the sixth gate driver integrated device 102F is coupled to the sixth transistor 120F.

[0049] exist Figure 1 In the illustrated examples, gate driver integrated devices 102A to F are integrated circuits that control the switching operation of transistors 120A to F. In some examples, gate driver integrated devices 102A to F include bootstrap circuitry (e.g., Figure 2 , 3 The first exemplary bootstrap circuit 232 depicted in 4 and / or 5 is configured to have a cutoff reference voltage based on the output of the gate driver integrated devices 102A to F. In such examples, the bootstrap circuit may be configured to reduce and / or otherwise eliminate overcharging of the bootstrap capacitor associated with the bootstrap circuit. In some such examples, the bootstrap circuit may be configured to reduce overcharging of the bootstrap capacitor even when the output decreases below a zero voltage threshold.

[0050] In some instances, gate driver integrations 102A to F include bootstrap circuitry to increase the charging rate of the bootstrap capacitor while improving the reliability, safety, and / or operational life of the corresponding transistors 120A to F and / or more generally, the high-voltage power electronics system 100. For example, the bootstrap circuitry may include a first current-limiting circuit that can be triggered and / or otherwise invoked in response to activation, switching, or other actions of the high-voltage power electronics system 100 to increase the charging rate of the bootstrap capacitor. In such instances, the bootstrap circuitry may trigger the first current-limiting circuitry to charge the bootstrap capacitor within a predefined width of a negative pulse signal generated by the gate driver integrations 102A to F. In some such instances, the bootstrap circuitry may charge the bootstrap capacitor relatively quickly (e.g., less than 250 nanoseconds (ns), less than 300 ns, etc.) and with a sufficient current (e.g., 200 milliamperes (mA), 250 mA, etc.).

[0051] In some instances, the bootstrap circuitry of the corresponding transistors 102A to F includes a second current-limiting circuit that can be triggered and / or otherwise invoked in response to an elapsed predefined time period to improve the reliability, safety, and / or operational life of the transistors 120A to F and / or more generally, the high-voltage power electronic device system 100. In such instances, the bootstrap circuitry can trigger the second current-limiting circuitry to charge (e.g., further charge) the bootstrap capacitor with a second amount of current less than a first amount generated by the first current-limiting circuitry. In some such instances, the bootstrap circuitry can charge the bootstrap capacitor with the second amount of current (e.g., 30 mA, 45 mA, etc.) while preventing the corresponding transistors 120A to F from heating above a heating threshold level, which could lead to damage to the transistors 120A to F.

[0052] exist Figure 1 In the illustrated example, the high-voltage power electronic device system 100 includes an exemplary sensing circuit system 130 and an exemplary encoder 132. Figure 1 In one example, the sensing circuitry 130 is configured to perform isolated current and voltage sensing to measure the phase current and phase voltage generated by the traction inverter 116. For example, the sensing circuitry 130 may include one or more current sensors, one or more voltage sensors, and / or combinations thereof. Figure 1 In this context, encoder 132 is a sensor configured to measure the speed of motor 118.

[0053] exist Figure 1 In the illustrated example, the high-voltage power electronics system 100 includes an exemplary controller 134 configured to perform and / or otherwise implement closed-loop control of the speed and torque of the motor 118. For example, the controller 134 may increase or decrease the switching speed of the power converter 114 to increase or decrease the voltage supplied to the motor 118 based on measurements from the sensing circuitry 130 and / or the encoder 132. In other examples, the controller 134 may control the speed and / or torque of the motor 118 based on measurements from the sensing circuitry 130 and / or the encoder 132.

[0054] exist Figure 1 In the illustrated example, controller 134 can generate commands, instructions, etc., and transmit them to the exemplary battery charger controller 136 via exemplary industry protocol communication bus 138. Figure 1In one example, the battery charger controller 136 is configured to control the conversion of AC power from the main transmission network 108 to DC power based on at least one of a first measurement from the sensing circuitry 130 or a second measurement from the encoder 132. Figure 1 In this configuration, the industry protocol communication bus 138 is a CAN bus that facilitates communication of Controller Area Network (CAN) protocol packets. Alternatively, the controller 134 can control the battery charger controller 136 via any other communication protocol, such as the Serial Peripheral Interface (SPI) protocol, the Process Fieldbus (PROFIBUS) protocol, the Modbus protocol, etc.

[0055] Figure 2 It includes the first instance gate driver stage 202 Figure 1 A schematic illustration of an embodiment of the first exemplary gate driver integrated device 102A. Although Figure 2 The schematic diagram illustrates a single gate driver integrated device 102A, but Figure 2 The schematic illustrations illustrate several examples that can be used to implement multiple gate driver integrated devices, such as Figure 1 The gate driver integrated devices 102A to F. For example, combined with Figure 2 The instructions provided are applicable to Figure 1 One or more of the second to sixth gate driver integrated devices 102B to F.

[0056] exist Figure 2 In the illustrated example, the first gate driver integrated device 102A is an isolated single-channel gate driver integrated circuit comprising a first exemplary die 204 and a second exemplary die 206, wherein the first die 204 is separated from the second die 206 via an exemplary isolation barrier 208. Alternatively, the first gate driver integrated device 102A may be implemented using one or more dies. Figure 2 In this example, the isolation barrier 208 is a silicon dioxide (SiO2) isolation barrier. Alternatively, the isolation barrier 208 can be any other type of isolation barrier. Figure 2 In this context, dies 204 and 206 are silicon dies. Alternatively, one or both dies 204 and 206 can be implemented using different types of dies (e.g., gallium arsenide (GaAs) dies).

[0057] exist Figure 2In the illustrated example, the first gate driver stage 202 is implemented on the second die 206. Alternatively, the first gate driver stage 202 may be implemented on the first die 204. Alternatively, a first portion of the first gate driver stage 202 may be implemented on the first die 204 and a second portion of the first gate driver stage 202 may be implemented on the second die 206. Alternatively, in other embodiments, the first gate driver stage 202 may be implemented on multiple dies and / or multiple integrated circuits and / or... Figure 1 Any of the components shown in the first gate driver integrated device 102A.

[0058] exist Figure 2 In the illustrated example, the first die 204 of the first gate driver integrated device 102A includes a first instance logic circuit system 210. The first instance logic circuit system 210 includes one or more logic circuits to implement pulse width modulation (PWM) input (e.g., generating a PWM input), error status feedback, power supply monitoring, clock monitoring, reference (voltage) clock monitoring, shoot-through protection (STP), thermal cut-off (TSD), and built-in self-test (BIST) functions. For example, the first logic circuit system 210 may include a first logic circuit for receiving and propagating a PWM signal. In such an example, the first logic circuit system 210 may include a second logic circuit for monitoring the voltage of the power supply of the first gate driver integrated device 102A, a third logic circuit for monitoring the clock signal received by the first gate driver integrated device 102A, and so on.

[0059] exist Figure 2 In the illustrated example, the first die 204 of the first gate driver integrated device 102A includes an instance SPI logic 212, a first instance register set 214, a first instance digital core 216, and a first instance inter-die communication (COMM) circuit 218. Figure 2 In one example, the first gate driver integrated device 102A includes SPI logic 212 to perform reconfiguration, verification, monitoring, and diagnostics of the first gate driver integrated device 102A. For example, the SPI logic 212 receives and / or can be otherwise configured to receive commands to program the settings of the first gate driver integrated device 102A. Figure 2 In one example, the first gate driver integrated device 102A includes a first register set 214 for storing data. For example, the first register set 214 may correspond to non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), etc.).

[0060] exist Figure 2 In the illustrated example, the first gate driver integrated device 102A includes a first digital core 216 to provide and / or otherwise implement the power-on and power-off sequences of the various blocks or components depicted in the first die 204. The first digital core 216 may be configured to function as and / or otherwise act as a communication hub between one or more of the blocks, components, logic circuits, etc., depicted in the first die 204. For example, SPI logic 212 may be configured to interface with a first register set 214 via the first digital core 216. Figure 2 In the first gate driver integrated device 102A, a first die-to-die communication circuit 218 is included to transmit data to and / or receive data from the second die 206.

[0061] exist Figure 2 In the illustrated example, the second die 206 of the first gate driver integrated device 102A includes a second instanced register set 220, a second instanced digital core 222, an instanced multiplexer (MUX) 224, an instanced analog-to-digital converter (ADC) core 226, and second inter-die communication circuitry 228. Figure 2 In one example, the first gate driver integrated device 102A includes a second register group 220 for storing data. For example, the second register group 220 may correspond to non-volatile memory, volatile memory, etc.

[0062] exist Figure 2 In the illustrated example, the first gate driver integrated device 102A includes a second digital core 222 to execute power-on and power-off sequences of the various blocks, logic circuit systems, components, etc. depicted in the second die 206. The second digital core 222 is configured to function as, and / or otherwise perform, as a communication hub between one or more of the blocks, logic circuit systems, components, etc. depicted in the second die 206. For example, inter-die communication circuitry 228 may be configured to interface with a second register set 220 via the second digital core 222.

[0063] exist Figure 2 In the illustrated example, the first gate driver integrated device 102A includes a multiplexer 224 to switch one of several input lines to a single common output line by the application, generation, etc., of control signals. For example, the multiplexer 224 can be configured to switch with... Figure 2 One of several analog inputs associated with the first transistor 120A, such as the emitter current measurement of the first transistor 120A, the gate voltage measurement of the first transistor 120A, etc. In Figure 2In one example, the first gate driver integrated device 102A includes an ADC core 226 to convert one or more analog signals into one or more digital signals. For instance, the ADC core 226 may be configured to convert the emitter current, gate voltage, etc., of the first transistor 120A into digital representations (e.g., binary values, hexadecimal values, logic zero '0', logic one '1', etc.). Figure 2 In the first gate driver integrated device 102A, a second inter-die communication circuit 228 is included to transmit data to and / or receive data from the first die 204.

[0064] exist Figure 2 In the illustrated example, the second die 206 of the first gate driver integrated device 102A includes a second exemplary logic circuit system 230. This second exemplary logic circuit system 230 includes one or more logic circuits to implement power supply monitoring, clock monitoring, reference voltage monitoring, TSD, desaturation protection (DESAT), short circuit protection (SCP), overcurrent protection (OCP), overtemperature protection (OTP), VCE clamping, active short circuit (ASC) support, and BIST functions. For example, the second logic circuit system 230 may include one or more logic circuits for implementing OCP and SCP functions based on shunt resistor sensing. In other examples, the second logic circuit system 230 may include one or more logic circuits for implementing OTP functionality by sensing the junction temperature of the first transistor 120A, one or more logic circuits for monitoring the clock signal received by the first gate driver integrated device 102A, etc.

[0065] exist Figure 2 In the illustrated example, the second die 206 of the first gate driver integrated device 102A includes a first gate driver stage 202 to perform switching operations on the first transistor 120A. Figure 2 In one example, the first gate driver stage 202 is implemented on the second die 206. Alternatively, the first gate driver stage 202 may be implemented on the first die 204. Alternatively, the first gate driver stage 202 may be implemented on both the first die 204 and the second die 206. Alternatively, in other examples, the first gate driver stage 202 and / or any of the components shown in the first gate driver integrated device 102A may be implemented on multiple dies and / or multiple integrated circuits.

[0066] exist Figure 2In the illustrated example, the first gate driver integrated device 102A includes a first gate driver stage 202 to turn the first transistor 120A on or off. For example, the first gate driver stage 202 may include a first gate driver and a first gate driver transistor (e.g., a power transistor, an N-channel MOSFET, a P-channel MOSFET, etc.) and a second gate driver and a second gate driver transistor (e.g., a power transistor, an N-channel MOSFET, a P-channel MOSFET, etc.).

[0067] exist Figure 2 In the illustrated example, the first transistor 120A is configured to deliver current to a voltage output (VOUT) node (which can be coupled (e.g., configured to couple) to, for example... Figure 1 The arrangement of the load (of the motor 118). For example, the first transistor 120A may be coupled to... Figure 1 The inputs to the motor 118, sensing circuitry 130, and / or encoder 132. Alternatively, the first transistor 120A may be coupled to any other type of load, such as a battery (e.g., a lithium-ion battery).

[0068] In some instances, the first gate driver and the first gate driver transistor may be configured to pull up the gate voltage of the first transistor 120A. In some such instances, the first gate driver transistor may pull up the gate voltage such that the gate-to-source voltage (VGS) of the first transistor 120A is higher than the threshold voltage (VTH) of the first transistor 120A. For example, the first transistor 120A may be configured to turn on when the gate voltage is greater than VTH.

[0069] In some instances, the second gate driver and the second gate driver transistor may be configured to pull down the gate voltage of the first transistor 120A. In such instances, the second gate driver transistor may pull down the gate voltage such that the VGS of the first transistor 120A is lower than the VTH of the first transistor 120A. For example, the first transistor 120A may be configured to turn off when the gate voltage is less than VTH.

[0070] exist Figure 2In the illustrated example, the first gate driver stage 202 includes a first instance bootstrap circuit 232 configured to have a cutoff reference voltage based on the output of the first gate driver stage 202. In such examples, the first bootstrap circuit 232 may be configured to reduce and / or otherwise eliminate overcharging of the instance bootstrap capacitor (CBST) 234 associated with the first bootstrap circuit 232. In some such examples, the first bootstrap circuit 232 may be configured to reduce overcharging of the bootstrap capacitor 234 even when the output of the first gate driver stage 202 decreases below a zero voltage threshold (e.g., less than 0V).

[0071] In some instances, the first bootstrap circuit 232 is configured to increase the charging rate of the bootstrap capacitor 234 while improving the reliability, safety, and / or operational life of the first transistor 120A and / or more generally, the first gate driver integrated device 102A. For example, the first bootstrap circuit 232 may include a first current-limiting circuit that can be configured to increase the charging rate of the bootstrap capacitor 234. In some instances, the first bootstrap circuit 232 may include a second current-limiting circuit that can be configured to improve the reliability, safety, and / or operational life of the first transistor 120A and / or more generally, the first gate driver integrated device 102A. In such instances, the first bootstrap circuit 232 may be configured to charge the bootstrap capacitor 234 with a second amount of current less than a first amount generated by the first current-limiting circuit. In some such instances, the first bootstrap circuit 232 may charge the bootstrap capacitor 234 with the second amount of current while preventing the first transistor 120A from overheating to a level exceeding a heating threshold, which could lead to damage to the first transistor 120A.

[0072] Although Figure 2 Chinese illustrations explain implementation Figure 1 The first gate driver integrated device 102A is an example of such a method, but may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Figure 2 One or more of the components, processes, and / or devices illustrated in the diagrams. Furthermore, Figure 1The first gate driver stage 202, first die 204, second die 206, first logic circuit system 210, SPI logic 212, first register group 214, first digital core 216, first inter-die communication 218, second register group 220, second digital core 222, multiplexer 224, ADC core 226, second inter-die communication 228, second logic circuit system 230, first bootstrap circuit 232, and / or more generally, the first gate driver integrated device 102A may be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Therefore, for example, the first gate driver stage 202, the first die 204, the second die 206, the first logic circuit system 210, the SPI logic 212, the first register group 214, the first digital core 216, the first inter-die communication 218, the second register group 220, the second digital core 222, the multiplexer 224, the ADC core 226, the second inter-die communication 228, the second logic circuit system 230, the first bootstrap circuit 232, and / or more generally, any of the first gate driver integrated device 102A may be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or field-programmable logic devices (FPLDs). When reading any of the device or system claims of this patent covering purely software and / or firmware implementations, at least one of the following—first gate driver stage 202, first die 204, second die 206, first logic circuit system 210, SPI logic 212, first register group 214, first digital core 216, first inter-die communication 218, second register group 220, second digital core 222, multiplexer 224, ADC core 226, second inter-die communication 228, second logic circuit system 230, and / or first bootstrap circuit 232—is thereby expressly defined to include a non-transitory computer-readable storage device or storage disk, such as non-volatile memory (e.g., ROM, EEPROM, flash memory, etc.), volatile memory (e.g., SDRAM, DRAM, etc., and / or any other type of RAM device), including software and / or firmware. Furthermore, Figure 1 The first gate driver integrated device 102A of and / or 2 may include, except for or replace, Figure 2 The elements, processes and / or devices illustrated herein may include one or more of the elements, processes and / or devices illustrated herein, and / or may include one or more of any or all of the elements, processes and devices illustrated herein.

[0073] Figure 3 yes Figure 2A schematic illustration of the first exemplary gate driver stage 202 and the first exemplary bootstrap circuit 232. Figure 3 In the illustrated example, Figures 1 to 2 The first gate driver stage 202 and / or more generally the first gate driver integrated device 102A are coupled to via instance terminals 302, 304, 306, 308 comprising a first instance terminal (VBST) 302, a second instance terminal (OUTH) 304, a third instance terminal (OUTL) 306, and a fourth instance terminal (GND) 308. Figures 1 to 2 The first transistor 120A. For example, the first terminal 302 may be a bootstrap pin configured to bootstrap a voltage associated with the second terminal 304. The second terminal 304 may be a pull-up driver output pin configured to pull up the gate voltage of the first transistor 120A to turn on the first transistor 120A. The third terminal 306 may be a pull-down driver output pin configured to pull down the gate voltage of the first transistor 120A to turn off the first transistor 120A. The fourth terminal 308 may be a pull-down driver or a power return pin of the first transistor 120A (e.g., the source terminal of the first transistor 120A). For example, the fourth terminal 308 may be configured to deliver and / or otherwise provide a reference voltage rail, a ground voltage rail, etc., to the first transistor 120A.

[0074] exist Figure 3 In the illustrated examples, terminals 302, 304, 306, and 308 may be constructed of aluminum, copper, or any other conductive material or combinations thereof, and / or otherwise. Figure 3 In this example, terminals 302, 304, 306, and 308 are pins (e.g., IC pins). Alternatively, terminals 302, 304, 306, and 308 may be legs (e.g., conductive legs), lugs (e.g., conductive lugs), or any other type of electrical contact.

[0075] exist Figure 3 In the illustrated example, the first terminal 302 is coupled (e.g., configured to couple) to the first instance node 310. Figure 3 In this instance, the second terminal 304 is coupled (e.g., configured to couple) to the second instance node 312. Figure 3 In this configuration, the third terminal 306 is coupled (e.g., configured to couple) to the third instance node 314. Figure 3 In the middle, the fourth terminal 308 is coupled to the fourth instance node 316.

[0076] exist Figure 3In the illustrated example, bootstrap capacitor 234 is coupled to first node 310 and second node 312. For example, first gate driver stage 202 and / or more generally, first gate driver integrated device 102A may be configured to be coupled to bootstrap capacitor 234 via first node 310 and second node 312. Figure 3 In one example, the first capacitor terminal of the bootstrap capacitor 234 is coupled to the first node 310 and the second capacitor terminal of the bootstrap capacitor 234 is coupled to the second node 312.

[0077] exist Figure 3 In the illustrated example, a first resistor terminal of the first exemplary resistor 318 is coupled to a second node 312, and a second resistor terminal of the first resistor 318 is coupled to a fifth exemplary node 320. For example, a first gate driver stage 202 and / or more generally a first gate driver integrated device 102A may be configured to be coupled to the first resistor 318 via the fifth node 320.

[0078] exist Figure 3 In the illustrated example, the first transistor 120A has an exemplary gate terminal 322, a first exemplary current terminal 324, and a second exemplary current terminal 326. Figure 3 In the example, the first current terminal 324 is the collector current terminal and the second current terminal 326 is the emitter current terminal.

[0079] exist Figure 3 In the illustrated example, gate terminal 322 is coupled (e.g., configured to be coupled) to fifth node 320. Figure 3 In this example, the first current terminal 324 is coupled (e.g., configured to couple) to the sixth instance node 328. Figure 3 In the middle, the sixth node 328 is coupleable (e.g., configured to be coupled) to Figure 1 The output voltage of the power converter 114 is at the input (VIN) node. Figure 3 In one example, the second current terminal 326 is coupled (e.g., configured to couple) to the seventh instance node 330, which may be coupled to the fourth node 316. Figure 3 In the example, the fourth node 316 and the seventh node 330 are coupleable (e.g., configured to be coupled) to Figure 1 The voltage output (VOUT) node is the input to the motor 118, sensing circuit system 130, and / or encoder 132. Alternatively, the fourth node 316 may be combined with the seventh node 330.

[0080] exist Figure 3In the illustrated example, the second exemplary resistor 332 is coupled to the third node 314 and the fifth node 320. For example, the first gate driver stage 202 and / or more generally, the first gate driver integrated device 102A can be configured to be coupled to the second resistor 332 via the third node 314. Figure 3 In this example, the third resistor terminal of the second resistor 332 is coupled to the third node 314, and the fourth resistor terminal of the second resistor 332 is coupled to the fifth node 320. Figure 3 In one example, the fourth terminal 308 is coupled (e.g., configured to couple) to the fourth node 316.

[0081] exist Figure 3 In the illustrated examples, one or more of nodes 310, 312, 314, 316, 320, 328, and 330 may be constructed and / or otherwise formed from aluminum, copper, or any other conductive material or combination thereof. For example, one or more of nodes 310, 312, 314, 316, 320, 328, and 330 may be conductive printed circuit board (PCB) pads, vias (e.g., conductive vias), or any other type of electrical contact or interconnect or combination thereof.

[0082] exist Figure 3 In the illustrated example, the first transistor 120A, bootstrap capacitor 234, first resistor 318, and second resistor 332 are coupled to the first gate driver stage 202 and / or more generally, the first gate driver integrated device 102A. Alternatively, one or more of the first transistor 120A, bootstrap capacitor 234, first resistor 318, and second resistor 332 may not be coupled to the first gate driver stage 202 and / or more generally, the first gate driver integrated device 102A. For example, after the first gate driver stage 202 and / or the first gate integrated device 102 has been assembled and / or otherwise manufactured, one or more of the first transistor 120A, bootstrap capacitor 234, first resistor 318, and second resistor 332 may be coupled to the first gate driver stage 202 and / or more generally, the first gate driver integrated device 102A. In such instances, one or more of the first transistor 120A, bootstrap capacitor 234, first resistor 318, and / or second resistor 332 may be distributed and / or sold separately from the first gate driver stage 202 and / or more generally the first gate driver integrated device 102A.

[0083] exist Figure 3 In the illustrated example, the first gate driver stage 202 includes a first exemplary gate driver 334, a second exemplary gate driver 336, a first exemplary gate driver transistor 338, and a second exemplary gate driver transistor 340. Figure 3 In one example, the first gate driver 334 is a buffer stage having a first voltage input 334A, a first control input 334B, a first control output 334C, and a first reference voltage input 334D. For instance, the first gate driver 334 may be more sensitive than the input from a controller (e.g., Figure 1 The controller 134) outputs a high current intensity to drive the first gate terminal 338G. Figure 3 In one example, the second gate driver 336 is a buffer stage having a second control input 336A, a second control output 336B, and a second reference voltage input 336C. ​​For instance, the second gate driver 336 may be more efficient than the input from a controller (e.g., ...). Figure 1 The controller 134) outputs a high current intensity to drive the second gate terminal 340G. Alternatively, one or both of the gate drivers 334 and 336 can be a power amplifier. Figure 3 In this configuration, the first control input 334B and the second control input 336A are coupled (e.g., configured to be coupled) to the output of the controller, for example... Figure 1 The output of controller 134.

[0084] exist Figure 3 In the illustrated example, the first gate driver transistor 338 and the second gate driver transistor 340 are N-channel MOSFETs. Alternatively, a P-channel MOSFET may be used instead of one or more of the gate driver transistors 338 and 340 to implement the first gate driver stage 202. Figure 3 In one example, the first gate driver transistor 338 has a first gate terminal 338G, a first current terminal 338D, and a second current terminal 338S. Figure 3 In one example, the second gate driver transistor 340 has a second gate terminal 340G, a third current terminal 340D, and a fourth current terminal 340S. Figure 3 In this configuration, the first current terminal 338D and the third current terminal 340D are drain terminals (e.g., drain current terminals). Figure 3 In this configuration, the second current terminal 338S and the fourth current terminal 340S are source terminals (e.g., source current terminals).

[0085] exist Figure 3 In the illustrated example, the first bootstrap circuit 232 has an exemplary enable input 342, a voltage input (e.g., VCC input) 344, a bootstrap output 346, and a bootstrap reference voltage input 348. Figure 3In some instances, voltage input 344 can supply a voltage greater than 0V to the positive power rail, voltage rail, etc., of bootstrap circuit 232. In some instances, in response to the rising edge of an instance enable signal 350 supplied to enable input 342, first bootstrap circuit 232 can be triggered and / or otherwise invoked to perform bootstrap functions, such as charging bootstrap capacitor 234 via bootstrap output 346.

[0086] exist Figure 3 In the illustrated example, voltage input 344 and first current terminal 338D are coupled and / or otherwise configured to have a voltage of VCC. Figure 3 In this example, the bootstrap output 346 is coupled to the first voltage input 334A, the first terminal 302, and the bootstrap capacitor 234 via the first terminal 302. Figure 3 In this configuration, the first control output 334C is coupled to the first gate terminal 338G, and the second control output 336B is coupled to the second gate terminal 340G. Figure 3 In the process, the bootstrap reference voltage input 348 is coupled to the first reference voltage input 334D, the second current terminal 338S, and the second terminal 304, and is coupled to the bootstrap capacitor 234 via the second terminal 304 and the first resistor 318 via the second terminal 304.

[0087] exist Figure 3 In the illustrated example, the third current terminal 340D is coupled to the third terminal 306, coupled via the third terminal 306 to the second resistor 332, and coupled via the third terminal 306 and the second resistor 332 to the gate terminal 322 of the first transistor 120A. Alternatively, the third current terminal 340D may be coupled to the gate terminal 322 of the first transistor 120A without the second resistor 332. Figure 3 In one example, the fourth current terminal 340S is coupled to the second reference voltage input 336C, the fourth terminal 308, and the second current terminal 326 via at least one of the fourth node 316 or the seventh node 330.

[0088] In exemplary operation, the first bootstrap circuit 232 charges the bootstrap capacitor 234. In response to charging the bootstrap capacitor 234, the voltage at the first voltage input 334A can be increased. Advantageously, by increasing the voltage at the first voltage input 334A, the first gate driver 334 can generate a control signal at the first control output 334C to maintain the first gate driver transistor 338 in an ON, ON, or OFF state, wherein the first gate driver transistor 338 conducts current generated by VCC. In exemplary operation, the first bootstrap circuit 232 can implement the first gate driver 334 to generate a sufficient voltage output at the first control output 334C to ensure that the first gate driver transistor 338 remains ON.

[0089] Advantageously, the first bootstrap circuit 232 is coupled to the HS output (OUTH) of the first gate driver stage 202 to address a short negative pulse generated by the first gate driver 334. OUTH may correspond to the output voltage of the first gate driver stage 202 (e.g., the HS output voltage). In some instances, the short negative pulse may cause OUTH to downsurge below power ground (e.g., below a zero voltage threshold) before the first gate driver 334 invokes the first transistor 120A to return to a high state, an on state, an enabled state, etc. Advantageously, by coupling the first bootstrap circuit 232 to OUTH instead of the low-side (LS) output (OUTL), the first gate driver stage 202 can reduce and / or otherwise eliminate the charging of the bootstrap capacitor 234.

[0090] Figure 4 yes Figures 2 to 3 A schematic illustration of the first example bootstrap circuit 232. Figure 4 In the illustrated example, the first bootstrap circuit 232 includes an exemplary level shifter 402, an exemplary reference voltage circuit 404, an exemplary voltage regulation loop 406, an exemplary control stage circuit 408, a first exemplary transistor (MAIN) 410, a second exemplary transistor (SENSE) 412, a first exemplary diode 414, a second exemplary diode 416, a first exemplary current limiting circuit 418, and a second exemplary current limiting circuit 420. Furthermore, Figure 4 Examples also depict Figure 3 The first terminal 302, the second terminal 304, and the enable signal 350.

[0091] exist Figure 4In the illustrated example, level shifter 402 is a buffer that can be configured to translate between two different voltage domains (e.g., from a first voltage to a second voltage). For example, level shifter 402 can translate a first signal (e.g., enable signal 350) into a second signal (e.g., the output of level shifter 402). In such examples, the first signal may be and / or correspond to a ground-referenced enable signal (e.g., a signal with voltage referenced to ground). In some such examples, the second signal may be and / or correspond to a signal referenced to a first voltage at first terminal 302 or a second voltage at second terminal 304.

[0092] exist Figure 4 In one example, the reference voltage circuit 404 includes one or more diodes arranged in series. For instance, the reference voltage circuit 404 may include a diode series-coupled to a Zener diode. Figure 4 In one example, the voltage regulation loop 406 includes a first instance comparator 422. Figure 4 In this configuration, the first comparator 422 is a Schmitt trigger. Alternatively, the first comparator 422 can be any other type of comparator.

[0093] exist Figure 4 In the illustrated example, the first transistor 410 and the second transistor 412 are N-channel FETs. For example, the first transistor 410 and the second transistor 412 could be N-channel MOSFETs (e.g., silicon N-channel MOSFETs, SiC N-channel MOSFETs, etc.). Alternatively, a P-channel FET could be used as one or both of transistors 410 and 412 to implement the first bootstrap circuit 232. Figure 4 In one example, the first transistor 410 has a first exemplary gate terminal 410G, a first exemplary current terminal 410D, and a second exemplary current terminal 410S. Figure 4 In one example, the second transistor 412 has a second exemplary gate terminal 412G, a third exemplary current terminal 412D, and a fourth exemplary current terminal 412S. Figure 4 In this configuration, the first current terminal 410D and the third current terminal 412D are drain terminals (e.g., drain current terminals). Figure 4 In this configuration, the second current terminal 410S and the fourth current terminal 412S are source terminals (e.g., source current terminals).

[0094] exist Figure 4In the illustrated example, the first transistor 410 has a first size and the second transistor 412 has a second size, wherein the ratio of the first size to the second size is X:1 (e.g., 30:1, 40:1, etc.). Alternatively, the ratio can be any other value. For example, the sizes of transistors 410 and 412 can be based on gate oxide thickness, conduction parameters, channel width, channel width to length (W / L) ratio, etc., which corresponds to the pull-down strength of transistors 410 and 412. In such examples, the first size of the first transistor 410 can correspond to the first transistor 410 having a first conduction parameter, a first W / L ratio, etc., which is X times larger than the second conduction parameter, second W / L ratio, etc., of the second transistor 412. Advantageously, the resistor 424, the second diode 416, and / or the second transistor 412 can be coupled to reduce the... Figure 4 The power dissipation and current consumption configuration of the bootstrap circuit 232 illustrated in the example are shown.

[0095] exist Figure 4 In the illustrated example, the first current-limiting circuit 418 is configured to deliver a first amount of first current in response to the activation of the first bootstrap circuit 232. Figure 4 In one example, the second current-limiting circuit 420 is configured to deliver a second current of a second quantity in response to a time delay (e.g., a predetermined time delay, a predefined time delay, etc.). In such examples, the first quantity may be greater than the second quantity. For example, the first quantity may be 200mA, 300mA, etc., and the second quantity may be 30mA, 40mA, etc. In some examples, the time delay may be 2 microseconds, 2.4 microseconds, 2.8 microseconds, etc.

[0096] exist Figure 4 In the illustrated example, the input of level shifter 402 (e.g., level shifter input) is configured to obtain Figure 3 The activation signal is 350. In Figure 4 In this example, the output of level shifter 402 (e.g., level shifter output) is coupled to a first input of control stage circuitry 408 (e.g., control input, control stage input, control stage circuit input, etc.). Figure 4 In this configuration, the reference input of the control-level circuit 408 (e.g., control reference input, control-level reference input, control-level reference circuit input, etc.) is coupled to the second terminal 304. Figure 4 In this process, the output of the control stage circuit 408 (e.g., control output, control stage output, control stage circuit output, etc.) is coupled to the first gate terminal 410G and the second gate terminal 412G (e.g., coupled to the node coupled to the output and gate terminals 410G, 412G).

[0097] exist Figure 4 In this example, transistors 410 and 412 are configured as source followers (e.g., common-drain amplifiers). For instance, transistors 410 and 412 are coupled to bootstrap circuit 232 in a source follower configuration (e.g., first transistor 410 is configured as a source follower, second transistor 412 is configured as a source follower, etc.). Figure 4 In this configuration, gate terminals 410G and 412G are used as inputs (e.g., source follower inputs), source terminals 410S and 412S are used as outputs (e.g., source follower outputs), and drain terminals 410D and 412D are common to the corresponding inputs and outputs. Figure 4 In this circuit, the control stage circuit 408 can control the input of the source follower (e.g., the control gate terminals 410G and 412G of transistors 410 and 412) to adjust the output of the source follower.

[0098] In other examples, transistors 410 and 412 may be bipolar junction transistors (BJTs) configured as emitter followers (e.g., common-emitter amplifiers) (e.g., NPN BJTs, PNP BJTs, etc.). For example, transistors 410 and 412 may be BJTs coupled to bootstrap circuit 232 in an emitter follower configuration (e.g., when the first transistor 410 is a BJT, the second transistor 412 is an emitter follower configuration, etc.). In such examples, the gate terminal of the BJT may be used as an input (e.g., an emitter follower input), the emitter terminal of the BJT may be used as an output (e.g., an emitter follower output), and the collector terminal of the BJT may be common to the respective input and output.

[0099] In some instances, the control stage circuitry 408 is and / or otherwise implements a buffer stage that increases or decreases the voltage at gate terminals 410G and 412G with respect to OUTH. In such instances, the control stage circuitry 408 can cause the source voltages of transistors 410 and 412 to vary with the gate voltage, such that the voltage difference is always greater than VTH of transistors 410 and 412.

[0100] exist Figure 4In an example, the control stage circuit 408 can (1) charge the node while the gate terminals 410G and 412G of transistors 410 and 412 are coupled, increasing the voltage reference at the node to OTH, or (2) discharge the node, decreasing the voltage reference at the node to OTH to approximately 0V. Therefore, the charging voltage between the first gate terminal 410G and OTH and / or between the second gate terminal 412G and OTH is related to and / or based on negative feedback from the voltage regulation loop 406, the first current limiting circuit 418, and the second current limiting circuit 420. For example, the bootstrap circuit 232 includes the control stage circuit 408 to obtain feedback (e.g., negative feedback, feedback signal, etc.) from at least one of the first current limiting circuit 418, the second current limiting circuit 420, or the voltage regulation loop 406. In such instances, the feedback can be voltage (e.g., voltage from at least one of the first current limiting circuit 418 or the second current limiting circuit 420), current generated by resistor 424, voltage across resistor 424, voltage difference between VBST and OUTH, and / or combinations thereof.

[0101] In some instances, the control stage circuit 408 may be a buffer stage or a common-drain amplifier configured to turn one or both of transistors 410, 412 on or off. For example, the control stage circuit 408 and one or both of transistors 410, 412 may be coupled in a current mirror configuration (e.g., a current-controlled current source configuration) to deliver current to the bootstrap capacitor 234.

[0102] exist Figure 4 In the illustrated example, the second terminal 304 is coupled to the input of the reference voltage circuit 404 (e.g., negative terminal, negative input terminal, reference voltage circuit input, reference voltage circuit terminal, etc.). Figure 4 In this circuit, the output of the reference voltage circuit 404 (e.g., the reference voltage circuit output) is coupled to the second input of the first comparator 422 (e.g., the second comparator input, negative terminal, negative input, negative input terminal, etc.) (denoted by the '-' symbol). Figure 4 In this configuration, the first input of the first comparator 422 (e.g., first comparator input, positive terminal, positive input, positive input terminal, etc.) (denoted by the '+' symbol) is coupled to the second current terminal 410S, the fourth current terminal 412S, and the first terminal 302. Figure 4 In this example, the first input of the control stage circuit 408 is a non-inverting input and the second input of the control stage circuit 408 is an inverting input (e.g., changing logic '0' to logic '1', changing logic '1' to logic '0', etc.).

[0103] exist Figure 4In the illustrated example, the input of the first current-limiting circuit 418 (e.g., the current-limiting circuit input) is coupled to a first terminal of the exemplary resistor 424 (e.g., the first resistor terminal), the input of the second current-limiting circuit 420 (e.g., the current-limiting circuit input), and the anode of the second diode 416. Figure 4 In this example, the second terminal of resistor 424 (e.g., the second resistor terminal) is coupled (e.g., configured to couple) to VCC (e.g., the VCC input). Figure 4 In this circuit, the output of the first current limiting circuit 418 (e.g., the current limiting circuit output) is coupled to the output of the second current limiting circuit 420, the first output of the first comparator 422 (e.g., the first comparator output), and the second input of the control stage circuit 408 (e.g., the second control stage circuit input). Figure 4 In this configuration, the anode of the first diode 414 is coupled to VCC (e.g., VCC input), and the cathode of the first diode 414 is coupled to the first current terminal 410D. Figure 4 In the middle, the cathode of the second diode 416 is coupled to the third current terminal 412D. Figure 4 In this circuit, the bootstrap circuit 232 includes a first diode 414 and a second diode 416 to rectify the direction of the current in instances where VBST is greater than VCC.

[0104] exist Figure 4 In the illustrated example, the first transistor 410 is the main transistor, and the second transistor 412 is the sensing transistor. The sensing transistor generates a smaller current than the main transistor. Advantageously, the smaller current generated by the sensing transistor allows for the use of a smaller resistor 424, which reduces the die area required for the bootstrap circuit 232 and the current consumed by the bootstrap circuit 232.

[0105] exist Figure 4 In the illustrated example, the current flowing through the second transistor 412 (e.g., a smaller current than that flowing through the first transistor 410) also passes through resistor 424. Figure 4In this configuration, a first current-limiting circuit 418 and a second current-limiting circuit 420 are coupled to resistor 424 and second transistor 412, respectively, to measure the voltage across resistor 424. For example, the first current-limiting circuit 418 may be a P-type transistor that generates current based on the voltage across the source and gate terminals of the P-type transistor. In such examples, the second current-limiting circuit 420 may be an analog amplifier that compares the voltage across resistor 424 with an internal reference. In some such examples, bootstrap circuit 232 is configured to charge bootstrap capacitor 234 using negative feedback control. For example, bootstrap circuit 232 may use negative feedback control by causing the P-type transistor to generate current based on the voltage across the source and gate terminals of the P-type transistor. The generated current allows control stage circuit 408 to regulate the combined current generated by the first transistor 410 and second transistor 412 to a first amount of current. After a predetermined time period, the analog amplifier generates an amplified signal, causing the control stage circuit 408 to adjust the combined current generated by the first transistor 410 and the second transistor 412 to a second current that is smaller than the first current.

[0106] In an exemplary operation, a first voltage at the first terminal 302 is greater than a second voltage at the second terminal 304. The first comparator 422 confirms a logic signal (e.g., a logic high signal) destined for the second input of the control stage circuitry 408. In an exemplary operation, the level shifter 402 is configured to level-shift an enable signal 350 to control the operation of the control stage circuitry 408. For example, in response to confirming the enable signal 350, the level shifter 402 can confirm a level-shifted logic signal (e.g., a logic high signal corresponding to the digit '1' generated by current and / or voltage) destined for the first input of the control stage circuitry 408 to trigger the control stage circuitry 408 to turn on the first transistor 410 and the second transistor 412. In such an example, the level shifter 402 can turn on a current mirror circuit, which includes at least one of the control stage circuitry 408, the first transistor 410, or the second transistor 412. In some such instances, the level shifter 402 can turn on the current mirror by turning on the transistors included in the control stage circuit 408, which in turn turn on the first transistor 410 and the second transistor 412.

[0107] In an exemplary operation, a validated logic signal from the first comparator 422 and a validated logic signal from the first current-limiting circuit 418 can trigger the control stage circuit 408 to turn on the first transistor 410 and the second transistor 412. For example, the first transistor 410 and the second transistor 412 can conduct a first amount of current from VCC (e.g., 200mA, 250mA, etc.). In such an example, the first transistor 410 and the second transistor 412 can use the first amount of current to charge the bootstrap capacitor 234.

[0108] In exemplary operation, after a predetermined or predefined time period (e.g., 2.0 μs, 2.4 μs, etc.), time constant, etc., the first current limiting circuit 418 is turned off. In response to turning off the first current limiting circuit 418, the second current limiting circuit 420 is turned on. In response to turning on the second current limiting circuit 420, the second current limiting circuit 420 triggers the control stage circuit 408 to conduct a second current (e.g., 30 mA, 40 mA, etc.) smaller than the first current in the first transistor 410 and the second transistor 412. In such examples, the first transistor 410 and the second transistor 412 can use the second current to charge the bootstrap capacitor 234. In some such examples, the second current limiting circuit 420 is configured to deliver and / or supply (e.g., continuously, incessantly, etc.) the second current to the first terminal 302 to charge the bootstrap capacitor 234. Advantageously, the output (e.g., analog output) from the second current limiting circuit 420 can control the discharge current of transistors 410 and 412, such that the first VGS of the first transistor 410 and the second VGS of the second transistor 412 are negatively fed back to generate a second amount of current.

[0109] Advantageously, the second current-limiting circuit 420 can be configured to supply a second amount of current (e.g., continuously, incessantly, etc.) to the bootstrap capacitor 234 without heating it to a heat threshold that could damage the bootstrap capacitor 234. In exemplary operation, in response to the voltage at the second terminal 304 meeting a voltage threshold (e.g., the voltage at the first terminal 302), the voltage regulation loop 406 shuts off and / or disables the control stage circuit 408. Advantageously, the voltage regulation loop 406 can shut down the control stage circuit 408 in response to the voltage at the second terminal 304 meeting a voltage threshold to reduce current consumption.

[0110] Figure 5 yes Figure 4 A schematic illustration of an implementation scheme for an example control stage circuit 408, a first current limiting circuit 418, and a second current limiting circuit 420. Figure 5 In one example, the control stage circuit 408 includes an instance current source 502 and a third instance transistor 504.

[0111] exist Figure 5 In the examples, Figure 4 The level shifter 402 enables or disables the current source 502. Figure 5In this embodiment, current source 502 has a control input (e.g., a current source control input), a current source input, and a current source output. For example, the output of level shifter 402 can be transmitted to the control input to enable dual-state switching of current source 502 between on and off. In such an example, in response to turning on current source 502, current flows from VCC through the control source output to the control source input and the third transistor 504.

[0112] exist Figure 5 In the illustrated example, current source 502 is a current mirror (e.g., a P-type current mirror). For example, the output of level shifter 402 can turn on the current mirror to allow current to flow from VCC, or turn off the current mirror to prevent current from flowing from VCC. Alternatively, current source 502 can be a resistor (e.g., a variable resistor). For example, the output of level shifter 402 can be bi-state switched and / or otherwise adjust the resistance of the resistor to generate a voltage across the resistor to limit the current from VCC.

[0113] exist Figure 5 In the illustrated example, the third transistor 504 has a third gate terminal 504G, a fifth exemplary current terminal 504D, and a sixth exemplary current terminal 504S. Figure 5 In this example, the fifth current terminal 504D is the drain terminal (e.g., the drain current terminal), and the sixth current terminal 504S is the source terminal (e.g., the source current terminal). Figure 5 In this implementation, the third transistor 504 is an N-channel transistor (e.g., an N-channel MOSFET, a SiC N-channel MOSFET, a Si N-channel MOSFET, etc.). Alternatively, a P-channel FET or a PNP BJT can be used instead of the third transistor 504. Figure 5 The control stage circuit 408. In some embodiments, by increasing the voltage at the third gate terminal 504G, the third transistor 504 increases the voltage at gate terminals 410G and 412G, which in turn increases the current flowing through transistors 410 and 412. In other embodiments, by decreasing the voltage at the third gate terminal 504G, the third transistor 504 decreases the voltage at gate terminals 410G and 412G, which in turn decreases the current flowing through transistors 410 and 412.

[0114] exist Figure 5 In the illustrated example, the first current limiting circuit 418 includes a fourth exemplary transistor 506, which has a fourth gate terminal 506G, a seventh exemplary current terminal 506D, and an eighth exemplary current terminal 506S. Figure 5In this example, the seventh current terminal 506D is the drain terminal (e.g., the drain current terminal), and the eighth current terminal 506S is the source terminal (e.g., the source current terminal). Figure 5 In this embodiment, the fourth transistor 506 is a P-channel transistor (e.g., a P-channel MOSFET, a SiC P-channel MOSFET, a Si P-channel MOSFET, etc.). Alternatively, an N-channel transistor can be used as the fourth transistor 506. Figure 5 The first current limiting circuit 418.

[0115] exist Figure 5 In the illustrated example, the second current-limiting circuit 420 includes an exemplary voltage source 508, an exemplary amplifier 510, a second exemplary resistor 512, and a second exemplary capacitor 514. Figure 5 In this example, voltage source 508 is an internal reference voltage (e.g., an internal reference voltage source). Voltage source 508 has a first voltage source terminal (marked with a '+' sign) and a second voltage source terminal (marked with a '-' sign). For example, voltage source 508 may be configured to have voltage drops of 0.5V, 1.0V, 1.5V, etc., across the first voltage source terminal and the second voltage source terminal.

[0116] exist Figure 5 In this example, amplifier 510 has a first amplifier input (marked with a '+' sign), a second amplifier input (marked with a '-' sign), and an amplifier output. Figure 5 In this configuration, amplifier 510 is an analog amplifier configured to produce an output of any level of analog signal (e.g., amplified output, analog output, voltage, etc.) between the first amplifier input and the second amplifier input. For example, the voltage at the second amplifier input may correspond to and / or be based on a first voltage at the first terminal 302, a second voltage across resistor 424, etc.

[0117] exist Figure 5 In the illustrated example, the amplifier output is coupled to a second resistor 512, which is coupled to a second capacitor 514, which in turn is coupled to VCC. Figure 5 In this configuration, the second resistor 512 and the second capacitor 514 can be coupled to implement a configuration of a buffer with a substantially large internal RC constant, wherein the first stage of the buffer takes a relatively long time to transition from high to low or from low to high, and the second stage of the buffer generates a second output based on the first output from the first stage.

[0118] exist Figure 5 In the illustrated example, the current source input is coupled to VCC, the anode of the first diode 414, the first terminal of the resistor 424, the eighth current terminal 506S, and the first voltage source terminal. Figure 5 In this example, the current source output is coupled to the first gate terminal 410G, the second gate terminal 412G, and the fifth current terminal 504D. Figure 5 In the middle, the control input is coupled to Figure 4 The output of the level shifter 402.

[0119] exist Figure 5 In the illustrated example, the third gate terminal 504G is coupled to the seventh current terminal 506D, the first comparator output, and the second comparator output. Figure 5 In this example, the sixth current terminal 504S is coupled to the second terminal 304. Figure 5 In the illustrated example, the fourth gate terminal 506G is coupled to the second terminal of resistor 424, the anode of the second diode 416, and the input of the second amplifier. Figure 5 In this example, the second voltage source terminal is coupled to the input of the first amplifier.

[0120] In a typical operation, in response to the confirmation enable signal 350, the level shifter 402 can confirm the level-shifted logic signal (e.g., a level-shifted logic high signal) to the control input of the current source 502 to turn on the current mirror including the first transistor 410, the second transistor 412, and the third transistor 504.

[0121] In an exemplary operation, a first voltage at the first terminal 302 is greater than a second voltage at the second terminal 304. The first comparator 422 may confirm a logic signal (e.g., a logic high signal) destined for the third gate terminal 504G in response to the first voltage at the first comparator input being greater than the second voltage at the second comparator input.

[0122] In an exemplary operation, the fourth transistor 506 is turned on to confirm a logic signal (e.g., a logic high signal) leading to the third gate terminal 504G in response to the generation of VCC. For example, the fourth transistor 506 may be turned on (e.g., immediately turned on) in response to the generation of VCC because the source-gate voltage (VSG) of the fourth transistor 506 is greater than the threshold voltage (VTH) of the fourth transistor 506. The fourth transistor 506 can be turned on in response to the VSG of the fourth transistor 506 being greater than VTH.

[0123] In exemplary operation, in response to a validated logic signal from the first comparator 422 and a validated logic signal from the fourth transistor 506, the third transistor 504 is turned on to conduct a reference current from the current source 502. In response to the third transistor 504 conducting the reference current, the first transistor 410 and the second transistor 412 can conduct a first amount of current from VCC (e.g., 200mA, 250mA, etc.). Figure 5In one example, the first transistor 410 and the second transistor 412 can charge the bootstrap capacitor 234 using a first amount of current.

[0124] In exemplary operation, amplifier 510 generates an amplified analog signal of any level between the first amplifier input and the second amplifier input. Because the real-time negative feedback strength from the seventh current terminal 506D suppresses the gate voltages at the first gate terminal 410G and the second gate terminal 412G, the current from the seventh current terminal 506D limits the currents at the first current terminal 410D and the third current terminal 412D. This exemplary negative feedback operation can maintain the current from the second current terminal 410S and the fourth current terminal 412S at a first-level current.

[0125] During a predetermined time period (e.g., 2.0 μs, 2.4 μs, etc.), if a strong analog signal from the amplifier output appears at the third gate terminal 504G, the current from the first current terminal 410D and the third current terminal 412D decreases from a first amount to a second amount (e.g., 30 mA, 45 mA, etc.). Therefore, the decrease in current from the first amount to the second amount affects the voltage across resistor 424, making the voltage sufficiently small to be less than VTH of the fourth transistor 506. In response to generating a voltage across resistor 424 less than VTH of the fourth transistor 506, the fourth transistor 506 is turned off.

[0126] Figure 6 Is with Figure 2 , 3 The instance timing diagram 600 corresponds to the instance operation of the first instance bootstrap circuit 232 of 4 and / or 5. Figure 6 In the timing diagram 600 of the instance, instance waveforms 602, 604, and 606 are depicted with respect to time. Waveforms 602, 604, and 606 include the first instance waveform 602, the second instance waveform 604, and the third instance waveform 606.

[0127] exist Figure 6 In the illustrated example, the first waveform 602 corresponds to the bootstrap current (IBST) in amperes (A). For example, IBST could correspond to the current flowing to... Figures 2 to 5 The current in the bootstrap capacitor 234. Figure 6 In this example, the second waveform 604 corresponds to the voltage difference in volts (V) between the bootstrap voltage (VBST) and the HS output (OUTH). For instance, the voltage difference could correspond to... Figures 3 to 5 The first voltage at the first terminal 302 and Figures 3 to 5 The difference between the second voltage at the second terminal 304. Figure 6In this example, the third waveform 606 can correspond to the HS output (OUTH) in volts (V). For instance, OTH can correspond to... Figures 3 to 5 The second voltage at the second terminal 304.

[0128] exist Figure 6 In the instance timing diagram 600, at the first instance time (T1) 608, OTH transitions from a first instance voltage 610 to a second instance voltage 612, where the first voltage 610 is greater than the second voltage 612. The first voltage 610 may correspond to a validated logic signal (e.g., a logic high signal). The second voltage 612 may correspond to an unvalidated logic signal (e.g., a logic low signal). For example, Figure 3 The first gate driver 334 can be turned off Figure 3 The first gate driver transistor 338 is used in Figure 3 A second voltage 612 is generated at the second terminal 304.

[0129] At the first moment, at point 608, a response was made. Figures 3 to 5 The enable signal 350 is confirmed and OUTH is less than VCC. The level shifter 402 confirms the level-shifted enable signal of the enable signal 350 to the control stage circuit 408, and the first comparator 422 confirms that the logic signal to the control stage circuit 408 is turned on. Figures 4 to 5 The first transistor 410, Figures 4 to 5 The second transistor 412 and Figure 5 The third transistor 504. In response to the trigger control stage circuit 408, the first transistor 410, the second transistor 412, and the third transistor 504 are turned on. Figures 4 to 5 The first current limiting circuit 418 is triggered to supply current 616 of a first instance quantity from the first time 608 until the second instance time (T2) 614. Figures 2 to 5 The bootstrap capacitor 234 is charging. Figure 6 In this example, the first quantity of current is 200mA. Alternatively, any other quantity, level, or current quantity can be used for the first quantity of current 616.

[0130] exist Figure 6 In the illustrated example, the second waveform 604 increases between the first time 608 and the second time 614 because the voltage difference between the first terminal 302 and the second terminal 304 increases in response to the charging of the bootstrap capacitor 234. Figure 6 In this example, the instance time difference 618 between the first time period 608 and the second time period 614 is 2.4 μs. Alternatively, the time difference 618 can be any other time period.

[0131] exist Figure 6In the illustrated example, in response to the passing or ending of time difference 618, at the second time 614, Figures 4 to 5 The second current limiting circuit 420 reduces Figure 5 The gate voltage at the third gate terminal 504G reduces the charging current of the bootstrap capacitor 234 from a first amount of current to a second amount of current 620. Figure 6 In this example, the second current is 30mA. Alternatively, any other quantity, level, or amount of current can be used for the second current 616. Advantageously, the second current limiting circuit 420 can reduce the charging current to the second current 620 in response to the first terminal 302 being shorted to another node (e.g., a voltage node) to prevent short-circuit conditions.

[0132] exist Figure 6 In the illustrated example, the voltage difference between the first terminal 302 and the second terminal 304 increases in response to the charging of the bootstrap capacitor 234. Therefore, the second waveform 604 increases between the second time 614 and the third exemplary time 622. Figure 6 In this instance, the first instance ramp (e.g., the first charging ramp) 624 of the second waveform 604 is greater than the second instance ramp 626 of the second waveform 604. Figure 6 In this context, the first ramp 624 corresponds to and / or is based on a first charging rate for charging the bootstrap capacitor 234 in response to a first amount of current 616. Figure 6 In this context, the second ramp 626 corresponds to and / or is based on a second charging rate for charging the bootstrap capacitor 234 in response to a second current 616. Figure 6 In the example, the first charging rate is less than the second charging rate.

[0133] exist Figure 6 In the illustrated example, at the third time 622, the voltage difference between VBST and OUTH reaches the voltage regulation loop target. For example, the first comparator 422 may release the confirmation logic signal in response to a first voltage at the first terminal 302 being satisfied and / or less than or equal to a second voltage at the second terminal 304.

[0134] Figure 7 This is a schematic illustration of an instance gate driver integrated device 700 that includes a second instance gate driver stage 702 and a second instance bootstrap circuit 704. For example, Figure 7 The gate driver integrated device 700 can correspond to Figure 1 One or more of the gate driver integrated devices 102A to 102F. Figure 7 The second gate driver stage 702 includes Figure 3The first terminal 302, the second terminal 304, the third terminal 306, the fourth terminal 308, the first gate driver 334, the second gate driver 336, the first gate driver transistor 338, and the second gate driver transistor 340. Figure 7 Further description Figures 2 to 5 The bootstrap capacitor 234 is coupled to the first terminal 302 and the second terminal 304. Figure 7 It also depicts Figure 1 coupling to Figure 3 The first transistor 120A is a first resistor 318 and a second resistor 332.

[0135] exist Figure 7 In this circuit, the second bootstrap circuit 704 includes a second instance reference voltage circuit (VCHG) 706, an instance bootstrap diode (DBST) 708, and an instance bootstrap resistor (RBST) 710. Figure 7 In this circuit, the bootstrap resistor 710 is a current-limiting resistor. Figure 7 In this circuit, the second reference voltage circuit 706 and / or more generally the second bootstrap circuit 704 have a fixed voltage relative to power supply ground. The second bootstrap circuit 704 charges the bootstrap capacitor 234 through the bootstrap diode 708 and the bootstrap resistor 710. Advantageously, Figures 2 to 5 The first bootstrap circuit 232 improves upon the second bootstrap circuit 704 by having a reference voltage relative to the first terminal 302. For example, the first bootstrap circuit 232 can prevent the bootstrap capacitor 234 from being overcharged in response to an out-of-power surge below the power supply ground by referencing the second terminal 304 instead of the fourth terminal 308.

[0136] Figure 8 It corresponds to Figure 7 The timing diagram for an example operation of the second bootstrap circuit 704. Figure 8 In the timing diagram 800, instance waveforms 802, 804, and 806 are depicted with respect to time. Waveforms 802, 804, and 806 include the first instance waveform 802, the second instance waveform 804, and the third instance waveform 806.

[0137] exist Figure 8 In the first waveform 802, the bootstrap current (IBST) is expressed in amperes (A). For example, IBST could correspond to the current flowing to... Figure 7 The current in the bootstrap capacitor 234. Figure 8 In this context, the second waveform 804 can correspond to the voltage difference in volts (V) between the bootstrap voltage (VBST) and the HS output (OUTH). For example, the voltage difference can correspond to... Figure 7 The first voltage at the first terminal 302 and Figure 7The difference between the second voltage at the second terminal 304. Figure 8 In this context, the third waveform 806 can correspond to the HS output (OUTH) in volts (V). For example, OTH can correspond to... Figure 7 The second voltage at the second terminal 304.

[0138] exist Figure 8 In timing diagram 800, at a first time (T1) 808, OUTH transitions from a first voltage 810 to a second voltage 812, where the first voltage 810 is greater than the second voltage 812. The first voltage 810 may correspond to a validated logic signal (e.g., a logic high signal). The second voltage 812 may correspond to an unvalidated logic signal (e.g., a logic low signal). For example, the first gate driver 334 Figure 7 Can be turned off Figure 7 The first gate driver transistor 338 is used in Figure 7 A second voltage 812 is generated at the second terminal 304.

[0139] exist Figure 8 In the timing diagram 800, at the first time point 808, Figure 7 The second bootstrap circuit 704 is based on... Figure 7 The voltage generated by the second instance reference voltage circuit 706 is used for... Figure 7 The bootstrap capacitor 234 is charged. IBST decreases from the first time 808 to the second time (T2) 814 as the voltage difference between VBST and OUTH increases. Figure 7 In this process, IBST decreases to essentially zero at the second time 814 in response to VBST being satisfied and / or equal to VCHG (e.g., VBST is approximately equal to VCHG in a range of -0.05V to 0.05V). Advantageously, the first bootstrap circuit 232 is an improvement over the second bootstrap circuit 704 because the first bootstrap circuit 232 includes Figures 4 to 5 The first current-limiting circuit 418 and the first current-limiting circuit 418 that charge the bootstrap capacitor 234 relatively quickly using the first amount of current. Figures 4 to 5 A second current-limiting circuit 420 charges the bootstrap capacitor 234 using a second current, which is smaller than the first current. For example... Figure 6 and Figure 8 As described in the text, when the first bootstrap circuit 232 from Figure 6 The second time 614 until at least Figure 6 When the bootstrap capacitor 234 is charged at the third time 622, the second bootstrap circuit 704 cuts off the charging current at the second time 814.

[0140] Figure 9A Is with Figure 2 , 3The first timing diagram 900 corresponds to the instance operation of the first instance bootstrap circuit 232 of 4 and / or 5 during the charging operation. Figure 9B Is with Figure 7 The second instance bootstrap circuit 704 corresponds to the second timing diagram 902 during the charging operation. Advantageously, the first bootstrap circuit 232 utilizes a first amount current 904 that is larger than the second amount current 906 used by the second bootstrap circuit 704 to charge the bootstrap capacitor 234. Figures 2 to 5 And / or the bootstrap capacitor 234 of 7 is charged to improve the second bootstrap circuit 704. In Figure 9A In this example, the first current quantity 904 is 200mA. Alternatively, the first current quantity 904 can be any other value (e.g., 180mA, 250mA, etc.). Figure 9B In this context, the second quantity current 906 is based on the starting OTH voltage (VOUTHSTART). For example, based on the following equation (1), the second quantity current 906 may have a peak IBST:

[0141]

[0142] In the example of equation (1) above, VCHG can correspond to the equation (1) above. Figure 7 The voltage generated by the second reference voltage circuit 706, and RBST can correspond to Figure 7 The resistance of the bootstrap resistor 710.

[0143] exist Figures 9A to 9B In the illustrated example, the first quantity of current 904 is independent of the initial OUTH voltage, and therefore the first bootstrap circuit 232 can generate a larger IBST compared to the second bootstrap circuit 704. Figures 9A to 9B In one example, the first bootstrap circuit 232 can generate a first voltage difference (VDIFF1) 908 between VBST and OUTH, which is greater than the second voltage difference (VDIFF2) 910 generated by the second bootstrap circuit 704.

[0144] exist Figures 9A to 9B In the examples, Figure 9A First time (T1) 912 and Figure 9B The events occurred simultaneously with 9 / 12. Alternatively, Figure 9A The first time 912 can be different Figure 9B The first time was 912. Figures 9A to 9B In the examples, Figure 9A The second time (T2) 914 and Figure 9B The second time, 914, occurred simultaneously. Alternatively, Figure 9A The second time 914 may be different Figure 9B The second time was 914.

[0145] Figure 10A Is with Figure 2 , 3 The first timing diagram 1000 corresponds to the instance operation of the first bootstrap circuit 232 of 4 and / or 5 associated with the short-circuit condition. Figure 10B Is with Figure 7 The second bootstrap circuit 704 corresponds to the second timing diagram 1002 for an instance operation associated with a short-circuit condition. For example, it can respond to... Figures 3 to 5 And / or the first terminal 302 of 7 is shorted to an unplanned voltage rail (e.g., Figures 3 to 5 A short circuit may occur at the fourth terminal 308 of 7.

[0146] exist Figure 10A In the first timing diagram 1000, a short circuit occurs at the first time (T1) 1004. Figure 10A In the first timing diagram 1000, the first bootstrap circuit 232 reduces the first current 1006 to the second current 1008 in response to a short circuit condition.

[0147] exist Figure 10B In the second timing diagram 1002, in response to a short-circuit condition at the first time 1004, the second bootstrap circuit 704 does not reduce the third amount of current 1010 in IBST. Advantageously, the first bootstrap circuit 232 is an improvement on the second bootstrap circuit 704 because the first bootstrap circuit 232 can prevent device damage by reducing IBST to the second amount of current 1008, while the second bootstrap circuit 704 maintains the third amount of current 1010 in response to a short-circuit condition at the first time 1004. Advantageously, the first bootstrap circuit 232 can prevent damage by reducing IBST to the second amount of current 1008 in response to a short-circuit condition. Figures 2 to 5 And / or the bootstrap capacitor 234 and / or other components or devices coupled to or forming a circuit together with the bootstrap capacitor 234.

[0148] Figure 10A The diagram further depicts a first voltage difference waveform 1012 (indicated by solid lines) in response to a short-circuit condition and a second voltage difference waveform 1014 (indicated by dashed lines) in response to a condition where no short circuit occurs (e.g., the first bootstrap circuit 232 is operating normally and / or more generally the first gate driver stage 202 is operating normally).

[0149] Figure 10BThe diagram further depicts a third voltage difference waveform 1016 (represented by a solid line) in response to a short-circuit condition and a second voltage difference waveform 1018 (represented by a dashed line) in response to a condition where no short-circuit occurs (e.g., normal operation of the second bootstrap circuit 704 and / or more generally, normal operation of the second gate driver stage 702). Figures 10A to 10B In the examples, Figure 10A First time 1004 and Figure 10B The first occurrence is 1004 simultaneously. Alternatively, Figure 10A The first time 1004 may be different Figure 10B The first time was 1004.

[0150] Figure 11A Is with Figure 2 , 3 The first timing diagram 1100 corresponds to the exemplary operation of the first bootstrap circuit 232 of 4 and / or 5 associated with the undershoot condition of the gate driver output. Figure 11B Is with Figure 7 The second bootstrap circuit 704, associated with the gate driver output undershoot condition, corresponds to the second timing diagram 1102 in the example operation. For example, it can respond to... Figures 3 to 5 And / or the voltage output at the second terminal 304 of 7 drops below the power supply ground (e.g., Figures 3 to 5 The gate driver output undershoot occurs due to the voltage at the fourth terminal 308 of 7.

[0151] exist Figure 11A In the first time series diagram 1100, at the first time (T1) 1104, and Figures 3 to 5 The voltage at the second terminal 304 corresponds to the HS output (OUTH) becoming negative and / or dropping below the power supply ground. This event can correspond to a gate driver output undershoot condition. At the first time 1104, the voltage at the second terminal 304 corresponds to the voltage at the second terminal 304. Figures 2 to 5 The first bootstrap circuit 232 generates to... Figures 2 to 5 The bootstrap current (IBST) corresponding to the charging current of bootstrap capacitor 234 and / or 7 is a first-level current 1106. At a second time 1108, the first bootstrap circuit 232 reduces the first-level current 1106 to a second-level current 1110. Advantageously, by reducing IBST to the second-level current 1110 from the second time 1108 to the third time 1112, the first bootstrap circuit 232 prevents bootstrap capacitor 234 from being overcharged.

[0152] exist Figure 11B In the second time series diagram 1102, at the first time point 1104, and Figure 7The voltage at the second terminal 304 corresponds to the HS output (OUTH) becoming negative and / or dropping below the power supply ground. This event can correspond to a gate driver output undershoot condition. At the first time 1104 in the second timing diagram 1102, the voltage at the second terminal 304 corresponds to the voltage at the second terminal 304. Figure 7 The second bootstrap circuit 704 generates to... Figure 7 The bootstrap current (IBST) corresponding to the charging current of the bootstrap capacitor 234 is the third quantity current 1114. At the second time 1108 of the second timing diagram 1102, the second bootstrap circuit 704 reduces the third quantity current 1114 to the fourth quantity current 1116. Figures 11A to 11B In the example, the fourth quantity, current 1116, is greater than the second quantity, current 1110. Figure 11B In the example, in response to reducing the third current 1114 to the fourth current 1116, the second bootstrap circuit 704 overcharges the bootstrap capacitor 234 by (1). Figure 11A The first voltage difference 1120 between VBST and OUTH described in (2) Figure 11B The overcharge voltage difference 1118 between the second voltage difference 1122 between VBST and OUTH is quantified as described in the figure.

[0153] Advantageously, compared to the exemplary operation of the second bootstrap circuit 704, the first bootstrap circuit 232 prevents the bootstrap capacitor 234 from being overcharged by reducing the IBST to a second amount of current 1110 from the second time 1108 to the third time 1112. Figures 11A to 11B In the examples, Figure 11A The first time 11:04, the second time 11:08, and the third time 11:12 and Figure 11B The first time point 1104, the second time point 1108, and the third time point 1112 occur simultaneously. Alternatively, Figure 11A One or more of the first time 1104, the second time 1108, and / or the third time 1112 may differ from Figure 11B The first time is 11:04, the second time is 11:08, and / or the third time is 11:12.

[0154] Figure 12 The diagram illustrates a flowchart illustrating an instanced process that can be implemented using instanced hardware logic, instanced machine-readable instructions (e.g., hardware-readable instructions), instanced hardware-implemented state machines, and / or any combination thereof, wherein the aforementioned devices are configured to implement... Figures 2 to 5 The first instance of a bootstrap circuit 232 Figures 2 to 3 First instance gate driver stage 202 and / or more generally Figure 1The first instance gate driver integrated device 102A. The instance machine-readable instructions can be one or more executable programs or portions of executable programs executed by a programmable processor, programmable controller, GPU, DSP, ASIC, PLD, and / or FPLD. The program may be embodied as software stored on a non-transitory computer-readable storage medium (e.g., non-volatile memory, volatile memory, etc.), but the entire program and / or portions thereof may alternatively be embodied as firmware or dedicated hardware by any other means (e.g., a programmable device). Furthermore, although the instance program is referenced... Figure 12 The flowchart illustrated in the figure is used for description, but alternatively, implementation can be used. Figures 2 to 5 The first instance of a bootstrap circuit 232 Figures 2 to 3 First instance gate driver stage 202 and / or more generally Figure 1 Many other methods exist for the first exemplary gate driver integrated device 102A. For example, the execution order of the blocks can be changed and / or some blocks in the described blocks can be changed, eliminated, or combined. Alternatively or additionally, any or all blocks in the blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers, logic circuits, etc.) structured to perform the corresponding operations without executing software or firmware.

[0155] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, fragmented format, compiled format, executable format, packaged format, etc. The machine-readable instructions described herein can be stored as data (e.g., instructions, code, portions of code representation, etc.) that can be used to form, manufacture, and / or generate machine-executable instructions. For example, machine-readable instructions can be fragmented and stored on one or more storage devices. Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., so that they can be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, machine-readable instructions can be stored in multiple parts, which are individually compressed, encrypted, and stored on separate computing devices, wherein the parts, when decrypted, compressed, and combined, form an executable instruction set that implements, for example, the program described herein.

[0156] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HTML, SQL, Swift, etc.

[0157] As mentioned above, Figure 12 The instance process can be implemented using executable instructions (e.g., computer-readable instructions, machine-readable instructions, and / or hardware-readable instructions) on non-transitory computer and / or machine-readable media (e.g., flash memory, read-only memory, cache memory, random access memory, and / or any other storage device or storage disk) where information is stored for any duration (e.g., extended time period, permanent, short duration, temporary buffer, and / or used for caching information). As used herein, the terms non-transitory computer-readable media, non-transitory machine-readable media, and / or non-transitory hardware-readable media are expressly defined as including any type of computer, machine, and / or hardware-readable storage device and / or storage disk, and excluding propagation signals and transmission media.

[0158] As used herein, “include” and “comprise” (and all forms and tenses thereof) are open-ended terms. Therefore, whenever a claim is used as a preamble or in any kind of claim statement, and any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) is used, it should be understood that additional elements, items, etc., may exist, and this remains within the scope of the corresponding claim or statement. As used herein, the phrase “at least” as a transitional term in, for example, a claim preamble is also open-ended, as are the open-ended terms “include” and “comprise”. The term “and / or”, when used, for example, in the form of, for example, A, B, and / or C, refers to any combination or subgroup of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, and (7) A and B and C. As used herein in the context of describing structures, components, items, objects, etc., the phrase “at least one of A and B” is intended to refer to an implementation comprising any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, etc., the phrase “at least one of A or B” is intended to refer to an implementation comprising any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, and / or steps, the phrase “at least one of A and B” is intended to refer to an implementation comprising any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” is intended to refer to an implementation comprising any of the following: (1) at least one A, (2) at least one B and (3) at least one A and at least one B.

[0159] As used herein, singular references (e.g., "a (a / an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a (a or an)" refers to one or more of the entities mentioned. The terms "a (a or an)," "one or more," and "at least one" are used interchangeably herein. Furthermore, although individually listed, multiple components, elements, or method actions may be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different instances or claims, these features may be combined, and their inclusion in different instances or claims does not imply that the combination of said features is infeasible and / or unfavorable.

[0160] Figure 12 This means that it can be implemented using executable instance machine-readable instructions and / or configured to perform... Figures 2 to 5 The first instance bootstrap circuit 232, the first instance gate driver stage 202, and / or more generally Figure 1 The first instance of gate driver integrated device 102A is derived from the example hardware. Figure 3 The flowchart of instance process 1200 executed when the first instance gate driver 334 is executed. Figure 12 The instance process 1200 of the instance begins at block 1202, where the first bootstrap circuit 232 and / or more generally the first gate driver stage 202 determines whether the voltage difference between VCC and the gate driver high output (OUTH) is greater than a voltage threshold (e.g., 2V, 2.2V, 2.5V, etc.).

[0161] If at block 1202 the first bootstrap circuit 232 and / or more generally the first gate driver stage 202 determines that the voltage difference between VCC and OUTH is not greater than the voltage threshold, then control waits until the voltage difference is greater than the voltage threshold. If at block 1202 the first bootstrap circuit 232 and / or more generally the first gate driver stage 202 determines that the voltage difference is greater than the voltage threshold, then at block 1204 the first bootstrap circuit 232 and / or more generally the first gate driver stage 202 determines whether an enable signal has been confirmed. For example, level shifter 402 ( Figures 4 to 5 It can be confirmed that the bootstrap signal 350 has been validated. Figures 3 to 5 ).

[0162] If the first bootstrap circuit 232 and / or the first gate driver stage 202 at block 1204 determines that the enable signal has not yet been validated, then a control wait is implemented at block 1202 for validation of the enable signal. If the first bootstrap circuit 232 and / or the first gate driver stage 202 at block 1204 determines that the enable signal has been validated, then at block 1206, the first bootstrap circuit 232 and / or the first gate driver stage 202 triggers a first current limiting circuit to turn on the current mirror, thereby charging the bootstrap capacitor with a first current. For example, in response to OUTH being lower than VCC and in response to validation of the bootstrap signal 350, the first current limiting circuit 418 is triggered to turn on the control stage circuit 408 (…). Figures 4 to 5 ), first transistor 410 ( Figures 4 to 5 ) and the second transistor 412 ( Figures 4 to 5 The current mirror is described above. In response to turning on the current mirror, the first transistor 410 and the second transistor 412 can deliver a first amount of current to the bootstrap capacitor 234 to charge the bootstrap capacitor 234 to a voltage higher than VCC.

[0163] At block 1208, the first bootstrap circuit 232 and / or the first gate driver stage 202 determine whether a time threshold has been met. For example, in response to the expiration of a time delay (e.g., a predetermined time delay of 2.4 μs, 3.0 μs, etc.), the second current limiting circuit 420 may be invoked. Figures 4 to 5 This triggers the current mirror, thereby reducing the current supplied to the bootstrap capacitor 234 from the first amount of current to the second amount of current.

[0164] If at block 1208 the first bootstrap circuit 232 and / or the first gate driver stage 202 determines that the time threshold is not met, control returns to block 1204 to trigger the first current limiting circuit to turn on the current mirror, thereby charging the bootstrap capacitor with the first current. If at block 1208 the first bootstrap circuit 232 and / or the first gate driver stage 202 determines that the time threshold has been met and / or otherwise met, then at block 1210 the first bootstrap circuit 232 and / or the first gate driver stage 202 triggers a second current limiting circuit to adjust the operation of the current mirror, thereby charging the bootstrap capacitor with a second current. For example, the second current limiting circuit 420 may be invoked to trigger the current mirror to reduce the current supplied to the bootstrap capacitor 234 from the first amount of current to the second amount of current.

[0165] At block 1212, the first bootstrap circuit 232 and / or the first gate driver stage 202 determine whether the voltage difference between the bootstrap capacitor voltage (VBST) and the outH meets a threshold. For example, voltage regulation loop 406 ( Figures 4 to 5 The logic signal can be deauthenticated in response to a first voltage at the first terminal 302 being less than a second voltage at the second terminal 304. In such an example, the second voltage can be satisfied and / or otherwise satisfied in response to the second voltage being greater than the first voltage.

[0166] If at block 1212 the first bootstrap circuit 232 and / or the first gate driver stage 202 determines that the voltage difference between VBST and OUTH does not meet the threshold, then control returns to block 1210 to trigger the second current-limiting circuit to adjust the operation of the current mirror to charge the bootstrap capacitor with the second current. If at block 1212 the first bootstrap circuit 232 and / or the first gate driver stage 202 determines that the voltage difference between VBST and OUTH meets the threshold, then at block 1214 the first bootstrap circuit 232 and / or the first gate driver stage 202 turns off the current mirror. For example, voltage regulation loop 406 can decertify the logic signal to trigger control stage circuit 408 to turn off the first transistor 410 and the second transistor 412. In response to turning off the current mirror at block 1214, Figure 12 The instance procedure 1200 ends.

[0167] Based on the foregoing, it will be understood that exemplary systems, methods, apparatuses, and fabrications associated with gate driver bootstrap circuits have been disclosed to improve the power efficiency, reliability, and safety of high-voltage and / or high-current power devices while reducing the die area of ​​said power devices. The exemplary systems, methods, apparatuses, and fabrications disclosed herein avoid overcharging of the bootstrap capacitor in response to gate driver overshoot conditions. The exemplary systems, methods, apparatuses, and fabrications disclosed herein reduce and / or otherwise eliminate device damage in response to short-circuit conditions. The exemplary systems, methods, apparatuses, and fabrications disclosed herein can implement relatively rapid charging of the bootstrap capacitor with reference to relatively short negative pulses (e.g., 250 ns negative pulses). The exemplary systems, methods, apparatuses, and fabrications disclosed herein can reduce power consumption when not used by exemplary power conversion systems.

[0168] This paper discloses exemplary methods, apparatuses, systems, and fabrications of gate driver bootstrap circuits.

[0169] Additional instances and their combinations include the following:

[0170] Example 1 includes a gate driver stage comprising: a first terminal and a second terminal, the first terminal being coupled to a capacitor, the capacitor and the second terminal being coupled to a gate terminal of a power transistor; a gate driver coupled to the first terminal and the second terminal; and a bootstrap circuit coupled to the first terminal, the second terminal and the gate driver, the bootstrap circuit comprising: a control stage circuit having an output; and a first transistor having a first gate terminal and a first current terminal, the first gate terminal being coupled to the output and the first current terminal being coupled to the first terminal.

[0171] Example 2 includes a gate driver stage according to Example 1, wherein the bootstrap circuit is configured to increase a first voltage at the first terminal to a second voltage until a voltage regulation loop determines that the first voltage meets a voltage threshold, the second voltage being referenced to a third voltage at the second terminal.

[0172] Example 3 includes a gate driver according to Example 2, wherein the bootstrap circuit includes a second transistor having a second gate terminal and a second current terminal, the second gate terminal being coupled to the output, the second current terminal being coupled to the first terminal, and the first transistor and the second transistor being configured as a source follower or an emitter follower to increase the first voltage to the second voltage.

[0173] Example 4 includes a gate driver according to Example 3, wherein the first transistor and the second transistor are field-effect transistors in the source follower configuration, the first current terminal and the second current terminal are source terminals, and the control stage circuit includes a third transistor having a third current terminal and a fourth current terminal, the third current terminal being coupled to the first gate terminal and the second gate terminal, and the fourth current terminal being coupled to the second terminal.

[0174] Example 5 includes a gate driver according to Example 3, wherein the first transistor and the second transistor are bipolar junction transistors in the emitter follower configuration, the first current terminal and the second current terminal are emitter terminals, and the control stage circuit includes a third transistor having a third current terminal and a fourth current terminal, the third current terminal being coupled to the first gate terminal and the second gate terminal, and the fourth current terminal being coupled to the second terminal.

[0175] Example 6 includes a gate driver according to Example 1, wherein the bootstrap circuit includes a diode to rectify the direction of current to the first terminal in response to a first voltage at the first terminal being greater than a voltage input.

[0176] Example 7 includes a gate driver according to Example 1, wherein the bootstrap circuit includes a control stage circuit that obtains a feedback signal from at least one of a first current limiting circuit, a second current limiting circuit, or a voltage regulation loop.

[0177] Example 8 includes a gate driver according to Example 7, wherein the control stage circuitry includes a transistor having a gate terminal, and the control stage circuitry is a buffer stage coupled to the transistor, the buffer stage being used to drive the gate terminal to a first voltage having a second voltage greater than or less than that at the second terminal.

[0178] Example 9 includes a gate driver according to Example 1, wherein the bootstrap circuit comprises: a resistor; a current limiting circuit having a first input and a first output, the first input being coupled to the resistor; a transistor having a gate terminal, a first current terminal and a second current terminal, the first current terminal being coupled to a voltage input and the second current terminal being coupled to the first terminal; and a control stage circuit having a control input, a reference input and a control output, the control input being coupled to the first output, the reference input being coupled to the second terminal, and the control output being coupled to the gate terminal.

[0179] Example 10 includes a gate driver according to Example 9, wherein the current limiting circuit is a first current limiting circuit, and the bootstrap circuit includes a second current limiting circuit having a second input and a second output, the second input being coupled to the resistor and the first input, and the second output being coupled to the control input.

[0180] Example 11 includes a gate driver according to Example 10, wherein the first current limiting circuit and the second current limiting circuit are configured to measure the voltage across the resistor and compare the voltage with a voltage threshold.

[0181] Example 12 includes a gate driver according to Example 9, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, and the gate driver further includes: a diode having an anode and a cathode, the anode being coupled to the resistor and the first input; and a second transistor having a second gate terminal, a third current terminal and a fourth current terminal, the second gate terminal being coupled to the first gate terminal and the control output, the third current terminal being coupled to the cathode, and the fourth current terminal being coupled to the first terminal.

[0182] Example 13 includes a gate driver according to Example 12, wherein the first transistor has a first size and the second transistor has a second size smaller than the first size, and the resistor is coupled to the second transistor in a configuration to reduce power dissipation and current consumption of the bootstrap circuit.

[0183] Example 14 includes a gate driver according to Example 1, wherein the bootstrap circuit includes a control level circuit and a level shifter coupled to the control level circuit, the level shifter being used to convert a first signal into a second signal, the first signal corresponding to a ground reference enable signal, and the second signal corresponding to a signal referenced to a first voltage at the first terminal or a second voltage at the second terminal.

[0184] Example 15 includes a bootstrap circuit comprising: a first current limiting circuit having a first output; a second current limiting circuit having a second output; a control stage circuit having a first input, a second input, and a third output, the first input being coupled to the first output and the second output; a voltage regulation loop having a third input, a fourth input, and a fourth output, the fourth output being coupled to the first input; and a transistor having a gate terminal and a current terminal, the gate terminal being coupled to the third output and the current terminal being coupled to the third input.

[0185] Example 16 includes the bootstrap circuit according to Example 15, wherein the third input and the current terminal are coupled to a capacitor.

[0186] Example 17 includes a bootstrap circuit according to Example 15, wherein the gate terminal is a first gate terminal, the current terminal is a first current terminal, the second current limiting circuit has a fifth input, and the first current limiting circuit includes a P-channel field-effect transistor having a second gate terminal and a second current terminal, the second gate terminal being coupled to the fifth input, and the second current terminal being coupled to the first input.

[0187] Example 18 includes a bootstrap circuit according to Example 15, wherein the second output is an amplifier output, and the second current limiting circuit includes a voltage source and an amplifier having a first amplifier input, a second amplifier input, and the amplifier output, wherein the voltage source is coupled to the first amplifier input, and the amplifier output is coupled to the first input.

[0188] Example 19 includes a bootstrap circuit according to Example 18, wherein the first current limiting circuit has a fifth input, the transistor is a first transistor, the gate terminal is a first gate terminal, the current terminal is a first current terminal, and the bootstrap circuit further includes: a diode having an anode and a cathode, the anode being coupled to the second amplifier input and the fifth input; and a second transistor having a second gate terminal, a second current terminal, and a third current terminal, the second gate terminal being coupled to the third output, the second current terminal being coupled to the cathode, and the third current terminal being coupled to the first current terminal and the third input.

[0189] Example 20 includes a bootstrap circuit according to Example 15, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, the current terminal is a first current terminal, and the bootstrap circuit further includes: a second transistor having a second gate terminal and a second current terminal, the second gate terminal being coupled to the third output, and the second current terminal being coupled to the first current terminal and the third input.

[0190] Example 21 includes the bootstrap circuit according to Example 15, further comprising a level shifter having a level shifter input and a level shifter output, the level shifter output being coupled to the second input.

[0191] Example 22 includes the bootstrap circuit according to Example 15, further including a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output, the reference voltage circuit input being coupled to the fourth input and the reference voltage circuit input being coupled to a capacitor.

[0192] Example 23 includes a gate driver stage comprising: a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal, the second terminal, and the third terminal being coupled to a gate terminal of a transistor, and the fourth terminal being coupled to a current terminal of the transistor; a first gate driver coupled to the first terminal and the second terminal, the first gate driver being configured to turn on the transistor; a second gate driver coupled to the third terminal and the fourth terminal, the second gate driver being configured to turn off the transistor; and a bootstrap circuit coupled to the first terminal, the second terminal, and the first gate driver.

[0193] Example 24 includes a gate driver stage according to Example 23, wherein the first terminal is coupled to a first capacitor terminal of a capacitor, the second terminal is coupled to a first resistor terminal of a resistor and a second capacitor terminal of the capacitor, and the second resistor terminal of the resistor is coupled to the gate terminal.

[0194] Example 25 includes a gate driver stage according to Example 23, further comprising: a second transistor having a threshold voltage, the second transistor being coupled to the output of the first gate driver, and wherein the bootstrap circuit is configured to generate a voltage across the first gate driver to cause the first gate driver to generate an output voltage greater than the threshold voltage, the second transistor being turned on in response to the output voltage being greater than the threshold voltage.

[0195] Example 26 includes a gate driver stage according to Example 23, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, and the bootstrap circuit includes: a diode having an anode and a cathode; a first current limiting circuit having a first current limiting circuit input and a first current limiting circuit output, the first current limiting circuit input being coupled to the anode; a second current limiting circuit having a second current limiting circuit input and a second current limiting circuit output, the second current limiting circuit input being coupled to the anode; a second transistor having a second gate terminal, a first current terminal, and a second current terminal, the second current terminal being coupled to the first terminal; a third transistor having a third gate terminal, a third current terminal, and a fourth current terminal, the fourth current terminal being coupled to the second current terminal and the first terminal, the third current terminal being coupled to the cathode; and a control stage circuit having a control input, a control reference input, and a control output, the control input being coupled to the first current limiting circuit output and the second current limiting circuit output, the control reference input being coupled to the second terminal, and the control output being coupled to the second gate terminal and the third gate terminal.

[0196] Example 27 includes a gate driver stage according to Example 26, wherein the control input is a first control input, the control stage circuit has a second control input, and the gate driver stage further includes: a level shifter having a level shifter output coupled to the second control input; a reference voltage circuit having a first reference voltage circuit terminal and a second reference voltage circuit terminal, the second reference voltage circuit terminal being coupled to the second terminal; and a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input being coupled to the second current terminal, the fourth current terminal, and the first terminal, the second comparator input being coupled to the first reference voltage circuit terminal, and the comparator output being coupled to the first control input, the first current limiting circuit output, and the second current limiting circuit output.

[0197] Example 28 includes a gate driver stage according to Example 27, wherein the diode is a first diode and the reference voltage circuit includes a Zener diode coupled to a second diode.

[0198] Example 29 includes a gate driver stage according to Example 26, wherein the first current limiting circuit includes: a fourth transistor having a fourth gate terminal, a fifth current terminal, and a sixth current terminal, the fourth gate terminal being coupled to the anode; and the second current limiting circuit includes: a voltage source having a first voltage source terminal and a second voltage source terminal; and an amplifier having a first amplifier input, a second amplifier input, and an amplifier output, the first amplifier input being coupled to the second voltage source terminal, the second amplifier input being coupled to the anode, and the amplifier output being coupled to the sixth current terminal and the control input.

[0199] Example 30 includes a gate driver stage according to Example 26, further including a level shifter, and wherein the control stage circuitry includes: a current source coupled to the level shifter; and a fourth transistor having a fourth gate terminal, a fifth current terminal and a sixth current terminal, the fourth gate terminal being coupled to the output of the second current limiting circuit, the fifth current terminal being coupled to the current source, the first gate terminal and the second gate terminal, and the sixth current terminal being coupled to the second terminal.

[0200] Example 31 includes a gate driver integrated device comprising: a first terminal coupled to a capacitor; a second terminal coupled to a gate terminal of a transistor; a gate driver stage coupled to the first terminal and the second terminal, the gate driver stage including a gate driver configured to turn on the transistor; and a bootstrap circuit coupled to the first terminal, the second terminal and the gate driver.

[0201] Example 32 includes the gate driver integrated device according to Example 31, wherein the transistor is a silicon carbide transistor.

[0202] Example 33 includes a gate driver integrated device according to Example 31, wherein the gate driver integrated device is included in a traction inverter of an electric vehicle, and the transistor is coupled to the electric motor of the electric vehicle.

[0203] Example 34 includes a gate driver integrated device according to Example 31, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, and the bootstrap circuit includes: a diode having an anode and a cathode; a first current limiting circuit having a first current limiting circuit input and a first current limiting circuit output, the first current limiting circuit input being coupled to the anode; a second current limiting circuit having a second current limiting circuit input and a second current limiting circuit output, the second current limiting circuit input being coupled to the anode; a second transistor having a second gate terminal, a first current terminal, and a second current terminal, the second current terminal being coupled to the first terminal; a third transistor having a third gate terminal, a third current terminal, and a fourth current terminal, the fourth current terminal being coupled to the second current terminal and the first terminal, the third current terminal being coupled to the cathode; and a control stage circuit having a control input, a control reference input, and a control output, the control input being coupled to the first current limiting circuit output and the second current limiting circuit output, the control reference input being coupled to the second terminal, and the control output being coupled to the second gate terminal and the third gate terminal.

[0204] Although certain exemplary systems, methods, apparatuses, and articles have been disclosed herein, the scope of this patent is not limited thereto. Rather, this patent fairly covers all systems, methods, apparatuses, and articles that fall within the scope of the claims of this patent.

[0205] The appended claims are hereby incorporated in this embodiment by reference, wherein each claim is an independent embodiment of the invention.

Claims

1. A gate driver comprising: Bootstrapping terminal; Driver output; An amplifier having a supply terminal and a reference terminal, the supply terminal being coupled to the bootstrap terminal and the reference terminal being coupled to the driver output; and A bootstrap circuit coupled to the bootstrap terminal and the driver output, the bootstrap circuit comprising: Control stage circuit, which has output; and A first transistor has a first gate terminal and a first current terminal, the first gate terminal being coupled to the output and the first current terminal being coupled to the bootstrap terminal.

2. The gate driver of claim 1, wherein the bootstrap circuit is configured to increase a first voltage at the bootstrap terminal to a second voltage until a voltage regulation loop determines that the first voltage is greater than a voltage threshold.

3. The gate driver of claim 2, wherein the bootstrap circuit includes a second transistor having a second gate terminal and a second current terminal, the second gate terminal being coupled to the output, the second current terminal being coupled to the bootstrap terminal, and the first transistor and the second transistor being configured as a source follower or an emitter follower to increase the first voltage to the second voltage.

4. The gate driver of claim 3, wherein the first transistor and the second transistor are field-effect transistors in the source follower configuration, the first current terminal and the second current terminal are source terminals, and the control stage circuit includes a third transistor having a third current terminal and a fourth current terminal, the third current terminal being coupled to the first gate terminal and the second gate terminal, and the fourth current terminal being coupled to the driver output.

5. The gate driver of claim 3, wherein the first transistor and the second transistor are bipolar junction transistors in the emitter follower configuration, the first current terminal and the second current terminal are emitter terminals, and the control stage circuit includes a third transistor having a third current terminal and a fourth current terminal, the third current terminal being coupled to the first gate terminal and the second gate terminal, and the fourth current terminal being coupled to the driver output.

6. The gate driver of claim 1, wherein the bootstrap circuit includes a diode to rectify the direction of current to the bootstrap terminal in response to a first voltage at the bootstrap terminal being greater than a voltage input.

7. The gate driver of claim 1, wherein the bootstrap circuit comprises a control stage circuit that obtains a feedback signal from at least one of a current limiting circuit or a voltage regulation loop.

8. The gate driver of claim 7, wherein the control stage circuitry includes a transistor having a gate terminal, and the control stage circuitry is a buffer stage coupled to the transistor, the buffer stage being configured to drive the gate terminal to a first voltage having a second voltage greater than or less than the second voltage at the driver output.

9. The gate driver of claim 1, wherein the bootstrap circuit comprises: Resistor; A current limiting circuit having a first input and a first output, the first input being coupled to the resistor; A transistor having a gate terminal, a first current terminal and a second current terminal, the first current terminal being coupled to a voltage input and the second current terminal being coupled to the bootstrap terminal; and A control-level circuit having a control input, a reference input, and a control output, wherein the control input is coupled to the first output, the reference input is coupled to the driver output, and the control output is coupled to the gate terminal.

10. The gate driver of claim 9, wherein the current limiting circuit is a first current limiting circuit, and the bootstrap circuit includes a second current limiting circuit having a second input and a second output, the second input being coupled to the resistor and the first input, and the second output being coupled to the control input.

11. The gate driver of claim 10, wherein the first current limiting circuit and the second current limiting circuit are configured to measure the voltage across the resistor and compare the voltage with a voltage threshold.

12. The gate driver of claim 9, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, and the gate driver further comprises: A diode having an anode and a cathode, the anode being coupled to the resistor and the first input; and The second transistor has a second gate terminal, a third current terminal and a fourth current terminal, the second gate terminal being coupled to the first gate terminal and the control output, the third current terminal being coupled to the cathode, and the fourth current terminal being coupled to the bootstrap terminal.

13. The gate driver of claim 12, wherein the first transistor has a first size and the second transistor has a second size smaller than the first size, and the resistor is coupled to the second transistor in a configuration to reduce power dissipation and current consumption of the bootstrap circuit.

14. The gate driver of claim 1, wherein the bootstrap circuit includes a control stage circuit and a level shifter coupled to the control stage circuit, the level shifter being configured to convert a first signal into a second signal, the first signal corresponding to a ground reference enable signal, and the second signal corresponding to a signal referenced to a first voltage at the bootstrap terminal or a second voltage at the driver output.

15. A bootstrap circuit, comprising: A first current-limiting circuit, which has a first output; The second current-limiting circuit has a second output; A control-level circuit having a first input, a second input, and a third output, wherein the first input is coupled to the first output and the second output; A voltage regulation loop having a third input, a fourth input, and a fourth output, wherein the fourth output is coupled to the first input; and A transistor having a gate terminal and a current terminal, the gate terminal being coupled to the third output and the current terminal being coupled to the third input.

16. The bootstrap circuit of claim 15, wherein the third input and the current terminal are coupled to a capacitor.

17. The bootstrap circuit of claim 15, wherein the gate terminal is a first gate terminal, the current terminal is a first current terminal, the second current limiting circuit has a fifth input, and the first current limiting circuit includes a P-channel field-effect transistor having a second gate terminal and a second current terminal, the second gate terminal being coupled to the fifth input, and the second current terminal being coupled to the first input.

18. The bootstrap circuit of claim 15, wherein the second output is an amplifier output, and the second current limiting circuit includes a voltage source and an amplifier, the amplifier having a first amplifier input, a second amplifier input and the amplifier output, the voltage source being coupled to the first amplifier input and the amplifier output being coupled to the first input.

19. The bootstrap circuit of claim 18, wherein the first current limiting circuit has a fifth input, the transistor is a first transistor, the gate terminal is a first gate terminal, the current terminal is a first current terminal, and the bootstrap circuit further comprises: A diode having an anode and a cathode, the anode being coupled to the second amplifier input and the fifth input; and The second transistor has a second gate terminal, a second current terminal and a third current terminal, the second gate terminal being coupled to the third output, the second current terminal being coupled to the cathode, and the third current terminal being coupled to the first current terminal and the third input.

20. The bootstrap circuit of claim 15, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, the current terminal is a first current terminal, and the bootstrap circuit further comprises: The second transistor has a second gate terminal and a second current terminal, the second gate terminal being coupled to the third output, and the second current terminal being coupled to the first current terminal and the third input.

21. The bootstrap circuit of claim 15, further comprising a level shifter having a level shifter input and a level shifter output, the level shifter output being coupled to the second input.

22. The bootstrap circuit of claim 15, further comprising a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output, the reference voltage circuit input being coupled to the fourth input and the reference voltage circuit input being coupled to a capacitor.

23. A gate driver comprising: The first terminal, the second terminal, the third terminal, and the fourth terminal, each terminal representing a different node, the first terminal, the second terminal, and the third terminal are coupled to the gate terminal of the transistor, and the fourth terminal is coupled to the current terminal of the transistor. A first gate driver is coupled to the first terminal and the second terminal, and the first gate driver is configured to turn on the transistor; A second gate driver is coupled to the third terminal and the fourth terminal, and the second gate driver is configured to turn off the transistor; and A bootstrap circuit is coupled to the first terminal, the second terminal, and the first gate driver.

24. The gate driver of claim 23, wherein the first terminal is coupled to a first capacitor terminal of a capacitor, the second terminal is coupled to a first resistor terminal of a resistor and a second capacitor terminal of the capacitor, and the second resistor terminal of the resistor is coupled to the gate terminal.

25. The gate driver of claim 23, further comprising: The second transistor will have a threshold voltage and is coupled to the output of the first gate driver; and wherein The bootstrap circuit is configured to generate a voltage across the first gate driver so that the first gate driver generates an output voltage greater than the threshold voltage, and the second transistor turns on in response to the output voltage being greater than the threshold voltage.

26. The gate driver of claim 23, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, and the bootstrap circuit comprises: A diode has an anode and a cathode; A first current limiting circuit has a first current limiting circuit input and a first current limiting circuit output, wherein the first current limiting circuit input is coupled to the anode; A second current limiting circuit has a second current limiting circuit input and a second current limiting circuit output, wherein the second current limiting circuit input is coupled to the anode; The second transistor has a second gate terminal, a first current terminal and a second current terminal, wherein the second current terminal is coupled to the first terminal; A third transistor has a third gate terminal, a third current terminal and a fourth current terminal, the fourth current terminal being coupled to the second current terminal and the first terminal, and the third current terminal being coupled to the cathode; and A control stage circuit has a control input, a control reference input, and a control output. The control input is coupled to the output of the first current limiting circuit and the output of the second current limiting circuit. The control reference input is coupled to the second terminal. The control output is coupled to the second gate terminal and the third gate terminal.

27. The gate driver of claim 26, wherein the control input is a first control input, the control stage circuitry has a second control input, and the gate driver stage further comprises: A level shifter having a level shifter output coupled to the second control input; A reference voltage circuit having a first reference voltage circuit terminal and a second reference voltage circuit terminal, wherein the second reference voltage circuit terminal is coupled to the second terminal; and A comparator having a first comparator input, a second comparator input, and a comparator output, wherein the first comparator input is coupled to a second current terminal, a fourth current terminal, and the first terminal; the second comparator input is coupled to a first reference voltage circuit terminal; and the comparator output is coupled to a first control input, a first current limiting circuit output, and a second current limiting circuit output.

28. The gate driver of claim 27, wherein the diode is a first diode and the reference voltage circuit includes a Zener diode coupled to a second diode.

29. The gate driver of claim 26, wherein: The first current limiting circuit includes: A fourth transistor has a fourth gate terminal, a fifth current terminal, and a sixth current terminal, wherein the fourth gate terminal is coupled to the anode; and The second current limiting circuit includes: A voltage source having a first voltage source terminal and a second voltage source terminal; and An amplifier having a first amplifier input, a second amplifier input, and an amplifier output, wherein the first amplifier input is coupled to a second voltage source terminal, the second amplifier input is coupled to the anode, and the amplifier output is coupled to the sixth current terminal and the control input.

30. The gate driver of claim 26, further comprising a level shifter, and wherein the control stage circuitry comprises: A current source coupled to the level shifter; and A fourth transistor has a fourth gate terminal, a fifth current terminal and a sixth current terminal, the fourth gate terminal being coupled to the output of the second current limiting circuit, the fifth current terminal being coupled to the current source, the first gate terminal and the second gate terminal, and the sixth current terminal being coupled to the second terminal.

31. A gate driver integrated device, comprising: The first terminal is coupled to a capacitor; The second terminal is coupled to the gate terminal of the transistor; A gate driver stage coupled to the first terminal and the second terminal, the gate driver stage comprising: A gate driver configured to turn on the transistor; and A bootstrap circuit is coupled to the first terminal, the second terminal, and the gate driver. The bootstrap circuit includes a control stage circuit coupled to the second terminal and a current limiting circuit coupled to the control stage circuit.

32. The gate driver integrated device of claim 31, wherein the transistor is a silicon carbide transistor.

33. The gate driver integrated device of claim 31, wherein the gate driver integrated device is included in the traction inverter of an electric vehicle, and the transistor is coupled to the electric motor of the electric vehicle.

34. The gate driver integrated device of claim 31, wherein the transistor is a first transistor, the gate terminal is a first gate terminal, and the bootstrap circuit comprises: A diode has an anode and a cathode; A second transistor having a second gate terminal, a first current terminal, and a second current terminal, wherein the second current terminal is coupled to the first terminal; and A third transistor has a third gate terminal, a third current terminal and a fourth current terminal, the fourth current terminal being coupled to the second current terminal and the first terminal, and the third current terminal being coupled to the cathode; The current limiting circuit mentioned above includes: A first current-limiting circuit having a first current-limiting circuit input and a first current-limiting circuit output, the first current-limiting circuit input being coupled to the anode; and A second current-limiting circuit has a second current-limiting circuit input and a second current-limiting circuit output, the second current-limiting circuit input being coupled to the anode; and The control stage circuit has a control input, a control reference input, and a control output. The control input is coupled to the output of the first current limiting circuit and the output of the second current limiting circuit. The control reference input is coupled to the second terminal. The control output is coupled to the second gate terminal and the third gate terminal.

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