Method and apparatus for testing bonding wires in integrated circuits

Abstract

Disclosed herein is a test apparatus and method for identifying potential defects in IC devices based on capacitive coupling between welding wires. A welding wire may have a potential defect that does not appear as a hard short or hard open when tested, but may cause a high risk of developing into a hard short or hard open over time. A potential defect may be formed when two adjacent welding wires are disturbed and become close to each other. According to some embodiments, capacitive coupling between a pair of pins can be used to provide an indication of a near short potential defect between welding wires connected to the pair of pins.

Description

[0001] Cross-references to related patent applications

[0002] This patent application claims priority under 35 U.S.C. § 120 to U.S. Non-Provisional Patent Application Serial No. 16 / 132,292, filed on September 14, 2018, under Attorney Docket No. T0529.70161US00, and entitled “METHOD AND APPARATUS FOR BOND WIRETESTING IN AN INTEGRATED CIRCUIT,” which is hereby incorporated by reference in its entirety. For purposes of the United States of America, this patent application will be deemed a continuation of U.S. Patent Application No. 16 / 132,292, filed on September 14, 2018. Background Art

[0003] The present patent application generally relates to methods and apparatus for testing integrated circuit (IC) devices. In particular, the present patent application relates to identifying IC devices that may experience defects related to bonding wires.

[0004] IC devices may be in the form of a package or chip with conductive leads or pads (sometimes called "pins") on the outer surface of the package. Some IC devices use wire bonds to connect connection points on a substrate (such as a silicon die) to a lead frame. The lead frame, in turn, may be connected to the pins of the device package. When manufacturing ICs, testing is performed at one or more stages to ensure that the finished product functions properly.

[0005] Testing can be performed in a semiconductor test system, such as automatic test equipment (ATE), by connecting a test probe to a test access point on an IC device. The test probe is connected to the test equipment to provide electrical stimulation or perform electrical measurements at the test access point. For testing semiconductor dies that will be packaged to form a semiconductor device, the test access point may be a pad on the die. For testing a finished product, the test probe may be connected to a pin on the outside of the package.

[0006] Testing the packaged product may identify shorts between the wires or opens in some of the wires. Such testing may identify defects that exist at the time of testing. However, some semiconductor devices may not be usable even if the testing does not identify any defects at the time of manufacturing. Summary of the invention

[0007] According to some embodiments, a method of operating a test system to identify potential defects in a device is provided. The device includes a plurality of pins having welding wires attached thereto. The method includes providing an excitation signal to the device; measuring a response to the excitation signal. The response indicates a capacitive coupling between a welding wire attached to a first pin of the plurality of pins and a welding wire attached to a second pin of the plurality of pins. The method also includes determining whether a capacitance providing the capacitive coupling is within a predetermined range; and when it is determined that the capacitance is outside the predetermined range, providing an indication that the device may be faulty.

[0008] According to some embodiments, a method of operating a test system to identify a potential defect in a device is provided. The device includes a plurality of pins having solder wires attached thereto. The method includes testing the device to identify hard shorts and hard opens between a plurality of pairs of the plurality of pins; when the test does not identify a hard short or a hard open, testing a potential defect for each pair of the plurality of pairs of pins; measuring a fringe capacitance between a solder wire attached to a first pin of the pair of pins and a solder wire attached to a second pin of the pair of pins; and

[0009] determining whether the fringe capacitance is within a predetermined range; and providing an indication that the device has a potential defect when it is determined that the fringe capacitance of one pair of the plurality of pairs of pins is outside the predetermined range.

[0010] According to some embodiments, at least one non-transitory computer-readable medium is provided. The at least one non-transitory computer-readable medium is encoded with computer-executable instructions, which, when executed by a processor of a test system, control the processor to perform a method of operating the test system to identify potential defects in a device, the device comprising a plurality of pins having welding wires attached thereto. The method includes configuring the test system to measure the capacitance of a first pin and a second pin in the pair of pins for each pair of the plurality of pins. The configuration includes connecting an AC voltage source to a first pin in the pair of pins; measuring the current induced by the AC voltage source; calculating the capacitance of the capacitive coupling between the welding wire attached to the first pin and the welding wire attached to the second pin; determining whether the capacitance is within a predetermined range; and when it is determined that the capacitance is outside the predetermined range, providing an indication that the device has a potential defect.

[0011] The foregoing is a non-limiting summary of the present invention which is defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various aspects and embodiments will be described in conjunction with the following drawings. It should be understood that the drawings are not necessarily drawn to scale. In the drawings, each identical or nearly identical component shown in different figures is represented by the same reference numeral. For clarity, not every component in each drawing is labeled.

[0013] Figure 1 A schematic diagram showing a device 100 tested using a test system 10 according to some aspects of the present patent application;

[0014] Figure 2A To illustrate the operation of the test system 10 according to some aspects of the present patent application to test Figure 1 A schematic flow chart of an exemplary method 200A for detecting welding wire defects in the apparatus 100 is shown;

[0015] Figure 2B To illustrate some aspects of the present patent application, a method for operating the test system 10 to identify Figure 1 A schematic flow chart of an exemplary method 200B for detecting potential defects in the device 100 is shown;

[0016] Figure 3A A schematic diagram illustrating an exemplary implementation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application;

[0017] Figure 3B A schematic diagram illustrating an exemplary variation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application;

[0018] Figure 4A A schematic diagram illustrating another exemplary implementation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application;

[0019] Figure 4B A schematic diagram illustrating another exemplary implementation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application;

[0020] Figure 5 A data bar graph showing an example of a series of measured pin capacitances and predetermined capacitive coupling ranges according to some aspects of the present patent application;

[0021] Figure 6 A bar graph of data showing a series of measured pin capacitances on two devices according to some aspects of the present patent application; and

[0022] Figure 7 FIG. 7 is a schematic flow chart illustrating an exemplary method 700 for selecting a predetermined capacitance range according to some aspects of the present patent application. DETAILED DESCRIPTION

[0023] The inventors have recognized and appreciated that certain values ​​of capacitive coupling between certain test access points of a semiconductor device may indicate a high likelihood of the device failing in operation. Those values ​​of capacitive coupling may be associated with incorrect positioning of a bonding wire, which may cause the device to fail in operation. Thus, those values ​​of capacitive coupling may enable the semiconductor device to be classified as having latent defects that cannot be detected by conventional semiconductor testing techniques because they are not present when tested during manufacturing. Test apparatus and methods for identifying such latent defects in IC devices based on capacitive coupling between bonding wires are disclosed herein.

[0024] The inventors have recognized and appreciated that as IC functionality continues to increase, the number of pins in IC packages and the probability of wire defects will continue to increase. Wire defects can include hard shorts and hard opens. A hard short is a defect that occurs when two wires are electrically shorted together (e.g., when the wires inadvertently contact each other). A hard open is a defect that occurs when a wire is not electrically connected to the intended circuit within the device.

[0025] Both hard shorts and hard opens can be detected based on measurements at the test access point connected to the welding wire. When an IC device is identified as a hard short or hard open defect, it can be rejected as a faulty device. The inventor has also recognized and understood that the welding wire may have a potential defect that does not appear as a hard short or hard open when tested, but may cause a high risk of developing into a hard short or hard open over time. For example, when two adjacent welding wires are disturbed to contact each other due to temperature changes, vibrations during equipment processing, etc., the potential defect may cause equipment failure. Such potential defects may be caused by "near short circuits". Equipment with near short circuits has a high probability of failure from near short circuits to hard short circuits. When the IC device is subjected to a harsh environment accompanied by temperature changes and / or mechanical vibrations, such as when used in an automobile or other vehicle, the near short circuit may also develop into a hard short circuit. Therefore, it is desirable to identify potential defects in the device during the manufacturing process before transporting or deploying the IC device. The technology as described herein may be particularly suitable for IC devices designed for vehicles or other environments where high vibrations will exist. However, these techniques can be used with any type of equipment that has welding wire.

[0026] The technology as described herein provides a faster and cheaper electrical testing method for identifying potential defects than conventional methods that can be used to identify such potential defects. Potential defects such as near short circuits of welding wires can be identified, for example, by imaging the position of each of the welding wires using known X-ray radiography. However, the inventors have recognized and appreciated that X-ray radiography methods are expensive in terms of capital equipment and supply costs, as well as downtime in the manufacturing process due to the time-consuming imaging process. X-ray imaging is also prone to human error when interpreting large amounts of image data.

[0027] The inventors have also recognized and appreciated that a wire in a "near short" state has a different capacitive coupling than a properly positioned wire. Although the capacitance difference is very small, the inventors have recognized a measurement technique that can identify such a small difference with sufficient reliability to predict that an IC device has a high risk of failure.

[0028] According to one aspect of the present patent application, capacitive coupling between a pair of pins connected to adjacent welding wires can be used to provide an indication of a potential defect of a near short circuit between the welding wires connected to the pair of pins. According to one aspect of the present patent application, because the capacitive coupling between the welding wires (hereinafter referred to as "fringe capacitance") is inversely proportional to the distance between the welding wires, welding wires that are close to each other in a near short circuit state will exhibit a greater amount of fringe capacitance than welding wires that are properly spaced. The fringe capacitance can be measured at the pins of the device to which the welding wires are connected.

[0029] According to some embodiments, to measure the fringe capacitance, an excitation signal such as a sinusoidal or alternating current (AC) voltage signal may be provided to the device under test, and a response to the excitation signal may be measured. The response may indicate capacitive coupling between a wire attached to a first pin and a second pin of the device under test. In some embodiments, the response to the AC excitation signal may be measured in a 2-wire configuration by measuring the AC current between the first pin of the device under test and the substrate.

[0030] In other embodiments, the response can be measured at the second pin of the device under test. In such a measurement configuration, the substrate of the IC device can be connected to a reference voltage level. The inventors have recognized and understood that the fringe capacitance between the welding wires can have a relatively small magnitude compared to the larger parasitic background capacitance from parasitic coupling (such as coupling between the pads and the substrate in the IC device). This means that the measurement of the fringe capacitance is a small capacitance measurement, and the AC current path through the capacitive coupling between the welding wires has a larger impedance than the AC current path through the parasitic background capacitance. In some embodiments, the response can be measured in a 3-wire configuration to reduce the influence of parasitic background capacitance when measuring the fringe capacitance between the welding wires connected to the two pins. In some embodiments, an excitation AC voltage signal can be applied to the first pin, and when the substrate is connected to the reference voltage, the response AC current is measured at the second pin. The inventors have understood that when the substrate is connected to a reference voltage (such as a ground voltage), the response AC current through the parasitic background capacitance will flow to the reference voltage substantially via the substrate rather than the second pin, so that the AC current measured at the second pin is substantially based on the fringe capacitance.

[0031] According to some aspects of the present patent application, the fringe capacitance between a pair of welding wires connected to two pins can be compared with a predetermined range to determine whether the device has a potential defect and may fail. The predetermined range can be a static range based on the average value of the measured baseline capacitance between similar pins in a plurality of known good devices. The inventors have recognized and understood that IC devices may have systematic changes in characteristic parameters (such as resistance and capacitance) between devices due to manufacturing batch changes or other reasons. In order to tolerate such process changes between devices, a predetermined range of fringe capacitance values ​​can be dynamically generated for each device. In some embodiments with a high pin count device, the capacitive coupling between multiple pairs of pins is measured to establish an average capacitance, and the capacitive coupling between the welding wires attached to a pair of pins is normalized based on the average capacitance.

[0032] See attached figure, Figure 1 A schematic diagram of a device 100 tested using a test system 10 according to some aspects of the present patent application is shown. The device 100 is a device under test (DUT) including a package 102. A substrate 130 is disposed within the package 102 and may be silicon or other suitable substrate material, and a semiconductor die may be formed by forming circuit elements therein or thereon. These circuit elements may be formed by creating semiconductor, dielectric, and conductive materials on or in a substrate layer to create various logic components, memories, interconnects, movable components for micro-electromechanical (MEMS) applications, and / or other suitable types of circuit elements.

[0033] In some embodiments, the apparatus 100 may include more than one die within the package 102. In such embodiments, the fringe capacitance between the wires connected to each such die may be measured individually or in any other suitable manner.

[0034] Package 102 may include a suitable ceramic, semiconductor, oxide, ceramic composite, or laminate of more than one material. Such a structure may serve as a mounting location for a semiconductor die formed by substrate 130, and may serve as a housing for the die and other components that make up the package. Leads, which may be formed as part of a lead frame, may provide electrical connections from the interior of the package to the exterior. For simplicity, Figure 1 The portions of the leads exposed inside or outside the package are shown as pins.

[0035] exist Figure 1 In the example of FIG. 1 , those pins are represented by pins 111, 112, 113, 114, at least a portion of which may be disposed on an exterior surface of package 102 such that they are electrically accessible from outside device 100. Although four pins are shown in a linear array, it should be understood that the package may have any suitable number of leads and any number of pins may be placed in any suitable arrangement on the exterior of package 102. The portion of the leads external to the package may have any suitable shape and size, such as a conductive pad, a metal pin, a copper pillar, or a conductive structure including a solder ball.

[0036] The outer portions of these leads can be connected to the portions of the leads inside the package 102 to which the wire can be attached. The portions inside the package 102 can similarly be shaped as square or rectangular pads, or have any other suitable shape. The portions of the leads inside and outside the package can be joined by a middle portion, which can also have any suitable shape. Since the shape and position of the inner, outer and middle portions of the pins are not critical to the present invention, all portions of the leads are represented by the same symbol, which is a square here.

[0037] The substrate 130 includes a plurality of connection points 131, 132, 133, 134, each of which is connected to a corresponding pin 111, 112, 113, 114 via a corresponding welding wire 121, 122, 123, 124. Here, a one-to-one relationship between connection points, welding wires, and pins is shown. However, it should be understood that other configurations are also possible, such as multiple welding wires connected to the same pin or the same connection point. In addition, it should be understood that none of the welding wires is shown to cross with other welding wires. It should be understood that the IC device can be designed to have welding wires attached to pins and connection points that require some welding wires to pass through adjacent welding wires.

[0038] The connection points 131, 132, 133, 134 may be pads or traces on the substrate 130 and electrically connected to various elements on the substrate 130. Although the connection points 131, 132, 133, 134 are shown in a linear array, it should be understood that any number of connection points may be formed on the substrate 130 and in any suitable arrangement.

[0039] like Figure 1 As shown, there may be additional connection points 135 on the substrate 130 that are not connected by wire bonds. For example, the substrate 130 may be a silicon substrate, and the connection points 135 may be electrically connected to the silicon substrate 130. The connection points 135 may also be disposed on any surface of the substrate 130 to provide an electrical path. For example, the connection points 135 may be placed on the bottom of the substrate 130 so that when the bottom surface of the substrate 130 is mechanically mounted on the surface of the package 102, the electrical connection between the connection points 135 may be achieved via the surface of the package or via pins on the package 102 that are electrically coupled to the connection points 135 to provide a path for biasing the substrate 102. Therefore, it should be understood that although Figure 1 Examples of mechanisms for making electrical connections for testing are provided as described herein, but other mechanisms for achieving electrical pathways may alternatively or additionally be used.

[0040] like Figure 1 As shown, the welding wires 121, 122 are spaced apart from each other so that they are separated by a distance 125, which provides a first capacitive coupling between these welding wires. In some embodiments, the welding wires 121, 122 have an appropriate or typical spacing from each other so that they are less likely to cause a hard short circuit, and therefore they are not positioned to produce a potential defect of a near short circuit. On the other hand, the welding wires 123, 124 have a shape that is bent toward each other to be separated by a distance 126, which provides a second capacitive coupling greater than the first capacitive coupling. In this example, if the welding wires 123, 124 are further bent to contact, the distance between them may become a hard short circuit, and therefore be positioned to produce a potential defect of a near short circuit. According to one aspect of the present patent application, determining that the second capacitive coupling between the welding wires 123 and 124 is greater than expected can provide a basis for identifying the presence of a potential defect in a pair of welding wires. Such determination can be achieved by comparing the second capacitive coupling with the first capacitive coupling between the welding wires 121 and 122 or by comparing the capacitive coupling of the welding wires 123 and 124 of the previously measured device. In some embodiments, the semiconductor device is tested for potential defects by measuring the capacitance between pins connected to a pair of wires. This test can be performed on all possible wire pairs, or in some embodiments, can be performed on a subset of possible wire pairs (such as wire pairs that are positioned close enough according to the design of the semiconductor device that they can produce potential defects if either or both are not in place).

[0041] The test system 10 may include components for providing an excitation signal 12 to the device 100 and for measuring a response 14 from the device 100. The test system 10 may be configured with multiple instruments that can generate the excitation signal. Commercially available test systems include multiple instruments that generate and measure AC signals and DC signals. In addition, the test system 10 may include a timing circuit so that the instrument that generates the excitation signal and the instrument that measures the response signal can be synchronized, so that the response to a specific excitation signal can be determined. The excitation signal and the measured response signal can be AC ​​signals with amplitude and phase characteristics. In some embodiments, the signal can be determined in a phase-sensitive manner. In one embodiment, the test system can calculate the orthogonal real signal components and imaginary signal components corresponding to the resistance measurement value and the reactance measurement value. This allows the capacitive current to be separated from any resistive current that may exist in a given measurement.

[0042] In addition, the test system may include or operate with components that connect specific inputs and outputs of instruments within the tester to specific connection points on the device under test. These components may include switching circuits so that instruments can be connected to connection points on the device under test at different times during the test process.

[0043] In a production environment, these instruments are controlled to generate and measure specific test signals at specific times, and the test system is configured so that these instruments are connected to different connection points at different times. Therefore, the operation of the test system is controlled by a program. In some embodiments, the test system 10 can be an ATE, which includes a computer 20 having a storage medium 21, a memory 23 and a processor 25, and such processing can be performed in the computer 20 or any other computing device. The storage medium 21 and the memory 23 can be any suitable non-transient computer-readable medium, such as, for example and not limited to, a circuit configuration or other tangible computer storage medium in a computer memory, a high-density optical disk, an optical disk, a magnetic tape, a flash memory, a field programmable gate array or other semiconductor device. In some embodiments, the storage medium 21 can be a non-volatile storage device, and the memory 23 can be a volatile storage device. Computer executable instructions can be loaded from the storage medium 21 to the memory 23 before being executed by the processor 25. However, the difference between the storage medium 21 and the memory 23 is not critical, and in some embodiments, either or both can exist.

[0044] Processor 25 may be any suitable processing device, such as, for example and without limitation, one or more processors, central processing units (CPUs), digital signal processors (DSPs), controllers, addressable controllers, general or special purpose microprocessors, microcontrollers, addressable microprocessors, programmable processors, programmable controllers, dedicated processors, dedicated controllers, or any other suitable processing device. In addition, it should be understood that Figure 1 is a schematic diagram of a test system 10. Actual implementations may have distributed processing. For example, a host may control the overall flow of the test and analyze the results. The test system may include one or more dedicated processors, each of which controls an instrument or group of instruments that generates and / or measures test signals.

[0045] Figure 2A To illustrate the operation of the test system 10 according to some aspects of the present patent application to test Figure 1 1 is a schematic flow chart of an exemplary method 200A for detecting welding wire defects in the device 100 shown in FIG. The test may be performed on the pins coupled to the welding wire pair within the device under test. In some embodiments, the overall average test time may be reduced by testing for hard opens and hard shorts in the welding wire before testing for potential defects. Figure 2A In the exemplary method 200A shown, in operation 201, the device is tested to identify hard shorts and hard opens between a portion or all of the pin pairs. Any suitable method for testing hard opens or hard shorts can be used for the test, such as but not limited to capacitance or impedance measurement. At operation 203, if the result of operation 201 indicates that there are one or more hard shorts or hard opens between the welding wires, the method 200A proceeds to optional operation 205, where the manufacturing process can be modified to correct the hard open / hard short defects identified in operation 201 in future manufacturing processes, and the method 200A will then end. When the test does not identify a hard short or hard open defect, the method 200A proceeds to perform a test for potential defects. In operation 207, a predetermined capacitance range is selected, which represents the expected edge capacitance value of the device with welding wires that do not have a near short potential defect. At operation 209, based on the predetermined capacitance range, the potential defects of the device are tested at the plurality of pins.

[0046] Figure 2B To illustrate some aspects of the present patent application, a method for operating the test system 10 to identify Figure 1 100. According to some aspects, the method 200B may be Figure 2A An exemplary implementation of operation 209 in method 200A. Figure 2BIn the illustrated embodiment, method 200B represents a test that can be performed on a pair of pins coupled to a corresponding pair of welding wires. Potential defects detected for the pair can display potential defects of the IC device. In order to determine that the IC device to be tested does not have a potential defect, all or multiple pairs of pins connected to the pair of welding wires can be tested, and these welding wires can be close enough to produce a near short circuit without forming a hard short circuit or a hard open circuit. Testing performed in this order can allow the test of the near short circuit state to be omitted in the presence of a hard short circuit or a hard open circuit.

[0047] like Figure 2B As shown, at operation 202, a stimulus signal 12 is provided from the test system 10 to the device 100. At operation 204, a response 14 is measured and received by the test system 10. Figure 1 The response 14 shown indicates capacitive coupling between the wires, such as capacitive coupling 126 between wires 123, 124. The response 14 is then used at operation 206 to determine a value for the fringe capacitance that provides the capacitive coupling between the pair of wires under test.

[0048] In some embodiments, an AC impedance method is used to measure capacitance. For example, the excitation 12 may be an AC voltage signal, and the response 14 may be an AC current in response to the AC voltage excitation. The impedance value Z may then be calculated based on the divisor of the root mean square (rms) value of the AC voltage signal and the AC current, which is used to calculate the capacitance C using Z=1 / (2πfC), where f is the frequency of the AC excitation signal 12. It should be understood that aspects of the present patent application are not limited to the use of an AC impedance method, and any reasonable manner of providing an excitation signal, measuring a response, and determining capacitance may be used in operations 202, 204, and 206. For example, a quasi-static capacitance measurement based on the timed accumulation of charge on a capacitor plate may be used to measure the capacitance value between two pins.

[0049] In addition, it should be understood that it is not necessary to convert the measured electrical parameter into a capacitance value via calculation. Instead, in some embodiments, many of the variables required to calculate the capacitance from one measurement to the next may be the same, so that the value indicating the capacitance may be based on the measurement. For example, in the above formula, the measurement frequency may be the same for all measurements, so that the capacitance may be inversely proportional to the measured impedance. In such embodiments, a comparison of the measured impedance with a range of impedance values ​​may be suitable for determining whether the capacitance is within a specific range.

[0050] Regardless of the specific calculation used to derive the capacitance value representative of the measurement, at operation 208 of method 200B, the determined capacitance is compared to a predetermined range of appropriate edge capacitances. If the determined capacitance value is within the predetermined range, method 200B ends and determines that the device 100 is unlikely to fail due to a potential defect in the tested welding wire pair. Method 200B may include determining at operation 214 whether continued testing of another pair of pins is required. If so, method 200B will restart at operation 202 to test a new pair of pins. If no more pins are to be tested, such as when the plurality of pins on the device under test have been tested for potential defects, method 200B may proceed to end.

[0051] On the other hand, if at operation 208 it is found that the determined capacitance value is outside of a predetermined range representing the edge capacitance of the pair of welding wires being tested, then method 200B also includes providing, at operation 210, an indication that the apparatus 100 has a potential defect and may be faulty. In some embodiments, the predetermined range may be a single-ended range. For example, the range may be defined by an upper threshold, and a capacitance measured above the upper threshold may indicate a potential defect. In some other embodiments, the predetermined range may be double-ended and may include a lower threshold. A capacitance measured below the lower threshold may indicate a potential defect, for example as an indication that the distance between the welding wires being tested is abnormally high compared to an appropriate distance, inferring that the welding wires being tested may have been disturbed and may form a near short circuit with other welding wires.

[0052] After operation 210, method 200B may optionally include operation 212, wherein the manufacturing process may be modified to correct potential defects in future manufacturing processes, and method 200B may then end.

[0053] The stimulation 12 and measurement 14 may be achieved by test probes connected to pins which in turn are coupled to the pair of wires being tested. Figures 3 and 4 show two alternative ways in which such connections may be made.

[0054] Figure 3A A schematic diagram illustrating an exemplary implementation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application. Figure 3A The device under test 300 is shown with a first pin 1 and a second pin 2 on a package 302. The AC voltage source S1 and the transimpedance amplifier M1 can be implemented by instruments within the test system. For example, the AC voltage source S1 can generate an excitation signal 12, and the transimpedance amplifier M1 can measure a response signal 14 ( Figure 1 ).

[0055] Pin 1 is connected to wire 1, and pin 2 is connected to wire 2. The fringe capacitance between wire 1 and wire 2 is C3. Wire 1 and wire 2 are each also connected to a substrate within package 302 and have respective parasitic substrate capacitances C1 and C2 with the substrate. Figure 3A The connection of the source and measurement instruments to the device under test is shown so that the value of C3, which represents the inclusion of C1 and C2, can be measured.

[0056] Device 300 has connection points 335 electrically connected to a substrate. In some embodiments, the substrate may be a silicon die, and connection points 335 may be pads on a side surface or bottom surface of the substrate and configured to electrically connect to a silicon body within the die. However, any suitable method for connecting to the substrate may be used.

[0057] Figure 3A A 2-wire configuration is shown for testing potential defects in the device 300. Figure 3A In the example shown, AC voltage source S1 is configured to provide an AC voltage excitation signal Vs relative to ground voltage 304 at excitation output S. It should be understood that "ground" need not be at ground potential. Rather, "ground" may be any voltage that serves as a suitable reference.

[0058] According to one aspect of the present patent application, the AC voltage excitation signal is a sinusoidal voltage signal having a frequency between 1 Hz and 500 kHz, between 100 Hz and 10 kHz, or between 1 kHz and 100 kHz (all inclusive). The inventors have recognized and understood that when an AC voltage is applied to a capacitor, a higher frequency will result in a lower impedance from the capacitor and a higher AC current amplitude in response. Therefore, in some embodiments, a high voltage signal frequency can result in a higher response current amplitude and a larger measured response signal.

[0059] According to another aspect, the AC voltage excitation signal V s The peak amplitude or peak voltage of V may be kept smaller than the characteristic voltage of the components in the substrate of IC device 300. For example, V s The characteristic voltage may be kept below the transistor turn-on voltage of the transistor so that the applied excitation voltage signal does not cause the transistor to turn on, which may result in more conductive paths within the device 100 to support current flow, which may interfere with the measurement of the small edge capacitance C3. In some embodiments, the characteristic voltage may be a junction voltage across a pn junction in one or more devices, such as a pn junction across a diode in an electrostatic discharge (ESD) protection circuit in the IC device 300. In some embodiments, the AC voltage excitation signal V sThe peak amplitude or peak voltage may be between 0.3V and 0.1V, between 0.3V and 0.65V, or between 0.3V and 0.45V (all inclusive).

[0060] C3 represents the capacitive coupling between adjacent wires, such as those connected to pins 1 and 2, as shown in Figure 3A As shown. In some embodiments, a voltage stimulus may be applied to each pin of the device while measuring the response current through the substrate. This value represents the capacitance between the wires adjacent to the wire attached to the stimulated pin. The response of each pin may be mapped and compared to a predetermined range to determine if there is a potential defect associated with the wire. The response may be measured using a transimpedance amplifier M1.

[0061] See also Figure 3A The transimpedance amplifier M1 is configured to convert the current 308 measured at the measurement input terminal M into an output voltage V0 proportional to the measured current 308. The measurement input terminal M is coupled to the inverting input terminal of an operational amplifier (op-amp) 306, wherein the non-inverting input terminal of the op-amp 306 is coupled to the ground voltage. The output terminal is connected to the feedback impedance Z f is coupled to the inverting input. As a result of the feedback, the amplifier will reach a steady state where the voltage at the inverting input is equal to the voltage at the non-inverting input. As will be appreciated by one of ordinary skill in the art, the inputs of an op-amp draw a near zero amount of current and have the same potential voltage, so the measurement input M can be considered a "virtual ground" having the same potential as the ground voltage, and the current I entering the inverting input terminal of the op-amp 306 is B Op-amp306 and feedback impedance Z f coupled together to form a transimpedance amplifier M1, so that the output voltage V o With input current 308 and impedance Z f is proportional to the product of .

[0062] To measure the wire edge capacitance C3 using a 2-wire configuration, an excitation output S is provided to one point in the device 300, a measurement input M is coupled to another point in the device 300, and the capacitance value is measured based on the current response measured at M using an AC impedance method. Figure 3A In the example shown, the excitation signal is provided by the excitation output S at Pin 1, while the current 308 is measured by the transimpedance amplifier M1 at the connection point 335 to the substrate.

[0063] The relationship between the value measured by the transimpedance amplifier M1 and the fringe capacitance can be understood as follows: Figure 3AIn the example shown, the measured current response 308 represents the current I flowing through C1, C2, and C3, respectively. X1 ,I X2 , Ix3 combination. Effective impedance Z eff The magnitude of the AC excitation voltage signal at S can be measured from the current response 308. eff is associated with C1, which is in parallel with the series combination of C2 and C3. Therefore, if C1 and C2 are known quantities based on, for example, previous and separate measurements, the measured effective impedance Z eff Can be used to infer the value of C3.

[0064] However, as described above, it is not required to explicitly calculate the value of C3. Instead, the techniques as described herein may operate based on measurements indicative of the value of C3. For example, such results may be achieved by comparing the measured current response with the expected current response when C3 is within a range corresponding to appropriately spaced wires, or conversely reaches a range corresponding to wires that are close enough together to present an undesirably high risk of failure. The appropriate range or ranges may be determined by calculation and / or measurement on known good equipment. The appropriate ranges may be determined for each pair of wires. These ranges may also be adjusted for process variations, as described below in conjunction with Figure 6 As described, or adjustments are made for any other variables that may affect the range indicating appropriate and / or improper spacing between welding wires.

[0065] In some embodiments, the measurement may be adjusted for parasitic capacitance. For example, the circuits within M1 and S1 may present various parasitic capacitances within themselves. For example, even without the M1 and S1 test device 300 and by leaving the measurement input M and the excitation output S floating, M1 may measure a non-zero amount of AC current in response to the AC excitation voltage signal Vs in S1. This is due to the contribution of the parasitic capacitive coupling between M1 and S1, and may be particularly noticeable when both M1 and S1 are integrated as part of a test system. In some embodiments, a baseline capacitance test may be performed without hooking up the device under test, and later subtracted when testing the wire capacitive coupling of the device under test in order to correct for background parasitic capacitance from the measurement device itself.

[0066] As an example of another variation of the testing techniques described herein, it will be appreciated that an excitation signal may also be applied at a connection point to a substrate while measuring a current response via one or more pins of the device under test.

[0067] It should also be understood that the connection points 335 to the substrate need not be used for applying the excitation signal or for measuring the current response. In another exemplary variation, the substrate may be left floating, and both the application of the excitation signal and the measurement of the current response are performed at the pins of the device under test. For example, Figure 3B Another 2-wire configuration for testing defects in device 300 is shown, where the substrate is floating. Figure 3B As shown in the exemplary configuration in FIG. 1 , the excitation signal is provided at pin 1 and the current response 309 is measured at pin 2. The measured current response 309 represents the combination of the currents flowing through C1, C2, and C3. The effective impedance Z eff It can be measured from the current response 309 based on the magnitude of the AC excitation voltage signal at S. eff is associated with C3, which is in parallel with the series combination of C1 and C2. Thus, if C1 and C2 are known quantities based on, for example, previous and separate measurements, the measured effective impedance Z eff Can be used to infer the value of C3.

[0068] Figure 4A A schematic diagram illustrating another exemplary implementation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application. Figure 4A A 3-wire configuration is shown for testing potential defects in device 400 that can reduce or eliminate the effects of substrate capacitances C1 and C2 when measuring small fringe capacitance C3. Figure 4A An embodiment of the invention may use a combination of Figure 3A The same components as described above are used to perform the measurement indicating the value of C3. However, as Figure 3A As can be seen from a comparison with FIG. 4 , these components are connected to the device under test in different ways. Different ranges of measured values ​​may indicate the presence of a potential defect, or conversely, the absence of a potential defect. However, the appropriate range may be determined and / or adjusted in a similar manner.

[0069] exist Figure 4A In the example shown, an AC voltage excitation signal Vs is applied to pin 1 while pin 2 is coupled to the measurement input M of the transimpedance amplifier M1 to measure the response current 408 at pin 2. A third connection point on the device 400 is established at a connection point 435 to the substrate. In some embodiments, the connection point 435 is coupled to a reference voltage so that the substrate is maintained at a constant level at the reference voltage. In some embodiments, the connection point 435 connects the substrate to the reference level. The connection point 435 can be directly coupled to the reference voltage level represented as ground, or in one example, the connection point 435 can be coupled to a ground guard node G on the package 402 of the device 400.

[0070] The reason why the measured current indicates C3 can be understood as follows: During testing of the device 400, pin 2 is coupled to a virtual ground at the measurement input M, and therefore pin 2 has the same ground potential as the substrate. Therefore, no current flows through C2. The current driven through capacitor C1 will flow into the grounded substrate and will not appear in the measured response current 408. When the voltage excitation signal V s When applied to Pin 1, the current I x1 By V s Driven to flow through the fringe capacitance C3 between wire 1 and wire 2. Because pin 2 has the same potential as the substrate, I x1 will continue to flow into pin 2 and become the response current 408 that can be measured by the transimpedance amplifier M1 as a whole. In other words, the measured response current 408 represents the entire I flowing through C3. x1 The current is applied to the voltage excitation signal V applied to C3 via pins 1 and 2. s response without any contribution from substrate capacitance C1 or C2.

[0071] When measuring the current I through C3 x1 When the voltage excitation signal V s The amplitude of the AC impedance method is used to calculate the value of C3. Therefore, Figure 4A The configuration shown can be used to subtract the effect of parasitic capacitance on the measured current and directly measure the relatively small fringe capacitance C3 between the two pins, and direct measurement of the capacitive coupling of adjacent wires becomes possible. Figure 3A Compared to the configuration of Figure 4A In the example, the response current 408 at the input terminal M of the transimpedance amplifier M1 only represents the small edge capacitance C3, so a higher front-end amplifier sensitivity can be used to amplify the response current 408 and improve the output voltage V o For example, combining Figure 4A , the transimpedance amplifier can have a front-end sensitivity in the range of 1V / A to 10V / A (inclusive), while combining Figure 3A , the transimpedance amplifier may have a front-end sensitivity of 0.1 V / A to 1 V / A (inclusive). In some embodiments, the edge capacitance value may be resolved into a range between 10 fF and 50 pF, between 20 fF and 20 pF, or between 20 fF and 10 pF.

[0072] The inventors have recognized and understood that Figure 4A The 3-wire configuration shown and Figure 3AThe 2-wire configurations shown may each have certain unique advantages for testing potential defects. For example, in a 2-wire configuration, background parasitic capacitance variations between tests at different pins may affect the accuracy of the fringe capacitance tested at different pins, whereas in a 3-wire configuration, parasitic capacitance does not affect the measurement. Further, and without wishing to be bound by a particular theory, for a 2-wire configuration, since only one pin is tested at a time, there is no need to obtain information about which wires are close to each other within the package, whereas for a 3-wire configuration, pairs of pins are tested, and prior art knowledge of how the pins correspond to the locations of wires within the device under test would be required to verify that the fringe capacitance tested by the pair of pins corresponds to wires positioned adjacent to each other.

[0073] Figure 4B A schematic diagram illustrating another exemplary implementation of a method of operating a test system to identify potential defects in a device according to some aspects of the present patent application. Figure 4B A variation of a 3-wire configuration for testing potential defects in device 400 is shown, which is similar in many respects to Figure 4A Configuration shown. Figure 4B An embodiment of the invention may use a combination of Figure 4A The same components as described above are used to perform the measurement indicating the value of C3. However, as Figure 4B and Figure 4A As can be seen from the comparison of the components, these components are connected to the device under test in different ways. Different ranges of measured values ​​may indicate the presence of a potential defect, or conversely, the absence of a potential defect. However, the appropriate range may be determined and / or adjusted in a similar manner.

[0074] exist Figure 4B In the example shown, the ground guard node G is coupled to the input of the transimpedance amplifier, for example Figure 4B The non-inverting input terminal of the transimpedance amplifier is shown to equalize the potentials between G and M. In some embodiments, connecting the guard node G to the non-inverting input terminal of the transimpedance amplifier can be referred to as a remote guard sensing configuration because the non-inverting input terminal of the transimpedance amplifier remotely senses the ground potential or other reference potential on the guard node G. According to one aspect of the present patent application, remote sensing of the guard node G can help eliminate the effects of IR or jwL based AC voltage drops based on the finite impedance at the connection between the guard node G and ground, so that the voltage on C2 will be forced to be substantially zero.

[0075] Figure 5 A bar graph showing an example of a series of measured pin capacitances and predetermined capacitive coupling ranges according to some aspects of the present patent application. For the same pin on each of the six chips, a 2-wire unprotected configuration (similar to Figure 3AThe cluster shows the minimum, average, and maximum values ​​of the capacitance measured for each of the six chips, where Min is the minimum value for each of the six chips and Max is the maximum recorded measurement value for the pins of all devices. The measured capacitance values ​​represent the combination of capacitances C1, C2, and C3, as shown in FIG. Figure 3A As shown and discussed above.

[0076] In this example, none of the chips have a hard short or open for those pins, but the one designated as Chip 0 has a potential defect. Figure 5 It is shown that chips with potential defects can be easily distinguished from good chips. Figure 5 A predetermined range 502 is shown, which in this example is between about 4.3 pF and 4.5 pF, within which a device may be considered free of latent defects and unlikely to fail. The predetermined range 502 may be set to cover a plurality of known good devices (e.g., Figure 5 The static range of capacitance values ​​measured between pairs of pins in chips 1, 2, 3, 4 and 5) is shown. Figure 5 Also shown is a known bad chip 0 with a nearly shorted bond wire, which has a measured pin capacitance of between 4.65 pF and 4.7 pF, which is outside of the predetermined range 502 .

[0077] like Figure 5 As shown, the data illustrates a method of setting a predetermined range against which to compare values ​​indicative of edge capacitance between wire bonds in order to determine if there is a potential defect involving those wire bonds. The difference between good chips and chips with potential defects is stable and repeatable. Thus, by measuring a sufficient number of chips, an acceptable range can be determined, and a range indicative of a defect or a threshold value reflecting the difference between measurements of good and defective chips can be selected. The range can be expressed as a capacitance, such as Figure 5 However, if combined with Figure 3A and Figure 4A As described above, the response representing the fringe capacitance may be measured as a voltage representing the current. These ranges and / or thresholds may be presented as measured currents and / or voltages rather than being converted into capacitances.

[0078] Figure 6 A bar graph is provided to illustrate a method of adjusting the range and / or threshold value applicable to a particular IC device. The inventors have recognized and appreciated that IC devices may have systematic variations in characteristic parameters such as resistance, capacitance between devices due to, for example, manufacturing batch variations. These variations may be compensated for. Figure 6 Shown is a series of measured pin capacitances on two devices measured using the techniques described herein.

[0079] like Figure 6 As shown, within device IC1, the pin capacitance measurements are systematically lower than the pin capacitance measurements within device IC2. Such variation patterns may be caused by process variations within a semiconductor manufacturing facility, causing IC devices manufactured at different times to have different characteristics. In order to tolerate such process variations from device to device, the capacitive coupling between the wires of different IC devices may be normalized to a reference IC device before determining whether the measured capacitive coupling is within a predetermined range. Alternatively, a predetermined range may be normalized, as the resulting comparison will be similarly normalized. Figure 6 It is shown how such normalization can be performed.

[0080] Figure 6 The pin capacitance of multiple pins on each of two IC devices (designated IC1 and IC2) is shown. The measurements were made using techniques as described herein so that the pin capacitance indicates the fringing capacitance associated with the wires connected to the pins being measured as well as the parasitic capacitances C1 and C2 in FIG. 3. Figure 6 , IC1 may be a reference IC device having a predetermined range of good pin capacitance values ​​601 based on measured pin edge capacitance. Good pin capacitance values ​​may be determined, for example, by first identifying outliers 602, 603, 604. Any suitable statistical method may be used to select outliers, such as values ​​that are several standard deviations above the mean. The predetermined range of good pin capacitance 601 for IC1 may then be selected based on the statistical distribution of the remaining pin capacitance values ​​that are not outliers.

[0081] IC1 may represent an IC device used to determine these ranges, and the measured values ​​representing the edge capacitance are compared relative to these ranges to determine whether the IC device has a potential defect. In contrast, IC2 may represent an IC device manufactured at a different time, such that the measured values ​​of the edge capacitance for a good pair of wires are different. Nevertheless, the measured values ​​of chip IC2 can be compared to the measured values ​​of IC1 via a normalization process.

[0082] After measuring the pin capacitance values ​​of IC2, each of the measured IC2 pin capacitances may be normalized relative to IC1. Normalization may be performed, for example, by scaling the IC2 pin capacitance by a ratio between the average pin capacitances of IC2 and IC1. However, it should be appreciated that any suitable scaling method may be used to compensate for the systematically higher pin capacitance in IC2.

[0083] In addition, it should be understood that normalization can be used to determine the range and / or threshold value for distinguishing good welding wires from welding wires with potential defects. For example, a nominal average pin capacitance value of an IC device can be established. For each device used as a reference device to determine a predetermined range and / or threshold, the pin capacitance can be measured. The average pin capacitance of the IC device can be calculated, and a scaling factor between the measured average and the nominal average can be calculated. The scaling factor can be applied to all measured values ​​so that the average value of the IC device is equal to the nominal average. These normalized values ​​can be combined with normalized values ​​of other IC devices to determine the range and / or threshold between the normalized values ​​that distinguish good welding wires from welding wires with potential defects. For normalization, the capacitance measured at all pins of the device can be used. Alternatively, a subset of the pins of the IC device can be used for normalization.

[0084] Figure 7 FIG. 7 is a schematic flow chart illustrating an exemplary method 700 for selecting a predetermined capacitance range according to some aspects of the present patent application. According to some aspects, the method 700 may be Figure 2A 200A. At operation 701, method 700 includes measuring a plurality of capacitances between welding wires attached to a plurality of the plurality of pins. At operation 703, method 700 includes calculating an average capacitance between the welding wires based on the plurality of measured capacitances. At operation 705, method 700 includes normalizing a capacitance providing a capacitive coupling between a welding wire attached to a first pin and a welding wire attached to a second pin based on the average capacitance.

[0085] Having described several aspects of at least one embodiment of the present invention, it should be appreciated that various changes, modifications, and improvements may be readily made by those skilled in the art.

[0086] For example, although chip package level testing is described, the testing method may also be applied to printed circuit board (PCB) level testing, where one or more IC chips are mounted on a PCB.

[0087] Such changes, modifications and improvements are intended to be part of this disclosure and are considered to fall within the spirit and scope of the present invention. In addition, although the advantages of the present invention are indicated, it should be understood that not every embodiment of the technology described herein will include each of the advantages. Some embodiments may not implement any of the features advantageously described herein, and in some cases, one or more of the features may be implemented to implement additional embodiments. Therefore, the above description and drawings are only by way of example.

[0088] The various aspects of the present invention may be used individually, in combination, or in various configurations not specifically discussed in the above embodiments, and therefore their application is not limited to the details and configurations of the components described in the above description or shown in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

[0089] In addition, the present invention can be implemented as a method, and examples thereof have been provided. The operations performed as part of the method can be ordered in any suitable manner. Therefore, embodiments can be constructed that perform operations in a different order than shown, which can include performing certain operations simultaneously, even though these operations are shown as sequential operations in each exemplary embodiment.

[0090] Such changes, modifications and improvements are intended to be part of this disclosure and are considered to fall within the spirit and scope of the present invention. In addition, although the advantages of the present invention are indicated, it should be understood that not every embodiment of the present invention will include each of the advantages. Some embodiments may not implement any of the features described herein and in some cases that are advantageous. Therefore, the above description and accompanying drawings are only used as examples.

[0091] The use of ordinal terms such as "first", "second", "third", etc. in the claims to modify claim elements does not in itself imply any priority, precedence or sequence of one claim element relative to another, or the temporal order of performing method operations, but is merely used as a label to distinguish one claim element with a certain name from another element with the same name (except for the ordinal term used) to identify the claim elements.

[0092] In addition, the phrases and terms used herein are for illustrative purposes and should not be considered as limiting. "Including," "comprising," or "having," "containing," "involving," and variations thereof used herein are meant to include the items listed thereafter and their equivalents as well as additional items.

Claims

1. A method of operating a test system to identify potential defects in a device, the device comprising a plurality of pins and a substrate, the plurality of pins having bonding wires attached thereto, the bonding wires being electrically connected to connection points on the substrate, the method comprising: providing an excitation signal to the device; measuring a response to the excitation signal, the response indicative of capacitive coupling between a bonding wire attached to a first pin of the plurality of pins and a bonding wire attached to a second pin of the plurality of pins, wherein the excitation signal is provided at the first pin; determining whether a capacitance providing the capacitive coupling is within a predetermined range; as well as When it is determined that the capacitance is outside the predetermined range, an indication that the device may be faulty is provided, wherein: The device further includes an additional connection point not connected by a wire bond, the additional connection point being a pad on a side surface or a bottom surface of the substrate and configured to be electrically connected to the substrate, and Measuring the response includes measuring a current at the additional connection point.

2. The method according to claim 1, wherein: The device also includes a package, the plurality of pins are disposed on the package, and The bond wire attached to the first pin is adjacent to the bond wire attached to the second pin. The method of claim 1 , wherein the predetermined range has an upper limit less than 10 pF. 4 . The method of claim 1 , wherein measuring the current comprises coupling an input of a transimpedance amplifier to the additional connection point, and outputting an output voltage representative of the current from the transimpedance amplifier. 5 . The method of claim 4 , wherein measuring the current further comprises coupling a reference input of the transimpedance amplifier to ground. The method according to claim 1 , wherein the excitation signal is a sinusoidal voltage signal with a first frequency between 1 kHz and 500 kHz. The method according to claim 1 , wherein the excitation signal is a sinusoidal voltage signal with a peak voltage between 0.1V and 0.75V.

8. The method according to claim 1, wherein: The device is a first device, and The method further includes measuring a baseline capacitance between a first pin and a second pin of a plurality of pins of a plurality of second devices; and The predetermined range is determined based on the measured baseline capacitance.

9. The method according to claim 1, further comprising: measuring a plurality of capacitances between bonding wires attached to a plurality of pairs of the plurality of pins; calculating an average capacitance between the welding wires based on the plurality of measured capacitances; as well as The capacitance providing capacitive coupling between the wire attached to the first pin and the wire attached to the second pin is normalized based on the average capacitance.

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