Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, on which fins are formed; forming an isolation structure on the substrate between adjacent fins, wherein the top of the isolation structure is flush with the top of the fin; etching the isolation structure and the substrate between any adjacent fins to form a first opening; filling the first opening with a conductive material to form a power rail, wherein the top of the power rail is lower than the top of the fin. The power rail formed by the method provided in the embodiment of the present invention can free up space for wiring traces in a standard cell, thereby reducing the size of the standard cell and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In the manufacture of integrated circuits, standard cells are often used as basic elements of devices that constitute integrated circuits. Standard cells are arranged and wired to form functional circuits. When used, each standard cell requires a power supply (Vdd) input and a ground (Vss) connection. In order to provide power to its various components, each standard cell is usually coupled to a power rail electrically connected to the active layer of the standard cell to provide power (Vdd). In some cases, multiple power rails can be provided for each standard cell to provide power (Vdd) and ground (Vss) respectively.

[0003] Typically a standard cell is designed to have a stacked structure of various metal layers including wiring traces in which various interconnects are formed to connect various components of the standard cell to each other and to connect various components of the standard cell to other standard cells.

[0004] The power rails in the prior art are usually arranged in one of the metal layers and then connected to the active layer of the standard cell through a path, which will occupy the space in the metal layer used to form wiring traces and various interconnects. In order to increase the response speed of the integrated circuit, the size of the standard cell needs to be expanded to provide a larger wiring trace space, which is not conducive to the further advancement of semiconductor process technology nodes. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the size of a standard unit and improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which fins are formed; forming an isolation structure on the substrate between adjacent fins, wherein the top of the isolation structure is flush with the top of the fin; etching the isolation structure and the substrate between any adjacent fins to form a first opening; filling the first opening with a conductive material to form a power rail, wherein the top of the power rail is lower than the top of the fin.

[0007] Optionally, the conductive material includes ruthenium, copper or graphene.

[0008] Optionally, the method of filling the conductive material includes electrochemical deposition.

[0009] Optionally, the step of etching the isolation structure between any adjacent fins and the substrate includes: first etching the isolation structure between any adjacent fins until the surface of the substrate is exposed to form a first groove; and then continuing to etch a partial thickness of the substrate along the first groove to form the first opening.

[0010] Optionally, the step of etching the isolation structure between any adjacent fins includes: forming a patterned photoresist layer on the surface of the isolation structure; using the patterned photoresist layer as a mask, etching a partial thickness of the isolation structure between any adjacent fins to form a second groove; removing the patterned photoresist layer; forming a first mask layer on the surface of the isolation structure, the sidewalls and the bottom of the second groove; etching the first mask layer to form a second opening, the second opening exposing the bottom of the second groove; etching the isolation structure along the second opening until the substrate surface is exposed to form the first groove.

[0011] Optionally, the step of etching the first mask layer includes: forming a second mask layer on the first mask layer, the second mask layer exposing the first mask layer located at the bottom of the second groove; using the second mask layer as a mask, etching and removing the first mask layer located at the bottom of the second groove to form the second opening.

[0012] Optionally, the material of the first mask layer includes silicon nitride, aluminum nitride or silicon carbide.

[0013] Optionally, the material of the second mask layer includes hydrocarbon polymer.

[0014] Optionally, the steps of forming the power rail include: filling the first opening with conductive material to form a conductive material layer; performing chemical mechanical polishing on the conductive material layer to make the top of the conductive material layer flush with the surface of the first mask layer; and etching a partial thickness of the conductive material layer to form a power rail.

[0015] Optionally, the method for etching the conductive material layer is dry etching, and the process parameters include: the etching atmosphere includes carbon tetrafluoride, boron trichloride, oxygen, chlorine and helium, the etching pressure is 2 to 100 mTorr, and the etching temperature is 0 to 150°C.

[0016] Optionally, a method of etching the isolation structure and the substrate between any adjacent fins includes plasma dry etching.

[0017] Optionally, after forming the power rail, a metal layer is also formed on the power rail.

[0018] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate, on which fins are formed; an isolation structure, located on the substrate between adjacent fins; a power rail, located in the isolation structure and the substrate between any adjacent fins, and the top of the power rail is lower than the top of the fin.

[0019] Optionally, the semiconductor structure further includes: a metal layer located on the power rail.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] A power rail is formed in the isolation structure and the substrate between any adjacent fins, and the top of the power rail is lower than the top of the fin. The power rail and the active layer of the standard cell are located in the same layer, which can release the space used for wiring traces in the metal layer. When the semiconductor structure meets the same reaction speed, the size of the standard cell can be reduced, which is conducive to the advancement of semiconductor technology to the next process node, or under the same standard cell size, there can be more space for wiring traces, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As can be seen from the background technology, the power rail is used to supply power to the standard cell in the integrated circuit. The power rail in the prior art is usually arranged in one or more of the metal layers of the standard cell, and then the power rail between the metal layers is connected through a path or the power rail is connected to the active layer of the standard cell. Usually, the metal layer includes wiring traces, and the more wiring traces, the faster the response speed of the semiconductor structure. The arrangement of the power rail in the metal layer will reduce the space available for the wiring traces, resulting in a decrease in the semiconductor speed and affecting the performance of the semiconductor structure. If you want to improve the performance of the semiconductor, you have to expand the size of the standard cell to provide more space for the wiring traces, which is not conducive to the further advancement of the semiconductor process technology node.

[0024] In order to solve the above problems, the inventors have provided a method for forming a semiconductor structure after research, wherein a first opening is formed in any adjacent isolation structure and the substrate, and a power rail is formed in the first opening. Part of the power rail is buried in the substrate and is on the same layer as the active layer of the semiconductor structure. It does not need to be connected through a path, and the space that can be used for wiring traces in the metal layer of the standard cell can be released. At the same reaction speed, the size of the standard cell can be reduced, or at the same size of the standard cell, more space can be used for wiring traces, thereby improving the reaction speed of the semiconductor structure.

[0025] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figures 1 to 10 It is a structural schematic diagram of each step in a semiconductor structure forming process according to an embodiment of the present invention.

[0027] refer to Figure 1 , providing a substrate 100 on which a fin 110 is formed.

[0028] In this embodiment, the substrate 100 is a silicon substrate; in other embodiments, the substrate 100 may also be a germanium substrate, a silicon-germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0029] In this embodiment, the material of the fin 110 is silicon; in other embodiments, the material of the fin 110 may also be germanium or silicon germanium.

[0030] In this embodiment, the method for forming the fin 110 on the substrate 100 includes: forming a patterned mask layer (not shown) on the substrate 100, the patterned mask layer corresponding to the position where the fin 110 needs to be formed, etching a portion of the thickness of the substrate 100 using the patterned mask layer as a mask, and forming a plurality of discretely arranged fins 110 on the substrate 100.

[0031] It should be noted that Figure 1 The spacings between adjacent fins 110 are shown to be equal, but in an actual semiconductor device, the spacings between fins are not necessarily equal.

[0032] In this embodiment, after the fin 110 is formed, the patterned mask layer may be directly removed; in other embodiments, the patterned mask layer may also be removed after the power rail is subsequently formed.

[0033] It should be noted that the standard cell may be any type of cell and may have different device architectures. In this embodiment, the standard cell is a fin FET, but the present invention is not limited thereto.

[0034] Continue to refer Figure 1 An isolation structure 200 is formed on the substrate 100 between adjacent fins 110 , and the top of the isolation structure 200 is flush with the top of the fin 110 .

[0035] In this embodiment, the material of the isolation structure 200 is silicon dioxide; in other embodiments, the material of the isolation structure may also be silicon oxynitride.

[0036] In this embodiment, the method for forming the isolation structure 200 includes: depositing an isolation material layer on the substrate 100 between adjacent fins 110, wherein the isolation material layer covers the surface of the substrate 100, the side walls and the top surface of the fins 110; performing chemical mechanical planarization on the isolation material layer so that the top of the isolation material layer is flush with the top of the fins 110, thereby forming the isolation structure 200.

[0037] After the isolation structure 200 is formed, the isolation structure and the substrate 100 between any adjacent fins 110 are etched to form a first opening.

[0038] It should be noted that, in the present embodiment, the etching of the isolation structure 200 and the substrate 100 is performed in steps, wherein the isolation structure 200 is first etched until the surface of the substrate 100 is exposed, and then a partial thickness of the substrate 100 is etched.

[0039] Specifically, the step of etching the isolation structure 200 between any adjacent fins 110 includes:

[0040] refer to Figure 2 , a patterned photoresist layer 300 is formed on the surface of the isolation structure 200 .

[0041] In this embodiment, the method for forming the patterned photoresist layer 300 includes: depositing photoresist on the surface of the isolation structure 200, developing and exposing the photoresist to form the patterned photoresist layer 300, wherein the patterned photoresist layer 300 exposes the isolation structure 200 between any adjacent fins 110.

[0042] The position exposed by the patterned photoresist layer 300 is the position where a power rail is to be formed subsequently.

[0043] refer to Figure 3 Using the patterned photoresist layer 300 as a mask, the isolation structure 200 between any adjacent fins 110 is partially etched to form a second groove 210 .

[0044] In this embodiment, the thickness of the etched isolation structure 200 is 1-10 nm.

[0045] In this embodiment, the second groove 210 provides positioning for subsequently forming a first mask layer for etching the isolation structure 200 .

[0046] After the second groove 210 is formed, the patterned photoresist layer 300 is removed by wet etching or ashing process.

[0047] refer to Figure 4 A first mask layer 400 is formed on the surface of the isolation structure 200 , the sidewall 211 and the bottom 212 of the second groove 210 .

[0048] In this embodiment, the method for forming the first mask layer 400 is atomic layer vapor deposition; in other embodiments, the first mask layer 400 may also be formed by chemical vapor deposition or physical vapor deposition.

[0049] In this embodiment, the material of the first mask layer 400 is silicon nitride; in other embodiments, the material of the first mask layer 400 also includes aluminum nitride or silicon carbide.

[0050] After forming the first mask layer 400 , the first mask layer 400 is etched to form a second opening.

[0051] Specifically, the step of etching the first mask layer 400 includes:

[0052] refer to Figure 5 , a second mask layer 500 is formed on the first mask layer 400 , and the second mask layer 500 exposes the first mask layer 400 located at the bottom 212 of the second groove 210 .

[0053] In this embodiment, the second mask layer 500 is formed by atomic layer vapor deposition. In other embodiments, the second mask layer 500 may be formed by chemical vapor deposition or physical vapor deposition.

[0054] In this embodiment, the material of the second mask layer 500 is hydrocarbon polymer.

[0055] refer to Figure 6 , using the second mask layer 500 as a mask, the first mask layer 400 located at the bottom 212 of the second groove 210 is etched away to form a second opening 410 .

[0056] In this embodiment, the process of etching the first mask layer 400 is dry etching.

[0057] After removing the first mask layer 400 located at the bottom 212 of the second groove 210 , the second mask layer 500 is removed by wet etching or ashing process.

[0058] refer to Figure 7 , the isolation structure 200 is etched along the second opening 410 until the surface of the substrate 100 is exposed, thereby forming a first groove 220 .

[0059] In this embodiment, the method for etching the isolation structure 200 is a plasma dry etching process, and the process parameters of the plasma dry etching process include: the etching atmosphere includes trifluoromethane (CHF3), carbon tetrafluoride (CF4), fluoromethane (CH3F) and oxygen, the etching pressure is 5 to 100 mTorr, and the etching temperature is 10 to 120°C.

[0060] refer to Figure 8 , etching a portion of the thickness of the substrate 100 along the second groove 220 to form a first opening 120 .

[0061] In this embodiment, the thickness of the substrate 100 is etched to The specific etching thickness of the substrate 100 is selected according to actual process requirements.

[0062] In this embodiment, the method for etching the substrate 100 is a plasma dry etching process, and the process parameters of the plasma dry etching process include: the etching atmosphere includes hydrogen bromide (HBr), nitrogen trifluoride (NF3), chlorine and oxygen, the etching pressure is 5 to 100 mTorr, and the etching temperature is 10 to 120°C.

[0063] In this embodiment, because the first mask layer 400 retains a portion located on the side wall 211 of the second groove 210, when the isolation structure 200 is subsequently etched using the first mask layer 400 as a mask, a certain thickness of the isolation structure 200 will be retained on both sides of the first groove 220. On the one hand, damage to the fin 110 when etching the isolation structure 200 is avoided; on the other hand, the width of the first groove 220 can be controlled by controlling the thickness of the first mask layer 400 deposited on the side wall 211 of the second groove 210. The width of the first groove 220 corresponds to the size of the power rail formed, thereby controlling the size of the power rail formed.

[0064] After the first opening 120 is formed, a conductive material is filled in the first opening 120 to form a power rail.

[0065] Specifically, the steps of forming the power rail include:

[0066] refer to Fig. 9, the first opening 120 is filled with a conductive material to form a conductive material layer 121 ; the conductive material layer is subjected to chemical mechanical polishing to make the top of the conductive material layer 121 flush with the surface of the first mask layer 400 .

[0067] In this embodiment, the first mask layer 400 can serve as a grinding stop layer for the conductive material layer 121 and can also protect the fin 110 from being damaged.

[0068] In this embodiment, the conductive material is ruthenium (Ru); in other embodiments, the conductive material may also be copper (Cu) or graphene.

[0069] In this embodiment, ruthenium is used as the material for forming the power rail. Ruthenium has good conductivity, high temperature corrosion resistance, and excellent electrical properties. It is an excellent choice to replace original conductive materials such as copper in the next semiconductor technology process.

[0070] In this embodiment, the method of filling the conductive material is electrochemical deposition.

[0071] refer to Fig.10 , etching a portion of the thickness of the conductive material layer 121 to form a power rail 600 . The top of the power rail 600 is lower than the top of the fin 110 .

[0072] In this embodiment, the method for etching the conductive material layer 121 is dry etching, and the etching process parameters include: the etching atmosphere includes carbon tetrafluoride (CF4), boron trichloride (BCl3), oxygen, chlorine and helium, wherein the flow rate of carbon tetrafluoride is 0-100 sccm, the flow rate of boron trichloride is 30-500 sccm, the flow rate of oxygen is 0-100 sccm, the flow rate of chlorine is 0-100 sccm, the flow rate of helium is 50-500 sccm, the etching pressure is 2-100 mTorr, and the etching temperature is 0-150°C.

[0073] After the power rail 600 is formed, the first mask layer 400 is removed by wet etching or ashing process.

[0074] In this embodiment, after the power rail 600 is formed, a metal layer (not shown) may be further formed on the power rail 600 .

[0075] The material of the metal layer includes metal materials such as cobalt, tungsten, copper, ruthenium or platinum.

[0076] The method for forming a semiconductor structure provided by an embodiment of the present invention forms a power rail in the isolation structure and the substrate between any adjacent fins, and the top of the power rail is lower than the top of the fin. The power rail and the active layer of the standard cell are located in the same layer, which can release the space used for wiring traces in the metal layer. When the semiconductor structure meets the same reaction speed, the size of the standard cell can be reduced, which is conducive to the advancement of semiconductor technology to the next process node.

[0077] refer to Fig.10 Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned formation method, comprising: a substrate 100, on which a fin 110 is formed; an isolation structure 200, located on the substrate 100 between adjacent fins 110; a power rail 600, located in the isolation structure 200 and the substrate 100 between any adjacent fins 110, and the top of the power rail 600 is lower than the top of the fin 110.

[0078] In this embodiment, the isolation structure 200 with a certain thickness is still reserved between the power rail 600 and the fin 110 .

[0079] In this embodiment, the material of the power rail 600 is ruthenium; in other embodiments, the material of the power rail 600 may also be copper or graphene.

[0080] In this embodiment, the semiconductor structure further includes: a metal layer (not shown), and the metal layer is located on the power rail 600 .

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, on which a fin is formed; forming an isolation structure on the substrate between adjacent fins, wherein the top of the isolation structure is flush with the top of the fin; Etching the isolation structure and the substrate between any adjacent fins to form a first opening, wherein the method for forming the first opening comprises: etching the isolation structure between any adjacent fins by a portion of the thickness to form a second groove; forming a first mask layer on the surface of the isolation structure, the sidewall and the bottom surface of the second groove; etching and removing the first mask layer at the bottom of the second groove to form a second opening; etching the isolation structure and the substrate along the second opening to form the first opening; A conductive material is filled in the first opening to form a power rail, wherein a top of the power rail is lower than a top of the fin.

2. The method for forming a semiconductor structure according to claim 1, wherein: The conductive material includes ruthenium, copper or graphene.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method of filling the conductive material includes an electrochemical deposition method.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of etching the isolation structure and the substrate between any adjacent fins comprises: Firstly, the isolation structure between any adjacent fins is etched until the substrate surface is exposed to form a first groove; Then, the substrate is etched continuously along the first groove to form a partial thickness thereof to form the first opening.

5. The method for forming a semiconductor structure according to claim 4, wherein: The step of etching the isolation structure between any adjacent fins comprises: forming a patterned photoresist layer on the surface of the isolation structure; Using the patterned photoresist layer as a mask, etching the isolation structure between any adjacent fins of a partial thickness to form a second groove; removing the patterned photoresist layer; forming a first mask layer on the surface of the isolation structure, the sidewall and the bottom of the second groove; Etching the first mask layer to form a second opening, wherein the second opening exposes the bottom of the second groove; The isolation structure is etched along the second opening until the substrate surface is exposed to form the first groove.

6. The method for forming a semiconductor structure according to claim 5, wherein: The step of etching the first mask layer comprises: forming a second mask layer on the first mask layer, wherein the second mask layer exposes the first mask layer at the bottom of the second groove; Using the second mask layer as a mask, the first mask layer located at the bottom of the second groove is etched away to form the second opening.

7. The method for forming a semiconductor structure according to claim 5, wherein: The material of the first mask layer includes silicon nitride, aluminum nitride or silicon carbide.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second mask layer includes hydrocarbon polymer.

9. The method for forming a semiconductor structure according to claim 5, wherein: The steps of forming the power rail include: Filling the first opening with a conductive material to form a conductive material layer; Performing chemical mechanical polishing on the conductive material layer to make the top of the conductive material layer flush with the surface of the first mask layer; A partial thickness of the conductive material layer is etched to form a power rail.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for etching the conductive material layer is dry etching, and the process parameters include: the etching atmosphere includes carbon tetrafluoride, boron trichloride, oxygen, chlorine and helium, the etching pressure is 2-100 mTorr, and the etching temperature is 0-150°C.

11. The method for forming a semiconductor structure according to claim 1, wherein: A method of etching the isolation structure and the substrate between any adjacent fins includes plasma dry etching.

12. The method for forming a semiconductor structure according to claim 1, wherein: After forming the power rail, a metal layer is also formed on the power rail.

13. A semiconductor structure, characterized in that: The method for forming a semiconductor structure according to any one of claims 1 to 12 comprises: a substrate having fins formed thereon; an isolation structure, located on the substrate between adjacent fins; A power rail is located in the isolation structure and the substrate between any adjacent fins, and a top of the power rail is lower than a top of the fin.

14. The semiconductor structure according to claim 13, wherein: Also includes: A metal layer is located on the power rail.

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