Method of forming pattern

Abstract

In the method for forming a pattern, a target layer is formed on a semiconductor substrate, and a plurality of first spacers having a cylindrical shape protruding from the target layer are formed. A second spacer is formed to cover the first spacers, provide gap spaces between the first spacers, and provide second internal spaces respectively within the first internal spaces of the first spacers. The second spacer is etched to form a first opening portion in which the second internal space and the gap space extend into the target layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0124037, filed on October 7, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a pattern. Background Art

[0004] When integrating the circuits of electronic devices into semiconductor substrates, efforts have been made to integrate a large number of patterns in a limited area. The integration of electronic devices or semiconductor devices is increasing, and efforts will be made to achieve fine patterns of smaller sizes. In order to form a dense array of contact holes with nanoscale line widths at the level of several nanometers (nm), various patterning techniques have been tried.

[0005] Given the limitations of the image resolution of photolithography equipment, there are still limitations in forming fine patterns below a certain size. It is difficult to form fine patterns at the nanometer level in a single exposure process. In order to overcome the resolution limitations of photolithography technology to form dense and fine-sized patterns, technologies that overlap several patterning steps, such as triple patterning technology, have been tried. Summary of the invention

[0006] The present disclosure provides a method for forming a pattern. The method for forming a pattern may include: forming a target layer on a semiconductor substrate; forming a plurality of first spacers, each of which has a cylindrical shape protruding from the target layer; forming a second spacer, the second spacer being formed to cover the first spacers, provide a gap space between the first spacers, and provide a second internal space within the first internal space of the first spacer; and etching the second spacer to form a first opening portion, in which the second internal space and the gap space extend into the target layer.

[0007] The present disclosure provides a method for forming a pattern according to another example. The method for forming a pattern may include: forming an array of line patterns on a semiconductor substrate; forming a base layer covering the line patterns; forming a target layer on the base layer; forming a plurality of first spacers, each of which has a cylindrical shape protruding from the target layer; forming a second spacer layer, the second spacer layer being formed to: cover the first spacers, provide gap spaces between the first spacers, and provide second internal spaces within the first internal spaces of each first spacer, respectively; etching the second spacer layer to form a first opening portion, in which the second internal space and the gap space extend in the target layer, thereby patterning the target layer, and using the target layer pattern as an etching mask, performing a transfer of the first opening portion pattern to the base layer and the line pattern.

[0008] The present disclosure provides a method for forming a pattern according to another example. The method for forming a pattern may include: forming a target layer and a buffer layer on a semiconductor substrate including a first region and a second region; selectively etching the buffer layer to form a first buffer layer pattern providing a second opening portion in the first region, and forming a second buffer layer pattern spaced apart from the first buffer layer pattern in the second region; forming a first spacer on the target layer to cover the first buffer layer pattern and the second buffer layer pattern; forming a local shielding pattern on the spacer to expose the first spacer covering the first buffer layer pattern and cover to shield the second buffer layer pattern; etching the first spacer portion exposed by the local shielding pattern to form a first sub-spacer located on the inner side of the first buffer layer pattern and having a protruding cylindrical shape, located on the first The invention relates to a method for preparing an outer side surface of a buffer layer pattern, a protruding second sub-spacer facing a second buffer layer pattern, and a third sub-spacer mask extending from the first spacer to at least cover the second buffer layer pattern; removing the first buffer layer pattern; forming a second spacer, the second spacer being formed to cover the first spacer, the second spacer providing a gap space between the first spacers, and providing a second internal space respectively within the first internal space of each first spacer; and etching the second spacer to form: a first target layer pattern, the first target layer pattern providing a first opening portion formed by extending the second internal space and the gap space, the second target layer pattern overlapping the second sub-spacer and the third target layer pattern overlapping the second buffer layer pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 17 is a schematic diagram illustrating a method of forming a pattern according to an embodiment of the present disclosure.

[0010] Figures 18 to 22 is a schematic diagram illustrating a method of forming a pattern according to another embodiment of the present disclosure.

[0011] Figures 23 to 32 is a schematic diagram illustrating a method for forming a pattern according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The terms used herein may be consistent with the words selected in view of their functions in the embodiments, and the meanings of the terms may be interpreted differently according to the intentions or habits of the technicians in the field to which the embodiments belong. If defined in detail, the terms may be interpreted according to these definitions. Unless otherwise defined, the terms used herein have the same meanings as those generally understood by the ordinary technicians in the field to which the embodiments belong.

[0013] In the description of the examples of the present disclosure, terms such as "first" and "second", "top" and "bottom or lower" are intended to distinguish components, but are not used to limit the components themselves or to indicate a specific order. The terms indicate a relative positional relationship, but do not limit a specific case where another component is further introduced at one component or is in direct contact with another component. The same explanation can be applied to other expressions describing the relationship between elements.

[0014] Hereinafter, various examples of the embodiments will be described below with reference to the accompanying drawings. Various examples of the embodiments are described herein with reference to a cross-sectional view, which is a schematic diagram of various examples of the embodiments (and intermediate structures). Therefore, changes in the illustrated shapes, such as due to manufacturing techniques and / or tolerances, are expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but may include shape deviations, such as those caused by manufacturing. In the accompanying drawings, the lengths and sizes of the layers and regions may be exaggerated for clarity. The same reference numerals in the accompanying drawings represent the same elements. It should be understood that when an element or layer is referred to as being "on" another element or layer, or "connected to" or "coupled to" another element or layer, it may be directly on other elements or layers or possible insertion elements or layers, or directly connected or coupled to other elements or layers or possible insertion elements or layers. On the contrary, when an element is referred to as being "directly" "on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no insertion element or layer.

[0015] For ease of description, spatial relative terms, such as "below", "below", "below", "above", "above", etc., may be used herein to describe the relationship between an element or feature as shown in the figure and another element or feature. It should be understood that in addition to the directions depicted in the drawings, spatial relative terms are also intended to cover different directions of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, examples of the term "below" can include both "above" and "below" directions. The device can be oriented in other ways (rotated 90 degrees or other directions), and the spatial relative descriptions used herein are interpreted accordingly.

[0016] It should be understood that, although the terms first, second, third, etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, without departing from the teaching of the present disclosure, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0017] The embodiments of the present disclosure may be applied to the technical field of implementing integrated circuits such as dynamic random access memory (DRAM) devices, phase change random access memory (PcRAM) devices, or resistive random access memory (ReRAM) devices. In addition, the embodiments of the present disclosure may be applied to the technical field of implementing memory devices such as static random access memory (SRAM) devices, flash memory devices, magnetic random access memory (MRAM) devices, or ferroelectric random access memory (FeRAM) devices, or to the technical field of implementing logic devices in which logic integrated circuits are integrated. The embodiments of the present disclosure may be used in the technical field of implementing various products that require fine patterns.

[0018] Throughout the specification, the same reference numerals refer to the same elements. Even if a reference numeral is not mentioned or described herein with reference to one figure, reference may be made to the reference numeral mentioned or described herein with respect to another figure. In addition, even if a reference numeral is not shown in a figure, reference may be made to the reference numeral mentioned or described herein with respect to another figure.

[0019] Figure 1 2 is a cross-sectional view showing a cross-sectional shape in which a photoresist pattern 100 is formed.

[0020] refer to Figure 1, a photoresist pattern 100 may be formed. The photoresist pattern 100 may be formed in a pattern providing a plurality of third opening portions 110. The plurality of third opening portions 110 may be formed in a through-hole shape having substantially the same size and shape as each other.

[0021] The photoresist pattern 100 may be formed on the buffer layer 200. The buffer layer 200 may be formed on the semiconductor substrate 500. Several layers may also be formed between the semiconductor substrate 500 and the buffer layer 200. A base layer 400 may be formed on the semiconductor substrate 500. The target layer 300 may be formed on the base layer 400, and the buffer layer 200 may be located on the target layer 300. The target layer 300 may be a layer to be patterned by the pattern forming method according to the embodiment, and may be a layer patterned by an etching mask pattern or a hard mask pattern. The base layer 400 may be a layer selectively etched by a hard mask pattern.

[0022] For example, the semiconductor substrate 500 may be a silicon (Si) wafer. The base layer 400 may be a polysilicon layer. The polysilicon layer may be formed to be approximately The target layer 300 may be a layer including a material having an etching selectivity relative to the base layer 400. The target layer 300 may be a layer including a material having a lower etching rate than the base layer 400 during etching of the base layer 400. The target layer 300 may be a layer including various dielectric materials for etching a mask pattern or a hard mask pattern. The target layer 300 may have a multilayer structure in which a plurality of material layers are stacked.

[0023] The target layer 300 may have a multilayer structure including a target main layer 310 and a target cover layer 320 formed thereon. The target main layer 310 may include a carbon layer or a spin-on carbon (SOC) layer. The SOC layer may be formed by a coating process. The carbon layer may be an amorphous carbon layer formed by a deposition process. The target cover layer 320 may include a silicon oxynitride (SiON) layer covering the SOC layer. The SOC layer may be formed to be approximately The thickness of the SiON layer can be formed to be approximately Thickness.

[0024] The buffer layer 200 may be formed on the target layer 300. The buffer layer 200 may be formed as a single layer. It is effective that the buffer layer 200 is formed as a composite layer in which material layers overlap each other. The buffer layer 200 may have a multilayer structure including a buffer main layer 210 and a buffer cover layer 220 formed thereon. The buffer main layer 210 may include a carbon layer or a spin-on carbon (SOC) layer. The buffer cover layer 220 may include a silicon oxynitride (SiON) layer covering the SOC layer. The SOC layer may be formed to be approximately The thickness of the SiON layer can be formed to be approximately The buffer capping layer 220 may be formed as a bottom anti-reflective coating (BARC) of the photoresist pattern 100. The BARC may be used as an auxiliary layer in a photolithography process of forming the photoresist pattern 100.

[0025] The third opening 110 of the photoresist pattern 100 may be formed in a hole shape, the bottom of which exposes a portion of the surface of the buffer layer 200. The third opening 110 of the photoresist pattern 100 may be formed in a hole shape, the bottom of which exposes a portion of the surface of the SiON layer of the buffer capping layer 220.

[0026] Figure 2 is a cross-sectional view showing a cross-sectional shape in which a buffer layer pattern 201 is formed.

[0027] refer to Figure 2 , a portion of the buffer layer 200 exposed by the third opening portion 110 may be selectively etched and removed using the photoresist pattern 100 as an etching mask pattern. The exposed portion of the buffer layer 200 may be removed, and the second opening portion 209 of the buffer layer may be formed in a hole shape substantially penetrating the buffer layer 200. The buffer layer 200 may be patterned into a buffer layer pattern 201 providing the second opening portion 209. The plurality of second opening portions 209 provided by the buffer layer pattern 201 may each have a shape substantially identical to the shape of each third opening portion 110 of the photoresist pattern 100. The second opening portion 209 may be formed in a hole shape, the bottom of which exposes a portion of the surface of the target layer 300. The second opening portion 209 may be formed in a hole shape, the bottom of which exposes a portion of the surface of the target capping layer 320.

[0028] After forming the buffer layer pattern 201 , the photoresist pattern 100 may be selectively removed.

[0029] Figure 3 2 is a plan view showing a planar shape of the second opening 209 of the buffer layer pattern 201 . Figure 4 It is shown along Figure 3 A cross-sectional view of the cross-sectional shape of the cutting line XX'. Figure 4 It is shown that a first spacer layer 600 is formed on the buffer layer pattern 201 .

[0030] refer to Figure 3, the buffer layer 201 may provide an array of a plurality of second openings 209. In a plan view, the second openings 209 may be arranged in a square or a rhombus. In a plan view, the second openings 209 may be arranged to be located at the vertices of the square or the rhombus. The second openings 209 may be arranged so that the spacing distance D between any second opening 209-1 and another second opening 209-2 among the second openings 209 is smaller than the radius R of the second opening 209. The second opening 209-1 may be formed to have a radius R greater than the spacing distance D from the other most adjacent second openings 209-2.

[0031] Figure 4 2 is a cross-sectional view showing a cross-sectional shape in which a first spacer layer 600 is formed on the buffer layer pattern 201 .

[0032] refer to Figure 4 , a first spacer 600 covering the buffer layer pattern 201 may be formed. The first spacer 600 may be formed to extend to cover the side 202 and the upper surface 203 of the buffer layer pattern 201 and the surface portion 303 of the target layer 300 exposed at the bottom of the second opening 209. The first spacer 600 may be formed to extend to cover the surface portion 303 of the target layer 300 exposed at the bottom of the second opening 209 continuous with the side 202 of the buffer layer pattern 201 to provide a concave first internal space 609.

[0033] The first spacer layer 600 may include a dielectric material layer having an etching selectivity with respect to the buffer layer pattern 201 or the buffer body layer 210. The first spacer layer 600 may include a layer of a dielectric material different from the buffer layer pattern 201 or the buffer body layer 210. The first spacer layer 600 may include a silicon oxide layer, for example, having a dielectric material of about The first spacer layer 600 may include a dielectric material layer having an etching selectivity with respect to the underlying target layer 300 or the target body layer 310. The first spacer layer 600 may include a dielectric material layer having an etching selectivity with respect to the amorphous carbon layer or the SOC layer.

[0034] Figure 5 and Figure 6 1 and 2 are a sectional view and a plan view respectively showing a cross-sectional shape and a plan shape in which the spacer layer 600 is divided into a plurality of parts to form the first spacer 601 .

[0035] refer to Figure 5 and Figure 6, a first spacer 601 covering the side 202 of the buffer layer pattern 201 may be formed. The first spacer 600 may be spacer-etched so that it remains only on the side 202 of the buffer layer pattern 201, thereby separating a portion of the first spacer 600 into the first spacer 601. Spacer etching may be performed by an anisotropic etching process using a fluorinated carbon (CFx)-based gas. Some portions of the first spacer 600 covering the upper surface 203 of the buffer layer pattern 201 and another portion of the first spacer 600 covering the partial surface portion 303 of the target layer 300 may be removed by spacer etching, and only another portion of the first spacer 600 covering the side 202 of the buffer layer pattern 201 may be retained, thereby forming the first spacer 601. The first spacer 601 may be formed to cover the side 202 of the buffer layer pattern 201 and expose the upper surface 203 of the buffer layer pattern 201 and some surface portions of the target layer 300.

[0036] When the first spacer 601 exposes some surface portions 303 of the target layer 300, Figure 4 The first internal space 609 of the buffer layer pattern 201 may extend to become a first internal space 609-1, exposing a portion of the surface portion 303 of the top of the target layer 300. The first spacer 601 may be formed to provide the first internal space 609-1 extending inside the first spacer 601, respectively. The first internal space 609-1 may be formed in the shape of a through hole, which substantially penetrates the structure including the buffer layer pattern 201 and the first spacer 601. The first internal space 609-1 may be formed in the shape of an opening portion, which exposes some of the surface portion 303 of the target layer 300. The inner side 601SI of the first spacer 601 may be exposed to the first internal space 609-1 as a side facing the first internal space 609-1.

[0037] Figure 7 and Figure 8 1 and 2 are a sectional view and a plan view respectively showing a cross-sectional shape and a plan shape of the first spacer 601 protruding from the target layer 300 .

[0038] refer to Figure 7 and Figure 8 , the buffer layer pattern can be selectively removed ( Figure 5201). For example, the buffer cover layer 200 portion of the buffer layer pattern 201 may be etched and removed, and then a plasma etching process using oxygen (O2) may be performed to etch away the SOC layer forming the buffer body layer 210. Therefore, while maintaining the first inner space 609-1 inside the first spacer 601, some other surface portions 304 of the target layer 300 may be exposed outside the first spacer 601. The exposed other surface portions 304 of the target layer 300 may be portions where the buffer layer pattern 201 is to be removed and exposed.

[0039] The first spacers 601 may each have a cylindrical shape protruding from the target layer 300. The first inner space 609-1 may be positioned in a concave or through-hole shape within the cylindrical shape of each first spacer 601. A plurality of first spacers 601 may be formed to be arranged at predetermined intervals, such as Figure 8 The structure including the first spacer 601 and the first inner spacer 609-1 may be positioned at the second opening 209 (see Figure 3 ) overlap. The inner side 601S1 of the first spacer 601 may be exposed to the first inner space 609-1 as a side facing the first inner space 609-1. The outer side 601S0 of the first spacer 601 may be exposed on a side opposite to the inner side 601S1 of the first spacer 601. The first spacer 601 may be placed on the surface of the target layer 300 so that the outer sides 601S0 of the first spacer 601 face each other.

[0040] Fig. 9 and Fig.10 2 are a cross-sectional view and a plan view showing a cross-sectional shape and a plan shape in which the second spacer layer 700 is formed to cover the side surface of the first spacer 601. Fig.10 In the figure, in order to clearly show the gap space 708 and the second inner space 709, the bottom 705 of the second spacer layer is not shaded. The bottom 705 of the second spacer layer overlaps with the gap space 708 and the second inner space 709.

[0041] refer to Fig. 9 and Fig.10 , the second spacer layer 700 may be formed to cover the surfaces of the first spacer 601 and the target layer 300. The second spacer layer 700 may be formed to extend to cover the surface portions 303 and 304 of the target layer 300 exposed by the first spacer 601, and to cover the shape of the first spacer 601. The second spacer layer 700 may be formed to conformally cover the shape of the first spacer 601 along the shape of the first spacer 601.

[0042] The second spacer layer 700 may be formed of a layer of substantially the same material as that forming the first spacer 601. The second spacer layer 700 may include an oxide layer, for example, an ultra low temperature oxide layer.

[0043] The second spacer layer 700 may be formed to include an inner sidewall portion 704, an outer sidewall portion 701, and a bottom portion 705. The bottom portion 705 of the second spacer layer 700 may be a portion that covers the surface portions 303 and 304 of the target layer 300 located outside the first spacer 601. The inner sidewall portion 704 of the second spacer layer 700 may be a portion that covers the inner side 601SI of the first spacer 601. The inner sidewall portion 704 of the second spacer layer 700 may be formed to provide a second internal space 709 therebetween. The second internal space 709 provided by the second spacer layer 700 may be disposed at a position adjacent to the first internal space ( Figure 7 The second inner space 709 provided by the second spacer layer 700 may be a concave space formed inside the first spacer 601.

[0044] The outer sidewall portion 701 of the second spacer 700 may be a portion covering the outer side surface 601SO of the first spacer 601. The outer sidewall portion 701 of the second spacer 700 may extend to surround all outer side surfaces 601SO of the first spacer 601. The outer sidewall portion 701 of the second spacer 700 may be formed to provide a gap space 708 between the first spacers 601, such as Fig.10 When viewed from a plan view, the gap space 708 may be formed to be located at a central portion of four adjacent first spacers 601 .

[0045] The outer sidewall portion 701 of the second spacer layer 700 may extend in the horizontal direction so that the gap space 708 is provided in each central portion of four adjacent first spacers 601. The gap space 708 may be formed to have substantially the same interval as the four first spacers 601 closest to each other arranged around each gap space 708. Therefore, the gap space 708 may be formed at a position where each gap space 708 is evenly spaced from the four second inner spaces 709 closest to each other.

[0046] The gap space 708 may be a concave space provided by the side of the outer sidewall portion 701 of the second spacer 700 and the bottom 705 of the second spacer 700. The gap space 708 may be generated in the process of forming the second spacer 700 by the structural environment of the structure in which the first spacer 601 is formed.

[0047] Fig.11 and Fig.12 It is shown that the formation Fig. 9 and Fig.10 FIG. 7 is a plan view of the detailed sub-processing steps of the second spacer layer 700.

[0048] refer to Fig.11 , when forming the second spacer 700 on the structure in which the first spacer 601 is formed on the target layer 300, at the beginning of the deposition process for forming the second spacer 700, an initial second spacer 700S is formed, the thickness of which is thinner than the thickness of the final second spacer 700. As the process of depositing the second spacer 700 proceeds, initial outer sidewall portions 701-1S and 701-2S ​​of the initial second spacer 700S begin to grow horizontally outward from the outer side surface 601SO of the first spacer 601 (i.e., the first and second spacers 601-1 and 601-2). In some embodiments, the first spacer 601-1 may be referred to as a first individual spacer, and the second spacer 601-2 may be referred to as a second individual spacer.

[0049] The initial first outer sidewall portion 701-1S of the initial second spacer 700S may be formed to surround the outer side 601SO of the first spacer 601-1, and the initial second outer sidewall portion 701-2S ​​of the initial second spacer 700S may be formed to surround the outer side 601SO of the second spacer 601-2. The first spacer 601-1 and the second spacer 601-2 may be two spacers 601 that are closest to and adjacent to each other. The initial first outer sidewall portion 701-1S and the initial second outer sidewall portion 701-2S ​​of the initial second spacer 700S may be formed to face each other at a predetermined interval in the lateral direction.

[0050] refer to Fig.12 and Fig.11 As the process of depositing the second spacer 700 further proceeds, the initial first outer sidewall portion 701-1S and the initial second outer sidewall portion 701-2S ​​of the initial second spacer 700S may grow laterally to gradually approach each other. Accordingly, the growing first outer sidewall portion 701-1F may abut against and contact the growing second outer sidewall portion 701-2F, and the first outer sidewall portion 701-1F and the second outer sidewall portion 701-2F may form an interface 701-3 and contact each other. If the deposition process is further performed while the first outer sidewall portion 701-1F and the second outer sidewall portion 701-2F abut, the interface 701-3 may be further extended. A gap space 708 may be formed at the point where these interfaces 701-3 converge. When the gap space 708 maintains a constant size, the process of depositing the second spacer 700 may be terminated.

[0051] refer to Fig.12 and Fig.10, the second spacer layer 700 may be formed to provide a second internal space 709 and a gap space 708. The second internal space 709 may be located in the first spacers 601, and the gap space 708 may be located in the middle portion between the first spacers 601. In this case, the gap space 708 may be arranged to be equidistant from the surrounding first spacers 601. In some cases, the number of first spacers located around the gap space may vary, but at least three or more first gap members should be arranged at equal intervals around the gap space so that the second spacer layer generates the gap space.

[0052] Fig.13 is a cross-sectional view illustrating an etching process using an etch mask 750 including a first spacer 601 and a second spacer layer 700 .

[0053] refer to Fig.13 The resulting structure including the first spacer 601 and the second spacer 700 may provide an etch mask 750 for patterning the target layer 300 below. An etching process may be performed on the resulting structure in which the etch mask 750 is formed. The etching process may be performed by an anisotropic plasma etching process. The inner sidewall portion 704 and the outer sidewall portion 701 of the second spacer 700 forming the etch mask 750 and the first spacer 601 may provide an etch mask portion that prevents etching.

[0054] The inner sidewall portion 704 and the outer sidewall portion 701 of the second spacer 700 and the portion of the target layer 300 overlapping the first spacer 601 may be portions shielded by the inner sidewall portion 704 and the outer sidewall portion 701 of the second spacer 700 and the first spacer 601 so as not to be etched during the etching process. On the other hand, the bottom 705 of the second spacer 700 of the etch mask 750 is removed during the etching process, so that the other portions of the target layer 300 overlapping the bottom 705 of the second spacer 700 of the etch mask 750 may be portions to be removed and exposed to etching during the etching process. The other portions of the target layer 300 overlapping the bottom 705 of the second spacer 700 of the etch mask 750 may be etched and removed.

[0055] Fig.14 is a cross-sectional view illustrating a process of patterning the target capping layer pattern 321 using the etch mask 750 .

[0056] refer to Fig.14 and Fig.13As the etching process of the etching mask 750 proceeds, the bottom 705 of the second spacer 700 of the etching mask 750 may be removed. The bottom 705 of the second spacer 700 may be relatively thinner than the inner sidewall portion 704 and the outer sidewall portion 701 of the second spacer 700 and the first spacer 601. Therefore, the bottom 705 of the second spacer 700 may be removed first by the etching process performed on the second spacer 700, even when the inner sidewall portion 704 and the outer sidewall portion 701 of the second spacer 700 and the first spacer 601 are retained.

[0057] Because the bottom 705 of the second spacer 700 is removed first, the remaining inner sidewall portion 704 and outer sidewall portion 701 of the second spacer 700 and the first spacer 601 portion can constitute a basic etching mask 750. The etching mask 750 formed as described above can expose certain portions of the target layer 300 overlapping with the bottom 705 of the second spacer 700. The etching mask 750 can expose certain portions of the target capping layer 320 overlapping with the bottom 705 of the second spacer 700. Certain portions of the target capping layer 320 exposed by the etching mask 750 can be exposed to etching by another etching process. Certain portions of the target capping layer 320 exposed by the etching mask 750 can be selectively etched and removed, so that the portion of the target capping layer 320 overlapping with the etching mask 750 can be patterned into a target capping layer pattern 321.

[0058] Fig.15 is a cross-sectional view showing a step of forming a target body layer pattern 311 .

[0059] Reference together Fig.15 and Fig.14 , an etching process using the etching mask 750 may be further performed to selectively etch and remove a portion of the target body layer 310 exposed by the target capping layer pattern 321. A portion of the target body layer 310 overlapping the etching mask 750 and the target capping layer pattern 321 may be patterned into a target body layer pattern 311. A target layer pattern 301 including the target body layer pattern 311 and the target capping layer pattern 321 may be formed. Thereafter, the etching mask 750 may be selectively removed.

[0060] Fig.16 3 is a plan view showing a planar shape of a first opening portion 307 formed in a target layer pattern 301 .

[0061] Reference together Fig.16 and Fig.15 , the target layer pattern 301 may be patterned to provide a pattern of a first opening portion 307. The first opening portion 307 may have a substantially penetrating shape of the target layer 300 ( Fig. 9300) through hole shape or contact hole shape. Fig.16 As shown, the first openings 307 may be arranged in a very dense arrangement.

[0062] The size or diameter of the first opening 307 may be smaller than the size or diameter formed by the photolithography process. Therefore, the first opening 307 may be formed to have a diameter smaller than the size limit formed in the photolithography process. Figure 1 The third opening 110 of the photoresist pattern 100 shown in FIG. 1 has a limit size formed in the photolithography process, then each first opening 307 may be formed to have a size smaller than the third opening 110. The first openings 307 may be arranged at least twice as densely as the third openings 110. The first openings 307 may be arranged as the second openings ( Figure 3 The first opening 307 may be composed of a first group of first openings 309 and a second group of first openings 308. The first group of first openings 309 may be formed in a through-hole shape, which is formed by the second spacer layer ( Fig. 9 The second internal space (700) provided by Fig. 9 The first openings 309 of the first group may be positioned at a position overlapping with the second inner space 709 provided by the second spacer layer 700. The first openings 308 of the second group may be formed in a through-hole shape extending from the gap space ( Fig. 9 The first openings 308 of the second group may be positioned at the gap space ( Fig. 9 708) overlaps.

[0063] Fig.17 4 is a cross-sectional view showing a step of forming a base layer pattern 401 .

[0064] refer to Fig.17 The pattern forming method according to the embodiment can be used to form a pattern on a substrate layer ( Fig.15 The process of forming a fourth opening portion 409 substantially penetrating the base layer 400 in the target layer 400 can be further performed using the target layer pattern ( Fig.15 The exposed portion of the base layer 400 exposed by the target layer pattern 301 may be selectively etched and removed so that a fourth opening portion 409 may be formed in the base layer 400. The base layer pattern 401 providing the fourth opening portion 409 may be formed. The fourth opening portion 409 may have a through-hole shape in which the first opening portion ( Fig.15 and Fig.16 307) extension.

[0065] The pattern forming method may include forming a semiconductor substrate ( Figure 1 The target layer (500) is formed on Figure 1 300), and a plurality of first spacers having cylindrical protrusions ( Figure 7 601) is formed on the target layer 300. The pattern forming method may include forming a second spacer layer ( Fig.10 700), which is formed to cover the first spacer 601, providing a gap space ( Fig.10 708), and respectively to the first inner space ( Figure 7 609-1) provides a second internal space ( Fig.10 709). The pattern forming method may include etching the second spacer layer to form a first opening portion ( Fig.15 307), wherein the second internal space and the gap space extend into the target layer.

[0066] refer to Fig.10 , the second spacer layer ( Fig.10 The second spacer layer 700 may be formed to fill the spacing gap portion between at least two first spacers closest to each other in the first spacer 601. The second spacer layer 700 may be formed to provide a gap space 708 between a portion and another portion of the filling spacing gap portion between at least two first spacers closest to each other. The gap space 708 formed at a position equidistant from at least four first spacers adjacent to each other in the first spacer 601 may be removed. The gap space 708 may be formed to maintain an equal interval with the second inner space 709 surrounding each gap space 708 and disposed closest to each other.

[0067] like Fig.12 As shown, the second spacer layer 700 can grow horizontally from the inner side of the first spacer 601, so that each second internal space 709 follows the shape of the first internal space and is smaller than the size of the first internal space. The second spacer layer 700 can be formed along the outer side ( Fig. 9 The first spacer grows in the direction of 601SO) and at the same time grows in the horizontal direction from the inner side of the first spacer.

[0068] Re-reference Fig.15 and Fig.16 , the target layer pattern 301 providing the first opening portion 307 may be applied to a cutting process for cutting the middle portion of the line pattern, so that the target layer pattern 301 may be used as an etching mask or a hard mask for a selective etching process. The cutting process may refer to a selective etching process that selectively removes some middle portions of the line pattern to separate a plurality of isolation patterns from one line pattern.

[0069] Fig.18 and Fig.19 14 and 15 respectively are a schematic cross-sectional view and a schematic plan view illustrating a cross-sectional shape in which the first opening portion 307 of the target layer pattern 301 overlaps with the line pattern 1450 . Fig.18 Shown along Fig.19 The cross-sectional shapes of the cutting line X1-X1' and the cutting line X2-X2'. Fig. 20 is a schematic plan view showing an array of line patterns 1450 .

[0070] refer to Fig.18 and Fig.19 , a target layer pattern 301 may be introduced on the array of line patterns 1450. The target layer pattern 301 may be introduced to overlap with the array of line patterns 1450 so that the first opening portion 307 of the target layer pattern 301 is positioned to overlap with the middle portion of the line pattern 1450. The target layer pattern 301 may be formed by the above reference Figures 1 to 17 The target layer pattern 301 may be formed to provide an array of first openings 307 .

[0071] refer to Fig. 20 and Fig.18 , the line patterns 1450 may be formed on the semiconductor substrate 500, spaced apart from each other at predetermined intervals. The line patterns 1450 may each be formed in a strip shape extending in an inclined direction with a predetermined line width. The line patterns 1450 may be formed of a dielectric material layer such as a silicon oxide layer or a silicon nitride layer. The base layer 1400 may be formed to cover the line patterns 1450. The base layer 1400 may be formed to be Figure 1 The base layer 400 is substantially the same layer as the base layer 400. The base layer 1400 may be formed to fill the space between the line patterns 1450.

[0072] Fig.21 and Fig. 22 14 and 15 , which are respectively a schematic cross-sectional view showing a cross-sectional shape and a schematic plan view showing a plan shape, in which a target layer pattern 301 is introduced onto an array of line patterns 1450 .

[0073] refer to Fig.21 and 22, the exposed portion 1451 of the line pattern 1450 exposed by the target layer pattern 301 may be selectively etched and removed using the target layer pattern 301 as an etching mask. As the exposed portion 1451 of the line pattern 1450 is selectively removed, each line pattern 1450 may be separated into a plurality of isolation patterns 1450. The exposed portion 1451 of the line pattern 1450 may be removed, and the line pattern 1450 may be broken into a plurality of portions to provide a plurality of isolation patterns 1452. The separated isolation patterns 1452 may be patterned into patterns that overlap with active regions to be disposed in the semiconductor substrate 500, respectively. The region outside the isolation pattern 1452 on the semiconductor substrate 500 may be a device isolation region where an active region is disposed, which region does not overlap with the separated isolation pattern 1452. The separated isolation pattern 1452 may be formed into a pattern that divides and disposes a device isolation region of the semiconductor substrate 500. Thereafter, a portion of the semiconductor substrate 500 exposed by the isolation pattern 1452 may be partially removed using the separated isolation pattern 1452 as an etch mask, thereby forming a device isolation trench.

[0074] Therefore, the target layer pattern 301 patterned by the exemplary pattern forming method can be used as an etching mask or a hard mask in an etching process of separating the line pattern 1450 into a plurality of isolation patterns 1452. In the etching process of separating into the isolation patterns 1452, the target layer pattern 301 can be introduced as a cutting mask for cutting the line pattern 1450.

[0075] The pattern forming method may include forming a semiconductor substrate ( Fig.18 A line pattern is formed on the 500 Fig.18 1450) array, and a base layer ( Fig.18 1400). Target layer ( Fig. 9 300) may be formed on the base layer, and a plurality of first spacers ( Fig. 9 The second spacer layer ( Fig. 9 700) may be formed to cover the first spacers, providing a gap space ( Fig.10 708), and respectively to the first inner space ( Figure 7 609-1) provides a second internal space ( Fig.10 709). The second spacer layer ( Fig.13 700) performs an etching process to form a first opening portion ( Fig.21 307), wherein the second internal space ( Fig.21 609-1) and interstitial space ( Fig.10 708) extends in the target layer so that the target layer pattern ( Fig.21The target layer pattern ( Fig.21 301) as an etching mask, the first opening portion 307 pattern is transferred to the base layer 1400 and the line pattern 1450. The pattern transfer first opening portion 307 can extend the first opening portion so that the first opening portion selectively removes some parts of the line pattern to separate the isolation pattern ( Fig.21 and 22 1452).

[0076] The example of the pattern forming method may be applied to a process of forming a target layer pattern 301 and a spaced peripheral pattern together. The peripheral pattern may be a pattern having a shape different from the shape of the first opening portion provided by the target layer pattern 301. The peripheral pattern and the target layer pattern may be formed together so that the first opening portion 307 is provided in, for example, a cell region of the semiconductor substrate 500, and the peripheral pattern is provided in a peripheral circuit region adjacent to the cell region. The cell region may refer to a region in which a memory cell device is arranged, and the peripheral circuit region may refer to a region in which a circuit for operating the memory cell device is arranged.

[0077] Fig.23 2 is a schematic cross-sectional view showing a cross-sectional shape in which a first photoresist pattern 2100 and a second photoresist pattern 2150 are formed.

[0078] refer to Fig.23 , a first photoresist pattern 2100 and a second photoresist pattern 2150 may be formed. The first photoresist pattern 2100 may be formed to provide a pattern of a plurality of third opening portions 2110, such as Figure 1 Each third opening 2110 may be formed to provide Figure 3 The first photoresist pattern 2100 may be formed on the first region 2501 of the semiconductor substrate 2500. The first region 2501 of the semiconductor substrate 2500 may be a cell region.

[0079] The second photoresist pattern 2150 may be formed in the second region 2501 of the semiconductor substrate 2500. The second region 2502 of the semiconductor substrate 2500 may be a peripheral circuit region. The second photoresist pattern 2150 may be a pattern of various peripheral patterns that may be required in the peripheral circuit region. The first photoresist pattern 2100 may be a pattern for providing the third opening portion 2110, and the second photoresist pattern 2150 may be a pattern for providing a peripheral pattern having a shape different from that of the third opening portion 2110.

[0080] The second photoresist pattern 2150 may be formed together with the photoresist pattern 2100. The second photoresist pattern 2150 and the first photoresist pattern 2100 may be separate patterns in the same photoresist layer. The second photoresist pattern 2150 and the first photoresist pattern 2100 may be formed by a photolithography process of forming a photoresist, exposing the photoresist layer, and developing.

[0081] A stack of the base layer 2400, the target layer 2300, and the buffer layer 2200 may be formed between the semiconductor substrate 2500 and the first photoresist pattern 2100 and the second photoresist pattern 2150. The stack of the base layer 2400, the target layer 2300, and the buffer layer 2200 may be formed to be Figure 1 The stack of substrate layer 400, target layer 300 and buffer layer 200 shown is substantially the same or similar stack. Figure 1 The stack of the base layer 400, the target layer 300 and the buffer layer 200 shown in the figure is used to form a stack of the base layer 2400, the target layer 2300 and the buffer layer 2200. The target layer 2300 can be formed as a layer including a target main layer 2310 and a target cover layer 2320. The buffer layer 2200 can be formed as a layer including a buffer main layer 2210 and a buffer cover layer 2220. In addition, as shown in FIG. Fig.18 and Fig. 20 The illustrated line pattern 1400 may also be formed between the base layer 2400 and the semiconductor substrate 2500 .

[0082] Fig.24 2 is a schematic cross-sectional view showing a cross-sectional shape in which a first buffer layer pattern 2201 and a second buffer layer pattern 2202 are formed. Fig.25 22 is a schematic plan view showing the planar shapes of the first buffer layer pattern 2201 and the second buffer layer pattern 2202. Fig.24 It is shown along Fig.25 Schematic cross-sectional view of the cross-sectional shape of the cutting line X3-X3'.

[0083] refer to Fig.24 and 25, the first photoresist pattern 2100 and the second photoresist pattern 2150 may be used as an etching mask to selectively etch and remove the portion of the buffer layer 2200 exposed by the first photoresist pattern 2100 and the second photoresist pattern 2150. Accordingly, the first buffer layer pattern 2201 may be formed in the first region 2501 of the semiconductor substrate 2500 to provide a second opening portion 2209 extending from the third opening portion 2100. The pattern shape of the second photoresist pattern 2150 is transferred to the second buffer layer pattern 2202, and the second buffer layer pattern 2202 may be formed in the second region 2502 of the semiconductor substrate 2500. The second buffer layer pattern 2202 may be formed as a pattern spaced apart from the first buffer layer pattern 2201 by a predetermined interval. The second buffer layer pattern 2202 may be patterned in a pattern different from the shape of the second opening portion 2209 (for example, may be a rectangle or a polygon).

[0084] Fig.26 2 is a schematic cross-sectional view illustrating a cross-sectional shape in which a first spacer 2600 is formed in the first buffer layer pattern 2201 and the second buffer layer pattern 2202 .

[0085] refer to Fig.26 , the first spacer layer 2600 may be formed to cover the first buffer layer pattern 2201 and the second buffer layer pattern 2202. Figure 4 The first spacer 2600 may be formed by a process substantially the same as or similar to the process of forming the first spacer 600. The first spacer 2600 may be formed to cover the first buffer layer pattern 2201 and may extend so that the first inner space 2609 is formed in a shape following the shape of the second opening 2209.

[0086] The first spacer 2600 may extend to cover the second buffer layer pattern 2202. When the first spacer 2600 extends to cover the second buffer layer pattern 2202 and the first buffer layer pattern 2201, the first spacer 2600 may extend while generating a concave gap 2608 in the space between the second buffer layer pattern 2202 and the first buffer layer pattern 2201.

[0087] Fig. 27 21 is a schematic cross-sectional view showing a cross-sectional shape in which a partial blocking pattern 2170 is formed.

[0088] refer to Fig. 27, a partial blocking pattern 2170 may be formed on the first spacer 2600. The partial blocking pattern 2170 may be formed as a pattern that opens the first region 2501 of the semiconductor substrate 2500 and covers to block the second region 2502. The partial blocking pattern 2170 may be formed as a pattern that exposes a portion 2604 of the first spacer 2600, the portion 2604 being located at a boundary between the first region 2501 and the second region 2502 of the semiconductor substrate 2500. The exposed portion 2604 of the first spacer 2600 exposed by the partial blocking pattern 2170 may be a portion of the first spacer 2600 that covers a side 2205 of the first buffer layer pattern 2201 facing the second buffer layer pattern 2202. In order to expose the exposed portion 2604 of the first spacer 2600, the partial blocking pattern 2170 may be formed such that one side of the partial blocking pattern 2170 is located in a concave gap 2608 provided by the first spacer 2600.

[0089] The local blocking pattern 2170 may be formed as a photoresist pattern formed through a photolithography process.

[0090] Fig.28 26 is a schematic cross-sectional view showing a cross-sectional shape in which the first spacer 2601 is separated from the first spacer layer 2600.

[0091] Reference together Fig.28 and Fig. 27 , the first sub-spacer 2601 may be formed to cover the inner side of the first buffer layer pattern 2201. The second sub-spacer 2604 may be formed on the outer side 2205 of the first buffer layer pattern 2201, and the outer side 2205 faces the second buffer layer pattern 2202. In addition, the third sub-spacer mask 2606 may be formed to cover the pattern shape of the second buffer layer pattern 2202. As shown in FIG. Figure 5 As described above, the first sub-spacer 2601 may be separated from the first spacer 2600 by performing spacer etching on the first spacer 2600. In addition, the second sub-spacer 2604 and the third sub-spacer mask 2606 may be separated from the first spacer 2600.

[0092] Thereafter, the first buffer layer pattern 2201 may be selectively removed, the first buffer layer pattern 2201 is exposed and the first sub-spacer 2601 and the second sub-spacer 2604 are simultaneously formed. Figure 5The process of removing the first buffer layer pattern 2201 is performed by an etching process substantially the same as the process of removing the first buffer layer pattern 2201. In the etching process of removing the first buffer layer pattern 2201, since the second buffer layer pattern 2202 is blocked by the third sub-spacer mask 2606, the second buffer layer pattern 2202 can maintain a pattern shape. As the first buffer layer pattern 2202 is removed, the first sub-spacer 2601 can be formed to protrude from the target layer 2300. The first sub-spacer 2601 can have a cylindrical shape protruding from the target layer 300, similar to Figure 7 and Figure 8 The first sub-spacer 2601 may be formed by substantially the same process as the process of forming the first spacer 601.

[0093] Fig.29 26 is a schematic cross-sectional view showing a cross-sectional shape in which the second spacer layer 700 is formed to cover the side of the first sub-spacer 2601.

[0094] refer to Fig.29 , the second spacer layer 2700 may be formed to cover the first sub-spacer 2601, the second sub-spacer 2604, the third sub-spacer mask 2606, and the target layer 2300. The second spacer layer 2700 may be formed to cover the structure obtained as follows: wherein the first sub-spacer 2601, the second sub-spacer 2604, and the third sub-spacer mask 2606 are formed on the target layer 2300. Fig. 9 The process described for forming the second spacer layer 700 is substantially the same as the process for forming the second spacer layer 2700 .

[0095] The second spacer layer 2700 may be formed as a layer including a first portion 2701, a second portion 2704, and a third portion 2706. The first portion 2701 of the second spacer layer may be a portion of the second spacer layer covering the first sub-spacer 2601, the second portion 2704 of the second spacer layer may be a different portion of the second spacer layer covering the second sub-spacer 2604, and the third portion 2706 of the second spacer layer may be another different portion of the second spacer layer covering the third sub-spacer mask 2606. The first portion 2701 of the second spacer layer may form a gap space 2708 between the first sub-spacers 2601 and extend to create an inner space 2709 within the cylindrical shape of the first sub-spacer 2601. The first portion 2701 of the second spacer layer may be formed by comparing with the reference Fig.10 The process described for forming the second interior space 709 and the interstitial space 708 is substantially the same process for forming the interstitial space 2708 and the interior space 2709 provided by the first portion 2701 of the second spacer layer.

[0096] The etch masks 2750, 2754, and 2756 may include a first sub-spacer 2601, a second sub-spacer 2604, a third sub-spacer mask 2606, and a second buffer layer pattern 2202. The etch masks 2750, 2754, and 2756 may be used to selectively etch the target layer 2300 below to form a target layer pattern. The etch masks 2750, 2754, and 2756 may be divided into a first portion 2750, a second portion 2754, and a third portion 2756. The first portion 2750 of the etch mask may include a first sub-spacer 2601 and a first portion 2701 of the second spacer layer. The first portion 2750 of the etch mask may be Fig.13 The second portion 2754 of the etch mask may include the second sub-spacer 2604 and the second portion 2704 of the second spacer. The third portion 2756 of the etch mask may include the third sub-spacer mask 2606 and the third portion 2706 of the second spacer.

[0097] Fig.30 2750 , 2754 , and 2756 , are schematic cross-sectional views illustrating a process of etching a target body layer using etching masks 2750 , 2754 , and 2756 .

[0098] refer to Fig.30 , an etching process may be performed on the resulting structure in which etching masks 2750, 2754, and 2756 are formed. Fig.13 and Fig.14 The etching process is performed by a process substantially the same as the etching process described in the previous embodiment. Through the etching process, the target capping layer 2320 of the target layer 2300 can be selectively etched to pattern it into a first target capping layer pattern 2321, a second target capping layer pattern 2324, and a third target capping layer pattern 2325. The first target capping layer pattern 2321 can be patterned as Fig.14 The second target overlay layer pattern 2324 may be patterned as a pattern overlapping the second sub-spacer 2604. The third target overlay layer pattern 2325 may be patterned as a pattern shape including the second buffer layer pattern 2202, the remaining portion of the third sub-spacer mask 2606 (which remains on the side of the second buffer layer pattern 2202), and the remaining portion of the third portion 2706 of the second spacer layer (which remains on the side of the second buffer layer pattern 2202). The third target overlay layer pattern 2325 may be patterned as a pattern substantially overlapping the second buffer layer pattern 2202.

[0099] Fig.31 23 is a schematic cross-sectional view illustrating a process of forming target body layer patterns 2311 , 2314 , and 2315 . Fig.322301 , 2304 , and 2305 .

[0100] Reference together Fig.31 and 32 as well as Fig.30 , an etching process using etching masks 2750, 2754, and 2756 may be further performed to selectively etch and remove a portion of the target body layer pattern 2310, which is exposed by the target capping layer patterns 2321, 2324, and 2325. The portion of the target body layer 2310 overlapping the first portion 2750 of the etching mask and the first target capping layer pattern 2321 may be patterned into a first target body layer pattern 2311. A first target layer pattern 2301 including the first target capping layer pattern 2321 and the first target body layer pattern 2311 may be formed. The first target layer pattern 2301 may be patterned to provide a first opening portion 2307, and the first opening portion 2307 may be aligned with the reference Fig.15 and Fig.16 The first openings 2307 are similar to the first openings 307 described above. The first openings 2307 may each be formed in the shape of a through hole and may be densely formed in the first region 2501 of the semiconductor substrate.

[0101] Another portion of the target body layer 2310 overlapping the second portion 2754 of the etch mask and the second target capping layer pattern 2324 may be patterned as a second target body layer pattern 2314. A second target layer pattern 2304 including the second target body layer pattern 2314 and the second target capping layer pattern 2324 may be formed. The second target layer pattern 2304 may be formed as a pattern adjacent to a boundary portion between the first region 2501 and the second region 2502 of the semiconductor substrate, such as Fig.32 The second target layer pattern 2304 may have a pattern shape different from the first target layer pattern 2301 providing the first opening portion 2307. The second target layer pattern 2304 may be formed in a linear pattern or a stripe pattern.

[0102] Another portion of the target body layer 2310 overlapping the third portion 2756 of the etch mask and the third target capping layer pattern 2325 may be patterned into a third target body layer pattern 2315. A third target layer pattern 2305 including the third target body layer pattern 2315 and the second target capping layer pattern 2325 may be formed. The third target layer pattern 2305 may be formed into a polygonal pattern located in the second region 2502 of the semiconductor substrate, such as Fig.32 The pattern shape of the third target layer pattern 2305 may be different from the first target layer pattern 2301 providing the first opening portion 2307 .

[0103] Therefore, it can be Fig.15The process of forming the target layer pattern 301 providing the first opening portion 307 as shown in FIG. Fig.31 and Fig.32 The process of forming the third target layer pattern 2305 is shown.

[0104] like Fig.23 As shown, the pattern forming method may include: forming a target layer 2300 and a buffer layer 2200 on a semiconductor substrate 2500 including a first region 2501 and a second region 2502. The buffer layer 2200 may be selectively etched to form a first buffer layer pattern ( Fig.24 2201), the first buffer layer pattern provides a second opening ( Fig.25 2209), and forming a second buffer layer pattern ( Fig.24 2202), the second buffer layer pattern is separated from the first buffer layer pattern. The first spacer layer ( Fig.26 2600) may be formed on the target layer to cover the first buffer layer pattern and the second buffer layer pattern.

[0105] Partial Occlusion Pattern ( Fig. 27 2170) may be formed on the first spacer layer to expose the first spacer portion covering the first buffer layer pattern and at least cover the second buffer layer pattern. The first spacer portion exposed by the local shielding pattern may be etched. The first buffer layer pattern ( Fig. 27 2201) and having an inner side surface and a first sub-spacer ( Fig.28 2601), a second sub-spacer ( Fig.28 2604), and a third sub-space mask ( Fig.28 The first buffer layer pattern may be removed.

[0106] The second spacer layer ( Fig.29 2700) may be formed to extend to cover the first sub-spacer and the second sub-spacer and the third sub-spacer mask to provide a gap space ( Fig.29 2708), and the second internal space ( Fig.29 The second spacer layer may be etched so that the first target layer pattern ( Fig.31 2301) is patterned to provide a first opening ( Fig.31 2307), the first opening is formed by extending the second inner space and the gap space in the target layer, the second target layer pattern ( Fig.312304) overlaps with the second sub-spacer, and the third target layer pattern ( Fig.31 The first photoresist pattern (2305) can be formed to overlap with the second buffer layer pattern. Fig.23 2100) and the second photoresist pattern ( Fig.23 2150), the first photoresist pattern provides a third opening ( Fig.23 2110), on which the third opening is to form the second opening ( Fig.24 The buffer layer of 2209) is partially opened, and the second photoresist pattern is connected to the second buffer layer pattern ( Fig.24 2202) overlap.

[0107] These concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive point of view but from an illustrative point of view. The scope of these concepts is not limited to the above description, but is defined by the appended claims, and all unique features within the scope of equivalents should be interpreted as included in the present concept.

Claims

1. A method for forming a pattern, the method comprising: forming a target layer on a semiconductor substrate; forming a plurality of first spacers, each of the first spacers having a cylindrical shape protruding from the target layer; forming a second spacer layer, the second spacer layer being formed to: cover the first spacers, provide gap spaces between the first spacers, and provide a second inner space within the first inner space of the first spacer; as well as etching the second spacer layer to form a first opening portion in which the second inner space and the gap space extend into the target layer, wherein each first spacer has an inner space, an inner side surface and an outer side surface; wherein the inner side faces the first inner space and is exposed to the first inner space; wherein the outer side surface is opposite to the inner side surface; wherein the second spacer layer covers the inner side surface to provide the second inner space, and Wherein, the second spacing layer further covers the outer side surface to provide the gap space.

2. The method according to claim 1, wherein: The second spacer layer is formed to fill a space gap portion between at least two of the first spacers that are closest to each other.

3. The method according to claim 2, wherein: The second spacer layer is formed to provide the gap space between a portion filling the space gap portion and the other portion between two first spacers that are closest to each other.

4. The method according to claim 1, wherein: The second spacer layer is formed to provide the gap space at positions substantially equidistant from at least four first spacers adjacent to each other among the first spacers.

5. The method according to claim 1, wherein: The second spacer layer provides the gap spaces such that each of the gap spaces is substantially equally spaced from the second inner spaces that are closest to each other around the gap spaces.

6. The method according to claim 1, wherein: The second spacer layer is formed to grow from an inner side of the first spacer in a horizontal direction so that the second inner space follows a shape of the first inner space and has a size smaller than that of the first inner space.

7. The method according to claim 6, wherein: The second spacer layer is formed to grow in a direction away from an outer side surface of the first spacer and to grow in a horizontal direction from the inner side surface of the first spacer.

8. The method according to claim 1, further comprising: forming a buffer layer on the target layer; selectively etching the buffer layer to form a buffer layer pattern providing an array of second openings; forming a first spacer layer covering the buffer layer pattern; as well as The first spacer layer is etched to form a first spacer located on a side of the buffer layer pattern from the first spacer layer.

9. The method according to claim 8, wherein: The buffer layer pattern provides the second opening portion, so that a spacing gap between the second opening portion and an adjacent second opening portion is smaller than a radius of the second opening portion.

10. The method according to claim 8, further comprising: A photoresist pattern is formed on the buffer layer, the photoresist pattern providing a third opening portion to an opening portion of the buffer layer where the second opening portion is to be formed.

11. The method according to claim 8, further comprising: forming a base layer between the target layer and the semiconductor substrate; as well as The first opening pattern is transferred onto the base layer using the target layer as an etching mask.

12. The method according to claim 11, wherein: The base layer is formed of a layer including a dielectric material different from that of the target layer.

13. The method according to claim 12, wherein: The base layer includes a polysilicon layer, and Wherein, each of the target layer and the buffer layer includes a double layer of a carbon layer and a silicon oxynitride layer.

14. A method for forming a pattern, the method comprising: forming an array of line patterns on a semiconductor substrate; forming a base layer covering the line pattern; forming a target layer on the base layer; forming a plurality of first spacers, each of the first spacers having a cylindrical shape protruding from the target layer; forming a second spacer layer, the second spacer layer being formed to: cover the first spacers, provide gap spaces between the first spacers, and provide second internal spaces within the first internal spaces of each of the first spacers; etching the second spacer layer to form a first opening in which the second inner space and the gap space extend into the target layer, thereby patterning the target layer; as well as Using the target layer pattern as an etching mask, transferring the first opening pattern to the base layer and the line pattern; wherein each first spacer has an inner space, an inner side surface and an outer side surface; wherein the inner side faces the first inner space and is exposed to the first inner space; wherein the outer side surface is opposite to the inner side surface; wherein the second spacer layer covers the inner side surface to provide the second inner space, and Wherein, the second spacing layer further covers the outer side surface to provide the gap space.

15. The method according to claim 14, wherein: When pattern transfer is performed on the first opening, Portions of the line pattern are selectively removed to extend the first opening portion so that the first opening portion separates the spaced-apart isolation patterns from the line pattern.

16. A method for forming a pattern, the method comprising: forming a target layer and a buffer layer on a semiconductor substrate including a first region and a second region; selectively etching the buffer layer to form a first buffer layer pattern providing a second opening portion in the first region, and to form a second buffer layer pattern spaced apart from the first buffer layer pattern in the second region; forming a first spacer layer on the target layer to cover the first buffer layer pattern and the second buffer layer pattern; forming a local shielding pattern on the first spacer layer, wherein the local shielding pattern exposes the first spacer layer covering the first buffer layer pattern and covers to shield the second buffer layer pattern; Etching the first spacer layer portion exposed by the local shielding pattern to form: a first sub-spacer located on the inner side of the first buffer layer pattern and having a protruding cylindrical shape; a protruding second sub-spacer located on the outer side of the first buffer layer pattern and facing the second buffer layer pattern; and a third sub-spacer mask extending from the first spacer layer to at least cover the second buffer layer pattern; removing the first buffer layer pattern; forming a second spacer layer, the second spacer layer being formed to cover the first sub-spacers, the second spacer layer providing a gap space between the first sub-spacers and providing a second inner space within the first inner space of each of the first sub-spacers; as well as etching the second spacer layer to form: a first target layer pattern providing a first opening portion formed by extending the second inner space and the gap space; a second target layer pattern overlapping the second sub-spacer; and a third target layer pattern overlapping the second buffer layer pattern.

17. The method of claim 16, further comprising: A first photoresist pattern and a second photoresist pattern are formed, the first photoresist pattern providing a third opening portion to open a portion of the buffer layer in which the second opening portion is to be formed, and the second photoresist pattern overlapping the second buffer layer pattern.

18. The method according to claim 16, The first opening is located in the first region. wherein the third target layer pattern is located in the second region, and The second target layer pattern is located between the first opening and the third target layer pattern.

19. The method according to claim 16, in, The third target layer pattern is formed to have a polygonal pattern different in shape from the first opening.

20. The method according to claim 16, in, The second target layer pattern is formed to have a line pattern different in shape from the first opening portion.

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