Integrated Circuit Device and Method of Manufacturing the Same

Abstract

An integrated circuit (IC) device and a method of manufacturing the same are provided. The integrated circuit (IC) device includes: a lower electrode including a main portion having sidewalls and a top portion, the sidewalls having at least one stepped portion, the top portion having a width smaller than the width of the main portion in a lateral direction. An upper support pattern contacts the top portion of the lower electrode. The upper support pattern includes a seam portion. To manufacture the IC device, a molded pattern and an upper sacrificial support pattern are formed on a substrate, and a plurality of holes pass through the molded pattern and the upper sacrificial support pattern. A plurality of lower electrodes are formed inside the plurality of holes. A peripheral space is formed on the molded pattern. An enlarged peripheral space is formed by reducing the width and height of the top portion. An upper support pattern is formed to fill the enlarged peripheral space.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0131687, filed with the Korean Intellectual Property Office on Oct. 22, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present inventive concept relates to an integrated circuit (IC) device, and more particularly, to an IC device including a capacitor and a method of manufacturing the IC device. Background Art

[0003] Due to the development of electronic technology, the downscaling of IC devices has been rapidly progressing, and thus, patterns included in electronic devices have been miniaturized. Accordingly, regarding capacitors having a miniaturized size, there is an increasing expectation to develop a structure capable of improving its capacitance while maintaining desired electrical characteristics. Summary of the Invention

[0004] The present inventive concept provides an integrated circuit (IC) device configured to suppress a failure caused by a bridging phenomenon between adjacent lower electrodes and have improved reliability even when the aspect ratios of a plurality of lower electrodes included in a plurality of capacitors become relatively high and the distance between the respective lower electrodes decreases.

[0005] The present inventive concept also provides a method of manufacturing an IC device, which can suppress a failure caused by a bridging phenomenon between adjacent lower electrodes and have improved reliability even when the aspect ratios of a plurality of lower electrodes included in a plurality of capacitors become relatively high and the distance between the respective lower electrodes decreases.

[0006] According to an aspect of the inventive concept, there is provided an IC device including: a lower electrode including a main portion and a top portion, the main portion longitudinally extending in a vertical direction on a substrate and having sidewalls having at least one stepped portion, and the top portion having a width smaller than the width of the main portion in a lateral direction; and an upper support pattern in contact with the top portion of the lower electrode and extending parallel to the substrate. The upper support pattern includes a seam portion formed inside the upper support pattern at a position separated from the top portion of the lower electrode in the lateral direction.

[0007] According to another aspect of the inventive concept, there is provided an IC device including: a lower electrode extending vertically from a first horizontal level to a second horizontal level on a substrate, the lower electrode including a first stepped portion and a top portion, wherein the first stepped portion is formed at a sidewall of the lower electrode at a third horizontal level between the first horizontal level and the second horizontal level, and the top portion has a top surface at the second horizontal level; and an upper support pattern extending parallel to the substrate at the second horizontal level and contacting the top portion of the lower electrode to support the lower electrode. The upper support pattern includes a seam portion formed inside the upper support pattern at a position laterally spaced apart from the top portion of the lower electrode.

[0008] According to another aspect of the inventive concept, there is provided an IC device including: a plurality of lower electrodes spaced apart from each other on a substrate; an upper support pattern extending in a lateral direction parallel to the substrate, the upper support pattern having a plurality of holes through which the plurality of lower electrodes pass; and a lower support pattern extending in the lateral direction between the substrate and the upper support pattern and contacting each of the plurality of lower electrodes. The upper support pattern includes a seam portion formed inside the upper support pattern at a position laterally spaced apart from the plurality of lower electrodes.

[0009] According to another aspect of the inventive concept, there is provided a method of manufacturing an IC device. The method includes: forming a molding pattern and an upper sacrificial support pattern on a substrate. A plurality of holes pass through the molding pattern and the upper sacrificial support pattern. Forming a plurality of lower electrodes inside the plurality of holes. Forming a peripheral space on the molding pattern by removing the upper sacrificial support pattern such that a top portion of each of the plurality of lower electrodes protrudes above a top surface of the molding pattern. Reducing a width and a height of the top portion of each of the plurality of lower electrodes to form an enlarged peripheral space. Forming an upper support pattern to fill the enlarged peripheral space, the upper support pattern contacting the top portion of each of the plurality of lower electrodes. Removing the molding pattern to expose sidewalls of a first portion of each of the plurality of lower electrodes.

[0010] According to another aspect of the inventive concept, a method of manufacturing an IC device is provided. The method includes: forming a molded structure pattern including a molded pattern and an upper sacrificial support pattern on a substrate. A plurality of holes pass through the molded pattern and the upper sacrificial support pattern. A plurality of sacrificial spacers are formed inside the plurality of holes. The plurality of sacrificial spacers cover upper sidewalls of the molded structure pattern. A plurality of lower electrodes are formed to fill the plurality of holes, and the plurality of lower electrodes are in contact with the plurality of sacrificial spacers. A part of each of the plurality of sacrificial spacers and the upper sacrificial support pattern are removed to form a peripheral space on the molded pattern. The peripheral space exposes top portions of each of the plurality of lower electrodes. The width and height of the top portion of each of the plurality of lower electrodes are reduced. An upper support pattern is formed on the molded pattern. The upper support pattern fills the peripheral space and is in contact with the top portion of each of the plurality of lower electrodes. The remaining part of each of the plurality of sacrificial spacers and the molded pattern are removed to expose sidewalls of each of the plurality of lower electrodes below the top portion.

[0011] According to another aspect of the inventive concept, a method of manufacturing an IC device is provided. The method includes: forming a molded structure pattern including a lower molded pattern, a lower support pattern, an upper molded pattern, and an upper sacrificial support pattern on a substrate. A plurality of holes pass through the lower molded pattern, the lower support pattern, the upper molded pattern, and the upper sacrificial support pattern. A plurality of sacrificial spacers are formed inside the plurality of holes. The plurality of sacrificial spacers cover upper sidewalls of the molded structure pattern. A plurality of lower electrodes are formed to fill the plurality of holes, and the plurality of lower electrodes are in contact with the plurality of sacrificial spacers. A part of each of the plurality of sacrificial spacers and the upper sacrificial support pattern are removed to form a peripheral space on the molded structure pattern. The peripheral space exposes top portions of each of the plurality of lower electrodes. The width and height of the top portion of each of the plurality of lower electrodes are reduced. An upper support pattern is formed on the molded structure pattern. The upper support pattern fills the peripheral space and extends parallel to the substrate. The upper support pattern includes a seam portion at a position separated from the plurality of lower electrodes in a lateral direction. The remaining part of each of the plurality of sacrificial spacers and the upper molded pattern are removed to expose first sidewalls of each of the plurality of lower electrodes between the lower support pattern and the upper support pattern. A part of each of the plurality of lower electrodes is removed from the first sidewalls of each of the plurality of lower electrodes, thereby forming a stepped portion at the first sidewalls of each of the plurality of lower electrodes. The lower molded pattern is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1is a schematic plan layout of some components of a memory cell array region of an integrated circuit (IC) device according to an exemplary embodiment;

[0014] Figure 2A is a plan view of some components of an IC device according to an exemplary embodiment;

[0015] Figure 2B is along Figure 2A a schematic cross-sectional view of some components taken along line 1X - 1X';

[0016] Figure 2C is Figure 2B a cross-sectional view of only some components of the IC device shown in

[0017] Figure 2D and Figure 2E is Figure 2A an enlarged cross-sectional view of a modified example of a partial region of the IC device shown in

[0018] Figure 3 is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0019] Figure 4A is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0020] Figure 4B is Figure 4A a cross-sectional view of only some components of the IC device shown in

[0021] Figure 5 is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0022] Figure 6A is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0023] Figure 6B is Figure 6A a cross-sectional view of only some components of the IC device shown in

[0024] Figure 7A is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0025] Figure 7B is Figure 7A a cross-sectional view of only some components of the IC device shown in

[0026] Figure 8 is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0027] Figure 9Ais a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0028] Figure 9B is Figure 9A a cross-sectional view of only some components of the IC device shown in

[0029] Figure 10 is a schematic cross-sectional view of some components of an IC device according to an exemplary embodiment;

[0030] Figures 11A to 11M is a cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an exemplary embodiment;

[0031] Figures 12A to 12D is a cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an exemplary embodiment; and

[0032] Figures 13A to 13D is a cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments will be described in detail with reference to the drawings. The same reference numerals are used in the drawings to denote the same elements, and their repeated description will be omitted.

[0034] Figure 1 is a schematic planar layout of some components of a memory cell array region of an IC device 10 according to an exemplary embodiment.

[0035] Referring to Figure 1 , the IC device 10 may include a plurality of active regions AC that extend in a third lateral direction which, when viewed from above, is inclined with respect to a first lateral direction (X direction) and a second lateral direction (Y direction). A plurality of word lines WL may cross the plurality of active regions AC and extend longitudinally parallel to each other in the X direction. A plurality of bit lines BL may extend longitudinally parallel to each other in the Y direction on the plurality of word lines WL. Each of the plurality of bit lines BL may be connected to an active region AC through a direct contact DC.

[0036] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. A plurality of conductive landing pads LP (also referred to as "pads") may be formed on the plurality of buried contacts BC. Each of the plurality of conductive landing pads LP may be arranged to at least partially overlap with a buried contact BC. A plurality of lower electrodes LE may be formed on the plurality of conductive landing pads LP and be separated from each other. The plurality of lower electrodes LE may be connected to the plurality of active regions AC through the plurality of buried contacts BC and the plurality of conductive landing pads LP.

[0037] Figure 2A is a plan view of some components of the IC device 100 according to an exemplary embodiment. Figure 2B is along Figure 2A a schematic cross-sectional view of some components taken along line 1X-1X'. Figure 2C is Figure 2B a cross-sectional view of only some components of the IC device 100 shown in

[0038] Referring to Figures 2A to 2C , the IC device 100 may form Figure 1 a part of the IC device 10 shown in Figures 2A to 2C Some components of the IC device 100 are omitted or some components of the IC device 100 are shown briefly in Figures 2A to 2C . However, the configuration of the IC device 100 is not limited to the configuration shown in

[0039] The IC device 100 may include a substrate 110 and a lower structure 120 formed on the substrate 110. The substrate 110 includes a plurality of active regions AC. A plurality of conductive regions 124 may pass through the lower structure 120 and be connected to the plurality of active regions AC.

[0040] The substrate 110 may include semiconductor elements (such as silicon (Si) and germanium (Ge)) or compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The substrate 110 may include a semiconductor substrate, at least one insulating film formed on the semiconductor substrate, or a structure including at least one conductive region. The conductive region may include, for example, a doped well or a doped structure. A device isolation region 112 may be formed in the substrate 110 to define the plurality of active regions AC. The device isolation region 112 may include an oxide film, a nitride film, or a combination thereof.

[0041] In an exemplary embodiment, the lower structure 120 may include an insulating film including a silicon oxide film, a silicon nitride film, or a combination thereof. In other exemplary embodiments, the lower structure 120 may include various conductive regions (e.g., interconnect layers, contact plugs, and transistors) and an insulating film configured to insulate the conductive regions from each other. The plurality of conductive regions 124 may include polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof. The lower structure 120 may include a plurality of bit lines BL described with reference to Figure 1 . Each of the plurality of conductive regions 124 may include a buried contact BC and a conductive bonding pad LP described with reference to Figure 1 .

[0042] An insulating pattern 126P having a plurality of openings 126H may be disposed on a lower structure 120 and a plurality of conductive regions 124. The insulating pattern 126P may include a silicon nitride film, a silicon carbonitride film, a boron-containing silicon nitride film, or a combination thereof.

[0043] A plurality of capacitors CP1 including a plurality of lower electrodes LE1, a dielectric film 160, and an upper electrode UE1 may be located on the plurality of conductive regions 124. Each of the plurality of lower electrodes LE1 may have a column shape that longitudinally extends away from the substrate 110 through the opening 126H of the insulating pattern 126P from the top surface of the conductive region 124 in a vertical (z-axis) direction. The plurality of lower electrodes LE1 may face the upper electrode UE1 with the dielectric film 160 therebetween. Although Figure 2B and Figure 2C an example is shown in which each of the plurality of lower electrodes LE1 has a column shape, the inventive concept is not limited thereto. For example, each of the plurality of lower electrodes LE1 may have a cup shape with a blocked bottom or a cross-sectional structure of a cylindrical shape. An article, layer, or a part of an article or layer described as extending "longitudinally" in a specific direction has a length in the specific direction and a width perpendicular to the direction, where the length is greater than the width.

[0044] Each of the plurality of lower electrodes LE1 and the upper electrode UE1 may include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal oxynitride film, or a combination thereof. In an exemplary embodiment, each of the plurality of lower electrodes LE1 and the upper electrode UE1 may include titanium (Ti), Ti oxide, Ti nitride, Ti oxynitride, cobalt (Co), Co oxide, Co nitride, Co oxynitride, niobium (Nb), Nb oxide, Nb nitride, Nb oxynitride, tin (Sn), Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. For example, each of the lower electrode LE1 and the upper electrode UE1 may include titanium nitride (TiN), cobalt nitride (CoN), niobium nitride (NbN), tin oxide (SnO2), or a combination thereof. The dielectric film 160 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O3), niobium oxide (Nb2O5), cerium oxide (CeO2), titanium oxide (TiO2), germanium oxide (GeO2), or a combination thereof.

[0045] A plurality of lower electrodes LE1 may longitudinally extend in a vertical direction from a first level LV1 to a second level LV2 on a substrate 110. As used herein, the term "level" refers to the distance from the main surface 110M of the substrate 110 in a vertical direction (Z direction or -Z direction). The plurality of lower electrodes LE1 may be supported by a lower support pattern 142P and an upper support pattern 148. Each of the plurality of lower electrodes LE1 may include a first portion 152, a second portion 154, and a top portion 156. The first portion 152 may longitudinally extend in a vertical direction (Z direction) between a conductive region 124 and the lower support pattern 142P. For example, the first portion 152 may extend from the upper surface of the conductive region 124 to a third level LV3. The second portion 154 may longitudinally extend in a vertical direction (Z direction) between the lower support pattern 142P and the upper support pattern 148. For example, the second portion 154 may extend from the third level LV3 to a fourth level LV4. The top portion 156 may have a sidewall in contact with the upper support pattern 148. The top portion 156 may have a top surface at the second level LV2. The first portion 152, the second portion 154, and the top portion 156 may be materially continuous with each other, and the first portion 152 and the second portion 154 may constitute a main portion MP of the lower electrode LE1. The top portion 156 may have a width smaller than the width of the main portion MP in a lateral direction. As used herein, the term "materially continuous" may refer to a structure, pattern, and / or layer formed of the same material simultaneously without an interruption in the continuity of the material forming them. As an example, a "materially continuous" structure, pattern, and / or layer may be a homogeneous monolithic structure.

[0046] A first step portion ST1 may be formed at a sidewall of each of the plurality of lower electrodes LE1 at a third level LV3 between the first level LV1 and the second level LV2. The first step portion ST1 may be formed at a sidewall of the main portion MP of each of the plurality of lower electrodes LE1 between the first portion 152 and the second portion 154.

[0047] A second step portion ST2 may be formed at a sidewall of each of the plurality of lower electrodes LE1 at a fourth level LV4 between the second level LV2 and the third level LV3. The second step portion ST2 may be formed at a sidewall of each of the plurality of lower electrodes LE1 between the second portion 154 and the top portion 156. The top portion 156 may extend from the fourth level LV4 to the second level LV2 in a direction away from the substrate 110.

[0048] In each of the plurality of lower electrodes LE1, the lateral width of the top portion 156 may be smaller than the lateral width of the first portion 152 that extends in the vertical direction between the first level LV1 and the third level LV3. The lateral width of each of the plurality of lower electrodes LE1 may change abruptly with respect to the first step portion ST1 and the second step portion ST2 that serve as boundaries between the first portion 152 and the second portion 154 and between the second portion 154 and the top portion 156, respectively. By using the first step portion ST1 as a boundary, the lateral width of the second portion 154 at a level higher than the first step portion ST1 may be smaller than the lateral width of the first portion 152 at a level lower than the first step portion ST1. In addition, by using the second step portion ST2 as a boundary, the lateral width of the top portion 156 at a level higher than the second step portion ST2 may be smaller than the lateral width of the second portion 154 at a level lower than the second step portion ST2. For example, near the second step portion ST2, the width 154W of the second portion 154 in the lateral direction may be larger than the width 156W of the top portion 156 in the lateral direction.

[0049] Each of the lower support pattern 142P and the upper support pattern 148 may extend in the lateral direction parallel to the substrate 110. For example, the upper and lower surfaces of the lower support pattern 142P and the upper support pattern 148 may be parallel to the main surface 110M of the substrate 110. A plurality of holes 142H through which the plurality of lower electrodes LE1 pass may be formed in the lower support pattern 142P, and a plurality of holes 148H through which the plurality of lower electrodes LE1 pass may be formed in the upper support pattern 148. In addition, a plurality of upper holes UH may be formed in the upper support pattern 148. Although Figure 2A it is shown that each of the plurality of upper holes UH has a planar profile passing through four adjacent lower electrodes LE1, the planar shape of each of the plurality of upper holes UH is not limited to Figure 2A the planar shape shown in and may be variously modified and changed within the scope of the inventive concept. A plurality of lower holes (not shown) having a planar shape corresponding to the planar shape of the plurality of upper holes UH may be formed in the lower support pattern 142P.

[0050] The lower support pattern 142P may be in contact with the first step portion ST1 of each of the plurality of lower electrodes LE1 and support the main portion MP of each of the plurality of lower electrodes LE1 between the first level LV1 and the third level LV3. The lower support pattern 142P may include a silicon nitride film, a silicon carbonitride film, a boron-containing silicon nitride film, or a combination thereof, but is not limited thereto.

[0051] The upper support pattern 148 may be in contact with the sidewalls and the second step portions ST2 of the top portions 156 of each of the plurality of lower electrodes LE1. The top surface of the upper support pattern 148 and the top surface of the top portion 156 may extend in the same plane at the second level LV2. For example, the top surface of the upper support pattern 148 and the top surface of the top portion 156 may be coplanar with each other. The upper support pattern 148 may include a seam portion 148S formed therein. The seam portion 148S may be formed to be separated from the top portion 156 of each of the plurality of lower electrodes LE1 in the lateral direction in the upper support pattern 148, and formed to be separated from the bottom surface of the upper support pattern 148 in the vertical direction. The seam portion 148S may extend continuously or intermittently in a substantially vertical direction at a substantially central portion of the space between the corresponding top portions 156 of two adjacent lower electrodes LE1. The bottom portion of the seam portion 148S may be below the second level LV2 and above the fourth level LV4. When observed in cross-section, the seam portion 148S may be substantially perpendicular to the main surface 110M of the substrate 110. The upper support pattern 148 may include a silicon nitride film, a silicon oxycarbide (SiOC) film, a silicon carbonitride (SiCN) film, a silicon boron nitride (SiBN) film, a silicon boron carbonitride (SiBCN) film, or a combination thereof, but is not limited thereto.

[0052] Figure 2D and Figure 2E is Figures 2B to 2C An enlarged cross-sectional view of a modified example of a partial region including the second step portion ST2 in the IC device 100 shown.

[0053] In an exemplary embodiment, as Figure 2D shown, the second step portion ST2 of each of the plurality of lower electrodes LE1 may include a concave portion E1A in contact with the upper support pattern 148, a convex portion E1B in contact with the dielectric film 160, and a flat portion E1C extending parallel to the main surface 110M of the substrate 110 between the concave portion E1A and the convex portion E1B.

[0054] In other exemplary embodiments, as Figure 2E shown, the second step portion ST2 of each of the plurality of lower electrodes LE1 may include a concave portion E2A in contact with the upper support pattern 148 and a convex portion E2B in contact with the dielectric film 160. The concave portion E2A may be inclinedly connected to the convex portion E2B without a flat portion extending parallel to the main surface 110M of the substrate 110. In reference to Figures 2A to 2CIn the described IC device 100, a relatively large insulation distance can be ensured between the top portions of the respective lower electrodes LE1. Therefore, even if the height of the plurality of lower electrodes LE1 increases and the aspect ratio of the plurality of lower electrodes LE1 relatively increases, failures caused by an undesired bridge phenomenon between adjacent lower electrodes LE1 can be prevented, and the mass production efficiency and reliability of the IC device 100 can be improved.

[0055] Figure 3 is a schematic cross-sectional view of some components of an IC device 200 according to an exemplary embodiment. The IC device 200 can form Figure 1 a part of the IC device 10 shown in

[0056] Referring to Figure 3 and Figures 2A to 2C , the IC device 200 can have a construction substantially the same as that of the IC device 100 described with reference to Figures 2A to 2C . However, the IC device 200 can include an upper support pattern 248 that contacts the sidewalls and the top surface of the top portion 156 of each of the plurality of lower electrodes LE1. The vertical distance from the main surface 110M of the substrate 110 to the top surface of the upper support pattern 248 can be greater than the vertical distance from the main surface 110M of the substrate 110 to the top surface of the top portion 156. The upper support pattern 248 covering the top surface of the top portion 156 of each of the plurality of lower electrodes LE1 can have a thickness D2 of about 1 nm to about 30 nm, but the inventive concept is not limited thereto. A seam portion 248S can be formed in the upper support pattern 248. The detailed configurations of the upper support pattern 248 and the seam portion 248S can be substantially the same as the detailed configurations of the upper support pattern 148 and the seam portion 148S described with reference to

[0057] Figure 4A is a schematic cross-sectional view of some components of an IC device 300 according to an exemplary embodiment. Figure 4B is Figure 4A a cross-sectional view of only some components of the IC device 300 shown in Figure 1 a part of the IC device 10 shown in

[0058] Referring to Figure 4A and Figure 4B , the IC device 300 can have a construction substantially the same as that of the IC device 100 described with reference to Figures 2A to 2CThe structure is substantially the same as that of the described IC device 100. However, in the IC device 300, a plurality of capacitors CP3 including a plurality of lower electrodes LE3, a dielectric film 360, and an upper electrode UE3 may be located on the plurality of conductive regions 124. Each of the plurality of lower electrodes LE3 may include a first portion 352, a second portion 154, and a top portion 156. The first portion 352 may have substantially the same structure as the first portion 152 described with reference to Figures 2A to 2C However, a recessed surface 352R may be formed at the sidewall of the first portion 352 between a first level LV1 and a third level LV3. In addition, a plurality of third step portions (e.g., ST31 and ST32) defining the vertical height of the recessed surface 352R may be formed at the sidewall of the first portion 352.

[0059] A protrusion PR may be formed at the sidewall of each of the plurality of lower electrodes LE3 and protrude toward the lower support pattern 142P. The protrusion PR may be formed between a first step portion ST1 and a third step portion ST32 and contact the lower support pattern 142P. In some embodiments, the upper surface and the lower surface of the protrusion PR may be coplanar with the corresponding upper surface and lower surface of an adjacent lower support pattern 142P. As used herein, terms such as "same", "equal", "flat", or "coplanar" cover substantially the same, including, for example, variations that may occur due to manufacturing processes.

[0060] The detailed structures of the lower electrode LE3, the dielectric film 360, and the upper electrode UE3 may be the same as the detailed structures of the lower electrode LE1, the dielectric film 160, and the upper electrode UE1 described with reference to Figures 2A to 2C respectively.

[0061] Figure 5 is a schematic cross-sectional view of some components of an IC device 400 according to an exemplary embodiment. The IC device 400 may form Figure 1 a part of the IC device 10 shown in

[0062] With reference to Figure 5 , the IC device 400 may have substantially the same structure as the IC device 300 described with reference to Figure 4A and Figure 4B However, the IC device 400 may include an upper support pattern 248 that contacts the sidewall and the top surface of the top portion 156 of each of the plurality of lower electrodes LE3. The upper support pattern 248 covering the top surface of the top portion 156 of each of the plurality of lower electrodes LE3 may have a thickness D4 of about 1 nm to about 30 nm, but the inventive concept is not limited thereto. A seam portion 248S may be formed in the upper support pattern 248.

[0063] Figure 6ASchematic cross-sectional view of some components of the IC device 500 according to an exemplary embodiment. Figure 6B is Figure 6A a cross-sectional view of only some components of the IC device 500 shown in Figure 1 The IC device 500 may form part of the IC device 10 shown in

[0064] Referring to Figure 6A and Figure 6B the IC device 500 may have a construction substantially the same as that of the IC device 100 described with reference to Figures 2A to 2C However, in the IC device 500, a plurality of capacitors CP5 including a plurality of lower electrodes LE5, a dielectric film 160, and an upper electrode UE1 may be located on a plurality of conductive regions 124. Each of the plurality of lower electrodes LE5 may include a first portion 152, a second portion 554, and a top portion 156. The second portion 554 may have a construction substantially the same as that of the second portion 154 described with reference to Figures 2A to 2C However, the sidewall of each of the plurality of lower electrodes LE5 may not include a stepped portion at the fourth level LV4 corresponding to the boundary between the second portion 554 and the top portion 156 in each of the plurality of lower electrodes LE5. The detailed construction of the lower electrode LE5 may be the same as the detailed construction of the lower electrode LE1 described with reference to Figures 2A to 2C

[0065] Figure 7A Schematic cross-sectional view of some components of the IC device 600 according to an exemplary embodiment. Figure 7B is Figure 7A a cross-sectional view of only some components of the IC device 600 shown in Figure 1 The IC device 600 may form part of the IC device 10 shown in

[0066] Referring to Figure 7A and Figure 7B the IC device 600 may have a construction substantially the same as that of the IC device 100 described with reference to Figures 2A to 2C However, in the IC device 600, a plurality of capacitors CP6 including a plurality of lower electrodes LE6, a dielectric film 660, and an upper electrode UE6 may be located on a plurality of conductive regions 124. Each of the plurality of lower electrodes LE6 may include a first portion 152, a second portion 654, and a top portion 156. The second portion 654 may have a construction substantially the same as that of the second portion 154 described with reference to Figures 2A to 2C However, in the lateral direction, the lateral width 654W of the second portion 654 may be smaller than the lateral width 156W of the top portion 156. The second portion 654 of each of the plurality of lower electrodes LE6 may extend longitudinally in the vertical direction between the third level LV3 and the fourth level LV4.​

[0067] The first stepped portion ST61 may be formed at the sidewalls of each of the plurality of lower electrodes LE6 at the third level LV3. The first stepped portion ST61 may be formed at the sidewalls of the main portion MP of each of the plurality of lower electrodes LE6 between the first portion 152 and the second portion 654. The second stepped portion ST62 may be formed at the sidewalls of each of the plurality of lower electrodes LE6 at the fourth level LV4. The second stepped portion ST62 may be formed at the sidewalls of each of the plurality of lower electrodes LE6 between the second portion 654 and the top portion 156. By using the second stepped portion ST62 as a boundary, the lateral width of the top portion 154 at a level higher than the second stepped portion ST62 may be larger than the lateral width of the second portion 654 at a level lower than the second stepped portion ST62. For example, near the second stepped portion ST62, the lateral width 156W of the top portion 156 may be larger than the lateral width 654W of the second portion 654.

[0068] The detailed structures of the lower electrode LE6, the dielectric film 660, and the upper electrode UE6 may be the same as the detailed structures of the lower electrode LE1, the dielectric film 160, and the upper electrode UE1 described with reference to Figures 2A to 2C respectively.

[0069] Figure 8 is a schematic cross-sectional view of some components of the IC device 700 according to an exemplary embodiment. The IC device 700 may form Figure 1 a part of the IC device 10 shown in

[0070] With reference to Figure 8 , the IC device 700 may have a structure substantially the same as that of the IC device 600 described with reference to Figure 7A and Figure 7B However, the IC device 700 may include an upper support pattern 248 that contacts the sidewalls and the top surface of the top portion 156 of each of the plurality of lower electrodes LE6. The upper support pattern 248 covering the top surface of the top portion 156 of each of the plurality of lower electrodes LE6 may have a thickness D7 of about 1 nm to about 30 nm, but the inventive concept is not limited thereto. A seam portion 248S may be formed in the upper support pattern 248.

[0071] Figure 9A is a schematic cross-sectional view of some components of the IC device 800 according to an exemplary embodiment. Figure 9B is Figure 9A a cross-sectional view of only some components of the IC device 800 shown in Figure 1 The IC device 800 may form

[0072] With reference to Figure 9Aand Figure 9B ,the IC device 800 may have a structure substantially the same as that of the IC device 600 described with reference to Figure 7A and Figure 7B . However, in the IC device 800, a plurality of capacitors CP8 including a plurality of lower electrodes LE8, a dielectric film 860, and an upper electrode UE8 may be located on a plurality of conductive regions 124. Each of the plurality of lower electrodes LE8 may include a first portion 852, a second portion 654, and a top portion 156. The first portion 852 may have a structure substantially the same as that of the first portion 152 described with reference to Figures 2A to 2C . However, a recessed surface 852R may be formed at a sidewall of the first portion 852 between a first level LV1 and a third level LV3. In addition, a plurality of third stepped portions (e.g., ST81 and ST82) defining a vertical height of the recessed surface 852R may be formed at the sidewall of the first portion 852.

[0073] A protrusion PR8 may be formed at a sidewall of each of the plurality of lower electrodes LE8 and protrude toward the lower support pattern 142P. The protrusion PR8 may be formed between a first stepped portion ST61 and a third stepped portion ST82 and contact the lower support pattern 142P.

[0074] The detailed structures of the lower electrode LE8, the dielectric film 860, and the upper electrode UE8 may be the same as the detailed structures of the lower electrode LE1, the dielectric film 160, and the upper electrode UE1 described with reference to Figures 2A to 2C respectively.

[0075] Figure 10 is a schematic cross-sectional view of some components of an IC device 900 according to an exemplary embodiment. The IC device 900 may form Figure 1 a part of the IC device 10 shown in

[0076] With reference to Figure 10 , the IC device 900 may have a structure substantially the same as that of the IC device 800 described with reference to Figure 9A and Figure 9B . However, the IC device 900 may include an upper support pattern 248 that contacts a sidewall and a top surface of a top portion 156 of each of the plurality of lower electrodes LE8. The upper support pattern 248 covering the top surface of the top portion 156 of each of the plurality of lower electrodes LE8 may have a thickness D9 of about 1 nm to about 30 nm, but the inventive concept is not limited thereto. A seam portion 248S may be formed in the upper support pattern 248.

[0077] In accordance with the reference to Figures 2A to 10In the IC devices 100, 200, 300, 400, 500, 600, 700, 800, and 900 of the described embodiments, a relatively large insulation distance can be ensured between the respective top portions of the plurality of lower electrodes LE1, LE3, LE5, LE6, and LE8. Therefore, even if the heights of the plurality of lower electrodes LE1, LE3, LE5, LE6, and LE8 increase and the aspect ratios of the plurality of lower electrodes LE1, LE3, LE5, LE6, and LE8 relatively increase, failures caused by an undesired bridging phenomenon between adjacent lower electrodes among the plurality of lower electrodes LE1, LE3, LE5, LE6, and LE8 can be prevented, and the mass production efficiency and reliability of the IC devices 100, 200, 300, 400, 500, 600, 700, 800, and 900 can be improved.

[0078] Figures 11A to 11M is a cross-sectional view showing a process sequence of a method for manufacturing an IC device according to an exemplary embodiment. Reference will be made to Figures 11A to 11M Describe the manufacturing according to an exemplary embodiment Figures 2A to 2C The method of the IC device 100 shown in

[0079] Refer to Figure 11A , a lower structure 120 and a conductive region 124 can be formed on a substrate 110, and an active region AC is defined by a device isolation region 112 in the substrate 110. The conductive region 124 can pass through the lower structure 120 and be connected to the active region AC. Thereafter, an insulating film 126 can be formed to cover the lower structure 120 and the conductive region 124.

[0080] The insulating film 126 can be used as an etch stop layer during subsequent processes. The insulating film 126 can include an insulating material having an etch selectivity with respect to the lower structure 120. In an exemplary embodiment, the insulating film 126 can include a silicon nitride film, a silicon carbonitride film, a boron-containing silicon nitride film, or a combination thereof.

[0081] Refer to Figure 11B , a molding structure MST can be formed on the insulating film 126.

[0082] The molding structure MST may include a plurality of molding films and a plurality of support films. For example, the molding structure MST may include a lower molding film 132, a lower support film 142, an upper molding film 134, and an upper sacrificial support film 144 that are sequentially stacked on the insulating film 126. Each of the lower molding film 132 and the upper molding film 134 may include a material that may have a relatively high etching rate with respect to an etchant including ammonium fluoride (NH4F), hydrofluoric acid (HF), and water, and each of the lower molding film 132 and the upper molding film 134 may be removed by a lift-off process using the etchant. In an exemplary embodiment, the lower molding film 132 and the upper molding film 134 may include an oxide film, a nitride film, or a combination thereof. For example, the lower molding film 132 may include a borophosphosilicate glass (BPSG) film. The BPSG film may include at least one of a first portion in which the concentration of a dopant B (e.g., boron (B)) varies in the thickness direction of the BPSG film and a second portion in which the concentration of a dopant P (e.g., phosphorus (P)) varies in the thickness direction of the BPSG film. The upper molding film 134 may include a multilayer insulating film formed by alternately and repeatedly stacking a silicon oxide film and a silicon nitride film having a relatively small thickness one after another a plurality of times. The specific structure of the molding structure MST is not limited to the above description and may be variously modified and changed within the scope of the inventive concept. The uppermost surface of the molding structure MST may include an oxide etch stop film. The oxide etch stop film may be used as an etch stop film, for example, during the process of wet-etching the upper sacrificial support pattern 144P described below with reference to Figure 11F The process for wet-etching the upper sacrificial support pattern 144P is described.

[0083] Each of the lower support film 142 and the upper sacrificial support film 144 may include a silicon nitride film, a silicon carbonitride film, a boron-containing silicon nitride film, or a combination thereof. In an exemplary embodiment, the lower support film 142 may include the same material as the upper sacrificial support film 144. In other exemplary embodiments, the lower support film 142 may include a material different from the upper sacrificial support film 144. The thickness of the upper sacrificial support film 144 may be greater than the thickness of the lower support film 142, but the inventive concept is not limited thereto, and each of the lower support film 142 and the upper sacrificial support film 144 may be formed to have various thicknesses as needed.

[0084] Referring to Figure 11C , it may be possible to Figure 11BA mask pattern MP is formed on the molded structure MST in the resulting structure. Thereafter, the mask pattern MP can be used as an etch mask and the insulating film 126 can be used as an etch stop layer to anisotropically etch the molded structure MST, thereby forming a molded structure pattern MSP including a plurality of holes BH. The molded structure pattern MSP can include a lower molded pattern 132P, a lower support pattern 142P, an upper molded pattern 134P, and an upper sacrificial support pattern 144P. The upper sacrificial support pattern 144P can include a plurality of holes 144H.

[0085] The mask pattern MP can include a nitride film, an oxide film, a polysilicon film, a photoresist film, or a combination thereof. The process of forming the plurality of holes BH can further include a wet process for the resulting structure obtained by anisotropically etching the molded structure MST. During the process of anisotropically etching the molded structure MST and the wet process for the resulting structure, a portion of the insulating film 126 can be etched together. Thus, an insulating pattern 126P having a plurality of openings 126H exposing the conductive region 124 can be obtained. An etchant including a dilute sulfuric acid peroxide (DSP) solution can be used to perform the wet process according to the exemplary embodiment.

[0086] During the process of wet-processing the resulting structure obtained by anisotropically etching the molded structure MST using an etchant, the wet etching amount of the lower molded film 132 can increase in the direction toward the substrate 110. For example, when the lower molded film 132 includes a BPSG film and the concentration of dopant B or dopant P in the BPSG film increases in the direction toward the substrate 110, the etching amount of the lower molded film 132 by the etchant can increase in the direction toward the substrate 110. Thus, the etching amount of the lower molded film 132 by the etchant can be larger near the bottom surface of the lower molded film 132 than near the top surface of the lower molded film 132. Therefore, after forming the plurality of holes BH, the sidewall of the lower molded pattern 132P exposed at the plurality of holes BH can extend away from the substrate 110 in a direction closer to the normal of the main surface of the substrate 110 than the sidewall of the upper molded pattern 134P exposed at the plurality of holes BH. That is, the angle between the sidewall of the lower molded pattern 132P and the normal of the substrate 110 can be smaller than the angle between the sidewall of the upper molded pattern 134P and the normal of the substrate 110.

[0087] Referring to Figure 11D ,, the mask pattern MP can be removed from the Figure 11C resulting structure, and a plurality of sacrificial spacers 146 can be formed to cover the upper portions inside and outside each of the plurality of holes BH of the molded structure pattern MSP.

[0088] The plurality of sacrificial spacers 146 may include a silicon nitride film, a silicon oxide film, or a combination thereof. The plurality of sacrificial spacers 146 may not be conformally formed on the molded structure pattern MSP, but may be formed on the molded structure pattern MSP to exhibit degraded step coverage. A chemical vapor deposition (CVD) process or a plasma enhanced CVD (PECVD) process may be used to form the plurality of sacrificial spacers 146. By controlling the deposition atmosphere (e.g., temperature, pressure, and plasma formation conditions) for forming the plurality of sacrificial spacers 146 or by considering the adhesion coefficient of the atoms to be included in the sacrificial spacers 146 to control the flow rate of the source gas, the plurality of sacrificial spacers 146 may be formed to cover only the upper portion of the molded structure pattern MSP. In a direction further away from the substrate 110, the plurality of sacrificial spacers 146 may cover the molded structure pattern MSP with a greater thickness or width. The width W11 of the portion of the plurality of sacrificial spacers 146 covering the sidewall of the upper sacrificial support pattern 144P may be greater than the width W12 of the portion of the plurality of sacrificial spacers 146 covering the sidewall of the molded pattern 134P.

[0089] In an exemplary embodiment, the upper sacrificial support pattern 144P may include the same material as the plurality of sacrificial spacers 146. For example, each of the upper sacrificial support pattern 144P and the plurality of sacrificial spacers 146 may include a silicon nitride film. In other exemplary embodiments, the upper sacrificial support pattern 144P may include a material different from the plurality of sacrificial spacers 146. For example, the upper sacrificial support pattern 144P may include a silicon nitride film while the plurality of sacrificial spacers 146 may include a silicon oxide film.

[0090] Referring to Figure 11E , a conductive layer may be formed to fill the plurality of holes BH and cover Figure 11D the top surfaces of the plurality of sacrificial spacers 146 in the resulting structure. Thereafter, the conductive layer and the plurality of sacrificial spacers 146 may be planarized to expose the top surface of the upper sacrificial support pattern 144P. Accordingly, a plurality of conductive patterns 150 including the portions of the conductive layer remaining inside the plurality of holes BH may be formed. A etch-back process or a chemical mechanical polishing (CMP) process may be used to planarize the conductive layer and the plurality of sacrificial spacers 146.

[0091] After obtaining the plurality of conductive patterns 150, a portion of each of the plurality of sacrificial spacers 146 may remain between the plurality of conductive patterns 150 and the molded structure pattern MSP. Each of the plurality of sacrificial spacers 146 remaining on the substrate 110 may have an annular shape covering the upper sidewall of the conductive pattern 150. For example, each of the plurality of sacrificial spacers 146 may surround the upper sidewall of the conductive pattern 150. Due to the plurality of sacrificial spacers 146, the distance between the upper portions of the respective conductive patterns 150 may be increased.

[0092] The plurality of conductive patterns 150 may include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal oxynitride film, or a combination thereof. In an exemplary embodiment, the conductive pattern 150 may include Ti, Ti oxide, Ti nitride, Ti oxynitride, Co, Co oxide, Co nitride, Co oxynitride, Nb, Nb oxide, Nb nitride, Nb oxynitride, Sn, Sn oxide, Sn nitride, Sn oxynitride, or a combination thereof. For example, the conductive pattern 150 may include TiN, CoN, NbN, SnO2, or a combination thereof, but is not limited thereto. The formation of the plurality of conductive patterns 150 may be performed using a CVD process, a PECVD process, a metal organic CVD (MOCVD) process, or an atomic layer deposition (ALD) process.

[0093] Referring Figure 11F , a wet etching process may be used to remove a portion of each of the plurality of sacrificial spacers 146 and the upper sacrificial support pattern 144P from the Figure 11E resulting structure, thereby forming a peripheral space TS that exposes the top portions 156 of the sidewalls of each of the plurality of conductive patterns 150.

[0094] The wet etching process may be performed using an etchant containing phosphoric acid, an etchant containing ammonium fluoride, hydrofluoric acid, and water, or a combination thereof. The wet etching process may be performed using the upper molding pattern 134P as an etch stop layer.

[0095] After the peripheral space TS is formed, the top surface of the upper molding pattern 134P and the top surface of each of the plurality of sacrificial spacers 146 may be exposed at the bottom surface of the peripheral space TS. After the upper sacrificial support pattern 144P is removed, the top portion 156 of each of the plurality of conductive patterns 150 may protrude a first height H1 above the top surface of the upper molding pattern 134P.

[0096] Referring Figure 11G , the top portion 156 of each of the plurality of conductive patterns 150 that protrudes above the top surface of the upper molding pattern 134P may be trimmed in the Figure 11F resulting structure. Accordingly, the width and height of the top portion 156 may be reduced to form an enlarged peripheral space ETS.

[0097] A trimming process can be performed using an etchant capable of selectively etching only the plurality of conductive patterns 150 among the upper molded pattern 134P, the plurality of sacrificial spacers 146, and the plurality of conductive patterns 150 exposed on the substrate 110. For example, when each of the upper molded pattern 134P and the plurality of sacrificial spacers 146 includes a silicon oxide film, a silicon nitride film, or a combination thereof, and the plurality of conductive patterns 150 include TiN, an etchant including sulfuric acid and oxygenated water can be used in the trimming process. After performing the trimming process, the top portion 156 of each of the plurality of conductive patterns 150 can protrude above the top surface of the upper molded pattern 134P by a second height H2 (the second height H2 is smaller than the first height H1), and the distance between the respective top portions 156 of the plurality of conductive patterns 150 can be increased.

[0098] Referring Figure 11H , an upper support film 148L can be formed on the resulting structure of Figure 11G to fill the enlarged peripheral space ETS and cover the top portion 156 of each of the plurality of conductive patterns 150.

[0099] The upper support film 148L can be formed using a CVD process or an ALD process. During the formation of the upper support film 148L, a seam portion 148S can be formed in the region of the upper support film 148L that is between the top portions 156. The seam portion 148S can have a linear shape that extends longitudinally in the vertical direction. During the deposition of the upper support film 148L, the material layer included in the upper support film 148L can grow to a uniform thickness, and the enlarged peripheral space ETS can be filled with the material layer during the growth of the material layer. As a result, the portions of the material layer that grow while facing each other from the sidewalls of the top portion 156 can contact each other in the enlarged peripheral space ETS, and thus, the seam portion 148S can be formed. For example, the seam portion 148S can be a boundary formed by the contact of two adjacent portions of the material layer. The seam portion 148S can continuously or intermittently extend in a substantially vertical direction in a substantially central portion of the space between the two top portions 156, and the two top portions 156 face each other across the enlarged peripheral space ETS.

[0100] The upper support film 148L can include a material having an etching selectivity with respect to the lower molded pattern 132P and the upper molded pattern 134P. In an exemplary embodiment, the upper support film 148L can include a silicon nitride film, a SiOC film, a SiCN film, a SiBN film, a SiBCN film, or a combination thereof, but is not limited thereto.

[0101] Referring Figure 11I , it can be from Figure 11HThe resulting structure removes a portion of the upper support film 148L to expose the top portions 156 of each of the plurality of conductive patterns 150, thereby forming the upper support pattern 148.

[0102] The formation of the upper support pattern 148 may include removing a portion of the upper support film 148L by performing a CMP process using the top portion 156 of each of the plurality of conductive patterns 150 as a polishing stop layer. As a result, the upper support pattern 148 can be obtained, and the upper support pattern 148 includes a portion that fills the enlarged peripheral spaces (e.g., see the enlarged peripheral space ETS in Figure 11G ).

[0103] Referring to Figure 11J , a plurality of upper holes UH (e.g., see the upper holes UH in Figure 2A ) can be formed in the upper support pattern 148, and the upper molding pattern 134P and the sacrificial spacers 146 can be removed wet etchingly through the plurality of upper holes UH. After removing the upper molding pattern 134P and the sacrificial spacers 146, the sidewalls of the first portion 150U, which is the upper portion of each of the plurality of conductive patterns 150, can be exposed.

[0104] When each of the upper molding pattern 134P and the sacrificial spacers 146 includes an oxide film, the upper molding pattern 134P and the sacrificial spacers 146 can be removed using a first etchant containing ammonium fluoride, hydrofluoric acid, and water. When the upper molding pattern 134P includes an oxide film and the sacrificial spacers 146 include a nitride film, the upper molding pattern 134P can be removed using the first etchant, and the exposed sacrificial spacers 146 can be removed using a second etchant containing phosphoric acid.

[0105] Referring to Figure 11K , the first portion 150U of each of the plurality of conductive patterns 150 can be trimmed in the Figure 11J resulting structure, thereby reducing the width of the first portion 150U in the lateral direction.

[0106] In an exemplary embodiment, the trimming of the first portion 150U can be performed using an etchant that can selectively etch only the plurality of conductive patterns 150 among the upper support pattern 148, the lower support pattern 142P, and the plurality of conductive patterns 150. For example, when the upper support pattern 148 and the lower support pattern 142P include a nitride film and the plurality of conductive patterns 150 include TiN, an etchant including sulfuric acid and oxygenated water can be used in the trimming process. After the first portion 150U is trimmed, a lower electrode LE1 having sidewalls with a first step portion ST1 and a second step portion ST2 can be obtained.

[0107] Referring to Figure 11L , it can be fromFigure 11K In the resulting structure, the portion of the lower support pattern 142P that is exposed by forming a plurality of upper holes (e.g., see the upper holes UH in Figure 2A ) in the upper support pattern 148 is removed to form a plurality of lower holes (not shown). Thereafter, the lower molding pattern 132P can be wet-etched through the plurality of lower holes to expose the top surface of the insulating pattern 126P. The lower molding pattern 132P can be removed using the same method as the process for removing the upper molding pattern 134P described with reference to Figure 11J . After the lower molding pattern 132P is removed, the sidewalls of the lower portion of the lower electrode LE1 can be exposed.

[0108] Referring to Figure 11M , a dielectric film 160 can be formed to cover Figure 11L the exposed surface of the lower electrode LE1 in the resulting structure. The dielectric film 160 can be formed using an ALD process. Thereafter, an upper electrode UE1 can be formed to cover the dielectric film 160, thereby completing the fabrication of the IC device 100 shown in Figures 2A to 2C . The upper electrode UE1 can be formed using a CVD process, an MOCVD process, a physical vapor deposition (PVD) process, or an ALD process.

[0109] According to the method of manufacturing the IC device 100 described with reference to Figures 11A to 11M , even when the aspect ratios of the plurality of lower electrodes LE1 are relatively high and the distance between the respective lower electrodes LE1 is reduced, the insulation distance between the upper portions of the respective lower electrodes LE1 can be increased. Accordingly, malfunctions caused by a bridging phenomenon between adjacent lower electrodes LE1 can be suppressed, and the reliability and mass-production efficiency of the IC device 100 can be improved.

[0110] Figures 12A to 12D FIG. Figures 12A to 12D is a cross-sectional view showing the process sequence of a method of manufacturing an IC device according to an exemplary embodiment. A method of manufacturing the IC device 200 shown in Figure 3 will be described with reference to

[0111] Referring to Figure 12A , the process described with reference to Figures 11A to 11H can be performed. Accordingly, after performing the process of forming the upper support film 148L, an upper support pattern 248 can be formed on the resulting structure of Figure 11H . The upper support pattern 248 can have a top surface that is planarized by polishing a partial thickness of the top surface of the upper support film 148L of Figure 11H . The seam portion 148S of the upper support film 148L described with reference to Figure 11H can be retained as the seam portion 248S of the upper support pattern 248. The upper support pattern 248 can fill the enlarged peripheral space (e.g., seeFigure 11G the enlarged peripheral space ETS) and covers the top surface of the top portion 156 of each of the plurality of conductive patterns 150.

[0112] Since the upper support pattern 248 covers the sidewalls and the top surface of the top portion 156 of each of the plurality of conductive patterns 150 and extends in the lateral direction between the top portions 156 of the respective conductive patterns 150, the position of each of the plurality of conductive patterns 150 can be stably fixed without changing the position of the top portion 156 of each of the plurality of conductive patterns 150 due to the stress of the peripheral film or deteriorating the arrangement regularity of the plurality of conductive patterns 150.

[0113] Referring to Figure 12B , a method similar to the method described with reference to Figure 11J can be used to form a plurality of upper holes (not shown) in the upper support pattern 248. Thereafter, the upper molding pattern 134P and the sacrificial spacer 146 can be removed through the plurality of upper holes, thereby exposing the sidewalls of the first portion 150U.

[0114] Referring to Figure 12C , a method the same as the method described with reference to Figure 11K can be used to trim each of the first portions 150U of the plurality of conductive patterns 150 in the Figure 12B resulting structure. Accordingly, the lateral width of the first portion 150U can be reduced, thereby forming a lower electrode LE1 having sidewalls with a first step portion ST1 and a second step portion ST2.

[0115] Referring to Figure 12D , a method the same as the method described with reference to Figure 11L can be used to remove the lower molding pattern 132P from the Figure 12C resulting structure. A method the same as the method described with reference to Figure 11M can be used to form a dielectric film 160 and an upper electrode UE1 on the lower electrode LE1, thereby forming the IC device 200.

[0116] Figures 13A to 13D is a cross-sectional view showing a process sequence of a method of manufacturing an IC device according to an exemplary embodiment. The method of manufacturing the Figures 13A to 13D and Figure 4A and Figure 4B shown in the IC device 300 according to the exemplary embodiment will be described with reference to

[0117] Referring to Figure 13A , the process described with reference to Figures 11A to 11J can be performed. Thereafter, from Figure 11JThe lower support pattern 142P is removed from the resulting structure to form a plurality of lower holes (not shown). Afterwards, a portion of the lower molding pattern 132P may be wet-removed through the plurality of lower holes to form a lowered lower molding pattern 132Q. Figure 11L The process of wet-removing a portion of the lower mold pattern 132P may be performed in the same manner as described above with respect to the process of removing the lower mold pattern 132P.

[0118] The second portion 150L, which is a lower portion of each of the plurality of conductive patterns 150 , may be exposed between the lowered lower molding pattern 132Q and the lower support pattern 142P.

[0119] Reference Figure 13B , can be used with reference Figure 11K A similar approach is described in Figure 13A The exposed portion of the first portion 150U and the exposed portion of the second portion 150L of each of the plurality of conductive patterns 150 are trimmed in the resulting structure. Therefore, the lateral width of each of the first portion 150U and the second portion 150L can be reduced. After performing the trimming process, the lower electrode LE3 having a sidewall having the first step portion ST1, the second step portion ST2, and a plurality of third step portions (e.g., ST31 and ST32) can be obtained.

[0120] Reference Figure 13C , can be formed in the lower support pattern 142P through a plurality of lower holes (not shown) from Figure 13B The lower mold pattern 132Q is wet-removed from the resulting structure, thereby exposing the top surface of the insulating pattern 126P. Figure 11J The process of removing the lowered lower mold pattern 132Q is performed in the same manner as described for the process of removing the upper mold pattern 134P.

[0121] Reference Figure 13D , you can Figure 13C A dielectric film 360 is formed on the resulting structure to cover the exposed surface of the lower electrode LE3. An upper electrode UE3 may be formed on the dielectric film 360, thereby completing the manufacture of the IC device 300. Figure 11M The dielectric film 360 and the upper electrode UE3 are formed by the same method as the process described for forming the dielectric film 160 and the upper electrode UE1.

[0122] Although referenced Figures 11A to 11M , Figures 12A to 12D as well as Figures 13A to 13D Describes the manufacturing Figures 2A to 2C , Figure 3 , Figure 4A and Figure 4BThe methods of the IC devices 100, 200, and 300 shown, but it will be understood that within the scope of the inventive concept, various modifications and changes can be made to the methods described with reference to Figures 11A to 11M , Figures 12A to 12D and Figures 13A to 13D to manufacture the IC devices 400, 500, 600, 700, 800, and 900 shown in Figures 5 to 10 and various IC devices having a structure similar thereto.

[0123] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes can be made to the inventive concept in form and detail without departing from the spirit and scope of the claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: A lower electrode, including a main portion and a top portion, the main portion longitudinally extending in a vertical direction on a substrate and having sidewalls, the sidewalls having at least one stepped portion, and the top portion having a width smaller than the width of the main portion in a lateral direction; And An upper support pattern, in contact with the top portion of the lower electrode and extending parallel to the substrate, Wherein, the upper support pattern includes a seam portion, the seam portion being formed inside the upper support pattern and being at a position separated from the top portion of the lower electrode in the lateral direction.

2. The integrated circuit device according to claim 1, the integrated circuit device further comprising: A lower support pattern, configured to support the main portion of the lower electrode, Wherein, the lower electrode includes a first stepped portion in contact with the lower support pattern.

3. The integrated circuit device according to claim 1, Among them, The lower electrode includes a first stepped portion formed in the main portion of the lower electrode and a second stepped portion formed in a boundary portion between the main portion and the top portion of the lower electrode, and Wherein, the upper support pattern is in contact with the second stepped portion.

4. The integrated circuit device according to claim 1, wherein, The upper support pattern is in contact with the sidewall of the top portion of the lower electrode, and the top surface of the upper support pattern and the top surface of the top portion of the lower electrode extend in the same plane.

5. The integrated circuit device according to claim 1, wherein, The upper support pattern is in contact with the sidewall and the top surface of the top portion of the lower electrode, and the vertical distance from the substrate to the top surface of the upper support pattern is greater than the vertical distance from the substrate to the top surface of the top portion of the lower electrode.

6. The integrated circuit device according to claim 1, wherein, The upper support pattern is in contact with the sidewall and the top surface of the top portion of the lower electrode, and the upper support pattern includes a portion extending parallel to the substrate on the top surface of the top portion of the lower electrode.

7. The integrated circuit device according to claim 1, the integrated circuit device further comprising: A lower support pattern, in contact with the main portion of the lower electrode and extending parallel to the substrate, Wherein, the lower electrode further includes a protrusion protruding towards the lower support pattern.

8. An integrated circuit device, the integrated circuit device comprising: A lower electrode, longitudinally extending in a vertical direction from a first level to a second level on a substrate, the lower electrode including a first stepped portion and a top portion, wherein, the first stepped portion is formed at the sidewall of the lower electrode at a third level between the first level and the second level, and the top portion has a top surface at the second level; and An upper support pattern, extending parallel to the substrate at the second level and in contact with the top portion of the lower electrode to support the lower electrode, Wherein, the upper support pattern includes a seam portion, the seam portion being formed inside the upper support pattern and being at a position separated from the top portion of the lower electrode in the lateral direction.

9. The integrated circuit device according to claim 8, the integrated circuit device further comprising: A lower support pattern, configured to support the lower electrode between the first level and the third level, Wherein, the lower support pattern is in contact with the first stepped portion.

10. The integrated circuit device according to claim 8, wherein, The lateral width of the top portion of the lower electrode is smaller than the lateral width of the first portion of the lower electrode, the first portion extending vertically between the first level and the third level.

11. The integrated circuit device according to claim 8, Among them, The lower electrode further includes a second stepped portion formed at a sidewall of the lower electrode at a fourth level between a second level and a third level. wherein a top portion of the lower electrode extends in a vertical direction from the fourth level to the second level, and wherein the upper support pattern contacts the second stepped portion of the lower electrode.

12. The integrated circuit device according to claim 8, Among them, The lower electrode further includes a second stepped portion formed at a sidewall of the lower electrode at a fourth level between a second level and a third level. wherein a lateral width of a second portion of the lower electrode is larger than a lateral width of a top portion of the lower electrode, and wherein the second portion extends in a vertical direction from the third level to the fourth level.

13. The integrated circuit device according to claim 8, Among them, The lower electrode further includes a second stepped portion formed at a sidewall of the lower electrode at a fourth level between a second level and a third level. wherein a lateral width of a second portion of the lower electrode is smaller than a lateral width of a top portion of the lower electrode, wherein the second portion extends in a vertical direction from the third level to the fourth level.

14. The integrated circuit device according to claim 8, wherein, The upper support pattern contacts a sidewall and a top surface of a top portion of the lower electrode, and the upper support pattern includes a portion extending parallel to the substrate on the top surface of the top portion of the lower electrode.

15. An integrated circuit device, the integrated circuit device comprising: a plurality of lower electrodes spaced apart from each other on a substrate; an upper support pattern extending in a lateral direction parallel to the substrate, the upper support pattern having a plurality of holes through which the plurality of lower electrodes pass; and a lower support pattern extending in a lateral direction between the substrate and the upper support pattern and contacting each of the plurality of lower electrodes, wherein the upper support pattern includes a seam portion formed inside the upper support pattern and at a position laterally spaced apart from the plurality of lower electrodes.

16. A method of manufacturing an integrated circuit device, the method comprising: forming a molding pattern and an upper sacrificial support pattern on a substrate, wherein a plurality of holes pass through the molding pattern and the upper sacrificial support pattern; forming a plurality of lower electrodes inside the plurality of holes; forming a peripheral space on the molding pattern by removing the upper sacrificial support pattern such that a top portion of each of the plurality of lower electrodes protrudes above a top surface of the molding pattern; forming an enlarged peripheral space by reducing a width and a height of a top portion of each of the plurality of lower electrodes; forming an upper support pattern to fill the enlarged peripheral space, the upper support pattern contacting a top portion of each of the plurality of lower electrodes; and exposing a sidewall of a first portion of each of the plurality of lower electrodes by removing the molding pattern.

17. The method according to claim 16, wherein, The step of forming the upper support pattern includes: forming an upper support film to fill the enlarged peripheral space and cover a sidewall and a top surface of a top portion of each of the plurality of lower electrodes; and forming the upper support pattern by removing a portion of the upper support film to expose a top portion of each of the plurality of lower electrodes, the upper support pattern extending parallel to the substrate inside the enlarged peripheral space.

18. The method according to claim 16, wherein, The steps of forming the upper support pattern include: forming an upper support film to fill the enlarged peripheral space and cover the sidewalls and top surfaces of the top portions of each of the plurality of lower electrodes; and forming the upper support pattern by removing a portion of the upper support film, the upper support pattern filling the enlarged peripheral space and extending parallel to the substrate on the top surfaces of the top portions of each of the plurality of lower electrodes.

19. The method according to claim 16, wherein The steps of forming the upper support pattern are performed using a chemical vapor deposition process or an atomic layer deposition process, wherein a seam portion is formed inside the upper support pattern during the formation of the upper support pattern, and the seam portion extends in the vertical direction.

20. The method according to claim 16, wherein the method further comprises: After the sidewalls of the first portions of each of the plurality of lower electrodes are exposed, a portion of the first portions is removed from the sidewalls of the first portions to reduce the lateral width of the first portions.

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