Semiconductor device, electronic device including the semiconductor device, and method for manufacturing the same

Abstract

A semiconductor device, an electronic device and a method for manufacturing the same. The semiconductor device comprises a circuit substrate, a semiconductor package, a connection terminal and a support. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connection terminal is located on the second side of the circuit substrate and is electrically connected to the semiconductor package via the circuit substrate. The support is located on the second side of the circuit substrate next to the connection terminal. The material of the support has a melting temperature higher than the melting temperature of the connection terminal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, an electronic device including the semiconductor device, and a method for manufacturing the same. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic devices (e.g., cellular phones and other mobile electronic devices) are typically manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged together with other semiconductor devices or die at the wafer level, and various technologies and applications have been developed for wafer-level packaging. The integration of multiple semiconductor devices has become a challenge in this field. In response to the increasing demand for miniaturization, higher speeds, and better electrical performance (e.g., lower transmission loss and insertion loss), more creative packaging and assembly technologies are actively being researched. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, including a circuit substrate, a semiconductor package, a connection terminal and a support member. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connection terminal is located on the second side of the circuit substrate and is electrically connected to the semiconductor package via the circuit substrate. The support member is located on the second side of the circuit substrate next to the connection terminal. The material of the support member has a melting temperature higher than the melting temperature of the connection terminal.

[0004] An embodiment of the present invention provides an electronic device, including a circuit carrier and a semiconductor device. The semiconductor device is connected to the circuit carrier, including a circuit substrate, a semiconductor package, a connection terminal and a support column. The circuit substrate has a core layer sandwiched between a first stacking layer and a second stacking layer. The semiconductor package is connected to the first stacking layer. The connection terminal is connected to the second stacking layer and is electrically connected to the semiconductor package via the circuit substrate. The support column is located on the second stacking layer next to the connection terminal and is electrically insulated from the circuit substrate. The connection terminal and the support column are arranged between the circuit carrier and the circuit substrate, and the support column has a first melting temperature higher than the second melting temperature of the connection terminal.

[0005] An embodiment of the present invention provides a method for manufacturing an electronic device, comprising connecting a semiconductor package to a first side of a circuit substrate, placing a connection terminal on a second side of the circuit substrate opposite to the first side, placing a support column on the second side of the circuit substrate, wherein the support column has a first melting temperature higher than a second melting temperature of the connection terminal, and performing a heating step to attach the circuit substrate to a circuit carrier via the connection terminal, wherein the heating step is performed at a temperature higher than the second melting temperature and lower than the first melting temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1G are schematic cross-sectional views of structures produced at various stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 1H is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure.

[0009] Figure 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0010] FIG. 3A to FIG. 3E is a schematic bottom view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 4A and Figure 4B is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0012] Description of Figure Numbers

[0013] 10, 20, 30, 40, 50, 60, 70, 80, 90: semiconductor devices;

[0014] 15, 85, 95: electronic devices;

[0015] 100: semiconductor packaging;

[0016] 100e: edge;

[0017] 100e1, 100e2, 100e3, 100e4: part;

[0018] 110: chip;

[0019] 110a: active surface;

[0020] 111, 121: semiconductor substrate;

[0021] 113, 127: contact pad;

[0022] 115: passivation layer;

[0023] 117: contact column;

[0024] 119: protective layer;

[0025] 120: Insert;

[0026] 123: Internal connection structure;

[0027] 125: semiconductor perforation;

[0028] 130: Connector;

[0029] 140, 320: bottom filling material;

[0030] 150: Encapsulation body;

[0031] 200: Circuit substrate;

[0032] 200a: side;

[0033] 200b: side;

[0034] 200e, 400o: outer edge;

[0035] 210: core layer;

[0036] 211, 221, 231, 1231: dielectric layer;

[0037] 213: through hole;

[0038] 215: Perforation;

[0039] 217: Dielectric filler;

[0040] 220, 230: accumulation layer;

[0041] 223, 233, 1232: conductive pattern;

[0042] 310: conductive terminal;

[0043] 400: Ring;

[0044] 402: flange;

[0045] 402i: inner edge;

[0046] 404: Top plate;

[0047] 406: Opening;

[0048] 410: bonding material;

[0049] 420, 430: coating layer;

[0050] 422, 432: capping;

[0051] 424, 434: fixing flange;

[0052] 426, 436: support flange;

[0053] 510, 520, 530: welding materials;

[0054] 532: adhesive part;

[0055] 600: connection terminal;

[0056] 700: Passive components;

[0057] 800, 802, 804, 806, 806A, 806B, 808: support columns;

[0058] 900: Circuit carrier;

[0059] 1233: Under Bump Metal;

[0060] α, β: angle;

[0061] D1, D2: direction;

[0062] PD1, PD2: minimum distance;

[0063] Px: first spacing;

[0064] Py: second spacing;

[0065] SF1, SF2: supporting frame;

[0066] T600, T700, T800: thickness;

[0067] X: first direction;

[0068] Y: second direction;

[0069] Z: Direction. DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. The specific examples of components and arrangements described below are for simplifying the present disclosure. Of course, these components and arrangements are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0071] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0072] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate that allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes intermediate verification of a known good die to increase yield and reduce cost.

[0073] Figure 1A to Figure 1G 1 is a schematic cross-sectional view of a structure produced at various stages of a method of manufacturing a semiconductor device 10 according to some embodiments of the present disclosure. Figure 1A In some embodiments, a semiconductor package 100 is provided. In some embodiments, the semiconductor package 100 includes one or more chips 110. In some embodiments, each chip 110 includes a semiconductor substrate 111, a contact pad 113, and a passivation layer 115. The contact pad 113 may be formed on the top surface of the semiconductor substrate 111. The passivation layer 115 may cover the top surface of the semiconductor substrate 111 and have a plurality of openings exposing at least a portion of each contact pad 113. In some embodiments, the chip 110 may further include a plurality of contact pillars 117 filling the openings of the passivation layer 115 and electrically connected to the contact pads 113 and a protection layer 119 surrounding the contact pillars 117.

[0074] In some embodiments, the semiconductor substrate 111 may be made of a semiconductor material (e.g., a semiconductor material of Group III-V of the periodic table). In some embodiments, the semiconductor substrate 111 includes: a basic semiconductor material, such as silicon or germanium; a compound semiconductor material, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or an alloy semiconductor material, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate 111 includes active components (e.g., transistors, etc.) formed therein and optionally includes passive components (e.g., resistors, capacitors, inductors, etc.). In certain embodiments, the contact pad 113 includes an aluminum pad, a copper pad, or other suitable metal pads. In some embodiments, the passivation layer 115 may be a single-layer or multi-layer structure, including a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a dielectric layer formed of other suitable dielectric materials, or a combination thereof. In some embodiments, the material of the contact pillar 117 includes copper, a copper alloy, or other conductive materials, and may be formed by deposition, plating, or other suitable techniques. In some embodiments, any chip 110 of the semiconductor package 100 may have features similar to those just discussed.

[0075] Each chip 110 may independently be or include a logic die, such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, a micro control unit (MCU) die, an input-output (I / O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, one or more chips 110 may be a memory die. The present disclosure is not limited to the type of chip 110 used in the semiconductor package 100.

[0076] refer to Figure 1AIn some embodiments, the chip 110 is bonded to the insert 120. In some embodiments, the insert 120 includes a semiconductor substrate 121, an interconnect structure 123, a through semiconductor via (TSV) 125, and a contact pad 127. The semiconductor substrate 121 is made of a semiconductor material, similar to that previously discussed with reference to the semiconductor substrate 111 of the chip 110. In some embodiments, the insert 120 includes a silicon wafer. In some embodiments, the interconnect structure 123 is disposed on the semiconductor substrate 121 and includes a dielectric layer 1231, a conductive pattern 1232, and an under bump metal 1233. For simplicity, the dielectric layer 1231 is shown as a single dielectric layer, and the conductive pattern 1232 is shown as embedded in the dielectric layer 1231. Nevertheless, from the perspective of the manufacturing process, the dielectric layer 1231 is composed of at least two dielectric layers. The conductive pattern 1232 can be sandwiched between two adjacent dielectric layers. Some of the conductive patterns 1232 may extend vertically through the dielectric layer 1231 to establish electrical connections between different metallization layers of the interconnect structure 123. In some embodiments, the (outermost) dielectric layer 1231 may be patterned to expose the underlying conductive pattern 1232. Optionally, the under bump metal 1233 may be conformally formed in the opening of the (outermost) dielectric layer 1231 that exposes the conductive pattern 1232, and may further extend over a portion of the exposed surface of the (outermost) dielectric layer 1231. In some embodiments, the under bump metal 1233 includes a plurality of stacked layers. For example, the under bump metal 1233 may include one or more metal layers stacked on a seed layer. In some embodiments, the material of the dielectric layer 1231 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzooxazole (PBO) or any other suitable polymer dielectric material. The dielectric layer 1231 can be formed, for example, by a suitable manufacturing technique, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the material of the conductive pattern 1232 and the under-bump metal 1233 includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive pattern 1232 and the under-bump metal 1233 can be formed, for example, by electroplating, deposition, and / or photolithography and etching. It should be noted that Figure 1AThe number of dielectric layers 1231, the number of conductive patterns 1232, and the number of under bump metals 1233 shown in the figure are for illustrative purposes only, and the present disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of dielectric layers 1231, conductive patterns 1232, or under bump metals 1233 may be formed depending on the circuit design.

[0077] In some embodiments, Figure 1A As shown in FIG. 1 , TSV 125 is formed in semiconductor substrate 121 and provides double-sided electrical connection via semiconductor substrate 121. In some embodiments, one end of TSV 125 is connected to conductive pattern 1232 of interconnect structure 123, and the other end of the same TSV 125 is connected to contact pad 127 formed on a side of semiconductor substrate 121 opposite to interconnect structure 123. In some embodiments, the material of TSV 125 includes one or more metals. In some embodiments, the metal material of TSV 125 includes copper, titanium, tungsten, aluminum, combinations thereof, and the like.

[0078] In some embodiments, the chip 110 is bonded to the interposer 120 via connectors 130. In some embodiments, the connectors 130 are microbumps mounted on the contact studs 117 and sandwiched between the contact studs 117 and the under bump metallurgy 1233 or TSV 125 (if the interconnect structure 123 is not included in the interposer 120). According to some embodiments, the chip 110 is arranged with the active surface 110a (the surface exposing the contact studs 117 or the contact pads 113 when the contact studs 117 are not included) facing the interposer 120.

[0079] In some embodiments, an underfill material 140 may be disposed between the chip 110 and the insert 120 to protect the connector 130 from thermal stress or physical stress and to ensure electrical connection between the chip 110 and the insert 120. In some embodiments, the underfill material 140 is formed by capillary underfill filling (CUF). A dispenser (not shown) may apply a filling material (not shown) along the periphery of the chip 110. In some embodiments, heating or heat treatment may be applied to allow the filling material to penetrate into the gap defined by the connector 130 between the chip 110 and the insert 120 through capillary action. In some embodiments, a curing process is performed to reinforce the underfill material 140. In some embodiments, as Figure 1A As shown in FIG. 1 , a plurality of underfill portions 140 are formed, each portion securing connectors 130 of chip 110. In some alternative embodiments, a single underfill (not shown) may extend under chip 110 depending on the spacing and relative positions of the chips above interposer 120.

[0080] refer to Figure 1A , the encapsulation body 150 is formed above the insert 120 that encapsulates the chip 110 and the underfill 140. In some embodiments, the encapsulation body 150 is formed by completely covering the chip 110 with an encapsulation material (not shown), and then performing a planarization process (e.g., a mechanical grinding process and / or a chemical mechanical polishing step) until the backside surface of the chip is exposed. In some embodiments, the encapsulation material can be a molding compound, a molding underfill, a resin (e.g., an epoxy resin), etc. In some embodiments, the encapsulation material is formed by an overmolding process. In some embodiments, the encapsulation material is formed by a compression molding process. In some embodiments, the encapsulation material may require a curing step.

[0081] exist Figure 1A For simplicity, only two chips 110 are shown on the insert 120, but the present disclosure is not limited thereto. In some embodiments, the semiconductor package 100 may include Figure 1A The chip shown in the figure may be more or less than the chip 110 and other components (such as dummy dies, stress release layers, interconnect structures, support pillars, etc.). In addition, although the process is currently shown for a chip-on-wafer (CoW) package 100, the present disclosure is not limited to the package structure shown in the figure, and other types of semiconductor packages (such as integrated fan-out (InFO) package, package-on-packages (PoP), etc.) are also meant to be covered by the present disclosure and fall within the scope of the appended claims.

[0082] refer to Figure 1AIn some embodiments, the circuit substrate 200 is disposed on the support frame SF1, and the semiconductor package 100 is connected to one side 200a of the circuit substrate 200. In some embodiments, the circuit substrate 200 includes a core layer 210 and a buildup layer 220, a buildup layer 230 disposed on opposite sides of the core layer 210. The core layer 210 may include a dielectric layer 211, and the dielectric layer 211 includes a through hole 213 passing through the dielectric layer 211 from one side to the other side. The through hole 213 may be lined with a conductive material forming a through hole 215. In some embodiments, the through hole 215 only partially fills the through hole 213 (for example, lining the edge of the through hole 213), and the through hole 213 is filled with a dielectric filler 217. In some alternative embodiments, the through hole 213 is filled with the through hole 215. In some embodiments, each of the buildup layers 220 or 230 includes a dielectric layer 221 or 231 and a conductive pattern 223 or 233 embedded in the corresponding dielectric layer 221 or 231 and providing electrical connection between opposite sides of the corresponding dielectric layer 221 or 231. In some embodiments, the buildup layers 220 and 230 may independently include a dielectric layer 221 or 231, depending on wiring requirements. Figure 1A 21 and 23. In some embodiments, the through-hole 215 establishes an electrical connection between the conductive pattern 223 of one build-up layer 220 and the conductive pattern 233 of another build-up layer 230. In some embodiments, the circuit substrate 200 is disposed on a support frame SF1, wherein the build-up layer 230 is oriented toward the support frame SF1 and the other build-up layer 220 is exposed for further processing. Thus, the semiconductor package 100 is connected to the circuit substrate 200 from one side (e.g., side 200a) of the build-up layer 220, while the opposite side 200b of the circuit substrate 200 is oriented toward the support frame SF1. In some embodiments, the conductive terminal 310 is disposed between the contact pad 127 of the semiconductor package 100 and the portion of the conductive pattern 223 of the build-up layer 220 exposed by the (outermost) dielectric layer 221. In some embodiments, the conductive terminal 310 is a C4 bump. In some embodiments, the underfill material 320 is disposed between the semiconductor package 100 and the circuit substrate 200 to protect the conductive terminals 310 from thermal and mechanical stresses.

[0083] refer to Figure 1BIn some embodiments, the ring 400 is fixed to the circuit substrate 200 from the side 200a, and the circuit substrate 200 surrounds the semiconductor package 100 and the bottom filler 320. In some embodiments, the ring 400 includes a flange 402 extending toward the circuit substrate 200 in a vertical direction and a roof 404 connected to the flange 402 and extending in a horizontal direction substantially parallel to the circuit substrate 200. In some embodiments, the inner edge 402i of the flange 402 faces the edge 100e of the semiconductor package 100. In some embodiments, the semiconductor package 100 is surrounded by the inner edge 402i of the flange 402 on all sides. The roof 404 can be formed integrally with the flange 402 (formed as a single piece). In some embodiments, the flange 402 and the roof 404 form a right angle shape at their joint, but the present disclosure is not limited thereto. In some embodiments, the flange 402 is joined to the roof 404 at an angle different from 90 degrees. In some embodiments, the top plate 404 includes an opening 406 that exposes the semiconductor package 100 (when viewed from the top). In some embodiments, a heat dissipation system (not shown) can be connected to the semiconductor package 100 via the opening 406 of the top plate 404. In some alternative embodiments, the top plate 404 does not include the opening 406 and constitutes a cover covering the semiconductor package 100. In some embodiments, the material of the ring 400 includes a metal (e.g., copper). In some embodiments, before the ring 400 is mounted on the circuit substrate 200, the ring 400 can be anodized or passivated (e.g., with nickel) to enhance its environmental resistance. In some embodiments, an outer edge 400o of the ring 400 opposite the inner edge 402i is vertically aligned with an outer edge 200e of the circuit substrate 200. In some embodiments, the outer edge 200e of the circuit substrate 200 corresponds to the peripheral surface of the bonding side 200a and the side 200b. In some embodiments, the footprint of the ring 400 substantially matches and is aligned with the footprint of the circuit substrate 200. In some embodiments, the ring 400 can be fixed to the circuit substrate 200 via a bonding material 410. The material of the bonding material 410 is not particularly limited and can be selected according to the materials used for the dielectric layer 231 and the ring 400 to which the bonding material 410 must be fixed. In some embodiments, the bonding material 410 includes a thermosetting adhesive, a light-curable adhesive, a thermally conductive adhesive, a thermosetting resin, a waterproof adhesive, a laminating adhesive, or a combination thereof. In some embodiments, the bonding material 410 includes a thermally conductive adhesive. In some embodiments, the bonding material 410 includes a metal layer (not shown) on which a solder paste (not shown) is deposited. Depending on the type of material used, the bonding material 410 can be formed by deposition, lamination, printing, plating, or any other suitable technique.

[0084] refer to Figure 1B and Figure 1C , which can make Figure 1BThe manufacturing intermediate shown in the figure is turned over on the support frame SF2. In some embodiments, the ring 400 can support the structure on the support frame SF2 to expose the buildup layer 230 of the circuit substrate 200 for further processing. That is, after the manufacturing intermediate is turned over, the side 200b can be exposed. In some embodiments, the dielectric layer 231 can be patterned to expose a portion of the conductive pattern 233 (if previously covered). In some embodiments, the welding material 510, the welding material 520, and the portion of the welding material 530 can be disposed on the buildup layer 230. In some embodiments, the welding material 510 and the welding material 520 are disposed on the opening of the dielectric layer 231 exposing the conductive pattern 233, and the portion of the welding material 530 can be disposed on the dielectric layer 231. That is, the welding material 510 and the welding material 520 can be electrically connected to the chip 110 of the semiconductor package 100 via the circuit substrate 200, and the portion of the welding material 530 can be electrically insulated from the chip 110 or even from the conductive pattern 233 of the circuit substrate 200. In some embodiments, the solder material comprises a eutectic solder containing lead or lead-free. In some embodiments, the solder material comprises a non-eutectic solder. In some embodiments, the solder material comprises Sn, SnAg, SnPb, SnAgCu, SnAgZn, SnZn, SnBiIn, SnIn, SnAu, SnCu, SnZnIn, SnAgSb or similar solder alloys. In some embodiments, the solder material is applied in the form of solder paste.

[0085] refer to Figure 1D In some embodiments, the connection terminal 600 is disposed on a portion of the solder material 510. In some embodiments, the connection terminal 600 is a solder ball for a ball grid array mount. In some embodiments, the connection terminal 600 is electrically connected to the semiconductor package 100 via the circuit substrate 200. Figure 1E , in some embodiments, the passive device 700 is connected to the circuit substrate 200 via a portion of the solder material 520. That is, the passive device is disposed on the side 200b of the circuit substrate 200 between the connection terminals 600. In some embodiments, the passive device 700 is a chip including passive devices formed in a semiconductor substrate. In some embodiments, the passive device 700 is an integrated passive device and can independently act as a capacitor, an inductor, a resistor, etc. In some embodiments, the passive device 700 is a functional device, that is, it is electrically connected to the circuit substrate 200 and the semiconductor package 100. Reference Figure 1FIn some embodiments, the support column 800 is mounted on a portion of the soldering material 530 between the connection terminal 600 and the passive device 700. In some embodiments, the support column 800 is a preform of a high temperature melting material. In some embodiments, the support column 800 is made of a material having a higher melting temperature than the material of the connection terminal 600. For example, the support column 800 may include a metal, a ceramic material (such as an oxide), a semiconductor material (such as a back surface mounted device, a chip top cover, a passive device), a polymer material, a combination thereof, and the like. In some embodiments, when passive devices are used as the support column 800, these may be electrically insulated from the circuit substrate 200 (such as non-functional passive devices). In some embodiments, one or more reflow processes may be performed to fix the connection terminal 600, the passive device 700, and the support column 800. The support column 800 may be placed on a portion of the soldering material 530 via a pick-and-place process. It should be noted that although Figure 1D to Figure 1F The connection terminal 600, the passive device 700, and the support column 800 are shown disposed on the circuit substrate 200 in this order, but the present disclosure is not limited thereto. In some alternative embodiments, the support column 800 may be disposed on the circuit substrate 200 before the passive device 700, the connection terminal 600, or both. In some alternative embodiments, the passive device 700 may be disposed on the circuit substrate 200 first.

[0086] refer to Figure 1F and Figure 1G , in some embodiments, the system can be removed from the support frame SF2, and then the semiconductor device 10 can be obtained. In some embodiments, the semiconductor device 10 includes a semiconductor package 100 connected to a substrate 200, a ring 400 disposed on the circuit substrate 200 and surrounding the semiconductor package 100, and a connection terminal 600 and a support column 800, both of which are disposed on the opposite side of the circuit substrate 200 relative to the semiconductor package 100. In some embodiments, the passive device 700 may also be disposed on the circuit substrate beside the support column 800 and the connection terminal 600. In some embodiments, the connection terminal 600 and the passive device 700 (if included) are electrically connected to the semiconductor package 100 via the circuit substrate 200. On the other hand, the support column 800 may be electrically insulated from the circuit substrate 200 and the semiconductor package 100. In some embodiments, the support column 800 is disposed on the circuit substrate 200, and the circuit substrate 200 is covered with a dielectric layer 231 of the buildup layer 230 further away from the semiconductor package 100. In some embodiments, the connection terminal 600 , the passive device 700 , and the support column 800 are fixed to the circuit substrate 200 via portions of the soldering material 510 , the soldering material 520 , and the soldering material 530 , respectively.

[0087] In some embodiments, Figure 1GAs shown in , the connection terminal 600 may be thicker (protruding further away from the circuit substrate 200) than the support column 800. In some embodiments, the thickness T600 of the connection terminal 600 may be in the range of from 300 microns to 700 microns, and the thickness T800 of the support column 800 may be in the range of from 200 microns to 600 microns. In some embodiments, the thickness T800 of the support column 800 may be as high as 60% to 85% of the thickness T600 of the connection terminal 600. In some embodiments, the thickness T800 of the support column 800 may be 20% to 100% greater than the thickness T700 of the passive device 700. In some embodiments, the thickness T700 of the passive device may be in the range of from 50 microns to 300 microns. In some embodiments, the material of the support column 800 may have a higher melting point than the material of the connection terminal 600. In some embodiments, the melting temperature of the support column 800 may be at least 300°C higher than the melting temperature of the connection terminal 600. For example, the connection terminal 600 may include a solder ball that begins to melt at a temperature ranging from 150° C. to 260° C., and the support column 800 may include aluminum, stainless steel, copper, silicon, or ceramic, and begins to melt at a temperature of approximately over 1000° C. In some embodiments, the connection terminal 600 may be used to integrate the semiconductor device 10 with other components. In some embodiments, the support column 800 may help maintain the standoff height of the connection terminal 600 during a high temperature heating step (e.g., a reflow process).

[0088] For example, Figure 1HA cross-sectional view of an electronic device 15 is depicted in which a semiconductor device 10 is connected to a circuit carrier 900 (e.g., a printed circuit board, a motherboard, etc.). A connecting terminal 600 establishes an electrical connection between a circuit substrate 200 and the circuit carrier 900. A support post 800 and a passive device 700 are also sandwiched between the circuit substrate 200 and the circuit carrier 900. The support post 800 may be electrically insulated from both the circuit carrier 900 and the circuit substrate 200. In some embodiments, the semiconductor device 10 may be fixed to the circuit carrier 900 via a soldering step, a reflow step, or some other process step that requires heating. In some embodiments, the temperature reached during the heating step may cause some warping in the circuit substrate 200. In some embodiments, the profile of the circuit substrate 200 after the soldering or reflow step may have some curvature, with some areas (first areas) being closer to the circuit carrier 900 than other areas (second areas). That is, the first area may be an area of ​​the circuit substrate 200 that becomes closer to the circuit carrier 900 after the soldering or reflow step. In some embodiments, the first area may be referred to as the minimum area in the warpage profile of the circuit substrate 200. In some embodiments, the support post 800 may be disposed on the circuit substrate 200 corresponding to the minimum area of ​​the warpage profile. For example, for a semiconductor device that does not include a support post, the warpage profile may be physically measured, the minimum area of ​​the warpage profile may be determined, and when a similar semiconductor device including the support post 800 is manufactured, the support post 10 may be disposed in the expected minimum area. In some embodiments, the warpage profile may be simulated, and the position of the support post 800 may be determined based on the results of the simulation. In some embodiments, the position of the support post 800 may be determined based on the results of the simulation, and when subsequent batches are manufactured based on the effectively observed warpage, the position may be further refined. In some embodiments, because the support post 800 has a melting temperature higher than the temperature at which the soldering or reflow of the connection terminal 600 is performed, the support post 800 may resist deformation during the soldering or reflow step. That is, the support post 800 may provide mechanical resistance to the warping (bending) of the circuit substrate 200 toward the circuit carrier 900. In some embodiments, by positioning the support pin 800 corresponding to the minimum area of ​​the warpage profile, the observed warpage can be reduced compared to a case where the support pin 800 is not included. In some embodiments, the reduced warpage of the circuit substrate 200 can avoid shortening of the connection terminal 600 that may occur in the minimum area, thereby increasing the reliability of the electronic device including the semiconductor device 10.

[0089] Figure 2is a schematic cross-sectional view of a semiconductor device 20 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 20 may be similar to the semiconductor device 10 and include: a semiconductor package 100 connected to a circuit substrate 200; a ring 400 disposed on the circuit substrate 200 and surrounding the semiconductor package 100; a connection terminal 600 disposed on the circuit substrate 200 on an opposite side relative to the semiconductor package 100 and the ring 400; a support column 800 disposed on the circuit substrate 200 adjacent to the connection terminal 600; and optionally, a passive device 700 disposed on the circuit substrate 200 on the same side 200b of the connection terminal 600 and the support column 800. In some embodiments, the semiconductor package 100 is a chip-on-wafer (CoW) system, but the present disclosure is not limited thereto. In some embodiments, Figure 1G The semiconductor device 10 and Figure 2 The difference between the semiconductor devices 20 of the present invention is the material that fixes the support column 800 to the circuit substrate 200. Because the support column 800 does not need to be electrically connected to the circuit substrate 200 or the semiconductor package 100, the adhesive portion 532 is used instead of the solder portion 530 of the semiconductor device 10. In some embodiments, the adhesive portion 532 includes a thermoplastic material, a thermosetting material, or a light-curable material. The adhesive portion 532 may include an epoxy resin, a phenolic resin, a polyolefin, or other suitable materials. In some embodiments, the adhesive portion 532 includes an organic adhesive. However, the present disclosure is not limited thereto, and other materials or polymers compatible with the semiconductor processing environment may be used. The adhesive portion 532 may be applied via lamination, spin coating, or other suitable techniques.

[0090] Figure 3A is a schematic bottom view of a semiconductor device 30 according to some embodiments of the present disclosure. Figure 3A The schematic bottom view of FIG. 1 shows the positions of the connection terminals 600, the passive components 700, and the support pillars 802 and 804 above the dielectric layer 231 of the circuit substrate 200. In addition, the coverage areas of the ring 400 and the semiconductor package 100 are also shown by dotted lines and dashed lines, respectively. For the ring 400, the projection of the outer edge 400o and the projection of the surface defining the opening 406 (that is, Figure 1B 404 in the top plate 404) and for the semiconductor package 100, only the outline of the edge 100e is shown. It should be noted that Figure 3AThe number of the connection terminals 600 and the passive devices 700 in the figure is for illustrative purposes only and does not constitute a limitation of the present disclosure. In some embodiments, more or less connection terminals 600 or passive devices 700 may be included depending on the circuit requirements. Similarly, for any of the semiconductor devices proposed herein, the number of support posts is not limited by the present disclosure. In some embodiments, more or less support posts may be included than those shown in the drawings. In some embodiments, the number and position of the support posts may be optimized according to the structural requirements of the semiconductor device. In some embodiments, the connection terminals 600, the support posts 802 and the passive devices 700 (if included) are arranged on the circuit substrate in an orderly manner along the first direction X and the second direction Y. In some embodiments, the first direction X and the second direction Y may be perpendicular to each other. In some embodiments, the connection terminals 600, the support posts 802 and the passive devices 700 are arranged along the first direction X with a first spacing Px and along the second direction Y with a second spacing Py. In some embodiments, the first spacing Px and the second spacing Py are determined according to the size of the connection terminals 600, the passive devices 700 and the support posts 802. In some embodiments, each of the first pitch Px and the second pitch Py may be independently within a range from 500 microns to 1500 microns. In some embodiments, the support pillars 802 are arranged corresponding to the coverage area of ​​the semiconductor package 100. That is, the support pillars 802 may be arranged so that the outline of the vertical projection of the semiconductor package 100 along the direction Z orthogonal to the direction X and the direction Y falls on the support pillars 802. In some embodiments, the minimum area of ​​the warpage profile of the circuit substrate 200 may fall along the edge 100e of the semiconductor package 100. In some embodiments, the minimum area in the warpage profile may be caused by the weight of the semiconductor package 100.

[0091] In some embodiments, the support pillars 804 are positioned at the corners of the circuit substrate 200 along the outer edge 200e within the coverage area of ​​the ring 400. In some embodiments, the closest distance between the support pillars 804 disposed at the corners and the closest connection terminals 600 may be arranged along a direction that is oblique to the first direction X and the second direction Y. For example, considering Figure 3A The support column 804 in the upper left corner of the , the minimum distance PD1 to the closest connection terminal 600 can be arranged along the direction D1 describing an angle α that is a (positive or negative) integer multiple of 0 and π / 2 radians with the first direction X. Similarly, for Figure 3A The support column 804 in the lower left corner, the minimum distance PD2 to the nearest connection terminal 600 can be arranged along a direction D2 describing an angle β with the first direction X that is a (positive or negative) integer multiple of angles α, 0 and π / 2 radians.

[0092] Figure 3Bis a schematic bottom view of a semiconductor device 40 according to some embodiments of the present disclosure. Figure 3A ,exist Figure 3B 4 shows the positions of the connection terminals 600 and the support pillars 802, 804, and 806 above the dielectric layer 231 of the circuit substrate 200. In addition, the coverage areas of the ring 400 and the semiconductor package 100 are also shown in dashed lines and dotted lines, respectively. In some embodiments, the semiconductor device 40 does not include the passive device 700. In addition, the support pillar 802 may be misaligned relative to the edge 100e of the semiconductor package 100. That is, the outline of the vertical projection of the semiconductor package 100 may not fall on the support pillar 802. In some embodiments, the support pillar 806 may be arranged corresponding to the edge 100e of the semiconductor package 100. In some embodiments, the support pillar 806 may have a curved shape, for example, including two parts extending from the corner joint in an orthogonal direction. In some embodiments, the support pillar 806 may be arranged below the corner of the semiconductor package 100, and the two parts may extend below the edge 100e.

[0093] Figure 3C is a schematic bottom view of a semiconductor device 50 according to some embodiments of the present disclosure. Figure 3A ,exist Figure 3C , the positions of the connection terminals 600, the passive devices 700, and the support pillars 804, 806A, and 806B above the dielectric layer 231 of the circuit substrate 200 are shown. In addition, the coverage areas of the ring 400 and the semiconductor package 100 are also shown by dotted lines and dashed lines, respectively. In some embodiments, at least some of the support pillars 806A and 806B have an elongated shape. In some embodiments, the support pillar 806A has an elongated shape along a first direction X, and the support pillar 806B has an elongated shape along a second direction Y. In some embodiments, the support pillars 806A and 806B are arranged corresponding to (vertically aligned with) the outline of the vertical projection of the semiconductor package 100, and the extension direction of the support pillars 806A and 806B can be aligned with the edge 100e of the semiconductor package 100 (for example, as shown in FIG. 1 ). Figure 1B That is, the support pillar 806A extended in the first direction X may be disposed under the portion 100e1 and the portion 100e3 of the edge 100e of the semiconductor package 100 extending along the first direction X, and the support pillar 806B extended in the second direction Y may be disposed under the portion 100e2 and the portion 100e4 of the edge 100e of the semiconductor package 100 extending along the second direction Y. In some embodiments, one or more connection terminals 600 are disposed between the support pillars 806A and the support pillars 806B located under the same portion 100e1, the portion 100e2, the portion 100e3, or the portion 100e4 of the edge 100e of the semiconductor package 100.

[0094] Figure 3D is a schematic bottom view of a semiconductor device 60 according to some embodiments of the present disclosure. Figure 3A ,exist Figure 3D 2 shows the positions of the connection terminals 600, the passive devices 700, and the support posts 804 and 808 above the dielectric layer 231 of the circuit substrate 200. In addition, the coverage areas of the ring 400 and the semiconductor package 100 are also shown in dashed lines and dotted lines, respectively. In some embodiments, the support post 808 has an annular shape and is arranged below the edge 100e of the semiconductor package 100. That is, the support post 808 may form a frame corresponding to the outline of the vertical projection of the semiconductor package 100. In some embodiments, some of the connection terminals 600 and the passive devices 700 may be arranged in a space surrounded by the frame, and the remaining connection terminals 600 and the passive devices 700 may be arranged outside the frame. In some embodiments, the support post 808 may form a continuous path. That is, there may be no gaps in the frame. In some alternative embodiments, there may be one or more gaps in the frame.

[0095] Figure 3E is a schematic bottom view of a semiconductor device 70 according to some embodiments of the present disclosure. Figure 3A ,exist Figure 3E 2 shows the positions of the connection terminal 600 and the support pillars 802, 804, and 808 above the dielectric layer 231 of the circuit substrate 200. In addition, the coverage areas of the ring 400 and the semiconductor package 100 are also shown by dotted lines and dashed lines, respectively. In some embodiments, the semiconductor device 70 includes different types of support pillars 802, 804, and 808. For example, the semiconductor device 70 may include a support pillar 802, a support pillar 804, and a support pillar 808. Figure 3D The frame-shaped support column 808 described for the semiconductor device 60 may also include the support column 808 as described for the semiconductor device 60 Figure 3A and Figure 3B The semiconductor device 70 may further include the support column 802 described in the semiconductor device 30 or the semiconductor device 40. Figure 3C The slender support column 806A or the slender support column 806B in the embodiment.

[0096] Figure 4Ais a schematic cross-sectional view of an electronic device 85 according to some embodiments of the present disclosure. The electronic device 85 includes a semiconductor device 80 connected to a circuit carrier 900. The semiconductor device 80 includes: a semiconductor package 100 connected to the side 200a of the circuit substrate 200; a cover layer 420 fixed to the side 200a of the circuit substrate 200; and a connection terminal 600 and a passive device 700 disposed on the side 200b of the circuit substrate 200 between the circuit substrate 200 and the circuit carrier 900. In some embodiments, the cover layer 420 is fixed to the circuit substrate 200 by a bonding material 410 disposed at the periphery of the circuit substrate 200. In some embodiments, the cover layer 420 can promote the dissipation of heat generated during the use of the electronic device 85. In some embodiments, the cover layer 420 includes: a cover 422 extending above the semiconductor package 100; a fixing flange 424 extending from the cover 422 to the circuit substrate 200; and a support flange 426 extending from the cover 422 to the circuit carrier 900. The fixing flange 424 contacts the bonding material 410, thereby fixing the cover 420 to the circuit substrate 200. On the other hand, the support flange 426 reaches the circuit carrier 900, which extends along the outer edge 200e of the circuit substrate 200 to the outside of the coverage area of ​​the circuit substrate 200. That is, the support flange 426 may contact the circuit carrier 900 outside the area covered by the circuit substrate 200. In some embodiments, the fixing flange 424 and the support flange 426 are formed as a single piece reaching the circuit substrate 200, wherein the fixing flange 424 ends and the support flange 426 further extends toward the circuit carrier 900. That is, in some embodiments, the support flange 426 may be regarded as a protrusion of the fixing flange 424, wherein a portion of the fixing flange 424 falls on the bonding material 410 on the circuit substrate 200, and the remaining portion of the fixing flange 424 extends beyond the outer edge 200e of the circuit substrate 200 and reaches the circuit carrier 900 as the support flange 426. In some embodiments, the coating 420 is formed integrally from a block of material (e.g., copper) having a higher melting point than the material of the connection terminal 600. In some embodiments, the coating 420 can provide structural support for the electronic device 85 by contacting the circuit carrier 900. In some embodiments, because the coating 420 has a melting temperature higher than the temperature at which the soldering or reflow of the connection terminal 600 is performed, the coating 420 can resist deformation during the soldering or reflow step. That is, the coating 420 can provide mechanical resistance to warping (bending) of the circuit substrate 200 toward the circuit carrier 900. In some embodiments, by including the coating 420 with the support flange 426, the observed warping can be reduced compared to the case where the support flange 426 is not included.In some embodiments, the reduced warping of the circuit substrate 200 may avoid shortening of the connection terminal 600 that may occur in a minimum area, thereby increasing the reliability of the electronic device 85 .

[0097] Figure 4B is a schematic cross-sectional view of an electronic device 95 according to some embodiments of the present disclosure. The electronic device 95 includes a semiconductor device 90 connected to a circuit carrier 900. The semiconductor device 90 includes: a semiconductor package 100 connected to a side 200a of a circuit substrate 200; a cover layer 430 fixed to the side 200a of the circuit substrate 200; and a connection terminal 600 and a passive device 700 disposed on the side 200b of the circuit substrate 200 between the circuit substrate 200 and the circuit carrier 900. In some embodiments, the cover layer 430 is fixed to the circuit substrate 200 by a bonding material 410 disposed on the side 200a of the circuit substrate 200. In some embodiments, the cover layer 430 includes: a cover 432 extending above the semiconductor package 100; a fixing flange 434 extending from the cover 432 to the circuit substrate 200; and a support flange 436 extending from the cover 434 to the circuit carrier 900. The fixing flange 434 contacts the bonding material 410, thereby fixing the coating 430 to the circuit substrate 200. On the other hand, the support flange 436 passes through the circuit substrate 200 to reach the circuit carrier 900. That is, the support flange 436 can pass through the core layer 210 and the dielectric layer 211, dielectric layer 221, and dielectric layer 231 of the buildup layer 220 and the buildup layer 230 to reach the circuit carrier 900. In some embodiments, the circuit substrate 200 can be perforated before the coating 430 is installed to accommodate the support flange 436. In some embodiments, the coating 430 is integrally formed of a block of material (e.g., copper) having a higher melting point than the material of the connection terminal 600. In some embodiments, the coating 430 can provide structural support for the electronic device 95 by contacting the circuit carrier 900. In some embodiments, because the coating 430 has a higher melting temperature than the temperature at which the welding or reflow of the connection terminal 600 is performed, the coating 430 can resist deformation during the welding or reflow step. That is, the coating layer 430 can provide mechanical resistance to the circuit substrate 200 from warping (bending) toward the circuit carrier 900. In some embodiments, the support flange 436 can be made to contact the circuit carrier 900 corresponding to the minimum area of ​​the warping profile. Thereby, the observed warping can be reduced compared to the case where the support flange 436 is not included. In some embodiments, the reduced warping of the circuit substrate 200 can avoid the shortening of the connection terminal 600 that may occur in the minimum area, thereby increasing the reliability of the electronic device 95.

[0098] In an electronic device according to some embodiments, an electrical connection between a circuit substrate and a circuit carrier is established via a connection terminal. In some embodiments, an electrically floating support is included between the circuit substrate and the circuit carrier next to the connection terminal. In some embodiments, the support may be a support column fixed to the circuit substrate via a welding material. In some alternative embodiments, the support may be a support flange fixed to the cladding of the circuit substrate, for example, via a bonding material. In some alternative embodiments, the support may be a passive device on the circuit substrate disposed on the same side of the connection terminal. The passive device used as a support may be electrically insulated from the circuit substrate. In some embodiments, the material of the support has a higher melting temperature (begins to melt at a higher temperature) than the material of the connection terminal. In some embodiments, the support may provide mechanical resistance to the circuit substrate that is warped (bent) toward the circuit carrier. In some embodiments, the support may contact the circuit carrier corresponding to the minimum area of ​​the warping profile of the circuit carrier, thereby possibly reducing the observed warping, compared to the case where the support is not included. In some embodiments, the reduced warping of the circuit substrate may avoid the shortening of the connection terminal that potentially exists in the minimum area of ​​the warping profile, thereby increasing the reliability of the device.

[0099] According to some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device includes a circuit substrate, a semiconductor package, a connection terminal and a support. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connection terminal is located on the second side of the circuit substrate and is electrically connected to the semiconductor package via the circuit substrate. The support is located on the second side of the circuit substrate next to the connection terminal. The material of the support has a melting temperature higher than the melting temperature of the connection terminal.

[0100] In some embodiments, the support member is a support column, and the first portion of the support column is disposed below the edge of the semiconductor package. In some embodiments, the first portion of the support column includes a support column having an annular shape. In some embodiments, the semiconductor device further includes a ring disposed on the first side of the circuit substrate and surrounding the semiconductor package, wherein the first support column is disposed at the corner of the circuit substrate below the ring. In some embodiments, the support member is a support flange belonging to a coating fixed to the first side of the circuit substrate. In some embodiments, the coating further includes a cover extending above the semiconductor package, and the support flange is connected to the cover and extends from the cover toward the circuit substrate. In some embodiments, the coating further includes a fixing flange fixed to the first side of the circuit substrate via a bonding material. In some embodiments, the support member is a passive device electrically insulated from the circuit substrate. In some embodiments, the connecting terminal is 20% to 100% thicker than the support member.

[0101] According to some embodiments of the present disclosure, an electronic device is provided. The electronic device includes a circuit carrier and a semiconductor device connected to the circuit carrier. The semiconductor device includes a circuit substrate, a semiconductor package, a connection terminal and a support column. The circuit substrate has a core layer sandwiched between a first stacking layer and a second stacking layer. The semiconductor package is connected to the first stacking layer. The connection terminal is connected to the second stacking layer and is electrically connected to the semiconductor package via the circuit substrate. The support column is located on the second stacking layer next to the connection terminal and is electrically insulated from the circuit substrate. The connection terminal and the support column are arranged between the circuit carrier and the circuit substrate. The support column has a first melting temperature higher than the second melting temperature of the connection terminal.

[0102] In some embodiments, the support column is fixed to the circuit substrate via a portion of an organic adhesive. In some embodiments, the support column is fixed to the circuit substrate via a portion of a welding material. In some embodiments, the connection terminal and a portion of the support column are arranged on the circuit substrate at a fixed spacing along a first direction between adjacent connection terminals and support columns. In some embodiments, the support column is electrically insulated from the circuit carrier. In some embodiments, a first support column of the support column is arranged below an edge of the semiconductor package. In some embodiments, the electronic device further includes a passive device connected to the second buildup layer and electrically connected to the semiconductor package via the circuit substrate.

[0103] According to some embodiments of the present disclosure, a method for manufacturing an electronic device is provided. The manufacturing method comprises the following steps. A semiconductor package is connected to a first side of a circuit substrate. A connecting terminal is disposed on a second side of the circuit substrate opposite to the first side. A support column is disposed on the second side of the circuit substrate. The support column has a first melting temperature higher than a second melting temperature of the connecting terminal. A heating step is performed to adhere the circuit substrate to a circuit carrier via the connecting terminal. The heating step is performed at a temperature higher than the second melting temperature and lower than the first melting temperature.

[0104] In some embodiments, the manufacturing method further includes placing a passive device on the second side of the circuit substrate. In some embodiments, the manufacturing method further includes dispensing a solder material on the second side of the circuit substrate before placing the connection terminal and the support column. In some embodiments, a first portion of the solder material is placed in electrical contact with a conductive pattern of the circuit substrate, a second portion of the solder material is placed on a dielectric layer of the circuit substrate, the connection terminal is placed on the first portion of the solder material, and the support column is placed on the second portion of the solder material.

[0105] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a circuit substrate having a first side and a second side opposite to the first side; a semiconductor package connected to the first side of the circuit substrate; a connection terminal located on the second side of the circuit substrate and electrically connected to the semiconductor package via the circuit substrate; as well as a plurality of support members located on the second side of the circuit substrate beside the connection terminals, wherein the semiconductor package is separated from at least one of the plurality of support members by a lateral gap, The material of the support member has a melting temperature higher than a melting temperature of the connection terminal.

2. The semiconductor device according to claim 1, wherein: The support member is a support column, and a first portion of the support column is disposed below an edge of the semiconductor package.

3. The semiconductor device according to claim 2, characterized in that The first portion of the support column includes a support column having an annular shape.

4. The semiconductor device according to claim 2, characterized in that Further included is a ring disposed on the first side of the circuit substrate and surrounding the semiconductor package, wherein first support posts are disposed at a corner of the circuit substrate below the ring.

5. The semiconductor device according to claim 1, wherein: The support is a support flange belonging to a cover layer fixed to the first side of the circuit substrate.

6. The semiconductor device according to claim 5, characterized in that The encapsulation layer further includes a cover extending over the semiconductor package, and the support flange is connected to the cover and extends from the cover toward the circuit substrate.

7. The semiconductor device according to claim 6, characterized in that The cover further includes a fixing flange fixed to the first side of the circuit substrate via a bonding material.

8. The semiconductor device according to claim 1, wherein: The support member is a passive component electrically insulated from the circuit substrate.

9. The semiconductor device according to claim 1, wherein: The connection terminal is 20% to 100% thicker than the support member.

10. An electronic device, characterized in that: include: a circuit carrier, and A semiconductor device, connected to the circuit carrier, comprising: A circuit substrate having a core layer sandwiched between a first buildup layer and a second buildup layer; a semiconductor package connected to the first buildup layer; a connection terminal connected to the second buildup layer and electrically connected to the semiconductor package via the circuit substrate; and a support column, located on the second buildup layer beside the connection terminal and electrically insulated from the circuit substrate, The connecting terminal and the supporting column are disposed between the circuit carrier and the circuit substrate, and the supporting column has a first melting temperature higher than a second melting temperature of the connecting terminal.

11. The electronic device according to claim 10, characterized in that: The support post is fixed to the circuit substrate via a portion of an organic adhesive.

12. The electronic device according to claim 10, characterized in that: The support column is fixed to the circuit substrate via a portion of solder material.

13. The electronic device according to claim 10, characterized in that: The connection terminals and a portion of the support pillars are disposed on the circuit substrate at a fixed interval along a first direction between adjacent connection terminals and support pillars.

14. The electronic device according to claim 10, characterized in that: The support column is electrically insulated from the circuit carrier.

15. The electronic device according to claim 10, characterized in that: A first support column of the support columns is disposed below an edge of the semiconductor package.

16. The electronic device according to claim 10, characterized in that: Further included is a passive device connected to the second build-up layer and electrically connected to the semiconductor package via the circuit substrate.

17. A method for manufacturing an electronic device, characterized in that: include: connecting a semiconductor package to the first side of the circuit substrate; placing connection terminals on a second side of the circuit substrate opposite to the first side; disposing a plurality of support pillars on the second side of the circuit substrate, wherein the plurality of support pillars have a first melting temperature higher than a second melting temperature of the connection terminals, and the semiconductor package is separated from at least one of the plurality of support pillars by a lateral gap; as well as A heating step is performed to attach the circuit substrate to a circuit carrier via the connecting terminals, wherein the heating step is performed at a temperature higher than the second melting temperature and lower than the first melting temperature.

18. The method for manufacturing an electronic device according to claim 17, characterized in that: The method further includes placing a passive device on the second side of the circuit substrate.

19. The method for manufacturing an electronic device according to claim 17, characterized in that: Further comprising dispensing solder material on the second side of the circuit substrate before disposing the connection terminals and the support pillars.

20. The method for manufacturing an electronic device according to claim 19, characterized in that: The first portion of the soldering material is disposed in electrical contact with the conductive pattern of the circuit substrate, the second portion of the soldering material is disposed on the dielectric layer of the circuit substrate, the connecting terminal is disposed on the first portion of the soldering material, and the supporting column is disposed on the second portion of the soldering material.

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