A semiconductor device and a forming method thereof

Abstract

Embodiments of the present invention provide a semiconductor device and a forming method. In the embodiments of the present invention, a bird's beak-shaped oxide layer is formed on the sidewalls of the floating gate material layer. Therefore, after removing the blocking layer and the oxide layer simultaneously, a sharpened floating gate cantilever angle is formed, avoiding the passivation of the floating gate cantilever angle. The electric field is concentrated at the floating gate cantilever angle, which is beneficial to the electrons in the floating gate tunneling into the erase gate through the floating gate cantilever angle, improving the erase efficiency. Thus, the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a forming method thereof. Background Art

[0002] With the continuous development of semiconductor manufacturing processes, the integration of semiconductor devices is getting higher and higher, and the feature size of semiconductor devices is gradually shrinking. However, the performance of semiconductor devices still needs to be improved. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a semiconductor device and a forming method thereof to improve the performance of semiconductor devices.

[0004] In a first aspect, an embodiment of the present invention provides a forming method of a semiconductor device, the method comprising:

[0005] Providing a front-end device layer, in which a floating gate material layer and a plurality of discrete control gate stack structures covering the floating gate material layer are formed;

[0006] Removing the floating gate material layer in a first region, the first region being located on a first side of the control gate stack structure;

[0007] Thinning the floating gate material layer in a second region, the second region being located on a second side of the control gate stack structure;

[0008] Forming a barrier layer covering at least the floating gate material layer and the sidewalls of the control gate stack structure;

[0009] Using the control gate stack structure and the barrier layer on the sidewalls of the control gate stack structure as a mask to etch the floating gate material layer to expose the sidewall of the floating gate material layer on the second side;

[0010] Oxidizing the sidewall of the floating gate material layer on the second side to form an oxide layer; and

[0011] Removing the oxide layer and the barrier layer to form a floating gate, so that the floating gate cantilever angle is sharpened.

[0012] Further, the floating gate cantilever angle is at the top of the second side of the floating gate.

[0013] Further, after forming the floating gate, the method further comprises:

[0014] Forming an erase gate structure in the second region;

[0015] Forming a word line in the first region.

[0016] Further, the oxidizing the sidewall of the floating gate material layer specifically is:

[0017] The floating gate material layer in a predetermined region is converted into an oxide layer by a thermal oxidation process.

[0018] Further, the predetermined region is a region that extends a predetermined size both laterally and longitudinally from the sidewall of the floating gate material layer on the second side.

[0019] Further, thinning the floating gate material layer in the second region specifically includes:

[0020] The floating gate material layer on the second side of the control gate stack structure is thinned by 20 Å - 50 Å using a self-aligned etching process.

[0021] Further, the material of the barrier layer is silicon oxide or silicon nitride, and the thickness of the barrier layer is 20 Å - 50 Å.

[0022] Further, removing the oxide layer and the barrier layer specifically includes:

[0023] The oxide layer and the barrier layer are etched using an isotropic etching process.

[0024] In a second aspect, an embodiment of the present invention provides a semiconductor device, which includes:

[0025] A front-end device layer;

[0026] A floating gate having a sharpened cantilever angle on one side; and

[0027] A control gate stack structure formed on the floating gate.

[0028] Further, the semiconductor device further includes:

[0029] An erase gate on the side where the floating gate has a sharpened cantilever angle;

[0030] A word line on the side where the floating gate does not have a sharpened cantilever angle.

[0031] In the embodiment of the present invention, a bird's beak-shaped oxide layer is formed on the sidewall of the floating gate material layer. Therefore, after removing the barrier layer and the oxide layer simultaneously, a sharpened floating gate cantilever angle is formed. The situation of floating gate cantilever angle passivation is avoided. The electric field is concentrated at the floating gate cantilever angle, which is beneficial for electrons in the floating gate to tunnel into the erase gate through the floating gate cantilever angle, improving the erase efficiency. Thus, the performance of the semiconductor device can be improved. Description of the Drawings

[0032] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0033] Figure 1 Is a schematic diagram of the basic structure of a split-gate flash memory;

[0034] Figures 2 - 4 is a cross-sectional schematic view of the structure formed in each step of the method for forming a semiconductor device of the comparative example;

[0035] Figure 5 is a flowchart of the method for forming a semiconductor device according to an embodiment of the present invention;

[0036] Figures 6 - 13 is a cross-sectional schematic view of the structure formed in each step of the method for forming a semiconductor device according to an embodiment of the present invention;

[0037] Figure 14 is a cross-sectional schematic view of the structure of a semiconductor device according to an embodiment of the present invention. Detailed Description of the Invention

[0038] The present invention will be described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details. In order to avoid obscuring the essence of the present invention, well-known methods, processes, procedures, elements, and circuits are not described in detail.

[0039] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0040] Unless the context clearly requires otherwise, words such as "including" and "comprising" in the application documents shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, they are in the sense of "including but not limited to".

[0041] In the description of this application document, it should be understood that terms such as "first" and "second" are used only for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0042] In the description of this application document, it should be understood that the term "layer" is used in its broadest sense, thus including films, cover layers, or the like, and a layer may include multiple sub-layers.

[0043] In the description of this application document, it should be understood that throughout the specification, traditional etching techniques known in the semiconductor manufacturing field for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide, or similar materials include, for example, wet chemical etching, plasma etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing process (Chemical Mechanical Polishing, CMP), and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques may be interchangeable. For example, stripping photoresist may include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly onto the sample.

[0044] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. Commonly used existing semiconductor devices include flash memories.

[0045] Flash Memory (FM) is a form of electronically erasable programmable read-only memory that allows a memory to be erased or written multiple times during operation. As an electrically programmable and erasable non-volatile storage device, flash memory is widely used in System On Chip (SOC). Structurally, flash memory devices can be mainly divided into stacked gate structures and split gate structures. Traditional stacked gate flash memories have reliability issues such as programming / erase interference, over-erasure, charge retention characteristics, and the durability of erase / write. The split gate flash memory applying a two-transistor cell structure can effectively avoid the reliability issues of stacked gate flash memories.

[0046] Figure 1 is a schematic diagram of the basic structure of a split gate flash memory. As Figure 1 shown, the split gate flash memory includes a front-end device layer 1. A floating gate oxide layer 101, a floating gate 102, a gate dielectric layer 103, a control gate 104, a control gate oxide layer 105, and a control gate silicon nitride 106 are sequentially formed on the front-end device layer by a stack self-alignment process. It also includes sidewall layers 107 formed on both sides of the control gate 104 and sidewall oxide layers 108 formed on the surface of the sidewall layers 107 and on both sides of the floating gate 102. Among them, active regions 111 and drain regions (not shown in the figure) are formed in the front-end device layer 1 on both sides of the floating gate 102. An erase gate 110 is formed on the source region 111. A word line 109 is formed on the drain region.

[0047] The working principle of a split-gate flash memory is as follows: When a data writing operation is performed on the flash memory, a high positive bias voltage is applied to the control gate, causing hot electrons to tunnel through the tunneling oxide layer from the source and inject into the floating gate. When the flash memory is erased, a high negative bias voltage is applied to the control gate, causing the hot electrons injected into the floating gate to flow into the source through the sidewall oxide layer by Fowler-Nordheim (FN) tunneling effect. Affected by the Fowler-Nordheim tunneling effect, the erasing time is longer than the programming time. Therefore, new methods are needed to improve the erasing efficiency of the flash memory.

[0048] As Figures 2 - 4 is a schematic diagram of the structure formed in each step of the method for forming a semiconductor device of the comparative example.

[0049] Referring to Figure 2 , an oxide layer 2 is formed on the side of the control gate sidewall layer 108 close to the erase gate. The floating gate is etched using the control gate, the sidewall layer, and the oxide layer as a mask.

[0050] Referring to Figure 3 , the oxide layer 2 is removed to form an oxide layer 3 covering the sidewall layer 108 and the floating gate 102.

[0051] In the comparative example, an oxide layer is formed on the sidewall layer adjacent to the erase gate, and then the floating gate is etched using the control gate, the sidewall layer, and the oxide layer as a mask. This makes the formed floating gate cantilever longer. During the erase operation, the electric field is concentrated at the floating gate cantilever corner, which is beneficial for the electrons in the floating gate to tunnel into the erase gate through the floating gate cantilever corner 4, resulting in a higher erase efficiency.

[0052] However, as Figure 4 shown, during the process of removing the oxide layer 2, the floating gate cantilever corner 4 will be passivated. The passivation directly affects the erase efficiency, resulting in a low yield of the semiconductor device.

[0053] In view of this, in order to improve the performance of the semiconductor device. Embodiments of the present invention provide a method for forming a semiconductor device. In the embodiments of the present invention, taking the formation of a flash memory as an example for illustration, further, the method of the embodiments of the present invention is used to form a flash memory with a split-gate structure. Further, the method of the embodiments of the present invention can also be used to form other semiconductor devices such as NAND memory (NAND Flash Memory) and static random access memory (Static Random Access Memory, SRAM).

[0054] Figure 5 is a flowchart of the method for forming a semiconductor device according to an embodiment of the present invention. As Figure 5 shown, the method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:

[0055] Step S100: Provide a front-end device layer. A floating gate material layer and a plurality of discrete control gate stack structures covering the floating gate material layer are formed in the front-end device layer.

[0056] Step S200: Remove the floating gate material layer in a first region, where the first region is located on a first side of the control gate stack structure.

[0057] Step S300: Thin the floating gate material layer in a second region, where the second region is located on a second side of the control gate stack structure.

[0058] Step S400: Form a barrier layer covering at least the floating gate material layer and the sidewalls of the control gate stack structure.

[0059] Step S500: Etch the floating gate material layer using the control gate stack structure and the barrier layer on the sidewalls of the control gate stack structure as a mask. To expose the sidewall of the floating gate material layer on the second side.

[0060] Step S600: Oxidize the sidewall of the floating gate material layer. To form an oxide layer.

[0061] Step S700: Remove the oxide layer and the barrier layer. To form a floating gate, making the floating gate cantilever angle sharp.

[0062] In an optional implementation, the method further includes:

[0063] Step S800: Form a floating gate oxide layer wrapping the floating gate.

[0064] Step S900: Form an erase gate structure in the second region.

[0065] Step S1000: Form a word line in the first region.

[0066] Figures 6 - 13 It is a schematic diagram of the structures formed by the steps of the method for forming a semiconductor device according to an embodiment of the present invention.

[0067] Reference Figure 6 , in Step S100, a front-end device layer is provided. A floating gate material layer 11 and a plurality of discrete control gate stack structures 12 covering the floating gate material layer 11 are formed in the front-end device layer.

[0068] Specifically, the front-end device layer provided in step S100 can be a semiconductor substrate or an intermediate structure of a semiconductor device. The intermediate structure of the semiconductor device may include a semiconductor substrate, active devices, passive devices, etc. Further, the active devices and passive devices in the front-end device layer may be capacitors, inductors, resistors, and various transistors, etc. In this embodiment, the front-end device layer includes a substrate 10, a floating gate material layer 11, and a plurality of discrete control gate stack structures 12 covering the floating gate material layer 11.

[0069] Among them, the semiconductor substrate can be a single-crystal silicon substrate, a single-crystal germanium substrate, or a silicon-germanium single-crystal substrate. Alternatively, the semiconductor substrate can also be a silicon-on-insulator (SOI) substrate, silicon-on-insulator stacked (SSOI), silicon-germanium-on-insulator stacked (S-SiGeOI), germanium-silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), a substrate with an epitaxial layer structure on silicon, a compound substrate, or an alloy substrate. The compound substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysproside, and the alloy substrate includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. The SOI substrate includes a semiconductor layer (such as a silicon layer, a silicon-germanium layer, a carbon-silicon layer, or a germanium layer) disposed on an insulating material layer. The material of the floating gate material layer 11 is polysilicon, and the floating gate material layer 11 is used to form a floating gate in subsequent processes.

[0070] The control gate stack structure 12 includes a gate dielectric layer 21, a control gate 22, a control gate oxide layer 23, and a control gate silicon nitride 24 stacked in sequence. Sidewall layers 25 are also formed on both sides of the control gate 22.

[0071] The materials of the sidewalls and the top of the control gate stack structure 12 are silicon oxide or silicon nitride, which are different from the material of the floating gate material layer. In subsequent processes, the control gate stack structure can be used as a mask for etching the floating gate material layer.

[0072] Reference Figure 7 , in step S200, the floating gate material layer 11 in the first region A is removed, and the first region A is located on the first side of the control gate stack structure 12.

[0073] Specifically, the floating gate material layer 11 in the first region A is removed by a lithography process. Using the mask used in the ion implantation process during the formation of the front-end device layer before, a photoresist pattern exposing the first region A is formed on the floating gate material layer, and the floating gate material layer in the first region is removed by a dry etching or wet etching process, and then the photoresist is removed.

[0074] In an alternative implementation, the floating gate material layer 11 is etched using a plasma etching process. The process parameters of the dry etching process are as follows: the flow rate of HBr is 50 sccm - 500 sccm, the flow rate of NF3 is 0 sccm - 50 sccm, the flow rate of O2 is 0 sccm - 50 sccm, the flow rate of He is 0 sccm - 200 sccm, the flow rate of Ar is 0 sccm - 500 sccm, the chamber pressure is 2 mTorr - 100 mTorr, the source power provided is 200 W - 1000 W, and the bias power provided is 0 W - 200 W.

[0075] Reference Figure 8 , in step S300, the floating gate material layer 11 in the second region B is thinned, and the second region B is located on the second side of the control gate stack structure 12.

[0076] The thinning of the floating gate material layer in the second region specifically refers to thinning the floating gate material layer on the second side of the control gate stack structure by 20 Å - 50 Å using a self-aligned etching process.

[0077] The self-aligned etching process specifically utilizes the difference in materials between the control gate stack structure 12 and the floating gate material layer 11, and selects an etching process with a high etching selectivity ratio to etch the floating gate material layer 11. Therefore, no mask is required, which can save costs.

[0078] In an alternative implementation, the second region B of the floating gate material layer 11 is etched using a plasma etching process until the floating gate material layer 11 in the second region B is thinned by 30 Å.

[0079] In this step, the floating gate material layer 11 in the second region B is thinned. In order to expose the upper end of the side wall of the floating gate material layer on one side of the second region B in subsequent processes, the upper end of the side wall of the floating gate material layer on one side of the second region B is then covered with a blocking layer, so as to form a bird's beak-shaped oxide layer in the upper end region of the side wall of the floating gate material layer on one side of the second region B during subsequent oxidation processes.

[0080] Reference Figure 9 , in step S400, a blocking layer 20 is formed that at least covers the floating gate material layer 11 and the side walls of the control gate stack structure 12.

[0081] Specifically, the blocking layer 20 can cover the entire intermediate structure formed in step S300.

[0082] The material of the blocking layer 20 can be silicon nitride or silicon oxide. The thickness of the blocking layer is 20 Å - 50 Å. The blocking layer 20 is used as a mask for etching the floating gate material layer 11 in subsequent processes.

[0083] In this embodiment, the material of the blocking layer 20 is silicon oxide, and the thickness of the blocking layer 20 is 30 angstroms.

[0084] Specifically, the blocking layer 20 can be formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), plasma chemical vapor deposition process (PCVD), low pressure chemical vapor deposition (LPCVD), rapid thermo chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), fluid chemical vapor deposition process (FCVD).

[0085] Reference Figure 10 Referring to

[0086] Specifically, an anisotropic etching process is used to etch the blocking layer 20. Since the etching rate of the anisotropic etching in the vertical direction is greater than that in the horizontal direction, after the blocking layer 20 on the floating gate material layer 11 is etched, the blocking layer 20 on the sidewall of the control gate stack structure 12 will not be completely etched. Therefore, in this step, a self-aligned etching process is adopted, without using a mask, and the floating gate material layer 11 is etched using the control gate stack structure 12 and the blocking layer 20 on the sidewall of the control gate stack structure 12 as a mask.

[0087] In this step, the sidewall of the floating gate material layer 11 on the second side is exposed for oxidation treatment of the sidewall on the second side in subsequent processes.

[0088] Reference Figure 11 Referring to

[0089] The oxidation of the sidewall of the floating gate material layer 11 specifically means: converting the floating gate material layer 11 in a predetermined area into an oxide layer 30 by a thermal oxidation process.

[0090] In the thermal oxidation process, the silicon wafer is placed in an environment of a gas containing an oxidant. The oxidant molecules will reach the surface of the silicon through a boundary layer (BL), and react with the silicon atoms to form silicon dioxide (SiO2). After the originally pure silicon surface grows silicon dioxide, the formed silicon dioxide layer prevents the direct contact between the oxidant and the silicon surface. The oxidant reaches the silicon dioxide / silicon interface through the silicon dioxide layer by diffusion and reacts with the silicon atoms to form a new silicon dioxide layer, causing the silicon dioxide film to thicken continuously.

[0091] In an alternative implementation, the oxidation gas (oxidant) used in the thermal oxidation treatment is oxygen (O2), and the flow rate of oxygen is 1.5 slm to 2.5 slm. The oxidation temperature is 800 °C to 810 °C. The oxidation time is 800 s to 1000 s.

[0092] The predetermined area is an area that extends a predetermined size in the lateral and longitudinal directions from the sidewall of the floating gate material layer 11 on the second side.

[0093] Through the thermal oxidation process, an oxide layer 30 is formed in the sidewall area of the second side of the floating gate not covered by the barrier layer 20. After oxygen atoms enter the polysilicon, they diffuse in all directions. During the growth of the sidewall oxide layer 30, the oxygen atoms diffuse laterally and also longitudinally, which means that there is also slight oxidation growth under the barrier layer 20, which is also called the bird's beak effect of local oxidation.

[0094] In this step, the sidewall of the floating gate material layer 11 on the second side is oxidized to form a bird's beak-shaped oxide layer 30, so that in subsequent processes, the oxide layer 30 and the floating gate material layer 11 have different etching rates, and the oxide layer is removed by a selective etching process to form a sharpened floating gate cantilever angle.

[0095] Reference Figure 12 , in step S700, the oxide layer 30 and the barrier layer 20 are removed to form a floating gate 11a, so that the floating gate cantilever angle 11b is sharpened.

[0096] The removal of the oxide layer 30 and the barrier layer 20 specifically is: etching the oxide layer 30 and the barrier layer 20 by an isotropic etching process. In the etching process, the etching rates of the oxide layer 30 and the barrier layer 20 are greater than the etching rate of the floating gate 11a.

[0097] Since a partial area of the oxide layer 30 is located under the floating gate 11a, the isotropic etching process can ensure that the oxide layer 30 is completely removed.

[0098] The floating gate cantilever angle 11b is less than 90 degrees. Further, the floating gate cantilever angle 11b is 60 degrees - 80 degrees. In the embodiment of the present invention, the floating gate cantilever angle 11b is 78 degrees.

[0099] In the embodiment of the present invention, since a bird's beak-shaped oxide layer is formed on the sidewall of the floating gate material layer, after removing the barrier layer and the oxide layer simultaneously, a sharpened floating gate cantilever angle is formed, avoiding the passivation of the floating gate cantilever angle caused during the removal of the oxide layer in the comparative example.

[0100] In an alternative implementation, a wet etching process is used to remove the barrier layer 20 and the oxide layer 30. The specific parameters include: the etching solution used is a hydrofluoric acid solution, the mass percentage of hydrofluoric acid is 1:100 - 1:1000, and the etching temperature is 15°C - 75°C.

[0101] Reference Figure 12 , in step S800, a floating gate oxide layer 20a covering the floating gate 11a is formed.

[0102] Reference Figure 13 , in step S900, an erase gate structure 40 is formed in the second region B.

[0103] The erase gate structure 40 includes an erase gate dielectric layer and an erase gate. The process of forming the erase gate structure 40 may include a chemical vapor deposition process.

[0104] Reference Figure 13 , in step S1000, a word line 50 is formed in the first region A.

[0105] The process of forming the word line 50 may include a chemical vapor deposition process.

[0106] In subsequent processes, an interconnect structure connected to the control gate stack structure, the erase gate, and the word line is formed. And the formed semiconductor structure is packaged to form a complete semiconductor device.

[0107] In the embodiment of the present invention, a bird's beak-shaped oxide layer is formed on the sidewall of the floating gate material layer. Therefore, after removing the barrier layer and the oxide layer simultaneously, a sharpened floating gate cantilever angle is formed, avoiding the passivation of the floating gate cantilever angle. The electric field is concentrated at the floating gate cantilever angle, which is beneficial for electrons in the floating gate to tunnel into the erase gate through the floating gate cantilever angle, improving the erase efficiency. Thus, the performance of the semiconductor device can be improved.

[0108] On the other hand, the embodiment of the present invention further provides a semiconductor device, which includes a front-end device layer, a floating gate, and a control gate stack structure.

[0109] Figure 14 is a cross-sectional schematic diagram of the semiconductor device according to the embodiment of the present invention. Reference Figure 14, in an optional implementation, the semiconductor device described in the embodiments of the present invention includes: a front-end device layer, a floating gate 11a', a control gate stack structure 12', a floating gate oxide layer 20a', an erase gate 40', and a word line 50'.

[0110] The front-end device layer includes a substrate 10'.

[0111] The floating gate 11a' has a sharpened cantilever angle 11b' on one side. The floating gate cantilever angle 11b' is less than 90 degrees. Further, the floating gate cantilever angle 11b' is 60 degrees - 80 degrees. In the embodiments of the present invention, the floating gate cantilever angle 11b' is 78 degrees.

[0112] The control gate stack structure 12' is formed on the floating gate. The control gate stack structure 12' includes a gate dielectric layer 21', a control gate 22', a control gate oxide layer 23', and a control gate silicon nitride 24' stacked in sequence. Sidewall layers 25' are also formed on both sides of the control gate.

[0113] The erase gate 40' is on the side where the floating gate 11a' has a sharpened cantilever angle 11b';

[0114] The word line 50' is on the side where the floating gate does not have a sharpened cantilever angle 11b'.

[0115] The floating gate oxide layer 20a' wraps the floating gate 11a'.

[0116] In the embodiments of the present invention, the floating gate has a sharpened floating gate cantilever angle. The electric field is concentrated at the floating gate cantilever angle, which is beneficial for electrons in the floating gate to tunnel into the erase gate through the floating gate cantilever angle, improving the erase efficiency. Thereby, the performance of the semiconductor device can be improved.

[0117] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: Providing a front-end device layer, in which a floating gate material layer and a plurality of discrete control gate stack structures covering the floating gate material layer are formed; Removing the floating gate material layer in a first region, the first region being located on a first side of the control gate stack structure; Thinning the floating gate material layer in a second region, the second region being located on a second side of the control gate stack structure; Forming a barrier layer covering at least the floating gate material layer and the sidewalls of the control gate stack structure; Using the control gate stack structure and the barrier layer on the sidewalls of the control gate stack structure as a mask to etch the floating gate material layer to expose the sidewall of the floating gate material layer on the second side, and at the same time, the barrier layer covers the sidewall of the floating gate material layer on the first side; Oxidizing the sidewall of the floating gate material layer on the second side that is not covered by the barrier layer to form an oxide layer; and Removing the oxide layer and the barrier layer to form a floating gate, so that the floating gate cantilever angle is sharpened.

2. The method for forming a semiconductor device according to claim 1, wherein, The floating gate cantilever angle is at the top of the second side of the floating gate.

3. The method for forming a semiconductor device according to claim 1, wherein, After forming the floating gate, the method further includes: Forming an erase gate structure in the second region; Forming a word line in the first region.

4. The method for forming a semiconductor device according to claim 1, wherein, The oxidizing the sidewall of the floating gate material layer on the second side that is not covered by the barrier layer specifically is: Converting the floating gate material layer in a predetermined region into an oxide layer by using a thermal oxidation process.

5. The method for forming a semiconductor device according to claim 4, wherein, The predetermined region is a region extending a predetermined size in the lateral and longitudinal directions from the sidewall of the floating gate material layer on the second side.

6. The method for forming a semiconductor device according to claim 1, characterized in that, The thinning the floating gate material layer in the second region specifically is: Thinning the floating gate material layer on the second side of the control gate stack structure by 20 Å - 50 Å using a self-aligned etching process.

7. The method for forming a semiconductor device according to claim 1, wherein The material of the barrier layer is silicon oxide or silicon nitride, and the thickness of the barrier layer is 20 Å - 50 Å.

8. The method for forming a semiconductor device according to claim 1, wherein The removing the oxide layer and the barrier layer specifically is: Etching the oxide layer and the barrier layer by using an isotropic etching process.

9. A semiconductor device, characterized in that, The semiconductor device is formed by the method for forming a semiconductor device according to any one of claims 1 - 8, and the semiconductor device includes: A front-end device layer; A floating gate having a sharpened cantilever angle on one side, the sharpened cantilever angle is formed by oxidizing the sidewall of the floating gate material layer on the second side to form a bird's beak-shaped oxide layer, and then removing the oxide layer by using selective etching; and A control gate stack structure formed on the floating gate; An erase gate, the floating gate forms a sharpened cantilever angle only on the side facing the erase gate; A word line, on the side of the floating gate where there is no sharpened cantilever angle, and the erase gate and the word line are respectively located on both sides of the floating gate.

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