Method and apparatus for improving switching conditions in a closed loop system

Abstract

To improve switching conditions in a closed loop system, an example apparatus includes a first switch (508) adapted to be coupled to a first node (528), a second switch (510) adapted to be coupled to a second node (526), and a capacitor (502) including a first terminal (504) and a second terminal (506). The first terminal (504) is coupled to the first switch (508), and the second terminal (506) is coupled to the second switch (510). A first multiplier (512) is coupled to the first terminal (504) and the second terminal (506). The first multiplier (512) is adapted to be coupled to at least a third node (530) and a fourth node (532). A second multiplier (514) is coupled to the first terminal (504) and the second terminal (506).

Description

Technical Field

[0001] This application relates generally to gate drivers, and more specifically to methods and apparatus for improving switching conditions in closed-loop systems. Background Technology

[0002] High-voltage and / or high-current applications utilize power electronic devices capable of operating effectively and efficiently at elevated temperatures. In such applications, power modules use power metal-oxide-semiconductor field-effect transistors (MOSFETs) to provide power. Power MOSFETs can be used as power delivery devices to support tens or hundreds of amperes during normal operation, delivering power to the load. Summary of the Invention

[0003] The example device includes: a first switch adapted to be coupled to a first node, a second switch adapted to be coupled to a second node, and a capacitor including a first terminal and a second terminal. The first terminal is coupled to the first switch, and the second terminal is coupled to the second switch. A first multiplier is coupled to the first and second terminals. The first multiplier is adapted to be coupled to at least a third and a fourth node. A second multiplier is coupled to both the first and second terminals. Attached Figure Description

[0004] Figure 1 This is a block diagram showing a device used to stop the output signal until the input signal stabilizes.

[0005] Figure 2 It is about Figure 1 A graph showing the voltage changes of the output and input signals over time.

[0006] Figure 3 This is a schematic diagram of an example gate driver system, which includes an example gate driver integrated circuit (IC) that includes an example converter for implementing the example described herein.

[0007] Figure 4 yes Figure 3 A schematic diagram of an example converter, which includes various components to improve startup time and / or reduce overshoot caused by frequency compensation.

[0008] Figure 5 yes Figure 4 A schematic diagram of an example compensator, which is used to improve... Figure 3 Gate driver IC and Figure 3 and Figure 4 The switching characteristics of the converter.

[0009] Figure 6 Is with Figure 5A schematic diagram of an example multiplier associated with a current mirror, used to adjust the effective capacitance of a capacitor.

[0010] Figure 7 yes Figure 4 and Figure 5 The following is a diagram illustrating the voltage and current of various compensation capacitors in an example compensator as a function of time.

[0011] Figure 8 yes Figure 4 and Figure 5 The following is a diagram illustrating the voltage and current variations over time for various additional compensators in an example compensator.

[0012] Figure 9 It includes various components to improve Figure 3 Gate driver IC and Figure 3 and Figure 4 A schematic diagram of an additional example compensator for the switching characteristics of the converter.

[0013] Figure 10 yes Figure 9 The following is a diagram illustrating the voltage and current of various compensation capacitors in an example compensator as a function of time.

[0014] Figure 11 This is a state diagram representing the example operation mode, where Figure 4 , Figure 5 or Figure 9 The compensator can operate in these operating modes.

[0015] Figure 12 This is a flowchart representing machine-readable instructions that can be executed to achieve... Figure 4 and Figure 5 compensator or Figure 9 The compensator is used to improve the performance by adjusting the charge of the example compensation capacitor. Figure 3 Example of switching conditions for a gate driver IC. Detailed Implementation

[0016] The accompanying drawings are not drawn to scale. Typically, the same reference numerals will be used throughout the drawings, and the description will denote the same or similar parts.

[0017] When identifying multiple elements or components that can be individually referenced, the descriptors “first,” “second,” “third,” etc., are used herein. Unless otherwise specified or understood based on their context of use, these descriptors are not intended to assign any meaning of priority or chronological order, but are merely labels to refer to multiple elements or components separately for ease of understanding of the described examples. In some examples, the descriptor “first” may be used to refer to an element in the specific embodiment, while different descriptors such as “second” or “third” may be used in the claims to refer to the same element. In such cases, it should be understood that such descriptors are used merely for ease of referencing multiple elements or components.

[0018] High-voltage and / or high-current isolated gate driver environments and applications, such as traction inverters in electric vehicles (EVs), hybrid electric vehicles (HEVs), etc., utilize power electronic devices capable of operating effectively and efficiently at elevated temperatures. Power delivery and / or management modules have been developed to provide the required power using low-impedance power MOSFETs made of silicon carbide (SiC). Power SiC MOSFETs can be used as power delivery devices to support tens or hundreds of amperes during normal operation for delivering power to the load. Alternatively, power modules using low-impedance isolated gate bipolar transistor (IGBT) devices have been developed to meet the necessary power requirements of applications such as traction inverters in EVs, HEVs, etc.

[0019] In such high-power applications, the temperature of the power SiC MOSFET can rise to levels that damage the SiC MOSFET, the load coupled to the SiC MOSFET, and / or surrounding components. In such isolated, high-voltage and / or high-current gate driver environments and applications, an analog signal representing the SiC MOSFET temperature can be sensed and converted into a digital temperature signal for use by an accompanying controller (e.g., a microcontroller unit (MCU)). In response to obtaining the digital temperature signal, the MCU can adjust the switching speed of the SiC MOSFET and / or stop operation. The digital temperature signal can be used by the accompanying controller (e.g., the MCU) to indirectly control the temperature of the SiC MOSFET or the corresponding switching device.

[0020] Converters (e.g., analog-to-pulse-width modulators (A2PWM)) can be used to convert analog signals representing temperature into digital temperature signals (e.g., pulse-width modulated signals (PWM signals)). In high-power and / or high-current gate driver applications, converters are typically noise-sensitive circuits designed to be included within high-power and / or high-current gate drivers to maintain performance specifications. Such performance specifications may include maintaining desired overall accuracy across the entire temperature range, desired duty cycle control, reduction of missed or skipped pulses, and / or negligible phase distortion. In such noise-sensitive converters, unwanted induced noise and / or ringing can cause deviations from the aforementioned performance specifications, damage to internal components, reduced performance efficiency, etc.

[0021] In isolated high-power and / or high-current gate driver applications, the switching characteristics of the converter (e.g., switching speed, total overshoot, settling time) typically dominate the switching characteristics of the isolated high-power and / or high-current gate driver (e.g., turn-on speed). For example, if the settling time of the compensated node converter is longer than the settling time of the isolated high-power and / or high-current gate driver signal, the switching speed of the isolated high-power and / or high-current gate driver will be reduced to a switching speed similar to that of the converter. Therefore, when the converter is affected by unwanted induced noise and / or ringing, it may fail to meet converter performance specifications, and the switching characteristics of the converter (e.g., turn-on speed, total overshoot) may be affected (e.g., switching speed slowed to over 100 ms and / or total overshoot increased to unsafe levels). Due to converter performance degradation, the switching characteristics of the isolated high-power and / or high-current gate driver IC (e.g., switching speed, total overshoot) may be affected (e.g., switching speed reduced to over 100 ms and / or total overshoot increased to unsafe levels).

[0022] Typical techniques for protecting and / or ensuring proper operation of noise-sensitive converters include utilizing large compensation capacitors (e.g., 200 picofarads) in the circuit containing the amplifier (e.g., inside or outside the amplifier) ​​to ensure proper frequency compensation. For example, the bandwidth of the converter may be partially set by a dominant pole implemented at or across the compensation node of the converter's operational amplifier. In such techniques, the frequency compensation method may be referred to hereinafter as dominant pole compensation.

[0023] Furthermore, when dominant pole compensation is implemented, the start-up time of the drive signals for the SiC MOSFET and / or suitable power switching devices is delayed (e.g., by orders of magnitude 500 microseconds to 1 millisecond) due to the inherently large compensation capacitance of appropriate frequency compensation. The switching characteristics of the converter may be affected, and therefore, the isolated high-voltage and / or high-power gate drivers experience poor switching characteristics (e.g., start-up time delays on the order of magnitude 500 microseconds to 1 millisecond, and / or overshoot during step response) due to the use of large compensation capacitors (e.g., 200 picofarads) in the converter.

[0024] Alternatively, techniques to protect and / or ensure proper operation of noise-sensitive converters include delaying (e.g., stopping) the output signal (e.g., PWM signal) until the input signal has been established (e.g., the input signal no longer experiences transients). Figure 1 This is a block diagram showing device 100, which stops outputting a signal (line 102) until the input signal (line 104) stabilizes. A disabler 106 disables the output signal (line 102) for 500 microseconds. Figure 2 It is about Figure 1 The graph 200 shows the voltage variation of the output signal (line 102) and input signal (line 104) over time. Delay segment 202 shows a 500-microsecond delay between the on-time of the input signal (line 104) and the on-time of the output signal (line 102). Figure 1 In this case, the startup time is delayed by an order of 500 microseconds.

[0025] Examples described herein include methods and apparatus for protecting and / or ensuring proper operation of noise-sensitive converters while maintaining fast (e.g., 60 microseconds) startup times. Examples described herein include using a converter (e.g., A2PWM) to convert analog signals (e.g., analog signals representing temperature) into digital signals (e.g., PWM signals representing temperature). Furthermore, examples described herein include utilizing frequency compensation to ensure appropriate converter loop bandwidth during analog-to-digital conversion (e.g., converting analog signals to PWM signals). Example frequency compensation techniques include dominant pole compensation.

[0026] In the examples described herein, the converter bandwidth is set low enough (e.g., 10 Hz to 100 Hz) to protect the noise-sensitive converter and reject noise and / or ringing due to high voltage and / or high power switching. In the examples described herein, a large compensation capacitor (e.g., 200 picofarads) is implemented at and / or across the compensation node in the converter (e.g., across the compensation node in the operational amplifier within the converter). The examples described herein include methods and apparatus for improving the switching characteristics of high-voltage and / or high-power gate driver applications or any suitable closed-loop system resulting from the use of a large compensation capacitor. The examples described herein include charging and / or discharging the respective terminals (e.g., plates) of the compensation capacitor to improve the switching conditions of the converter. In the examples described herein, the respective terminals of the compensation capacitor are charged and / or discharged in response to satisfying various voltage thresholds.

[0027] Examples described herein include the use of isolated high-voltage and / or high-power gate drivers. In such examples, the isolated high-voltage and / or high-power gate driver includes an isolated high-voltage side and an isolated low-voltage side. Example isolation techniques described herein include capacitive isolation, optocoupler isolation, or any suitable isolation technique. Examples described herein include sensing an analog voltage value representing the temperature of a SiC MOSFET, IGBT, and / or any suitable power switch. Examples described herein include using the sensed voltage value representing the temperature of a SiC MOSFET, IGBT, and / or any suitable power switch to regulate the temperature of the SiC MOSFET, IGBT, and / or any suitable power switch.

[0028] In the examples described herein, at least one capacitor multiplier is used in the converter to generate the electrical effect of a large compensation capacitor (e.g., 200 picofarads), while a small compensation capacitor (e.g., 10 picofarads) is used. In such examples described herein, a physically small compensation capacitor (e.g., 10 picofarads) is implemented in the converter, coupled to at least one capacitor multiplier. Furthermore, in such examples described herein, the small compensation capacitor (e.g., 10 picofarads) coupled to at least one capacitor multiplier acts as and is considered as a large compensation capacitor (e.g., 200 picofarads).

[0029] In the examples described herein, at least one variable capacitive multiplier is used in conjunction with the aforementioned at least one capacitive multiplier. In such examples, the variable capacitive multiplier includes multiple current mirrors, each comprising multiple current mirror branches. In the examples described herein, the variable capacitive multiplier can adjust the number of active current mirror branches to adjust the capacitance of the compensation capacitor, and thus accordingly adjust the slew rate of the compensation node controlled by the capacitor.

[0030] Figure 3 This is a schematic diagram of an example gate driver system 300, which includes an example gate driver integrated circuit (IC) 302 that includes an example converter 304 to implement the example described herein. The gate driver IC 302 is a high-voltage (e.g., rated 800 volts (V)) isolated gate driver for supplying power to high-voltage and / or high-current loads. For example, the gate driver system 300 can be used to supply power to a traction inverter or any other type of electrical equipment included in an EV, HEV, etc. Alternatively, the gate driver system 300 can be used to supply power to any other electrical equipment.

[0031] exist Figure 3 In the example, gate driver IC 302 includes an example low-voltage stage 306 and an example high-voltage stage 308. Figure 3 In this example, an isolation barrier 310 is used to isolate the low voltage level 306 from the high voltage level 308. For example, it isolates electrical faults occurring on the example high voltage level 308 from affecting (e.g., damage, conduction current, etc.) the low voltage level 306. In the example described herein, the gate driver IC 302 is implemented as an integrated circuit.

[0032] In the examples described herein, the low-voltage stage 306 is implemented on a first die (e.g., a silicon die) separate from the high-voltage stage 308 within the gate driver IC 302. Similarly, in the examples described herein, the high-voltage stage 308 is implemented on a second die (e.g., a silicon die) separate from the low-voltage stage 306 within the gate driver IC 302. In other examples described herein, the low-voltage stage 306 and the high-voltage stage 308 may be implemented on a single die (e.g., a silicon die) within the gate driver IC 302. In other examples described herein, the low-voltage stage 306 may be implemented on multiple dies (e.g., silicon dies) within the gate driver IC 302. In other examples described herein, the high-voltage stage 308 may be implemented on multiple dies (e.g., silicon dies) within the gate driver IC 302. Alternatively, in other examples described herein, any component shown in the gate driver IC 302 and / or the gate driver IC 302 may be implemented on multiple integrated circuits and / or any multiple dies (e.g., silicon dies).

[0033] exist Figure 3 In the example, isolation barrier 310 is a capacitive isolation barrier. Isolation barrier 310 ensures that the electrical grounding between the low voltage level 306 and the high voltage level 308 is separate. In some examples described herein, isolation barrier 310 may be implemented as an inductive isolation barrier, an optocoupler isolation barrier, or any other suitable isolation barrier.

[0034] exist Figure 3 In the example, the example switch 312 is a silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET). Alternatively, switch 312 can be any other suitable silicon carbide transistor (e.g., silicon carbide IGBT). Switch 312 can be a MOSFET made of any other material (e.g., silicon, gallium arsenide, etc.). Alternatively, switch 312 can be any other power device such as an IGBT. Figure 3 In this example, the gate 314 of switch 312 is coupled to the example output stage IC 316 via one or more example IC pins (318, 320, 322). IC pin 318 is pin 7 (CLAMPI) of gate driver IC 302. IC pin 320 is pin 4 (OUTH) of gate driver IC 302. IC pin 322 is pin 6 (OUTL) of gate driver IC 302. Alternatively, gate 314 may be coupled to the output stage IC 316 via one or more intermediate connections, vias, nodes, etc.

[0035] Example output stage IC 316 includes any number of gate drivers to turn switch 312 on and / or off. For example, output stage IC 316 may include an example high-side gate driver for turning switch 312 on and an example low-side gate driver for turning switch 312 off.

[0036] exist Figure 3 In this example, the example temperature sensor 324 is coupled to the vicinity of switch 312 (e.g., 1 mm apart, 1 micrometer apart, etc.). In operation, temperature sensor 324 senses and / or otherwise generates a signal representing the temperature of switch 312 (e.g., voltages at example first sensing diode 328, second sensing diode 330, and third sensing diode 332). Furthermore, temperature sensor 324 is coupled to example IC pin 326 of gate driver IC 302. IC pin 326 is pin 1 (AIN) of gate driver IC 302. In other examples described herein, temperature sensor 324 can be implemented as any suitable temperature sensing device (e.g., thermocouple, thermistor, resistance temperature detector (RTD), etc.).

[0037] exist Figure 3In this example, converter 304 is coupled to IC pin 326 to obtain a signal representing the temperature of switch 312 (e.g., a voltage from a temperature sensor). In the example described herein, the signal obtained at IC pin 326 is an analog signal affected by induced noise and / or ringing generated by switch 312, coupled load, and / or any surrounding electrical equipment. Converter 304 obtains the analog signal corresponding to the temperature of switch 312 from IC pin 326 and converts it into a digital signal (e.g., a PWM signal) to be transmitted to example controller 346 via isolation barrier 310. The digital signal (e.g., the PWM signal) includes a duty cycle corresponding to the temperature of switch 312 (e.g., a 90% duty cycle corresponds to 200 degrees Fahrenheit). Furthermore, converter 304 is coupled to example IC pin 327, which is pin 5 (VDD) of gate driver IC 302.

[0038] In the example described herein, converter 304 receives an analog signal corresponding to the temperature of switch 312 from IC pin 326 and converts the analog signal corresponding to the temperature of switch 312 into a digital temperature signal. Converter 304 provides the digital temperature signal to pass through isolation barrier 310 for use by controller 346.

[0039] exist Figure 3 In the example, the example fault coding IC 334 obtains at least a digital signal (e.g., a PWM signal) representing the temperature of switch 312 from converter 304. In the example described herein, fault coding IC 334 generates a corresponding fault signal in response to obtaining the digital signal from converter 304. For example, if the temperature of switch 312 is too high (e.g., above a threshold temperature), the fault signal encoded by fault coding IC 334 may correspond to a fault in system 300, or if the temperature of switch 312 is within the threshold temperature (e.g., normal operation), the fault signal generated by fault coding IC 334 may correspond to the absence of a fault in system 300.

[0040] exist Figure 3 In the example described herein, the first example modulator (MOD) IC 336 modulates the fault signal generated by the fault coding IC 334. In this example, the first MOD IC 336 modulates the frequency of the fault signal generated by the fault coding IC 334 to a sufficiently high value (e.g., 500 MHz) to cross the isolation barrier 310. In this type of example, the first MOD IC 336 is coupled to the first example demodulator (DEMOD) IC 338 via the isolation barrier 310.

[0041] exist Figure 3In this example, the first DEMOD IC 338 demodulates the modulated fault signal described above. In this type of example, the first DEMOD IC 338 is coupled to the example fault decoding IC 340.

[0042] exist Figure 3 In this example, the fault decoding IC 340 decodes at least the corresponding fault signal previously encoded by the fault encoding IC 334. The output of the fault decoding IC 340 is coupled to the example PWM driver 342.

[0043] exist Figure 3 In the example, the PWM driver 342 is coupled to the controller 346 via example IC pin 344. In the example described herein, IC pin 344 is pin 16 (APWM) of the gate driver IC 302.

[0044] exist Figure 3 In the example, the gate driver system 300 includes a controller 346 to control and / or otherwise manage the switching operation of the switch 312 via the gate driver IC 302. Figure 3 In this context, controller 346 is an IC. Alternatively, controller 346 can be implemented using hardware logic, machine-readable instructions, hardware-implemented state machines, and / or combinations thereof.

[0045] exist Figure 3 In this example, controller 346 generates an example signal (e.g., a current signal), which is converted into an example input voltage. The input voltage includes a first example input voltage (IN+) obtained by gate driver IC 302 at example IC pin 348. IC pin 348 is pin 10 of gate driver IC 302. The input voltage also includes a second example input voltage (IN-) obtained by gate driver IC 302 at example IC pin 350. IC pin 350 is pin 11 of gate driver IC 302. The input voltage is converted into a PWM signal via example PWM input IC 352.

[0046] exist Figure 3In the example, PWM input IC 352 generates a PWM signal and transmits it to a second example modulator (MOD) IC 354, which modulates the PWM signal. The second MOD IC 354 transmits the modulated PWM signal to a second example demodulator (DEMOD) IC 356, which demodulates the PWM signal. The second MOD IC 354 transmits the modulated PWM signal to the second DEMOD IC 356 through an example isolation barrier 310. The second DEMOD IC 356 transmits the demodulated PWM signal to an output stage IC 316. The output stage IC 316 processes the demodulated PWM signal from the second DEMOD IC 356 to facilitate operation at switch 312. For example, controller 346 may generate one or more control signals in response to the output of converter 304 to facilitate operation of switch 312. In the example described herein, the switching conditions (e.g., switching speed, total overshoot) of one or more control signals generated by controller 346 in response to the output of converter 304 are improved (e.g., undesirable switching speed or turn-on time due to frequency compensation is reduced).

[0047] By switching on switch 312, gate driver IC 302 provides power to example load 358. For example, load 358 can be an electric motor, traction inverter, or any other type of electrical equipment included in EVs, HEVs, etc. Alternatively, load 358 can be a battery, a power converter, such as a half-bridge power converter (e.g., boost converter, buck converter, buck-boost converter, etc.). Figure 3 In the example, voltage source 360 ​​is coupled to switch 312. Voltage source 360 ​​is a battery. Alternatively, voltage source 360 ​​can be a capacitor, a direct current (DC) voltage source, etc. Figure 3 In this circuit, switch 312 provides power to load 358. For example, switch 312 can provide load 358 with a voltage in the range of 400-1000V, a current in the range of 100-1000 Amperes (A), and / or combinations thereof. Figure 3 In this example, one or more intermediate switches 362 may be coupled between the load and the example ground rail 364. One or more intermediate switches 362 may be controlled by controller 346 or any suitable external or internal controller.

[0048] Figure 4 yes Figure 3 A schematic diagram 400 of an example converter 304 is provided, which includes various components to improve startup time and / or reduce overshoot caused by frequency compensation. The example converter 304 is coupled to IC pin 326 for connection to… Figure 3The analog signal corresponding to the temperature of switch 312. Furthermore, converter 304 is coupled to... Figure 3 The fault encoder IC 334. Figure 4 In the example, converter 304 includes an example first low-dropout regulator 402, an example second low-dropout regulator 404, an example starter 406, an example error amplifier 408, an example compensator 410, an example first threshold comparator 412, an example second threshold comparator 414, an example ramp generator 416, an example ramp comparator 418, an example level shifter 420, and an example filter 422.

[0049] exist Figure 4 In the example, the voltage at IC pin 327 is Figure 3 and Figure 4 The converter 304 is utilized. In such an example, the voltage at IC pin 327 is applied in converter 304 to the first low-dropout regulator 402 and the second low-dropout regulator 404 to power various electrical components in converter 304.

[0050] exist Figure 4 In the example, the first low-dropout regulator 402 ensures that the voltage supplied to the corresponding circuitry (e.g., error amplifier 408 and ramp comparator 418) is constant. For example, the input to the first low-dropout regulator 402 (e.g., the voltage at IC pin 327) could be 5.5 volts, and the output of the first low-dropout regulator 402 (e.g., the voltage supplying error amplifier 408 and ramp comparator 418) could be 5.1 volts. In other examples described herein, the output of the first low-dropout regulator 402 (e.g., the voltage supplying error amplifier 408 and ramp comparator 418) could be any numerical voltage.

[0051] exist Figure 4 In the example, the second low-dropout regulator 404 ensures that the voltage supplied to the corresponding circuit (e.g., level shifter 420) is constant. For example, the input of the second low-dropout regulator 404 (e.g., the voltage at IC pin 327) may be 5.5 volts, and the output of the second low-dropout regulator 404 (e.g., the voltage supplying the level shifter 420) may be 3.3 volts. In other examples described herein, the output of the second low-dropout regulator 404 (e.g., the voltage supplying the level shifter 420) may be any numerical voltage.

[0052] exist Figure 4In this example, the starter 406 monitors an example first output (line 423) of the first low-dropout regulator 402, an example second output (line 425) of the second low-dropout regulator 404, and an example clock input (line 427). Furthermore, the starter 406 is coupled to an error amplifier 408. In the example described herein, the starter 406 generates a trigger signal (line 429) in response to observing that the first output (line 423) of the first low-dropout regulator 402 has reached a steady state (e.g., a stable 5.1 volts), the second output (line 425) of the second low-dropout regulator 404 has reached a steady state (e.g., a stable 3.3 volts), and the clock input (line 427) has reached a steady state (e.g., a stable 600 kHz). In such examples, a determination of whether the first output (line 423) of the first low-dropout regulator 402, the second output (line 425) of the second low-dropout regulator 404, and / or the clock input (line 427) has reached a steady state occurs when the corresponding signals no longer experience transients.

[0053] exist Figure 4 In the example, voltage divider 407 obtains the same voltage as... Figure 3 The analog signal corresponding to the temperature of switch 312. Voltage divider 407 uses a series of resistive elements (e.g., resistors) to generate a signal representing... Figure 3 The temperature of switch 312 is a proportional analog signal. Figure 4 In this circuit, the voltage divider includes a first series resistor 409 and a second series resistor 411. The output of the voltage divider is an analog sensing signal (line 415) implemented at node 413.

[0054] exist Figure 4 In this example, error amplifier 408 compares the sensed signal (line 415) with an example feedback signal (line 417). In such an example, error amplifier 408 generates an error output (line 419) that includes a duty cycle that depends on the voltage difference between the sensed signal (line 415) and the feedback signal (line 417).

[0055] exist Figure 4 In the example, to filter out unwanted induced noise and / or ringing (e.g., induced noise and / or ringing affecting converter 304), a compensation capacitor is included at and / or across the compensation node in error amplifier 408. In the example described herein, the compensation capacitor is included in example compensator 410. The compensation capacitor is in Figure 5 Further detailed discussion is needed.

[0056] exist Figure 4In this circuit, compensator 410 is included in error amplifier 408 and coupled to starter 406, first threshold comparator 412, second threshold comparator 414, voltage divider 407, and filter 422. Compensator 410 provides frequency compensation for error amplifier 408 and, in addition, provides... Figure 3 and Figure 4 The converter 304 and Figure 3 The gate driver IC 302 provides frequency compensation. In the example described herein, a compensation capacitor is used to perform frequency compensation to set... Figure 3 The dominant pole of converter 304. Compensator 410 charges and discharges the respective terminals of the compensation capacitor in response to various trigger values ​​(e.g., various operating thresholds satisfied) obtained at least from starter 406, first threshold comparator 412, and / or second threshold comparator 414. Figure 5 The paper further discusses various trigger values ​​(e.g., various operation thresholds) and their corresponding actions.

[0057] exist Figure 4 In the example, an example first threshold comparator 412 is coupled to a filter 422, an error amplifier 408, and a compensator 410. The first threshold comparator 412 compares a feedback signal (line 417) with a sensed signal (line 415) from a voltage divider 407. In the example described herein, if the feedback signal (line 417) comprises at least 50% of the magnitude of the sensed signal (line 415) from the voltage divider 407, the first threshold comparator 412 outputs an example first trigger to comparator 410. In other examples described herein, if the feedback signal (line 417) differs from the sensed signal (line 415) from the voltage divider 407 by any predetermined amount (e.g., 20%, 70%, etc.), the first threshold comparator 412 may output a first trigger to compensator 410.

[0058] exist Figure 4 In the example, the example second threshold comparator 414 is coupled to filter 422, error amplifier 408, and compensator 410. The second threshold comparator 414 compares a feedback signal (line 417) with a sensed signal (line 415) from voltage divider 407. In the example described herein, if the feedback signal (line 417) includes at least 90% of the magnitude of the sensed signal (line 415) from voltage divider 407, the second threshold comparator 414 outputs an example second trigger to compensator 410. In other examples described herein, if the feedback signal (line 417) differs from the sensed signal (line 415) from voltage divider 407 by any predetermined amount (e.g., 65%, 95%, etc.), the second threshold comparator 414 may output a second trigger to compensator 410.

[0059] exist Figure 4 In this example, a ramp generator 416 is coupled to a ramp comparator 418. The ramp generator 416 includes an example oscillator 424 and an example ramp source 426. The ramp generator 416 generates a ramp signal (line 421) for use by the ramp comparator 418. In the example described herein, the oscillator 424 controls the frequency of the ramp source 426. The ramp source 426 outputs the ramp signal (line 421) at a desired frequency. In the example described herein, the desired frequency of the ramp signal (line 421) is 600 kHz; however, in other examples described herein, the desired frequency can be any suitable frequency for operation (e.g., 300 kHz, 450 kHz, etc.).

[0060] exist Figure 4 In the example, example ramp comparator 418 is coupled to the output of error amplifier 408 (e.g., error output (line 419)), ramp generator 416 (e.g., ramp signal (line 421)), and example level shifter 420. Ramp comparator 418 compares the error output (line 419) with the generated ramp signal (line 421). Depending on where the error output (line 419) is aligned with the ramp signal (line 421), ramp comparator 418 will generate a varying output. In the example described herein, the duty cycle of the output of ramp comparator 418 varies corresponding to the alignment of the error output (line 419) and the ramp signal (line 421).

[0061] exist Figure 4 In the example, the example level shifter 420 is coupled to the example ramp comparator 418 and the example filter 422. Figure 4 In this example, level shifter 420 shifts the incoming signal from ramp comparator 418 to a higher voltage for the output signal of level shifter 420. In other examples described herein, level shifter 420 may shift the voltage of the incoming signal from ramp comparator 418 to a lower voltage for the output signal of level shifter 420.

[0062] exist Figure 4 In the example, example filter 422 is coupled to level shifter 420 and error amplifier 408. Figure 4 In this filter, filter 422 includes filter resistor 430 and filter capacitor 432. Figure 4 The topology shown includes filter 422, which acts as a low-pass filter. In other examples described herein, filter 422 may be implemented as a high-pass filter, band-pass filter, band-stop filter, or any suitable filter. The output of filter 422 is a feedback signal (line 417), which is coupled to error amplifier 408.

[0063] exist Figure 4In the example, the output of level shifter 420 represents Figure 3 The DC signal of the temperature of the coupling switch 312. In this example, the duty cycle of the output of the level shifter 420 is adjusted by the ramp comparator 418 in response to the variation of the example error output (line 419) from the generated ramp signal (line 421).

[0064] Figure 5 It is used to improve Figure 3 Gate driver IC 302 and Figure 3 and Figure 4 The switching characteristics of converter 304 Figure 4 A schematic diagram 500 of a compensator 410 is provided. The compensator 410 includes: an example compensation capacitor 502 including an example first terminal 504 and an example second terminal 506; an example first switch 508; an example second switch 510; an example variable multiplier 512; an example multiplier 514; an example buffer 516; and an example voltage divider 518 including an example first resistor 520 and an example second resistor 522. The compensator capacitor 502 is coupled to IC pin 327 (e.g., indirectly via...). Figure 4 First low differential pressure regulator 402), starter 406, Figure 4 Voltage divider 407, Figure 4 First threshold comparator 412 Figure 4 The second threshold comparator 414, and Figure 4 The ramp comparator 418.

[0065] In the example described herein, first switch 508 and second switch 510 are coupled to example first output connector 524 to obtain an indication of whether conduction is occurring. In the example described herein, this indication is generated by coupled starter 406 in response to determining that the corresponding voltage and clock signals (e.g., the first output (line 423) of the first low-dropout regulator, the second output (line 425) of the second low-dropout regulator, and the ramp signal (line 421)) are in a stable state. Furthermore, second switch 510 and variable multiplier 512 are coupled to example second output connector 526 to obtain a voltage potential at IC pin 327.

[0066] exist Figure 5 In the example shown, voltage divider 518 is coupled to example third output connector 528 to obtain from Figure 4 voltage divider 407 Figure 4The voltage potential of the sensed signal (line 415). Variable multiplier 512 is coupled to example fourth output connector 530 and example fifth output connector 532 to obtain a first trigger from first threshold comparator 412 and a second trigger from second threshold comparator 414, respectively. Second terminal 506 is coupled to example sixth output connector 534 to provide the adjusted output of compensator 410 (e.g., Figure 4 Error output 419). The examples described herein include modifying the operation of variable multiplier 512 to indirectly improve Figure 3 and Figure 4 The switching conditions of converter 304 (e.g., improving the start-up time, setup time, and total overshoot of compensator 410, which are dominated by the start-up time, setup time, and total overshoot of compensator 410) Figure 3 and Figure 4 (The startup time, setup time, and total overshoot of converter 304).

[0067] exist Figure 5 In the example, the compensation capacitor 502 includes a first terminal 504 and a second terminal 506. The first terminal 504 is coupled to a first switch 508. Furthermore, the second terminal 506 is coupled to a second switch 510.

[0068] Compared to the capacitance seen in the circuit (e.g., 400 picofarads), the example compensation capacitor 502 is physically a small capacitor (e.g., 10 picofarads). The compensation capacitor 502 is coupled to variable multipliers 512 and 514. In the example described herein, variable multipliers 512 and 514 are used to ensure that space in the error amplifier 408 is saved by utilizing the physically small compensation capacitor 502 (e.g., 10 picofarads) and to include the electrical characteristics (e.g., capacitance, conductivity, etc.) of a large capacitor (e.g., 400 picofarads). The operation of variable multipliers 512 and 514 will be explained below. Figure 6 The details are described further in the text.

[0069] exist Figure 5 In the example, the first switch 508 is shown as a two-terminal unipolar switch. In other examples described herein, the first switch 508 may be implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET), an isolated gate bipolar transistor (IGBT), or any controllable switching device.

[0070] exist Figure 5 In this embodiment, the second switch 510 is shown as a two-terminal unipolar switch. In other examples described herein, the second switch 510 may be implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET), an isolated gate bipolar transistor (IGBT), or any controllable switching device.

[0071] exist Figure 5In the example, variable multiplier 512 is coupled to a first terminal 504 and a second terminal 506 of compensation capacitor 502. Variable multiplier 512 includes an example current mirror 513. In the example described herein, current mirror 513 may include any number of current mirrors (e.g., current mirror branches (K), current mirror ratio, and therefore current mirror current gain). In the example described herein, in response to... Figure 4 First threshold comparator 412 and / or Figure 4 Various triggers of the second threshold comparator 414 adjust (e.g., turn on and / or off) the branches of the current mirror 513 via the variable multiplier 512. Additionally, the variable multiplier 512 is coupled to IC pin 327 (e.g., indirectly via…). Figure 4 The first low-dropout regulator 402 is coupled to a first threshold comparator 412, coupled to a second threshold comparator 414, and coupled to a starter 406. Examples described herein include obtaining an initial trigger from the starter 406 to instruct the variable multiplier 512 to adjust the number of current mirror branches (K) to a first ratio. Examples described herein include utilizing a predetermined number of current mirror branches (K), wherein the predetermined number of current mirror branches (K) can be turned on and / or off with respect to an initial trigger from the starter 406.

[0072] In the examples described herein, the initial trigger signal sent by the starter 406 instructs the variable multiplier 512 to adjust the capacitance multiplication to a first ratio. In some examples described herein, the first ratio occurs when the number of active current mirror branches (K) is 16. In other examples described herein, the first ratio of the active current mirror branches (K) can be any numerical ratio. In such examples, the initial trigger places the compensator 410 in a first state, namely, pre-charge mode.

[0073] In the example described herein, a first trigger sent by a first threshold comparator 412 instructs variable multiplier 512 to adjust the capacitance multiplication of variable multiplier 512 (e.g., adjust the active branch in current mirror 513) to a second ratio. The example described herein includes utilizing a predetermined number of current mirror branches (K), wherein the predetermined number of current mirror branches (K) can be turned on and / or off with respect to a first trigger from the first threshold comparator 412. For example, if the first threshold comparator 412 outputs a first trigger, variable multiplier 512 adjusts the predetermined number of current mirror branches (K) to a lower ratio (e.g., if (K) is 16, then the second ratio is adjusted to include 8 of (K)). In other examples described herein, variable multiplier 512 can be implemented using any other suitable method and / or device for variable capacitance multiplication (e.g., based on an autotransformer, based on an operational amplifier, etc.). In such examples, the first trigger places compensator 410 in a second state, i.e., a fast charging mode.

[0074] Similarly, if the second threshold comparator 414 outputs a second trigger, the variable multiplier 512 adjusts a predetermined number of current mirror branches (K) to a third ratio. In the example described herein, the third ratio is higher than the first ratio (e.g., if (K) is 16, the third ratio is adjusted to include (K) 24). In such an example, the second trigger puts the compensator 410 into a third state, namely slow charging mode.

[0075] In such examples, the strength of the variable multiplier 512 is modulated in response to various triggers sent by at least the first threshold comparator 412 and / or the second threshold comparator 414.

[0076] exist Figure 5 In one example, multiplier 514 is coupled to a first terminal 504 and a second terminal 506 of compensation capacitor 502. Additionally, multiplier 514 is coupled to IC pin 327 (e.g., indirectly via variable multiplier 512). Examples described herein include achieving the desired capacitance multiplication using a second predetermined number of current mirrors 515. In such examples, the second predetermined number of current mirrors 515 is constant, and therefore, the desired capacitance multiplication ratio of multiplier 514 is constant. In other examples described herein, multiplier 514 may be a variable multiplier (e.g., similar to variable multiplier 512). In other examples described herein, multiplier 514 may be implemented using any other suitable method and / or device for capacitance multiplication (e.g., based on an autotransformer, based on an operational amplifier, etc.).

[0077] exist Figure 5 In the example, example buffer 516 includes an output terminal coupled to a first switch 508 and an input terminal coupled to a voltage divider 518. Buffer 516 acts as a voltage follower to provide a voltage on the input (e.g., the voltage at node 521) to the output (e.g., the first switch 508). In the example described herein, buffer 516 may be used to transfer an input voltage (e.g., a voltage potential at node 521) from a first impedance to a second impedance. In such examples, the first impedance is greater than the second impedance.

[0078] exist Figure 5 In the example, the example voltage divider 518 is coupled to Figure 4 Voltage divider 407. In other examples described herein, voltage divider 518 and Figure 4 The voltage divider 407 can be implemented as a single voltage divider. Figure 5 In the voltage divider 518, a first resistor 520 is included and coupled in series with a second resistor 522. The first resistor 520 and the second resistor 522 share a common node, namely node 521. Figure 5 In the middle, node 521 includes nodes corresponding to... Figure 4The voltage potential output of the voltage divider 407 is proportional to the voltage potential. Figure 5 In this context, the first resistor 520 and the second resistor 522 can be any suitable resistance value, and in fact, can be any suitable resistive element (e.g., a load).

[0079] Figure 6 Is with Figure 5 A schematic diagram 600 of an example multiplier associated with variable multipliers 512 and 514 for adjusting the effective capacitance of a capacitor is shown. In the example described herein, the theory of capacitance multiplication is governed by at least the following two equations.

[0080] I eq =β*I C +I C Equation 1

[0081] C eq = (1+β)*C C Equation 2

[0082] In Equation 1, the variable (β) is related to... Figure 5 The current gain of the current mirror 513 used in conjunction with the variable multiplier 512 and / or multiplier 514, I c It is the current through capacitor 602, and I eq This is the equivalent current of the equivalent capacitor 606. The current gain (β) of the current mirror 513 multiplied by the current through capacitor 602 represents the effective multiplier current 604.

[0083] In Equation 2, the variable (β) is related to... Figure 5 The current gain of the current mirror 513 used in conjunction with the variable multiplier 512 and / or multiplier 514, variable C C It is the capacitance of capacitor 602 in farads, and C eq It is the effective equivalent capacitance of the equivalent capacitor 606.

[0084] exist Figure 6 In the example, using and Figure 5 The variable multiplier 512 and / or multiplier 514 are associated with the current gain (β) of the current mirror 513 used to achieve the capacitance multiplication factor (e.g., variable C). eq In the other examples described herein, any suitable method of capacitance multiplication can be used, and in fact, any suitable method of generating current gain (β) can be used (e.g., operational amplifier gain, etc.).

[0085] Figure 7 yes Figure 4 and Figure 5The illustration 700 shows the voltage and current of various compensation capacitors in the example compensator 410 as a function of time. Figure 7 middle, Figure 5 The voltage at the second terminal 506 of the compensation capacitor 502 is depicted as line 702. Figure 5 The voltage at the first terminal 504 of the compensation capacitor 502 is depicted as line 704. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 5 The current in the current mirror 513 is depicted as line 706. (Through...) Figure 5 The current of the variable multiplier 512 is depicted as line 708. Figure 3 The voltage output of converter 304 is depicted as line 710. In the example described herein, the voltage output (line 710) of converter 304 is responsive to the voltage (line 704) at the first terminal 504 of compensation capacitor 502 and / or the voltage (line 702) at the second terminal 506 of compensation capacitor 502.

[0086] exist Figure 7 In the example illustration, during the example first time interval 712 and the example second time interval 714, the compensator 410 is in a pre-charge mode (e.g., Figure 4 and Figure 5 The compensator 410 is waiting for a trigger from the initiator. In this type of illustration, Figure 5 The first terminal 504 can be charged to a first threshold voltage (e.g., the voltage at the first terminal 504 (line 704) is 4.3 volts), and Figure 5 The second terminal 506 is charged to a second threshold voltage (e.g., the voltage at the second terminal 506 (line 702) is 5.1 volts). In the example described herein, the first threshold voltage is less than the second threshold voltage.

[0087] exist Figure 7 In the example illustration, at the second time interval 714, Figure 4 The starter 406 Figure 4 and Figure 5 The compensator 410 sends a trigger, indicating the corresponding voltage (e.g., the voltage at the first terminal 504 (line 704) and the voltage at the second terminal 506 (line 706)) and a clock signal (e.g., a ramp signal). Figure 4 Line 421) is in a stable state condition. During the second time interval 714 and the example third time interval 716, Figure 4 and Figure 5 The compensator 410 is in fast charging mode. Thus, in Figure 5The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 is reduced to include a current mirror 513 ratio of 8 (e.g., the number of active current mirror branches (K) is reduced to 8). In response, the effective capacitance of the compensation capacitor 502 is adjusted proportionally, and therefore, the voltage (line 702) at the second terminal 506 is rapidly established (e.g., 20 microseconds). In other examples described herein, during the fast charging mode between the second time interval 714 and the third time interval 716, Figure 5 The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 can be reduced to include any value of the current mirror ratio below the normal operating ratio. For example, if the normal operating ratio is 16 (e.g., the number of active current mirrors (K) is 16), then during fast charging mode, the ratio can be reduced to any value less than 16.

[0088] exist Figure 7 In the example illustration, at the third time interval 716, Figure 4 The first threshold comparator 412 to Figure 4 and Figure 5 The compensator 410 sends a first trigger, indicating Figure 4 The feedback signal (line 417) is Figure 4 50% of the sensed signal (line 415). In other examples described herein, Figure 4 The first threshold comparator 412 can respond to determining Figure 4 The feedback signal (line 417) and Figure 4 The first trigger is sent when the sensed signal (line 415) differs from the signal by any numerical percentage (e.g., 40%, 65%, etc.). During the third time interval 716 and, for example, the fourth time interval 718, Figure 4 and Figure 5 The compensator 410 is in slow charging mode. Thus, in Figure 5 The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 is increased to include a current mirror 513 ratio of 24 (e.g., the number of active current mirror branches (K) is increased to 24). In response, the effective capacitance of the compensation capacitor 502 is adjusted proportionally, and therefore, the voltage (line 702) at the second terminal 506 is built up slowly (e.g., 30 microseconds). In other examples described herein, during the slow charging mode between the third time interval 716 and the fourth time interval 718, Figure 5The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 can be increased to include any value of the current mirror ratio higher than the normal operating ratio. For example, if the normal operating ratio is 16 (e.g., the number of active current mirror branches (K) is 16), the ratio can be increased to any value greater than 16 during slow charging mode.

[0089] exist Figure 7 In the example illustration, at the fourth time interval 718, Figure 4 The second threshold comparator 414 directs... Figure 4 and Figure 5 The compensator 410 sends a second trigger, indicating Figure 4 The feedback signal (line 417) is Figure 4 90% of the sensed signal (line 415). In other examples described herein, Figure 4 The second threshold comparator 414 can respond to determining Figure 4 The feedback signal (line 417) and Figure 4 A second trigger is sent when the sensed signal (line 415) differs from the signal by any numerical percentage (e.g., 95%, 85%, etc.). After the fourth time interval 718, Figure 4 and Figure 5 The compensator 410 returns to normal operating mode. Thus, in Figure 5 The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 includes the normal operating ratio of the current mirror (e.g., the number of active current mirror branches (K)). Figure 7 It is clearly shown that the startup time (e.g., setup time) of the output (line 710) of converter 304 is less than 60 microseconds.

[0090] Figure 8 yes Figure 4 and Figure 5 The diagram 800 shows the voltage and current variations over time for the various additional compensators in the compensator 410. Figure 8 In Figure 5 The voltage at the second terminal 506 of the compensation capacitor 502 is depicted as line 802. Figure 5 The voltage at the first terminal 504 of the compensation capacitor 502 is depicted as line 804. Figure 4 The voltage potential of the feedback signal (line 417) is depicted as line 806. Figure 4 The voltage potential of the sensed signal (line 415) is depicted as line 808. Figure 3The voltage output of converter 304 is depicted as line 810. In the example described herein, the voltage output (line 810) of converter 304 is responsive to the voltage (line 804) at the first terminal 504 of compensation capacitor 502 and / or the voltage (line 802) at the second terminal 506 of compensation capacitor 502.

[0091] exist Figure 8 In the example illustration, during the example first time interval 812 and the example second time interval 814, the compensator 410 is in a pre-charge mode (e.g., Figure 4 and Figure 5 The compensator 410 is waiting for a trigger from the initiator. In this type of illustration, Figure 5 The first terminal 504 is charged to a first threshold voltage (e.g., the voltage at the first terminal 504 (line 804) is 4.3 volts), and Figure 5 The second terminal 506 is charged to a second threshold voltage (e.g., the voltage at the second terminal 506 (line 802) is 5.1 volts). In the example described herein, the first threshold voltage is less than the second threshold voltage.

[0092] exist Figure 8 In the example illustration, at the second time interval 814, Figure 4 The starter 406 Figure 4 and Figure 5 The compensator 410 sends a trigger, indicating the corresponding voltage (e.g., the voltage at the first terminal 504 (line 804) and the voltage at the second terminal 506 (line 706)) and a clock signal (e.g., a ramp signal). Figure 4 Line 421) is in a stable state. During the second time interval 814 and the example third time interval 816, Figure 4 and Figure 5 The compensator 410 is in fast charging mode. Thus, Figure 5 The ratio of the variable multiplier 512 is reduced to include a current mirror 513 ratio of 8 (e.g., the number of active current mirror branches (K) is reduced to 8). In response, the effective capacitance of the compensation capacitor 502 is adjusted proportionally, and therefore, the voltage at the second terminal 506 (line 802) is rapidly established (e.g., 20 microseconds). In other examples described herein, during the fast charging mode between the second time interval 814 and the third time interval 816, Figure 5 The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 can be reduced to include any current mirror ratio below the normal operating ratio. For example, if the normal operating ratio is 16 (e.g., the number of active current mirror branches (K) is 16), then during fast charging mode, this ratio can be reduced to any value less than 16.

[0093] exist Figure 8 In the example illustration, at the third time interval 816, Figure 4 The first threshold comparator 412 to Figure 4 and Figure 5 The compensator 410 sends a first trigger, indicating Figure 4 The feedback signals (line 417) (line 806) are Figure 4 50% of the sensed signal (line 415) (line 808). In other examples described herein, Figure 4 The first threshold comparator 412 can respond to determining Figure 4 The feedback signal (line 417) and Figure 4 The first trigger is sent when the sensed signal (line 415) differs from the signal by any numerical percentage (e.g., 40%, 65%, etc.). During the third time interval 816 and, for example, the fourth time interval 818, Figure 4 and Figure 5 The compensator 410 is in slow charging mode. Thus, in Figure 5 The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 is increased to include a current mirror 513 ratio of 24 (e.g., the number of active current mirror branches (K) is increased to 24). In response, the effective capacitance of the compensation capacitor 502 is adjusted proportionally, and therefore, the voltage at the second terminal 506 (line 806) is slowly built up (e.g., 30 microseconds). In other examples described herein, during the slow charging mode between the third time interval 816 and the fourth time interval 818, Figure 5 The ratio of the variable multiplier 512 can be increased to include any number of active current mirror branches (K) higher than the normal operating ratio. For example, if the normal operating ratio is 16 (e.g., the number of active current mirror branches (K) is 16), the ratio can be increased to any value greater than 16 during slow charging mode.

[0094] exist Figure 8 In the example illustration, at the fourth time interval 818, Figure 4 The second threshold comparator 414 directs... Figure 4 and Figure 5 The compensator 410 sends a second trigger, indicating Figure 4 The feedback signals (line 417) (line 806) are Figure 4 90% of the sensed signal (line 415) (line 808). In other examples described herein, Figure 4 The second threshold comparator 414 can respond to determining Figure 4 The feedback signal (line 417) and Figure 4 A second trigger is sent when the sensed signal (line 415) differs from the signal by any numerical percentage (e.g., 95%, 85%, etc.). After the fourth time interval 818, Figure 4 and Figure 5 The compensator 410 returns to normal operating mode. Thus, in Figure 5 The number of active current mirror branches (K) in the current mirror 513 of the variable multiplier 512 includes the normal operating ratio of the current mirror (e.g., the number of active current mirror branches (K)). Figure 8 As clearly shown, the startup time (e.g., setup time) of the output (line 810) of converter 304 is reduced (e.g., less than 60 microseconds).

[0095] Figure 9 This is a schematic diagram 900 of an example compensator 901, which includes various components to improve... Figure 3 Gate driver IC 302 and Figure 3 and Figure 4 The switching characteristics of converter 304. Example compensator 901 includes: an example compensation capacitor 902 including an example first terminal 904 and an example second terminal 906; an example first switch 908; an example second switch 910; an example variable multiplier 912; an example multiplier 914; an example first buffer 916; an example second buffer 918; and an example voltage divider 920 including an example first resistor 922, an example second resistor 924, and an example third resistor 926. Compensator 901 is coupled to IC pin 327 (e.g., indirectly via...). Figure 4 First low differential pressure regulator 402), error amplifier 408, Figure 4 Voltage divider 407, Figure 4 First threshold comparator 412 Figure 4 The second threshold comparator 414, and Figure 4 The ramp comparator 418.

[0096] In the example described herein, the first switch 908 and the second switch 910 are coupled to an example first output connector 928 to obtain an indication of whether conduction is performed (e.g., from...). Figure 4 The initiator 406 indicates that the voltage and clock signals are in a stable state. Additionally, the variable multiplier 912 is coupled to the example second output connector 930 to obtain the voltage potential derived from IC pin 327. Figure 9 The voltage divider 920 is coupled to the example third output connector 932 to obtain from Figure 4 voltage divider 407 Figure 4The voltage potential of the sensed signal (line 415). Variable multiplier 912 is coupled to example fourth output connector 934 and example fifth output connector 936 to obtain a first trigger from first threshold comparator 412 and a second trigger from second threshold comparator 414, respectively. Second terminal 906 is coupled to example sixth output connector 938 to provide the adjusted output of compensator 410 (e.g., Figure 4 The error output is 419). The examples described herein include modifying the operation of the variable multiplier 912 to indirectly improve... Figure 3 and Figure 4 The start-up time, setup time, and total overshoot of converter 304 (e.g., improving the start-up time, setup time, and total overshoot of compensator 410, the start-up time, setup time, and total overshoot of compensator 410 dominate) Figure 3 and Figure 4 (The startup time, setup time, and total overshoot of converter 304).

[0097] exist Figure 9 In the example, the compensation capacitor 902 includes a first terminal 904 and a second terminal 906. The first terminal 904 is coupled to a first switch 908. Furthermore, the second terminal 906 is coupled to a second switch 910.

[0098] The example compensation capacitor 902 is physically small (e.g., 10 picofarads) relative to the actual capacitance seen in the circuit (e.g., 400 picofarads). The compensation capacitor 902 is coupled to variable multipliers 912 and 914. In the example described herein, variable multipliers 912 and 914 are used to ensure space is saved in the error amplifier 408 by utilizing the physically small compensation capacitor 902 (e.g., 10 picofarads) and to include the electrical characteristics (e.g., capacitance, conductivity, etc.) of a large capacitor (e.g., 200 picofarads).

[0099] exist Figure 9 In the example, the first switch 908 is shown as a two-terminal unipolar switch. In other examples described herein, the first switch 908 may be implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET), an isolated gate bipolar transistor (IGBT), or any controllable switching device.

[0100] exist Figure 5 In the example, the second switch 910 is shown as a two-terminal unipolar switch. In other examples described herein, the second switch 910 may be implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET), an isolated gate bipolar transistor (IGBT), or any controllable switching device.

[0101] exist Figure 9In the example, variable multiplier 912 is coupled to a first terminal 904 and a second terminal 906 of compensation capacitor 902. Variable multiplier 912 includes an example current mirror 913. In the example described herein, current mirror 913 may include any number of current mirrors (e.g., current mirror branches (K), current mirror ratio, and therefore current mirror current gain). In the example described herein, in response to... Figure 4 First threshold comparator 412 and / or Figure 4 Various triggers of the second threshold comparator 414 adjust (e.g., turn on and / or off) the branches of the current mirror 913 via the variable multiplier 912. Furthermore, the variable multiplier 912 is coupled to IC pin 327 (e.g., indirectly via…). Figure 4 The first low-dropout regulator 402 is coupled to a first threshold comparator 412, coupled to a second threshold comparator 414, and coupled to a starter 406. In the example described herein, a first trigger sent by the first threshold comparator 412 instructs the variable multiplier 912 to adjust the capacitance multiplication of the variable multiplier 912 (e.g., adjust the active branch in the current mirror 913). The example described herein includes utilizing a predetermined number of current mirror branches (K), wherein the predetermined number of current mirror branches (K) can be turned on and / or off with respect to a first trigger from the first threshold comparator 412. For example, if the first threshold comparator 412 outputs a first trigger, the variable multiplier 912 adjusts the predetermined number of current mirror branches (K) to a lower ratio (e.g., if (K) is 16, the ratio is adjusted to include 8 of (K)). In other examples described herein, the variable multiplier 912 can be implemented using any other suitable method and / or device for variable capacitance multiplication (e.g., based on an autotransformer, based on an operational amplifier, etc.).

[0102] Similarly, if the second threshold comparator 414 outputs a second trigger, the variable multiplier 912 adjusts a predetermined number of current mirror branches (K) to a higher ratio (e.g., if (K) is 16, the ratio is adjusted to include (K) of 24). In such examples, the strength of the variable multiplier 912 is modulated in response to various triggers sent by at least the first threshold comparator 412 and / or the second threshold comparator 414.

[0103] exist Figure 9In one example, multiplier 914 is coupled to a first terminal 904 and a second terminal 906 of compensation capacitor 902. Furthermore, multiplier 914 is coupled to IC pin 327 (e.g., indirectly via variable multiplier 912). The examples described herein include achieving the desired capacitance multiplication using a second predetermined number of current mirrors 915. In such examples, the second predetermined number of current mirrors 915 is constant, and therefore, the desired capacitance multiplication ratio is constant. In other examples described herein, multiplier 914 may be a variable multiplier (e.g., similar to variable multiplier 912). In other examples described herein, multiplier 914 may be implemented using any other suitable method and / or device for capacitance multiplication (e.g., based on an autotransformer, based on an operational amplifier, etc.).

[0104] exist Figure 9 In the example, the example first buffer 916 includes an output terminal coupled to a first switch 908 and an input terminal at node 921 coupled to a voltage divider 920. The first buffer 916 acts as a voltage follower to provide the same voltage on the input (e.g., the voltage potential at node 921) to the output (e.g., to the first switch 908). In the example described herein, the first buffer 916 can be used to transfer an input voltage (e.g., the voltage potential at node 921) from a first impedance level to a second impedance level (e.g., the first impedance is greater than the second impedance).

[0105] exist Figure 9 In the example, the example second buffer 918 includes an output terminal coupled to the second switch 910 and an input terminal coupled to the voltage divider 920 at node 923. The second buffer 918 acts as a voltage follower to provide the same voltage on the input (e.g., the voltage potential at node 923) to the output (e.g., to the second switch 910). In the example described herein, the second buffer 918 can be used to transfer the input voltage (e.g., the voltage potential at node 923) from a first impedance level to a second impedance level (e.g., the first impedance is greater than the second impedance).

[0106] exist Figure 9 In the example, the example voltage divider 920 is coupled to Figure 4 The voltage divider 407. In other examples described herein, voltage divider 920 and... Figure 4 The voltage divider 407 can be implemented as a single voltage divider. Figure 9 In this configuration, voltage divider 920 includes a first resistor 922 coupled in series with a second resistor 924. The first resistor 922 and the second resistor 924 are further coupled in series with a third resistor 926. The first resistor 922 and the second resistor 924 share a common node, node 921. The second resistor 924 and the third resistor 926 share a common node, node 923. Figure 9 In the middle, node 921 includes nodes corresponding to... Figure 4 The voltage potential output of the voltage divider 407 is proportional to the first voltage potential of the first resistor 922 and the second resistor 924. Furthermore, in Figure 9 In the middle, node 923 includes nodes corresponding to... Figure 4 The voltage potential output of voltage divider 407 is proportional to the first voltage potential at node 921. Figure 9 In the topology shown, the first voltage potential is greater than the second voltage potential, and therefore, the second terminal 906 is charged to a voltage potential lower than that of the first terminal 904 (e.g., the first terminal 904 is charged to the first voltage potential, and the second terminal 906 is charged to the second voltage potential). Figure 9 In this context, the first resistor 922, the second resistor 924, and / or the third resistor 926 can be any suitable resistance value, and in fact, can be any suitable resistive element (e.g., a load).

[0107] Figure 10 yes Figure 9 The illustration 1000 shows the voltage and current of the various compensation capacitors 902 in the example compensator 901 as a function of time. Figure 9 middle, Figure 9 The voltage at the second terminal 906 of the compensation capacitor 902 is depicted as line 1002. Figure 9 The voltage at the first terminal 904 of the compensation capacitor 902 is depicted as line 1004. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 9 The current in the current mirror 913 is depicted as line 1006. (Through...) Figure 9 The current of the variable multiplier 912 is depicted as line 1008. Figure 3 The voltage output of converter 304 is depicted as line 1010. In the example described herein, the voltage output (line 1010) of converter 304 is responsive to the voltage (line 1004) at the first terminal 904 of compensation capacitor 902 and / or the voltage (line 1002) at the second terminal 906 of compensation capacitor 902.

[0108] exist Figure 10 In the example illustration, during the example first time interval 1012 and the example second time interval 1014, the compensator 901 is in a pre-charge mode (e.g., Figure 9 The compensator 901 is waiting for a trigger from the initiator. In this type of illustration, Figure 9 The first terminal 904 can be charged to a first threshold voltage (e.g., the voltage at the first terminal 904 (line 1004) is 4.3 volts), and Figure 9The second terminal 906 is charged to a second threshold voltage (e.g., the voltage at the second terminal 906 (line 1002) is 3.3 volts). In the example described herein, the first threshold voltage is greater than the second threshold voltage.

[0109] exist Figure 10 In the example illustration, at the second time interval 1014, Figure 4 The starter 406 Figure 9 The compensator 901 sends a trigger, indicating the corresponding voltage (e.g., the voltage at the first terminal 904 (line 1004) and the voltage at the second terminal 906 (line 1006)) and a clock signal (e.g., a ramp signal). Figure 4 Line 421) is in a stable state condition. During the second time interval 1014 and the example third time interval 1016, Figure 9 The compensator 901 is in fast charging mode. Thus, Figure 9 The number of active current mirror branches (K) in the current mirror 913 of the variable multiplier 912 is reduced to include a current mirror 913 ratio of 8 (e.g., the number of active current mirror branches (K) is reduced to 8). In response, the effective capacitance of the compensation capacitor 902 is adjusted proportionally, and therefore, the voltage (line 1002) at the second terminal 906 is rapidly established (e.g., 11 microseconds). In other examples described herein, during the fast charging mode between the second time interval 1014 and the third time interval 1016, Figure 9 The number of active current mirror branches (K) in the current mirror 913 of the variable multiplier 912 is reduced to include any current mirror ratio below the normal operating ratio. For example, if the normal operating ratio is 16 (e.g., the number of active current mirrors (K) is 16), the ratio can be reduced to any value less than 16 during fast charging mode.

[0110] exist Figure 10 In the example illustration, at the third time interval 1016, Figure 4 The first threshold comparator 412 to Figure 9 The compensator 901 sends a first trigger, indicating Figure 4 The feedback signal (line 417) is Figure 4 50% of the sensed signal (line 415). In other examples described herein, Figure 4 The first threshold comparator 412 can respond to determining Figure 4 The feedback signal (line 417) and Figure 4 The first trigger is sent when the sensed signal (line 415) differs from the signal by any numerical percentage (e.g., 40%, 65%, etc.). During the third time interval 1016 and, for example, the fourth time interval 1018, Figure 9 The compensator 901 is in slow charging mode. Thus, Figure 9 The number of active current mirror branches (K) in the current mirror 913 of the variable multiplier 912 is increased to include a current mirror 913 ratio of 24 (e.g., the number of active current mirror branches (K) is increased to 24). In response, the effective capacitance of the compensation capacitor 902 is adjusted proportionally, and therefore, the voltage (line 1002) at the second terminal 906 is built up slowly (e.g., 30 microseconds) compared to the discharge rate of the compensation capacitor 902 during the fast charging mode. In other examples described herein, during the slow charging mode between the third time interval 1016 and the fourth time interval 1018, Figure 9 The number of active current mirror branches (K) in the current mirror 913 of the variable multiplier 912 can be increased to include any value of the current mirror ratio higher than the normal operating ratio. For example, if the normal operating ratio is 16 (e.g., the number of active current mirror branches (K) is 16), then during slow charging mode, the ratio can be increased to any value greater than 16.

[0111] exist Figure 10 In the example illustration, at the fourth time interval 1018, Figure 4 The second threshold comparator 414 directs... Figure 9 The compensator 901 sends a second trigger, indicating Figure 4 The feedback signal (line 417) is Figure 4 90% of the sensed signal (line 415). In other examples described herein, Figure 4 The second threshold comparator 414 can respond to determining Figure 4 The feedback signal (line 417) and Figure 4 A second trigger is sent when the sensed signal (line 415) differs from the signal by any numerical percentage (e.g., 95%, 85%, etc.). After the fourth time interval 1018, Figure 9 The compensator 901 returns to normal operating mode. Thus, Figure 9 The number of active current mirror branches (K) in the current mirror 913 of the variable multiplier 912 includes the normal operating ratio of the current mirror (e.g., the number of active current mirror branches (K)). Figure 10 It is clearly shown that the startup time (e.g., setup time) of the output (line 1010) of converter 304 is less than 40 microseconds.

[0112] Figure 11 This is state diagram 1100, representing the example operation mode. Figure 4 , Figure 5 or Figure 9 The compensator 410 or 901 can operate in these operating modes. When in example first state 1102, Figure 4 , Figure 5 and / or Figure 9The compensator 410 or 901 can be in an example pre-charge mode. In the example first state 1102, the respective terminals of the example compensation capacitors 502 and / or 902 (e.g., first terminal 504 or 904 and second terminal 506 or 906) are charged to a first voltage threshold and a second voltage threshold, respectively. Once the corresponding voltages and clock signals (e.g., example first output (line 423) of the first low-dropout regulator 402, example second output (line 425) of the second low-dropout regulator 404, and example clock input (line 427)) are in a stable state, the example first operating condition 1104 is satisfied.

[0113] In response, compensator 410 or 901 enters example second state 1106, which may be example fast charging mode. In example second state 1106, compensator 410 or 901, or more specifically, variable multiplier 512 or 912, adjusts the number of active current mirror branches in example current mirror 513 or 913 to a first ratio (e.g., 1:8). In other examples described herein, the first ratio may be any numerical ratio lower than the normal operating mode ratio. Example second operating condition 1108 is satisfied once the feedback signal (line 417) is a first percentage (e.g., 50%) of the sensed signal (line 415).

[0114] In response, compensator 410 or 901 enters example third state 1110, which may be example slow charging mode. In example third state 1110, compensator 410 or 901, or more specifically, variable multiplier 512 or 912, adjusts the number of active current mirror branches in example current mirror 513 or 913 to a second ratio (e.g., 1:24). In other examples described herein, the second ratio may be any numerical ratio higher than the normal operating mode ratio. Example third operating condition 1112 is satisfied once the feedback signal (line 417) is a second percentage (e.g., 95%) of the sensed signal (line 415).

[0115] In response, compensator 410 or 901 enters example fourth state 1114, which can be example normal operating mode. In example fourth state 1114, compensator 410 or 901, or more specifically, variable multiplier 512 or 912, adjusts the number of active current mirror branches in example current mirror 513 or 913 to a third ratio (e.g., 1:16). In other examples described herein, the third ratio can be any numerical ratio that serves as the normal operating mode ratio. If compensation capacitor 502 or 902 is fully discharged, example fourth operating condition 1116 is satisfied. In response, compensator 410 or 901 enters example first state 1102.

[0116] Although Figure 4 , Figure 5 and Figure 9 The implementation is shown in the figure. Figure 4 , Figure 5 and Figure 9 The example method of compensators 410 and 901, but Figure 4 , Figure 5 and Figure 9 One or more of the elements, processes, and / or devices shown may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, example starter 406, example first threshold comparator 412, example second threshold comparator 414, example variable multiplier 512, example current mirror 513, example variable multiplier 912, example current mirror 913, and / or more generally, Figure 4 , Figure 5 or Figure 9 The example compensators 410 and 901 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the example initiator 406, the example first threshold comparator 412, the example second threshold comparator 414, the example variable multiplier 512, the example current mirror 513, the example variable multiplier 912, the example current mirror 913, and / or more generally, any of the example compensators 410 and 901 can be implemented by one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more programmable logic devices (PLDs), and / or one or more field-programmable logic devices (FPLDs). When reading any of the device or system claims of this patent to cover purely software and / or firmware implementations, at least one of the example initiator 406, example first threshold comparator 412, example second threshold comparator 414, example variable multiplier 512, example current mirror 513, example variable multiplier 912, and example current mirror 913 is hereby explicitly defined as including non-transitory computer-readable storage devices or disks containing software and / or firmware, such as non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), etc., and / or any other type of random access memory (RAM) device), etc. Furthermore, Figure 4 , Figure 5 or Figure 9 Example compensators 410, 901 may include additions to or replacements Figure 4 , Figure 5 or Figure 9One or more of the elements, processes, and / or devices shown may be included, and / or may include any or all of more than one of the elements, processes, and devices shown. As used herein, the phrase “communication,” including its variations, covers direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at regular intervals, planned intervals, non-periodic intervals, and / or one-off events.

[0117] exist Figure 12 The diagram shows the representation used for implementation. Figure 3 Controller 346 and / or Figure 4 , Figure 5 or Figure 9 The flowcharts illustrate example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof for the compensators 410 and 901. Machine-readable instructions can be an executable program or part of an executable program that is executed by one or more computer processors, one or more microcontrollers, etc. For example, machine-readable instructions can be executed by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. For example, one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers can be one or more semiconductor-based (e.g., silicon-based) devices. The program can be embodied in software associated with one or more computer processors, one or more microcontrollers, etc., stored on a non-transitory computer-readable storage medium such as non-volatile memory, volatile memory, etc., but the entire program and / or parts thereof can alternatively be executed by devices other than one or more computer processors, one or more microcontrollers, etc., and / or embodied in firmware or dedicated hardware. Furthermore, although references... Figure 12 The flowcharts shown depict example programs, but many other methods can be used to implement controller 346 and / or example compensators 410, 901. For example, the execution order of the blocks can be changed, and / or some of the blocks described can be modified, eliminated, or combined. Additionally or alternatively, any or all blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers, logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0118] In some of the examples described herein, a hardware processor (e.g., controller 346) may be used to perform the execution. Figure 12 Instructions to achieve Figure 3The controller 346. The hardware processor can be, for example, a server, a vehicle's electronic control unit (ECU), a personal computer, a workstation, or any other type of computing device. The hardware processor can be a semiconductor-based (e.g., silicon-based) device. For example, the hardware processor can obtain... Figure 3 The switch 312 is associated with measured values ​​(e.g., current measurements, voltage measurements, etc.), and / or generates values ​​that will be determined by... Figure 3 The control signal is obtained from the gate driver IC 302. In such an example, the hardware processor can generate the control signal obtained from the output stage IC 316 of the gate driver IC 302 to turn one or more switches on or off to provide power or from the gate driver IC 302. Figure 3 The load 358 removes power. For example, the hardware processor 3 may initiate and / or otherwise cause the output stage IC 316 to disconnect switch 312 in response to an indication of the temperature of switch 312.

[0119] As mentioned above, Figure 12 The example process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on non-transitory computer and / or machine-readable media (such as hard disk drives, flash memory, read-only memory, compact disks, digital multifunction disks, caches, random access memory, and / or any other storage device or disk that can store information for any duration (e.g., extended time periods, permanent, transient instances, temporary buffers, and / or caches of information)). As used herein, the term "non-transitory computer-readable media" is explicitly defined to include any type of computer-readable storage device and / or disk, excluding propagated signals and transmission media.

[0120] As used herein, when the phrase “at least” is used as a transitional term, such as in the preamble of a claim, it is open-ended, just as the terms “comprising” and “including” are open-ended. When used in the form of A, B, and / or C, the term “and / or” refers to any combination or subset of A, B, and C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; or (g) A, B, and C. As used herein in the context of describing structures, components, articles, objects, and / or things, the phrase “at least one of A and B” is intended to indicate an implementation including any of the following: (a) at least one A; (b) at least one B; or (c) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, articles, objects, and / or things, the phrase “at least one of A or B” is intended to indicate an implementation including any of the following: (a) at least one A; (b) at least one B; or (c) at least one A and at least one B. As used herein in describing the implementation or execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to indicate an implementation including any of the following: (a) at least one A; (b) at least one B; or (c) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A or B" is intended to indicate an implementation including any of the following: (a) at least one A; (b) at least one B; or (c) at least one A and at least one B.

[0121] Figure 12 This is flowchart 1200, representing machine-readable instructions that can be executed to implement controller 346. Figure 4 and Figure 5 The compensator 410 and / or Figure 9 The compensator 901, to adjust Figure 5 Example compensation capacitor 502 or Figure 9 The charge of the compensation capacitor 902 is used to improve Figure 3 Example switching conditions for gate driver IC 302. In Figure 12 In the example shown, the starter 406 triggers a transmission to the example first switch (e.g., example first switch 508 or example first switch 908) to operate (e.g., close), thereby charging the example first terminal (e.g., example first terminal 504 or example first terminal 904) to a first voltage potential (box 1210). In the example described herein, the first voltage potential is controlled by a proportional voltage generated by the example voltage divider (e.g., the voltage generated by example voltage divider 518 at node 521 or the voltage generated by example voltage divider 920 at node 921).

[0122] Furthermore, the starter 406 will trigger the transmission to the example second switch (e.g., example second switch 510 or example second switch 910) to operate (e.g., close), and thereby charge the example second terminal (e.g., example second terminal 506 or example second terminal 906) to a second voltage potential (box 1220). In the example described herein, the second voltage potential is controlled by the voltage potential at the output connector 526 or by a proportional voltage generated by the example voltage divider (e.g., the voltage generated by example voltage divider 920 at node 923).

[0123] The starter 406 determines whether the corresponding voltage and clock signals (e.g., an example first output (line 423) of the first low-dropout regulator 402, an example second output (line 425) of the second low-dropout regulator 404, and an example clock input (line 427)) are in a stable state (box 1230). If either of the aforementioned voltage and clock signals is not in a stable state, control returns to box 1230.

[0124] If the aforementioned voltage and clock signals are stable, the starter 406 transmits a signal to an example variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) to adjust the multiplier ratio to a first ratio (box 1240). The variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) determines whether the feedback signal (line 417) is a first percentage (e.g., 50%) of the sensed signal (line 415) (e.g., determining whether the example first threshold comparator 412 sent an example first trigger) (box 1250). If the variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) does not determine that the feedback signal (line 417) is a first percentage (e.g., 50%) of the sensed signal (line 415), control returns to box 1250. If the variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) does determine that the feedback signal (line 417) is a first percentage (e.g., 50%) of the sensed signal (line 415), then the variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) adjusts the multiplier ratio to a second ratio (box 1260). In the example described herein, the first voltage threshold determined during the instructions shown in box 1250 can vary.

[0125] A variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) determines whether the feedback signal (line 417) is a second percentage (e.g., 95%) of the sensed signal (line 415) (e.g., determining whether example second threshold comparator 414 sent example second trigger) (box 1270). If the variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) does not determine that the feedback signal (line 417) is a second percentage (e.g., 95%) of the sensed signal (line 415), control returns to box 1270. If the variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) does determine that the feedback signal (line 417) is a second percentage (e.g., 95%) of the sensed signal (line 415), the variable multiplier (e.g., variable multiplier 512 or variable multiplier 912) adjusts the multiplier ratio to a third ratio (box 1280). In the example described herein, the second voltage threshold determined during the instructions shown in box 1270 can vary.

[0126] In addition, the compensator (e.g., compensator 410 or compensator 901) determines whether to continue operation (box 1290). Examples of compensator (e.g., compensator 410 or compensator 901) ceasing operation include power loss, damaged equipment, etc. Alternatively, if the compensator (e.g., compensator 410 or compensator 901) determines to continue operation, control returns to box 1210.

[0127] Based on the foregoing, it will be understood that example methods, apparatuses, and articles of manufacture for improving switching conditions in closed-loop systems have been described. The methods, apparatuses, and articles of manufacture improve the efficiency of using computing devices by charging and discharging the terminals of a compensation capacitor in response to satisfying various voltage thresholds. The methods, apparatuses, and articles of manufacture control the slew rate of the compensation capacitor to improve the switching characteristics of an example isolated high-power and / or high-current gate driver IC. The methods, apparatuses, and articles of manufacture accordingly relate to one or more improvements in computer functionality.

[0128] Modifications to the examples described are possible within the scope of the claims, and other examples are also possible.

Claims

1. A compensator device, comprising: A compensation capacitor having a first terminal and a second terminal; First switch; A second switch, which is coupled to the second terminal; A first variable multiplier is coupled between the first terminal and the second terminal; A second multiplier is coupled between the first terminal and the second terminal; as well as A buffer having an input terminal and an output terminal, wherein the first switch is coupled between the output terminal and the first terminal.

2. The device according to claim 1 further includes a voltage divider coupled to the input terminal.

3. The device according to claim 1, wherein the input terminal is a first input terminal, the output terminal is a first output terminal, and the device further comprises: The second buffer has a second input terminal and a second output terminal, and the second switch is coupled between the second output terminal and the second terminal of the compensation capacitor; as well as A voltage divider having a first output and a second output, the first output being coupled to a first input terminal and the second output being coupled to a second input terminal.

4. The device of claim 1, wherein the first variable multiplier is adapted to be coupled to at least one trigger, and the first variable multiplier is configured to adjust the multiplication ratio of the first variable multiplier in response to the trigger.

5. The device of claim 1, wherein the first terminal is configured to be charged to a first threshold, and the second terminal is configured to be charged to a second threshold.

6. The device of claim 5, wherein the second terminal is configured to discharge to the first threshold.

7. The device of claim 1, wherein the first variable multiplier includes a current mirror configured to adjust the multiplication ratio of the first variable multiplier by generating a current gain.

8. A gate driver system comprising: A first capacitor has a first terminal and a second terminal; A low-voltage stage, which is coupled to the first terminal; A high-voltage stage coupled to the second terminal, the high-voltage stage including a converter, the converter including a compensation capacitor, the converter being configured to convert an analog signal to a digital signal, and the converter being configured to reduce the setup time of converting the analog signal to the digital signal by: - Charge the compensation capacitor; - In response to the compensation capacitor reaching a first voltage threshold, the multiplier ratio of the converter is adjusted to a first ratio; as well as - In response to the compensation capacitor reaching a second voltage threshold, the multiplier ratio is adjusted to a second ratio; as well as The high voltage level is configured to transmit the digital signal to the low voltage level via the first capacitor.

9. The system of claim 8 further includes a temperature sensor coupled to the high voltage level, the temperature sensor being configured to provide the analog signal.

10. The system of claim 8, wherein the first ratio corresponds to a first slew rate of the compensation capacitor, and the second ratio corresponds to a second slew rate of the compensation capacitor.

11. The system of claim 8, wherein the first capacitor is configured to capacitively isolate the low voltage level from the high voltage level.

12. The system of claim 8, wherein the high voltage level is coupled to a silicon carbide transistor.

13. The system of claim 12, wherein the low voltage level is coupled to a controller, and the controller is configured to adjust the switching speed of the silicon carbide transistor in response to the digital signal.

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