Thin film transistor and method for manufacturing the same

Abstract

The thin film transistor (101) has a gate electrode (2); a semiconductor layer (4) disposed over the gate electrode with a gate insulating layer (3) therebetween; a source electrode (8s) disposed over a part of the semiconductor layer (4) with a first contact layer (Cs) therebetween; and a drain electrode (8d) disposed over another part with a second contact layer (Cd) therebetween. The first and second contact layers have a stacked structure including a first amorphous silicon layer and N (N is an integer of 1 or more) double-layer structures S(n) (n is an integer of 1 or more and N or less). The first amorphous silicon layer is in direct contact with the source electrode or the drain electrode. The N double-layer structures S(n) are each composed of a second amorphous silicon layer 72(n) and a third amorphous silicon layer 73(n) in direct contact with the upper surface of the second amorphous silicon layer 72(n). The n-type impurity concentrations C2(n), C3(n) in the second amorphous silicon layer and the third amorphous silicon layer of each double-layer structure S(n) and the n-type impurity concentration Cl in the first amorphous silicon layer satisfy the relationship C2(n) < C3(n) < C1 for any n.

Description

Technical Field

[0001] The present invention relates to a thin film transistor and a method for manufacturing the same. Background Art

[0002] Thin Film Transistor (hereinafter referred to as "TFT") is used as a switching element in an active matrix substrate of a display device such as a liquid crystal display device, an organic EL display device, etc. In this specification, such a TFT is referred to as a "pixel TFT". In the past, as pixel TFTs, amorphous silicon TFTs with an amorphous silicon film (hereinafter referred to as "a-Si film") as an active layer and polycrystalline silicon TFTs with a polycrystalline silicon film (hereinafter referred to as "poly-Si film") as an active layer were widely used. Generally, since the field effect mobility of the poly-Si film is higher than that of the a-Si film, the polycrystalline silicon TFT has a higher current driving force (i.e., a large on-current) than the amorphous silicon TFT.

[0003] A TFT in which a gate electrode is arranged on the substrate side of the active layer is called a "bottom gate TFT", and a TFT in which a gate electrode is arranged above the active layer (on the opposite side of the substrate) is called a "top gate TFT". If a bottom gate TFT is formed as a pixel TFT, it may be more cost-effective than forming a top gate TFT. Polycrystalline silicon TFTs are generally top gate, but bottom gate polycrystalline silicon TFTs have also been proposed.

[0004] As bottom-gate TFTs, channel-etched TFTs (hereinafter referred to as "CE-type TFTs") and etching stopper TFTs (hereinafter referred to as "ES-type TFTs") are known. In CE-type TFTs, a conductive film is directly formed on an active layer, and the conductive film is patterned to obtain a source and a drain (source-drain separation). In contrast, in ES-type TFTs, a source-drain separation process is performed in a state where the channel portion of the active layer is covered with an insulating layer that functions as an etching stopper (hereinafter referred to as a "protective insulating layer").

[0005] For example, Patent Documents 1 and 2 disclose bottom-gate (ES-type) TFTs that use a polycrystalline (or amorphous) silicon layer as an active layer. In these documents, semiconductor layers containing impurities are provided between the active layer and the source and drain electrodes of the TFT. In this specification, the low-resistance semiconductor layer connecting the electrode and the active layer is referred to as a "contact layer."

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 6-151856

[0009] Patent Document 2: WO 2016 / 157351 SUMMARY OF THE INVENTION

[0010] Technical Problem to be Solved by the Invention

[0011] For the TFT for a pixel of an active matrix substrate, improvement in not only the conduction characteristics but also the cut-off characteristics is required.

[0012] However, in existing TFTs, in a region where the gate and the drain overlap, a leakage current (GIDL: Gate-Induced Drain Leakage) due to quantum mechanical tunneling effect is generated from a high electric field between the gate and the drain, and the cut-off leakage current becomes large. Details will be described later. When the cut-off leakage current is large, for example, display unevenness may occur when the display panel is lit, degrading the display characteristics.

[0013] One embodiment of the present invention has been completed in view of the above circumstances, and an object thereof is to provide a thin film transistor capable of reducing the cut-off leakage current and a method for manufacturing the same.

[0014] Technical Solution for Solving the Technical Problem

[0015] A thin film transistor according to an embodiment of the present invention includes: a substrate; a gate supported by the substrate; a gate insulating layer covering the gate; a semiconductor layer which is a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including: a first region, a second region, and a channel region located between the first region and the second region; a first contact layer disposed on the first region of the semiconductor layer; a second contact layer disposed on the second region of the semiconductor layer; a source electrode disposed on the first contact layer and electrically connected to the first region via the first contact layer; a drain electrode disposed on the second contact layer and electrically connected to the second region via the second contact layer, the first contact layer and the second contact layer each having a stacked structure including a first amorphous silicon layer, the first amorphous silicon layer being in direct contact with the source electrode or the drain electrode, the stacked structure including N (N is an integer of 1 or more) bilayer structures S(n) (n is an integer of 1 or more and N or less), the N bilayer structures S(n) each being composed of a second amorphous silicon layer and a third amorphous silicon layer in direct contact with the upper surface of the second amorphous silicon layer, when the concentration of the n-type impurity contained in the second amorphous silicon layer included in each of the bilayer structures S(n) is set to C2(n), the concentration of the n-type impurity contained in the third amorphous silicon layer is set to C3(n), and the concentration of the n-type impurity contained in the first amorphous silicon layer is set to Cl, for any n, the relationship of C2(n) < C3(n) < Cl is satisfied.

[0016] In one embodiment, N is 3 or more.

[0017] In one embodiment, N is 5 or more.

[0018] In one embodiment, the thickness of the second amorphous silicon layer and the third amorphous silicon layer in the double-layer structure S(n) is respectively less than 20 nm.

[0019] In one embodiment, the resistivity ρ1 of the first amorphous silicon layer is less than 300 Ω·cm, and the resistivity ρ2 of the second amorphous silicon layer is less than 1×10 5 Ω·cm or more, and the resistivity ρ3 of the third amorphous silicon layer is greater than 500Ω·cm and less than 90000Ω·cm.

[0020] In one embodiment, the concentration Cl is 5×10 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 the following.

[0021] In one embodiment, the concentration C3(n) is 1.2×10 17 atoms / cm 3 Above and 4×10 19 atoms / cm 3 the following.

[0022] In one embodiment, the stacked structure further includes a fourth amorphous silicon layer directly in contact with the first region or the second region of the semiconductor layer. When the concentration of n-type impurities contained in the fourth amorphous silicon layer is set to C4, for any n, the relationship C2(n)<C4 is satisfied.

[0023] In one embodiment, the semiconductor layer has a polysilicon region, the polysilicon region includes the first region, the second region and the channel region, and the concentration C4 of the n-type impurities contained in the fourth amorphous silicon layer satisfies the relationship C3(n)<C4 for any n.

[0024] In one embodiment, the concentration C4 is 5×10 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 the following.

[0025] In one embodiment, when viewed from the normal direction of the substrate, the semiconductor layer further includes an amorphous silicon region arranged outside the polycrystalline silicon region.

[0026] A thin film transistor according to other embodiments of the present invention includes: a substrate; a gate supported by the substrate; a gate insulating layer covering the gate; a semiconductor layer which is a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including: a first region, a second region, and a channel region located between the first region and the second region; a first contact layer disposed on the first region of the semiconductor layer; a second contact layer disposed on the second region of the semiconductor layer; a source electrode disposed on the first contact layer and electrically connected to the first region via the first contact layer; a drain electrode disposed on the second contact layer and electrically connected to the second region via the second contact layer, wherein the first contact layer and the second contact layer are each an amorphous silicon layer containing n-type impurities, and the amorphous silicon layer has: a contact region in contact with the source electrode or the drain electrode, and the concentration of the n-type impurities is R1 or more; a concentration modulation region located between the contact region and the semiconductor layer, and the concentration distribution of the n-type impurities in the depth direction from the source electrode or the drain electrode toward the semiconductor layer changes, and the concentration modulation region alternately has two or more first inclined regions and second inclined regions, the first inclined region includes a portion where the concentration in the depth direction decreases from R3 to R2 within a range of 20 nm, the second inclined region includes a portion where the concentration in the depth direction increases from R2 to R3 within a range of 20 nm, and the concentrations R1, R2, and R3 satisfy the relationship of R2 < R3 < R1.

[0027] In one embodiment, in the first inclined region, the concentration decreases by two or more orders of magnitude.

[0028] In one embodiment, the concentration R1 is 4.5×10 19 atoms / cm 3 , the concentration R2 is 1.5×10 17 atoms / cm 3 , the concentration R3 is 4.5×10 17 atoms / cm 3 .

[0029] According to another embodiment of the present invention, a thin film transistor includes: a substrate; a gate electrode supported by the substrate; a gate insulating layer covering the gate electrode; a semiconductor layer, which is a semiconductor layer arranged on the gate insulating layer, and the semiconductor layer includes: a first region, a second region, and a channel region located between the first region and the second region; a first contact layer arranged on the first region of the semiconductor layer; a second contact layer arranged on the second region of the semiconductor layer; a source electrode arranged on the first contact layer and electrically connected to the first region via the first contact layer; a drain electrode arranged on the second contact layer and electrically connected to the second region via the second contact layer, the first contact layer and the second contact layer respectively have a stacked structure including a first amorphous silicon layer, the first amorphous silicon layer is in direct contact with the source electrode or the drain electrode, the stacked structure includes N (N is an integer greater than 1) double-layer structures S(n) (n is an integer greater than 1 and less than N), the N double-layer structures S(n) are respectively composed of a second amorphous silicon layer and a third amorphous silicon layer in direct contact with the upper surface of the second amorphous silicon layer, when the resistivity of the second amorphous silicon layer of the double-layer structure S(n) is set to ρ2(n), the resistivity of the third amorphous silicon layer is set to ρ3(n), and the resistivity of the first amorphous silicon layer is ρ1, for any n, the relationship ρ2(n)>ρ3(n)>ρ1 is satisfied.

[0030] In one embodiment, the resistivity ρ1 is less than 300 Ω·cm, and the resistivity ρ2 is less than 1×10 5 Ω·cm or more, and the resistivity ρ3 is greater than 500Ω·cm and less than 90000Ω·cm.

[0031] In one embodiment, the thin film transistor is an etch stop type and also has a protective insulating layer covering the channel region of the semiconductor layer, a portion of the protective insulating layer is located between the semiconductor layer and the first contact layer, and another portion is located between the semiconductor layer and the second contact layer.

[0032] In one embodiment, the thin film transistor is a channel etch type and further includes an upper insulating layer that covers the semiconductor layer, the source electrode, and the drain electrode of the thin film transistor, and the upper insulating layer is in direct contact with the channel region of the semiconductor layer.

[0033] A display device according to an embodiment of the present invention includes: a thin film transistor as described in any one of the above; and a display area having a plurality of pixels, wherein the thin film transistor is configured on each of the plurality of pixels.

[0034] A method for manufacturing a thin film transistor according to an embodiment of the present invention is the above-mentioned method for manufacturing a thin film transistor, which comprises: step (A), forming the gate electrode, the gate insulating layer and the semiconductor layer on the substrate; step (B), which is a step of forming a stacked film including the N (N is an integer greater than 1) double-layer structures S(n) (n is an integer greater than 1 and less than N) on the semiconductor layer, wherein the step (B) comprises: step (B1), which is a step of forming the N double-layer structures S(n), wherein the layers of the double-layer structures S(n) are stacked in the following order: ) a second amorphous silicon film containing n-type impurities, and a third amorphous silicon film directly in contact with the upper surface of the second amorphous silicon film and containing n-type impurities at the concentration C3(n); step (B2), after the step (B1), forming a first amorphous silicon film containing n-type impurities at the concentration C1; step (C), forming a conductive film on the stacked film in direct contact with the first amorphous silicon film; and step (D), forming the source electrode and the drain electrode from the conductive film, and forming the first contact layer and the second contact layer from the stacked film by patterning the conductive film and the stacked film.

[0035] In one embodiment, the semiconductor layer contains a polycrystalline silicon region, and the process (B) further includes: before the process (B1), a process of forming a fourth amorphous silicon film in a manner connected to the polycrystalline silicon region, and the concentration C4 of n-type impurities contained in the fourth amorphous silicon film satisfies the relationship C3(n)<C4 for any n.

[0036] According to another embodiment of the present invention, a method for manufacturing a thin film transistor is the above-mentioned method for manufacturing a thin film transistor, comprising: step (A), forming the gate, the gate insulating layer and the semiconductor layer on the substrate; step (B), using an impurity-containing gas and a raw material gas containing the n-type impurities to form an amorphous silicon film containing the concentration modulation area and the contact area on the semiconductor layer by a CVD method, by changing the ratio of the impurity-containing gas to the raw material gas and controlling the concentration of the n-type impurities in the depth direction, thereby continuously forming the amorphous silicon film; step (C), forming a conductive film on the amorphous silicon film; step (D), by patterning the conductive film and the amorphous silicon film, forming the source electrode and the drain electrode from the conductive film, and forming the first contact layer and the second contact layer from the amorphous silicon film.

[0037] Beneficial Effects

[0038] According to one embodiment of the present invention, a thin film transistor capable of reducing off-leakage current and a method for manufacturing the same are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 (a) and (b) are respectively a schematic top view and a cross-sectional view of the TFT 101 according to the first embodiment. Figure 1 (c) is a schematic enlarged cross-sectional view of the contact layer of TFT101

[0040] Figure 2 1 is a schematic cross-sectional view showing a depletion layer D formed in a contact layer C.

[0041] Figure 3 (a) to (f) are schematic enlarged cross-sectional views for explaining an example of a method for manufacturing the TFT 101 .

[0042] Figure 4 (a) and (b) are respectively a schematic top view and a cross-sectional view of the TFT 102 of the modification example 1, and (c) is a schematic enlarged cross-sectional view of the contact layer of the TFT 102.

[0043] Figure 5 This is a schematic enlarged cross-sectional view of a contact layer of a TFT according to Modification Example 2.

[0044] Figure 6 (a) to (e) are schematic cross-sectional views showing the stacked structures e1 to e4 and r1 of the contact layers in the TFTs of Examples 1 to 4 and Comparative Example, respectively.

[0045] Figure 7 This is a cross-sectional SEM (Scanning Electron Microscope) image of the contact layer in the TFT of Example 4.

[0046] Figure 8 It is a graph showing VI characteristics of TFTs of Examples 1 to 4 and a comparative example.

[0047] Fig. 9 This is a diagram schematically showing the distribution of phosphorus concentration in the contact layer of the TFT of Example 4 in the depth direction.

[0048] Fig.10 is a diagram showing the poly-Si layer and n + Figure 2. The band structure of the type-Si layer near the bonding interface.

[0049] Fig.11 1 is a diagram showing the energy band structure near the bonding interface between the i-type a-Si layer and the poly-Si layer.

[0050] Fig.12 It is a schematic enlarged cross-sectional view of the interface between the poly-Si layer and the i-type a-Si layer.

[0051] Fig.13 (a) and (b) are schematic cross-sectional views respectively showing a heterojunction TFT 801 and a homojunction TFT 802 used in the measurement.

[0052] Fig.14 1 is a diagram showing the CV characteristics of the heterojunction TFT 801 and the homojunction TFT 802. DETAILED DESCRIPTION

[0053] <Insights of the inventors I: depletion layer>

[0054] In the existing bottom-gate TFT, high GIDL may occur. For example, in the TFT disclosed in Patent Document 1, a source / drain is provided on the active layer via a semiconductor layer (contact layer) containing impurities. In Patent Document 2, an intrinsic amorphous silicon layer and an n-type silicon layer are sandwiched on the active layer. + The present inventors have studied and found that in the above-mentioned conventional structure, a depletion layer (depletion layer barrier) with a sufficient thickness may not be formed, and in this case, GIDL increases.

[0055] Therefore, the inventors discovered a contact layer structure capable of increasing the thickness of the depletion layer formed between the active layer and the source / drain electrodes (when there are multiple depletion layers, their total thickness), and came up with the invention of this application.

[0056] <Insights of the Inventors II: Regarding Two-Dimensional Electron Gas>

[0057] On the other hand, the inventors have found that in a polycrystalline silicon TFT using a polycrystalline silicon (poly-Si) layer as an active layer, if a contact layer using an intrinsic amorphous silicon (i-type a-Si) layer as the lowest layer is formed on the poly-Si layer, a heterojunction is formed by the poly-Si layer and the i-type a-Si layer, and a two-dimensional electron gas (hereinafter referred to as "2DEG") can be generated in the same manner as a high electron mobility transistor (HEMT). When 2DEG is generated at the interface between the poly-Si layer and the contact layer (i.e., electrons are accumulated at the interface), there is a concern that GIDL will further increase.

[0058] 2DEG refers to a layer of electrons (a state of two-dimensional distribution of electrons) generated at the interface (a region with a thickness of about 10 nm near the interface) when two semiconductors with different band gap energies are bonded. 2DEG is known to be generated by compound semiconductors such as GaAs, InP, GaN, and SiGe, but it is not known that 2DEG is generated at the bonding interface between a poly-Si layer and another semiconductor layer with a larger band gap energy than poly-Si (e.g., an intrinsic amorphous silicon layer (hereinafter referred to as an "i-type a-Si layer")).

[0059] In this specification, the joining of two semiconductor layers with different band gap energies (e.g., the joining of an i-type a-Si layer and a poly-Si layer) is referred to as "semiconductor heterojunction", and the joining of two semiconductor layers with the same band gap energy (e.g., the joining of an i-type a-Si layer and a poly-Si layer) is referred to as "semiconductor heterojunction". + The bonding of two types of a-Si layers) is called "semiconductor homogeneous bonding".

[0060] Fig.11 This is a schematic diagram for explaining an example of the band structure near the interface of a semiconductor heterojunction. Here, a semiconductor heterojunction formed by configuring an i-type a-Si layer on an undoped poly-Si layer (active layer) in a bottom-gate polycrystalline silicon TFT is shown.

[0061] The band gap energy Eg1 of the poly-Si layer is about 1.1 eV, and the band gap energy Eg2 of the i-type a-Si layer is about 1.88 eV. A depletion layer is formed on the poly-Si layer side. Fig.11 In the figure, the flow of electrons is indicated by arrow 91, and the flow of holes is indicated by arrow 92. As shown in the figure, a quantum well qw is formed at the interface between the i-type a-Si layer and the poly-Si layer, and electrons are accumulated to generate 2DEG. Hereinafter, the region 84 where 2DEG is generated is referred to as a "2DEG region".

[0062] Fig.12 This is a schematic enlarged cross-sectional view of the interface between the poly-Si layer 81 and the i-type a-Si layer 82. When the poly-Si layer 81 is used as the active layer of the TFT and the i-type a-Si layer 82 is used as the bottom layer of the contact layer, a 2DEG region 84 may be generated at these interfaces. When the 2DEG region 84 is formed, the electrons in the 2DEG region 84 tend to move toward the poly-Si layer 82 side along the grain boundary (arrow 93) of the poly-Si layer 81, and the leakage current increases.

[0063] Next, the capacitance measurement performed by the present inventors in order to confirm the generation of 2DEG at the interface of the semiconductor heterojunction is described.

[0064] Fig.13 (a) and (b) are schematic cross-sectional views of ES-type TFTs 801 and 802 used in capacitance measurement. TFT 801 is a TFT having a semiconductor heterojunction between the gate and the source / drain (referred to as a "TFT containing a heterojunction"). TFT 802 is a TFT having a semiconductor homojunction between the gate and the source / drain (referred to as a "TFT containing a homojunction").

[0065] The TFT 801 having a heterojunction includes: a gate electrode 2 formed on a substrate; a gate insulating layer 3 covering the gate electrode 2; a semiconductor layer (active layer) 4 formed on the gate insulating layer 3; a protective insulating layer (etching stop layer) 5 covering the channel region of the semiconductor layer 4; and a source electrode 8s and a drain electrode 8d. The semiconductor layer 4 is a polycrystalline silicon layer (poly-Si layer). An i-type a-Si layer 6 composed of intrinsic amorphous silicon and an n-type a-Si layer 8 composed of n-type a-Si layer 8 are sequentially arranged between the semiconductor layer 4 and the protective insulating layer 5 and the source electrode 8s, and between the semiconductor layer 4 and the protective insulating layer 5 and the drain electrode 8d. + n-type amorphous silicon + The i-type a-Si layer 7 serves as a contact layer. The i-type a-Si layer 6 is in direct contact with the semiconductor layer 4. The junction g1 between the semiconductor layer 4, which is a poly-Si layer, and the i-type a-Si layer 6 is a semiconductor heterojunction.

[0066] On the other hand, the TFT 802 with a homojunction uses an amorphous silicon layer (a-Si layer) as the semiconductor layer 4, except that only n + The structure is the same as that of the TFT 801 including a heterojunction except that the a-Si layer 7 is used as a contact layer. + The junction g2 of the a-Si layer 7 is a semiconductor homojunction.

[0067] For the heterojunction TFT 801 and the homojunction TFT 802, an alternating current (10 kHz) is applied between the gate and the source using a TFT monitor to measure the capacitance C between the gate and the source.

[0068] Fig.14 : is a graph showing the CV characteristics of the heterojunction TFT 801 and the homojunction TFT 802, where the vertical axis is the capacitance C and the horizontal axis is the gate voltage Vg.

[0069] Depend on Fig.14 It can be seen that the capacitance change of the heterojunction TFT801 becomes smaller than that of the homojunction TFT802. This indicates the difference in carrier concentration (electron concentration). In general, it is known that the higher the carrier concentration, the closer the semiconductor is to the metal, and therefore the smaller the capacitance change. It is believed that in the heterojunction TFT801, electrons are retained in the quantum well qw formed at the interface of the junction g1 to generate 2DEG, and the carrier concentration increases the amount of electrons distributed in the 2DEG compared to the homojunction TFT802. Thus, it is confirmed that 2DEG is formed at the interface of the semiconductor heterojunction. In addition, if a positive voltage is applied to the gate voltage Vg, in the heterojunction TFT801, since the electrons retained in the quantum well qw at the interface of the junction g1 overflow to the semiconductor layer 4 side, it is believed that its carrier concentration becomes the same as that of the homojunction TFT802.

[0070] The present inventors have studied a TFT structure that can suppress the generation of the above-mentioned 2DEG at the interface between the active layer and the contact layer.

[0071] The invention of this application is completed based on the above insights I and II. According to one embodiment of the invention of this application, a bottom-gate TFT is provided, which can increase the thickness of the depletion layer formed in the contact layer and reduce GIDL. In addition, according to another embodiment of the invention of this application, a bottom-gate TFT is provided, which can increase the thickness of the depletion layer formed in the contact layer and suppress the generation of 2DEG at the interface between the contact layer and the active layer, thereby reducing GIDL.

[0072] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0073] (First Embodiment)

[0074] The thin film transistor (TFT) of the first embodiment is an etch stop (ES) type polysilicon TFT. The TFT of this embodiment can be applied to circuit substrates such as active matrix substrates, various display devices such as liquid crystal display devices and organic EL display devices, image sensors, electronic devices, etc.

[0075] Figure 1 (a) is a schematic top view of a thin film transistor (TFT) 101 of this embodiment. Figure 1 (b) is a cross-sectional view of the TFT 101 taken along line II'. Figure 1 (c) is a schematic enlarged cross-sectional view for explaining the structure of the contact layer of the TFT 101 .

[0076] The TFT 101 is supported by a substrate 1 such as a glass substrate, and includes a gate 2, a gate insulating layer 3 covering the gate 2, a semiconductor layer (active layer) 4 disposed on the gate insulating layer 3, and a source electrode 8s and a drain electrode 8d electrically connected to the semiconductor layer 4. A first contact layer Cs is disposed between the semiconductor layer 4 and the source electrode 8s, and a second contact layer Cd is disposed between the semiconductor layer 4 and the drain electrode 8d. A protective insulating layer (also referred to as an etching stopper layer) 5 is disposed between the semiconductor layer 4 and the first contact layer Cs and the second contact layer Cd in direct contact with a portion of the semiconductor layer 4.

[0077] The semiconductor layer 4 is a layer that functions as an active layer of the TFT 101, and includes a polycrystalline silicon region (poly-Si region) 4p. As shown in the figure, the semiconductor layer 4 may also include a poly-Si region 4p and an amorphous silicon region (a-Si region) 4a mainly containing amorphous silicon. Alternatively, the entire semiconductor layer 4 may be the poly-Si region 4p.

[0078] The poly-Si region 4p includes a first region Rs and a second region Rd, and a channel region Rc located between the first region Rs and the second region Rd and forming a channel of the TFT 101. The channel region Rc is arranged to overlap the gate 2 via the gate insulating layer 3. The first region Rs is electrically connected to the source 8s, and the second region Rd is electrically connected to the drain 8d.

[0079] The protective insulating layer 5 is arranged on a part of the semiconductor layer 4 in a manner covering the channel region Rc. In this example, the protective insulating layer 5 is formed in an island shape on the channel region Rc, and the first region Rs and the second region Rd are not covered by the protective insulating layer 5. A part of the protective insulating layer 5 is located between the channel region Rc and the first contact layer Cs, and another part is located between the channel region Rc and the second contact layer Cd. In addition, the protective insulating layer 5 may not be in an island shape. In this case, the protective insulating layer 5 may also have an opening that exposes the first region Rs and the second region Rd of the semiconductor layer 4.

[0080] The first contact layer Cs is formed on the first region Rs of the semiconductor layer 4. The lower surface of the first contact layer Cs may be in direct contact with the first region Rs, and the upper surface may be in direct contact with the source electrode 8s. The source electrode 8s is electrically connected to the first region Rs of the semiconductor layer 4 via the first contact layer Cs. The second contact layer Cd is formed on the second region Rd of the semiconductor layer 4. The lower surface of the second contact layer Cd may be in direct contact with the second region Rd, and the upper surface may be in direct contact with the drain electrode 8d. The drain electrode 8d is electrically connected to the second region Rd of the semiconductor layer 4 via the second contact layer Cd. The first contact layer Cs and the second contact layer Cd may also be configured separately from each other.

[0081] In this embodiment, the first contact layer Cs and the second contact layer Cd are amorphous silicon layers having a stacked structure.

[0082] Reference Figure 1 (c) describes an example of a stacked structure of a first contact layer Cs and a second contact layer Cd (hereinafter collectively referred to as “contact layer C”).

[0083] The contact layer C includes a first amorphous silicon layer (first a-Si layer) 71 as the uppermost layer of the stacked structure. The first a-Si layer 71 functions as a contact region that is in direct contact with the source 8s or the drain 8d. N double-layer structures S(n) (1≤n≤N) are formed below the first a-Si layer 71. The region 70 including the N double-layer structures S(n) is referred to as a "stacked region".

[0084] Each layer of the double-layer structure S(n) is composed of a second amorphous silicon layer (2a-Si layer) 72(n) and a third amorphous silicon layer (third a-Si layer) 73(n) that is in direct contact with the upper surface of the second a-Si layer 72(n). In each double-layer structure S(n), when the concentration of the n-type impurity contained in the second a-Si layer 72(n) is set as C2(n), the concentration of the n-type impurity contained in the third a-Si layer 73(n) is set as C3(n), and the concentration of the n-type impurity contained in the first a-Si layer 71 is set as C1, for any n, the relationship C2(n) < C3(n) < C1 is satisfied. The second a-Si layer 72(n) may be an intrinsic a-Si layer that substantially does not contain n-type impurities.

[0085] In Figure 1 In the example shown in (c) of, three (N = 3) double-layer structures S(1), S(2), and S(3) are arranged in sequence from the first a-Si layer 71 side. The concentrations C2(1) and C3(1) of the double-layer structure S(1) satisfy C2(1) < C3(1) < C1. Similarly, the concentrations C2(2) and C3(2) of the double-layer structure S(2) satisfy C2(2) < C3(2) < C1, and the concentrations C2(3) and C3(3) of the double-layer structure S(3) satisfy C2(3) < C3(3) < C1. In addition, the concentrations C2(1), C2(2), and C2(3) may be the same as or different from each other. Similarly, the concentrations C3(1), C3(2), and C3(3) may be the same as or different from each other.

[0086] The contact layer C may further include a fourth amorphous silicon layer (fourth a-Si layer) 74 that is in direct contact with the first region Rs or the second region Rd as the lowermost layer of the stacked structure. If the concentration of the n-type impurity in the fourth a-Si layer 74 is set as C4, then for any n, it may also be C4 > C2(n). Preferably, C4 > C3(n).

[0087] According to the TFT101 of the present embodiment, it is possible to increase the thickness (total thickness) of the depletion layer formed in the contact layer C. Hereinafter, with reference to Figure 2 explain the reason.

[0088] If a reverse bias (negative voltage) is applied to the gate 2 of the TFT101, then as Figure 2As shown, a depletion layer D(n) is formed at the interface between the second a-Si layer 72(n) and the third a-Si layer 73(n) of each second layer structure S(n). Each depletion layer D(n) is formed on the second a-Si layer 72(n) side. The thickness of the depletion layer D(n) can be controlled by, for example, concentrations C2(n) and C3(n). The concentration C3(n) is independently controlled from the concentration C1 (and C4) and is set to a predetermined concentration lower than the concentration C1. Therefore, a thicker depletion layer D(n) than before can be formed between the second a-Si layer 72(n) and the third a-Si layer 73(n), so that GIDL can be reduced by the depletion layer D(n).

[0089] In addition, a depletion layer D0 is also formed between the third a-Si layer 73 ( 3 ) and the first a-Si layer 71 , and its thickness is smaller than that of the depletion layer D(n).

[0090] In this example, two or more (here, three) depletion layers D(1), D(2), and D(3) are formed between the semiconductor layer 4 and the source electrode 8s or the drain electrode 8d. The total thickness of the depletion layer D is the sum of the thicknesses of the above depletion layers D(1), D(2), and D(3). In this way, by increasing the number of depletion layers D, the total thickness of the depletion layer D can be further increased. Thus, by stacking the potential barrier that carriers should penetrate, the thickness can be effectively increased, so that GIDL can be more effectively suppressed.

[0091] In addition, in conventional TFTs (such as Patent Document 2, etc.), there is an n-type contact region that becomes a contact region with a source / drain. + In such a TFT, the intrinsic amorphous silicon layer (lower layer) is configured under the n-type amorphous silicon layer (upper layer). + The impurity concentration of the amorphous silicon layer is set to a high concentration that allows it to function as a contact region, so the depletion layer formed at the interface with the lower layer becomes thinner.

[0092] The concentration C1 of the first a-Si layer 71 can be set to a concentration suitable for the contact area with the electrode, for example, 5×10 19 atoms / cm 3 Above 1×10 23 atoms / cm 3 The thickness of the first a-Si layer 71 may be, for example, not less than 10 nm and not more than 50 nm.

[0093] The concentration C2(n) of the second a-Si layer 72(n) is, for example, 0 atoms / cm 3 Above and 1×10 17 atoms / cm 3The second a-Si layer 72(n) does not substantially contain n-type impurities. For example, the concentration C2(n) of the second a-Si layer 72(n) may be below the measurement limit of SIMS (1×10 17 atoms / cm 3 The thickness of the second a-Si layer 72(n) may be, for example, not less than 5 nm and not more than 20 nm, and preferably not less than 10 nm and not more than 20 nm.

[0094] The concentration C3(n) of the third a-Si layer 73(n) is, for example, 1.2×10 17 atoms / cm 3 Above 4×10 19 atoms / cm 3 For any n, the concentration C3(n) may be more than 5 times the concentration C2(n). Thus, a depletion layer D(n) is more reliably formed between the third a-Si layer 73(n) and the second a-Si layer 72(n). The thickness of the third a-Si layer 73(n) may be, for example, greater than 0 nm and less than 20 nm, preferably greater than 10 nm and less than 20 nm. In addition, the thickness of the second a-Si layer 72(n) may be greater than the thickness of the third a-Si layer 73(n). Thus, a thicker depletion layer D(n) can be formed.

[0095] The number of stacking layers N of the double-layer structure S(n) in the contact layer C is not particularly limited, but if it is, for example, 2 or more, preferably 3 or more, and more preferably 5 or more, the total thickness of the depletion layer D can be further increased, so that a more significant effect can be obtained. The upper limit of N is not particularly limited, but if N is too large, film peeling may occur. N can be, for example, 20 or less. The overall thickness of the contact layer C can be, for example, 100 nm or more and 300 nm or less. As in the present embodiment, in the case of an ES-type TFT having a protective insulating layer 5, there is no need to retain an a-Si film on the channel region 4s to protect the channel region 4s, so the thickness of the contact layer C can be suppressed to less than 20 nm.

[0096] In addition, the bottom layer of the contact layer C may also be the second a-Si layer 72(N). Alternatively, a fourth a-Si layer 74 containing n-type impurities at a concentration C4 higher than the concentration C2(n) of the second a-Si layer 72(n) may be provided below the stacked region 70 as the bottom layer of the contact layer C. By providing the fourth a-Si layer 74 in direct contact with the semiconductor layer 4, the resistance of the interface between the semiconductor layer 4 and the contact layer C can be reduced, thereby suppressing the reduction of the on-current.

[0097] In this embodiment, the concentration C4 of the n-type impurity in the fourth a-Si layer 74 is set higher (for example, higher than the concentration C3(n)). This can suppress GIDL caused by the two-dimensional electron gas (2DEG). The reason is described below.

[0098] Reference Fig.11 as well as Fig.12 As described above, electrons are accumulated in the quantum well qw at the interface between the Poly-Si layer and the i-type a-Si layer, and 2DEG is generated. 2DEG may be a major factor causing the leakage current (GIDL) to increase.

[0099] The problem of leakage current due to 2DEG occurs when the Fermi level before the poly-Si layer and the a-Si layer serving as the bottom layer of the contact layer are connected to each other and the quantum well qw is formed by the connection ( Fig.11 In particular, at the interface between a poly-Si layer that does not contain impurities imparting conductivity (undoped) and an a-Si layer that does not contain substantially any impurities (intrinsic), the increase in leakage current due to the 2DEG region becomes significant.

[0100] In contrast, even in the case of a semiconductor heterojunction of a poly-Si layer and an a-Si layer, if the Fermi levels of the poly-Si layer and the a-Si layer before joining have such a relationship that a quantum well qw is not formed by joining (or even if it is formed, the quantum well qw becomes smaller), electrons are not easily retained in the joining portion, and 2DEG is difficult to generate.

[0101] Fig.10 This is a schematic diagram for explaining another example of the band structure near the interface of a semiconductor heterojunction. Here, it is shown that an a-Si layer (n-Si) containing impurities is arranged on an undoped poly-Si layer (active layer). + The poly-Si layer and the n-type a-Si layer form a semiconductor heterojunction. + The Fermi level of the poly-Si layer before bonding has a relationship that no quantum well qw is formed due to bonding. Therefore, electrons are not easily retained between the poly-Si layer and the n-type a-Si layer. + The bonding part of the type a-Si layer suppresses the generation of 2DEG.

[0102] In the TFT 101 of the present embodiment, the first region Rs and the second region Rd of the semiconductor layer 4 are polysilicon regions (e.g., undoped polysilicon regions), and the fourth a-Si layer 74 is disposed in direct contact with the polysilicon regions. The fourth a-Si layer 74 contains n-type impurities at a concentration C4 higher than the concentration C3. + Therefore, if Fig.10As illustrated, it is difficult to form a 2DEG at the interface between the semiconductor layer 4 and the fourth a-Si layer 74 (or even if formed, the electron density in the 2DEG region is small). Therefore, since GIDL caused by the 2DEG can be suppressed, the leakage current can be reduced more effectively.

[0103] The concentration C4 of the fourth a-Si layer 74 is set to a concentration that can suppress the formation of a 2DEG, for example, 5×10 19 atoms / cm 3 or more and 1×10 23 atoms / cm 3 or less. The thickness of the fourth a-Si layer 74 can be, for example, 5 nm or more and 20 nm or less. If it is 5 nm or more, the generation of a 2DEG can be suppressed. If it is 20 nm or less, an increase in the thickness of the entire contact layer can be suppressed.

[0104] In addition, the structure of each amorphous silicon layer in the contact layer C can also be expressed by the resistivity (specific resistance) ρ [Ω·cm] instead of the concentration C1 to C4 of the n-type impurity. The higher the concentration of the n-type impurity, the lower the resistivity ρ. That is, when the resistivity of the second amorphous silicon layer 72(n) of each layer of the double-layer structure S(n) is ρ2(n), the resistivity of the third amorphous silicon layer 73(n) is ρ3(n), and the resistivity of the first amorphous silicon layer 71 is ρ1, for any n, the relationship ρ2(n)>ρ3(n)>ρ1 is satisfied. In addition, when the contact layer C includes the fourth a-Si layer 74, when the resistivity of the fourth a-Si layer 74 is ρ4, for any n, it may also be ρ4<ρ2(n). Preferably, ρ4<ρ3(n). The resistivity ρ1 and ρ4 can be, for example, 300 Ω·cm or less. The resistivity ρ2 can also be, for example, above the measurement limit (here, 1×10 5 Ω·cm or more). The resistivity ρ3 can be, for example, 500 Ω·cm or more and less than 90000 Ω·cm.

[0105] <Manufacturing method of TFT101>

[0106] Next, an example of the manufacturing method of the TFT101 will be described.

[0107] Figure 3 (a) to Figure 3 (f) are schematic process cross-sectional views for explaining an example of the manufacturing method of the TFT101.

[0108] First, as shown in Figure 3 (a), a gate 2, a gate insulating layer 3, and an a-Si film 40 for an active layer are sequentially formed on a substrate 1.

[0109] As the substrate 1, for example, a substrate having an insulating surface such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (resin substrate) can be used.

[0110] The gate 2 is formed by forming a gate conductive film on the substrate 1 and patterning it. Here, for example, a gate conductive film (thickness: for example, about 500 nm) is formed on the substrate by sputtering, and the metal film is patterned using a known photolithography process. The gate conductive film is etched using, for example, wet etching.

[0111] The material of the gate 2 can be a single metal containing molybdenum (Mo), tungsten (W), copper (Cu), chromium (Cr), tantalum (Ta), aluminum (Al), titanium (Ti) and other materials that contain nitrogen, oxygen or other metals, or a transparent conductive material such as indium tin oxide (ITO).

[0112] The gate insulating layer 3 is formed on the substrate 1 on which the gate 2 is formed by, for example, a plasma CVD method. As the gate insulating layer (thickness: for example, about 0.4 μm) 3, for example, a silicon oxide (SiO2) layer, a silicon nitride (SiN x ) layer, or SiO2 layer and SiN x Layered film.

[0113] The a-Si film 40 for the active layer can be formed by a CVD method using, for example, hydrogen (H2) and silane gas (SiH4). The a-Si film 40 for the active layer can also be a non-doped amorphous silicon film that does not substantially contain n-type impurities. Non-doped amorphous silicon film refers to an a-Si film formed without actively adding n-type impurities (for example, using a raw material gas that does not contain n-type impurities). In addition, the a-Si film 40 for the active layer can contain n-type impurities at a relatively low concentration. The thickness of the a-Si film 40 for the active layer can be greater than 20nm and less than 70nm (for example, 50nm).

[0114] Then, if Figure 3 As shown in (b), in the a-Si film 40 for the active layer, at least the portion that becomes the channel region of the TFT is irradiated with laser 30. As the laser 30, ultraviolet lasers such as XeCl excimer lasers (wavelength 308nm) and solid lasers with a wavelength of 550nm or less such as the second harmonic of YAG lasers (wavelength 532nm) can be applied. By irradiating with laser 30, the region irradiated with laser 30 in the a-Si film 40 for the active layer is heated, melted and solidified to form a poly-Si region 4p. Thus, a semiconductor layer 4 including the poly-Si region 4p is obtained. In the poly-Si region 4p, the crystal grains grow in a columnar shape toward the upper surface of the semiconductor layer 4.

[0115] The crystallization method based on the laser 30 is not particularly limited. For example, the laser 30 from the laser light source can be focused on only a part of the a-Si film 40 for the active layer through a microlens array, so that the a-Si film 40 for the active layer is partially crystallized. In this specification, this crystallization method is referred to as "local laser annealing method". If local laser annealing is used, compared with the existing laser annealing in which a linear laser is scanned over the entire surface of the a-Si film, mass productivity can be improved because the time required for crystallization can be greatly shortened.

[0116] The microlens array has microlenses arranged in two dimensions or one dimension. When a plurality of TFTs are formed on the substrate 1, the laser 30 is focused by the microlens array and incident only on a plurality of predetermined areas (irradiation areas) separated from each other in the a-Si film 40 for the active layer. Each irradiation area is arranged corresponding to the portion that becomes the channel area of ​​the TFT. The position, number, shape, size, etc. of the irradiation area can be controlled by the size of the microlens array (not limited to lenses less than 1 mm), the arrangement pitch, the opening position of the mask arranged on the light source side of the microlens array, etc. Thus, the area irradiated by the laser 30 in the a-Si film 40 for the active layer is heated, melted and solidified to become the poly-Si area 4p. The area not irradiated by the laser remains in the state of the a-Si area 4a. When observed from the normal direction of the substrate 1, the a-Si area 4a is arranged, for example, outside the poly-Si area 4p.

[0117] Regarding a more specific method of local laser annealing and the structure of an apparatus for local laser annealing (including a microlens array and a mask structure), the entire contents of International Publication No. 2011 / 055618, International Publication No. 2011 / 132559, International Publication No. 2016 / 157351, and International Publication No. 2016 / 170571 are cited in the present application specification as references.

[0118] Then, if Figure 3 As shown in (c), a protective insulating film 50 (etching stop layer) is formed on the semiconductor layer 4 as a protective insulating layer. Here, a silicon oxide film (SiO2 film) is formed as the protective insulating film 50 by a CVD method. The thickness of the protective insulating film 50 can be, for example, not less than 30 nm and not more than 300 nm. Thereafter, although not shown in the figure, the semiconductor layer 4 can also be subjected to a dehydrogenation annealing treatment (for example, 450° C., 60 minutes).

[0119] Then, if Figure 3As shown in (d), the protective insulating film 50 is patterned to obtain a protective insulating layer 5 covering the portion of the semiconductor layer 4 that becomes the channel region. On the source side and the drain side of the portion that becomes the channel region, a portion of the poly-Si region 4p is exposed from the protective insulating layer 5. The exposed portions become the first region and the second region connected to the contact layers Cs and Cd.

[0120] Next, a Si film for a contact layer is formed on the semiconductor layer 4. Here, a stacked film (thickness: for example, about 150 nm) 700 is formed by a plasma CVD method. The stacked film 700 first forms a fourth a-Si film (thickness: for example, 10 nm) 740 containing an n-type impurity (here, phosphorus) at a concentration C4. Next, a double-layer structure S(1) is formed. The double-layer structure S(1) is formed by sequentially depositing a second a-Si film (thickness: for example, 15 nm) 720 containing an n-type impurity at a concentration C2(1) and a third a-Si film (thickness: for example, 10 nm) 730 containing an n-type impurity in direct contact with the upper surface of the second a-Si film 720 and at a concentration C3(n). Next, N double-layer structures (n) are formed by the same method. Then, a first a-Si film (thickness: for example, 15 nm) 710 containing an n-type impurity (here, phosphorus) is formed at a concentration C1. Each amorphous silicon film uses a mixed gas of silane, hydrogen and phosphine (PH3) as a raw material gas. The flow rate of phosphine (the flow rate ratio of phosphine to silane) is appropriately adjusted so that the phosphorus concentration of the amorphous silicon film becomes a desired value. When forming an intrinsic amorphous silicon film as the second a-Si film 720, a mixed gas containing silane and hydrogen and substantially not containing phosphine (PH3) is used as a raw material gas.

[0121] When forming a stacked structure of the contact layer C, the supply of the raw material gas may be temporarily stopped after forming an a-Si layer and before forming the a-Si layer thereon. The time for stopping the supply of the raw material gas is called "pause time" or "stabilization time". In this way, the concentration and thickness of each a-Si layer can be controlled more accurately, so the effect of the depletion layer barrier can be achieved more reliably. Alternatively, by continuously supplying the raw material gas and changing the flow ratio of the n-type impurity (for example, the flow ratio of phosphine to silane) at an appropriate time, a contact layer C having a concentration distribution in the thickness direction can also be formed.

[0122] Next, a conductive film for source and drain (thickness: about 0.3 μm, for example) and a resist mask M are formed on the stacked film 700. The conductive film for source and drain can be formed using the same material and method as the conductive film for gate.

[0123] Then, using the resist mask M, patterning of the conductive film for the source and drain and the stacked film 700 for the contact layer is performed by, for example, dry etching. Figure 3 As shown in (e), the source electrode 8s and the drain electrode 8d are formed from the conductive film (source / drain separation process). In addition, the first contact layer Cs and the second contact layer Cd are separated from the stacked film 700 and formed. During patterning, the protective insulating layer 5 functions as an etching stopper, so that the portion of the semiconductor layer 4 covered by the protective insulating layer 5 is not etched. The end portions of the first contact layer Cs and the second contact layer Cd on the channel side are located on the upper surface of the protective insulating layer 5. Then, the resist mask M is peeled off from the substrate 1. In this way, the TFT 101 is manufactured.

[0124] In addition, in order to passivate the dangling bonds in the poly-Si region 4p and reduce the defect density, the poly-Si region 4p may be subjected to hydrogen plasma treatment after the source-drain separation process.

[0125] When the TFT 101 is used as a pixel TFT of an active matrix substrate, Figure 3 As shown in (f), an interlayer insulating layer is formed so as to cover the TFT 101. Here, an inorganic insulating layer (passivation film) 11 and an organic insulating layer 12 are formed as the interlayer insulating layer.

[0126] As the inorganic insulating layer 11, a silicon oxide layer, a silicon nitride layer, or the like can be used. Here, as the inorganic insulating layer 11, for example, SiN is formed by a CVD method. x The inorganic insulating layer 11 is in contact with the protective insulating layer 5 between (in the gap between) the source electrode 8s and the drain electrode 8d.

[0127] The organic insulating layer 12 may be, for example, an organic insulating film (thickness: 1 to 3 μm, for example) made of a photosensitive resin material. Then, the organic insulating layer 12 is patterned to form an opening. Next, the inorganic insulating layer 11 is etched (dry etching) using the organic insulating layer 12 as a mask. Thus, a contact hole CH reaching the drain electrode 8 d is formed on the inorganic insulating layer 11 and the organic insulating layer 12.

[0128] Next, a transparent conductive film is formed on the organic insulating layer 12 and in the contact hole CH. As a material for the transparent electrode film, a metal oxide such as indium-tin oxide (ITO), indium-zinc oxide, ZnO, etc. can be used. Here, for example, an indium zinc oxide film (thickness: for example, about 100 nm) is formed as the transparent conductive film by a sputtering method.

[0129] Then, the transparent conductive film is patterned by, for example, wet etching to obtain the pixel electrode 13. The pixel electrode 13 is separately arranged for each pixel. Each pixel electrode 13 is in contact with the drain electrode 8d of the corresponding TFT in the contact hole. Although not shown in the figure, the source electrode 8s of the TFT 101 is electrically connected to the source bus line (not shown), and the gate electrode 2 is electrically connected to the gate bus line (not shown).

[0130] The semiconductor layer 4, the first contact layer Cs, and the second contact layer Cd may also be patterned in an island shape in the region where the TFT 101 is formed (TFT formation region). Alternatively, the semiconductor layer 4, the first contact layer Cs, and the second contact layer Cd may also extend to a region other than the region where the TFT 101 is formed (TFT formation region). For example, the semiconductor layer 4 may also extend in a manner overlapping with the source bus line connected to the source electrode 8s. The portion of the semiconductor layer 4 located in the TFT formation region may include the poly-Si region 4p, and the portion extending to the region other than the TFT formation region may also be the a-Si region 4a.

[0131] In addition, the method of crystallizing the active layer a-Si film 40 is not limited to the above-mentioned local laser annealing. Other well-known methods may be used to crystallize a part or all of the active layer a-Si film 40.

[0132] (Variation Example)

[0133] Figure 4 (a) is a schematic top view of the TFT 102 of the modification example 1 of this embodiment. Figure 4 (b) is a cross-sectional view of TFT 102 along line II-II'. Modification 1 is a channel-etched (CE) type polysilicon TFT. Figure 4 In, with Figure 1 The same components are marked with the same reference numerals. Figure 1 Description of the same structure as that of TFT101 shown.

[0134] In the TFT 102, no etching stopper layer ( Figure 1 The inorganic insulating layer 11 is between the source electrode 8s and the drain electrode 8d and is in direct contact with the channel region Rc of the semiconductor layer 4.

[0135] The first contact layer Cs and the second contact layer Cd have a first a-Si layer 71 and a stacked region 70 including N (here, three) double-layer structures S(1), S(2), and S(3). The bottom layer of the first contact layer Cs and the second contact layer Cd (the layer directly in contact with the first region Rs or the second region Rd) is the second a-Si layer 72(N) of the double-layer structure S(N). The second a-Si layer 72(N) may not be separated into the source side and the drain side, but may remain on the channel region Rc. According to such a structure, in the source / drain separation process, since the damage to the channel region Rc is reduced, the reduction in the reliability of the TFT 102 can be suppressed.

[0136] The second a-Si layer 72 (N) as the bottom layer may be an intrinsic amorphous silicon layer that does not substantially contain impurities imparting conductivity. Thus, the entire channel region Rc can be protected without causing conduction between the source and the drain.

[0137] TFT102 can be manufactured by the same method as TFT101. However, a protective insulating layer is not formed. In the source-drain separation process, the conductive film and the stacked film can be patterned under the condition that the lower part of the second a-Si layer 72 (N), which is the lowest layer of the stacked film, remains on the channel region 4s. In this case, the thickness p1 of the portion of the second a-Si layer 72 (N) located on the channel region Rc can also be smaller than the thickness p2 of the portion located on the first region Rs and the second region Rd. From the viewpoint that the second a-Si layer 72 (N) more reliably protects the channel region Rc (i.e., p1>0), the thickness of the second a-Si layer 72 (N) can be, for example, 10 nm or more.

[0138] Figure 5 1 is a cross-sectional view of TFT 103 of variant 2 of the present embodiment. Variant 2 is different from variant 1 in that the contact layer C has a fourth a-Si layer 74 as the bottom layer containing n-type impurities at a concentration of C4. By providing the fourth a-Si layer 74, an effect of reducing GIDL caused by 2DEG can be obtained. In addition, in variant 2, in the source / drain separation step, the fourth a-Si layer 74 is also separated into the source side and the drain side. At this time, etching (over-etching) is sometimes performed near the surface of the channel region Rc of the semiconductor layer 4.

[0139] <Examples and Comparative Examples>

[0140] The TFTs of the examples and comparative examples were evaluated for TFT characteristics.

[0141] The TFTs of Examples 1 to 4 and Comparative Examples are Figure 1101 shown in the figure. However, the structure of the contact layer C is different from each other. Table 1 shows the thickness of the semiconductor layer of each TFT, the laser irradiation conditions (energy density, pulse width, pulse number) of the semiconductor layer based on the laser annealing method, and the number of stacking layers N in the contact layer. In addition, the thickness of the entire contact layer is 120nm.

[0142] [Table 1]

[0143]

[0144]

[0145] Figure 6 (a) to (e) are schematic diagrams showing the stacked structures e1 to e4 and rl of the contact layer C in the TFTs of Examples 1 to 4 and Comparative Example, respectively.

[0146] The stacked structures e1 to e4 of the contact layer C in the embodiments 1 to 4 respectively include n ++ The first a-Si layer 71 (phosphorus concentration: 1×10 20 cm -3 ) and 1 to 4 double-layer structures S(n). Each double-layer structure S(n) is composed of a second a-Si layer 72 that is substantially free of phosphorus (phosphorus concentration: below the measurement limit) and n + The third a-Si layer 73 (phosphorus concentration: 5×10 18 cm -3 ) is formed. In Examples 1 and 2, the second a-Si layer 72 (1) and 72 (2) are the bottom layers. On the other hand, in Example 3, the second a-Si layer 72 (1) and 72 (2) are the bottom layers. + The fourth a-Si layer 74 (phosphorus concentration: 5×10 18 cm -3 ) as the bottom layer, in Example 4, there are n ++ The fourth a-Si layer 74 (phosphorus concentration: 1×10 20 cm -3 ) as the bottom layer.

[0147] On the other hand, the stacked structure r1 of the contact layer C in the comparative example includes n ++ a-Si layer 171 (phosphorus concentration: 1×10 20 cm -3 , thickness: 15nm) and an i-type a-Si layer 172 (thickness: 105nm) that is substantially free of phosphorus (phosphorus concentration: below the measurement limit). The i-type a-Si layer 172 is the bottom layer. ++ A double-layer structure S(n) (N=0) is not formed below the a-Si layer 171 .

[0148] The methods for making TFTs of Examples 1 to 4 and Comparative Examples are as follows: Figure 3 The contact layer C of each TFT is formed by CVD method. At this time, by adjusting the flow ratio of the raw material gas, a stacked structure of multiple a-Si layers with different phosphorus concentrations is formed.

[0149] As an example, Table 2 shows the formation conditions of each a-Si layer included in the stacked structure e4 of the contact layer C in Example 4. The "deposition time" in Table 2 is the supply time (seconds) of the raw material gas, and the "stabilization time" is the time (seconds) when the supply of the raw material gas is stopped after the formation of the layer until the deposition of the next layer begins. Here, each time an a-Si layer is formed, the supply of the raw material gas is temporarily stopped (i.e., the stabilization time>0 (seconds)). In addition, the spacing between the electrodes is 700 (mils).

[0150] [Table 2]

[0151]

[0152]

[0153] Figure 7 This is a cross-sectional SEM image of the contact layer in the TFT of Example 4.

[0154] Figure 8 It represents Example 1 4 is a graph showing the VI (gate voltage Vgs-drain current Id) characteristics of the TFTs of the examples and comparative examples. In addition, the mobility and the minimum value of the off-state current of the TFTs of the examples and comparative examples are also shown in Table 1.

[0155] Depend on Figure 8 It can be seen that in the TFTs of Examples 1 to 4, GIDL is improved and the cut-off current Ioff is lowered compared to the TFTs of the comparative examples. The cut-off current Ioff is dominated by GIDL, and the high electric field in the overlapping area of ​​the gate and the drain causes the tunneling current between the energy bands to flow, thereby generating the cut-off current Ioff. In the TFTs of Examples 1 to 4, it is believed that the depletion layer formed in the contact layer C becomes thicker, thereby reducing the tunneling current between the energy bands, resulting in a reduction in the cut-off current Ioff. In addition, it was confirmed that the more the number N of double-layer structures S(n) contained in the contact layer C increases, the more Vth drifts in the positive direction, and the lower the cut-off current Ioff. This is believed to be because the more the number N of double-layer structures S(n) increases, the more the number of depletion layers formed increases, and the greater the total thickness of the depletion layer, the further the tunneling current between the energy bands decreases.

[0156] Further, in setting n + Type or n ++In the TFTs of Examples 3 and 4, the fourth a-Si layer 74 of the type is used as the bottom layer of the contact layer C. In particular, the cut-off current (GIDL) when the gate voltage Vgs is close to the threshold voltage is greatly improved, and as a result, the rise of the VI characteristic becomes steeper. This is because, by setting the fourth a-Si layer 74, it is difficult to generate a 2DEG region at the junction of the contact layer C and the semiconductor layer 4, and the high electric field caused by the 2DEG in the overlapping region is reduced, and the GIDL is reduced. In particular, when a high concentration (n ++ When the fourth a-Si layer 74 of the a-Si type is formed, the GIDL can be more effectively reduced.

[0157] <Measurement of resistivity ρ>

[0158] The resistivities ρ1 to ρ4 of the a-Si layers 71 to 74 in the contact layer C of Example 4 were measured by the following method.

[0159] Amorphous silicon films (thickness: 200 to 300 nm) containing n-type impurities were prepared as samples a1 to a4. Samples a1 to a4 were formed under the same conditions as the a-Si layers 71 to 74 in Example 4, respectively, so that they contained n-type impurities at approximately the same concentration as the a-Si layers 71 to 74. The resistivities ρ(a1) to ρ(a4) of samples a1 to a4 were approximately the same as the resistivities ρ1 to ρ4 of the a-Si layers 71 to 74 in Example 4.

[0160] For samples a1 to a4, the resistivity ρ(a1) to ρ(a4) was measured using the 4-terminal resistance measurement method. The resistivity ρ(a1) and ρ(a4) of samples a1 and a4 were both 31.9Ω·cm, and the resistivity ρ(a3) of sample a3 was 1370Ω·cm. In addition, the resistivity ρ(a2) of sample a2 exceeded the measurement limit, exceeding 1×10 5 Ω·cm. From this result, it can be confirmed that the resistivity ρ1 and ρ4 of the first a-Si layer 71 and the fourth a-Si layer 74 are 31.9Ω·cm, the resistivity ρ3 of the third a-Si layer 73 is 1370Ω·cm, and the resistivity ρ2 of the second a-Si layer 72 exceeds 1×10 5 Ω·cm, becomes ρ2(n)>ρ3(n)>ρ1, ρ4.

[0161] <Concentration profile of n-type impurity in the depth direction of the contact layer>

[0162] Next, the concentration distribution of the n-type impurity in the depth direction of the contact layer in this embodiment is described by taking the TFT of Example 4 as an example. The concentration distribution in the depth direction can be measured by secondary ion mass spectrometry (SIMS), for example.

[0163] Fig. 9It is a diagram schematically showing the concentration distribution of n-type impurities (phosphorus in this case) in the depth direction of the contact layer of the TFT of Example 4. The "depth direction" refers to the direction from the source electrode or the drain electrode toward the semiconductor layer.

[0164] The concentration distribution includes a contact region (also referred to as the "upper contact region") 61 where the concentration of phosphorus is R1 or more and is arranged in contact with the source / drain electrodes, and a concentration modulation region 60 located between the contact region 61 and the active layer ( Figure 1 the semiconductor layer 4 shown). On the semiconductor layer 4 side of the concentration modulation region 60, a contact region ("lower contact region") 64 may further be included in contact with the semiconductor layer 4.

[0165] The contact region 61 corresponds to the first a-Si layer 71. The concentration R1 is greater than C3 and less than or equal to C1 (C3 < R1 ≤ C1), for example, 4.5×10 19 atoms / cm 3 .

[0166] The concentration modulation region 60 is a region where the concentration distribution of n-type impurities changes in the depth direction and corresponds to a stacked region 70 including N bilayer structures S(n). The concentration modulation region 60 has a first inclined region 62 and a second inclined region 63. The first inclined region 62 includes a portion where the concentration of n-type impurities in the depth direction decreases from R3 to R2 within a range of 20 nm, and the second inclined region 63 includes a portion where the concentration of n-type impurities in the depth direction increases from R2 to R3 within a range of 20 nm. The magnitude relationship between the concentrations R2 and R3 is R2 < R3 < R1. As an example, the concentration R2 is C2 or more and less than C3 (C2 ≤ R2 < C3), for example, 1.5×10 17 atoms / cm 3 . The concentration R3 is greater than C2 and less than or equal to C3 (C2 < R3 ≤ C3), for example, 4.5×10 17 atoms / cm 3 . The concentration modulation region 60 may also alternately have two or more first inclined regions 62 and second inclined regions 63 respectively. The first inclined region 62 is a part of the region where the concentration decreases from the maximum value to the minimum value, and the second inclined region 63 is a part of the region where the concentration increases from the minimum value to the maximum value.

[0167] The contact region 64 corresponds to the fourth a-Si layer 74. The contact region 64 is, for example, a region where the concentration is R4 or more. The concentration R4 can be greater than C2 (C2 < R4), preferably greater than C3. The concentration R4 can be less than or equal to C4, as shown in the figure, or R4 = R1.

[0168] The low concentration region (at the semiconductor layer 4 side of each first inclined region 62) with a substantially constant concentration Fig. 9 The regions (in which noise appears due to the measurement limit of SIMS) correspond to the second a-Si layer 72, and the high-concentration regions with a substantially constant concentration located on the electrode side of the first inclined region 62 correspond to the third a-Si layer 73.

[0169] The concentration modulation region 60 is a region where a depletion layer can be formed. In the first inclined region 62, the n-type impurity concentration can be reduced by more than two orders of magnitude. Similarly, in the second inclined region 63, the n-type impurity concentration can also be increased by more than two orders of magnitude. Since a depletion layer is formed in each first inclined region 62, by including more than two first inclined regions 62, more than two depletion layers are formed, and the total thickness of the depletion layer can be increased.

[0170] In this embodiment, the contact layer C has Fig. 9 The concentration distribution described above is sufficient, and its formation method (formation conditions) is not limited to the method shown in Table 2.

[0171] The entire contact layer C or a portion of the contact layer C (e.g., the concentration modulation region 60) may be continuously formed by the CVD method. In this case, by switching the flow rate ratio of the impurity-containing gas (gas containing n-type impurities, such as PH3) contained in the raw material gas at a predetermined time (including the case where the flow rate of the impurity-containing gas is set to zero), the contact layer C having a desired concentration distribution in the thickness direction can be formed.

[0172] For example, after forming the fourth a-Si layer 74 on the semiconductor layer 4, the supply of the raw material gas may be temporarily stopped, and then, while changing the ratio of the impurity-containing gas to the raw material gas, N double-layer structures S(n) (corresponding to the concentration modulation region 60) may be continuously formed. After that, the first a-Si layer 71 may be formed separately during the suspension time (stabilization time) of the raw material gas. Alternatively, N double-layer structures S(n) and the first a-Si layer 71 may be continuously formed on the fourth a-Si layer 74.

[0173] Hereinafter, a method of continuously forming the contact layer C (a stacked film forming the contact layer C) by CVD will be described, taking the contact layer C of the TFT of Example 4 as an example.

[0174] Table 3 shows the formation conditions of the contact layer C. The thickness of each a-Si layer is standard. In this example, after forming the fourth a-Si layer 74, the double-layer structure S(1) to S(4) and the first a-Si layer 71 are formed continuously. That is, the stabilization time (3 seconds) is set only before forming the second a-Si layer 72(4) after forming the fourth a-Si layer 74, and the stabilization time is not set after forming the other a-Si layers. The distance between electrodes is set to 700 (mils).

[0175] [Table 3]

[0176]

[0177]

[0178] In the continuous forming method, it is also possible to obtain Fig. 9 The contact layer C of the concentration distribution described above. In addition, when the concentration modulation region 60 including N double-layer structures S(n) is continuously formed, the concentration distribution of the concentration modulation region 60 becomes smoother (passive) compared to the case where the supply of the raw material gas is temporarily stopped each time an a-Si layer is formed. For example, the inclined regions 62 and 63 become thicker (the concentration gradient is gentle). In addition, the concentration distribution of the region between the inclined regions 62 and 63 becomes uneven.

[0179] The TFT of this embodiment can be any bottom-gate TFT including the contact layer C having the above-mentioned stacked structure or concentration distribution, and its structure is not limited to Figure 1 Figure 5 The illustrated structure. In addition, the TFT of this embodiment is not limited to a polycrystalline silicon TFT. As the active layer (semiconductor layer 4), it can be an amorphous silicon TFT using an amorphous silicon layer, or it can be a microcrystalline silicon TFT using a microcrystalline silicon layer. In addition, it can also be an oxide semiconductor TFT using an oxide semiconductor layer. The oxide semiconductor can be amorphous or crystalline. The crystalline oxide semiconductor can be, for example, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, a crystalline oxide semiconductor whose c-axis is oriented in a manner substantially perpendicular to the layer surface, etc. The materials, structures, film forming methods, etc. of amorphous or crystalline oxide semiconductors are described, for example, in Japanese Patent Gazette No. 6275294. For reference, the entire disclosure of Japanese Patent No. 6275294 is cited in this specification.

[0180] The TFT of this embodiment can be preferably used in an active matrix substrate of a display device, etc., for example. The active matrix substrate (or display device) has a display area including a plurality of pixels and a non-display area (also referred to as a peripheral area) outside the display area. A pixel TFT is provided in each pixel as a switching element. In the peripheral area, a driving circuit such as a gate driver can also be formed as a single chip. The driving circuit includes a plurality of TFTs (referred to as "circuit TFTs"). The TFT of this embodiment can be used as a pixel TFT and / or a circuit TFT.

[0181] The active matrix substrate is suitable for a liquid crystal display device. For example, a counter substrate provided with a counter electrode and a color filter layer is prepared, the active matrix substrate and the counter substrate are bonded together via a sealing material, and liquid crystal is injected between these substrates to obtain a liquid crystal display device.

[0182] In addition, not limited to liquid crystal display devices, various display devices can be obtained by using a material whose optical properties can be modulated or which can emit light according to an applied voltage as a display medium layer. For example, the active matrix substrate of this embodiment is also applicable to display devices such as organic EL display devices or inorganic EL display devices that use organic or inorganic fluorescent materials as display medium layers. Furthermore, it is also applicable to active matrix substrates used as X-ray sensors, storage elements, etc.

[0183] Industrial Applicability

[0184] The embodiments of the present invention can be widely applied to devices and electronic devices equipped with TFTs. For example, they can be applied to circuit substrates such as active matrix substrates, display devices such as liquid crystal display devices, organic electroluminescent element (EL) display devices, and inorganic electroluminescent display devices, imaging devices such as radiation detectors and image sensors, and electronic devices such as image input devices and fingerprint readers.

[0185] Description of Reference Numerals

[0186] 1: substrate, 2: gate, 3: gate insulating layer, 4: semiconductor layer, 4a: a-Si region, 4p: poly-Si region, 5: protective insulating layer, 6: i-type a-Si layer, 7: n +type a-Si layer, 8d: drain, 8s: source, 9: 2DEG region, 10: i-type a-Si island, 11: inorganic insulating layer, 12: organic insulating layer, 13: pixel electrode, 30: laser, 40: a-Si film for active layer, 50: insulating film, 60: concentration modulation region, 61: contact region (upper contact region), 62: first inclined region, 63: second inclined region, 64: contact region (lower contact region), 70: stacked region, 71: first amorphous silicon layer (first a-Si layer), 72(1), 72(2), 72( 3), 72(N): second amorphous silicon layer (second a-Si layer), 73(1), 73(2), 73(3), 73(N): third amorphous silicon layer (third a-Si layer), 80: conductive layer, 700: stacked film, Cs: first contact layer, Cd: second contact layer, D(1), D(2), D(3), D0: depletion layer, e1, e2, e3, e4, r1: stacked structure, M: resist mask, Rc: channel region, Rd: second region, Rs: first region, S(1), S(2), S(3), S(N): double-layer structure

Claims

1. A thin film transistor, characterized in that , comprising: a substrate; a gate electrode, supported by the substrate; a gate insulating layer, covering the gate electrode; a semiconductor layer, which is a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including: a first region, a second region, and a channel region located between the first region and the second region; a first contact layer, disposed on the first region of the semiconductor layer; a second contact layer, disposed on the second region of the semiconductor layer; a source electrode, disposed on the first contact layer and electrically connected to the first region via the first contact layer; a drain electrode, disposed on the second contact layer and electrically connected to the second region via the second contact layer, the first contact layer and the second contact layer each have a stacked structure, the stacked structure includes: a first amorphous silicon layer, which is in direct contact with the source electrode or the drain electrode; N bilayer structures S(n), where N is an integer of 3 or more, and n is an integer of 1 or more and N or less, the N bilayer structures S(n) are each composed of a second amorphous silicon layer and a third amorphous silicon layer in direct contact with the upper surface of the second amorphous silicon layer; and a fourth amorphous silicon layer, which is in direct contact with the first region or the second region of the semiconductor layer, when the concentration of the n-type impurity contained in the second amorphous silicon layer of the bilayer structure S(n) is set as C2(n), the concentration of the n-type impurity contained in the third amorphous silicon layer is set as C3(n), and the concentration of the n-type impurity contained in the first amorphous silicon layer is set as C1, for any n, the relationship C2(n) < C3(n) < C1 is satisfied, the concentration C4 of the n-type impurity contained in the fourth amorphous silicon layer satisfies the relationship C3(n) < C4 for any n.

2. The thin film transistor according to claim 1, characterized in that: The N is 5 or more.

3. The thin film transistor according to claim 1 or 2, characterized in that the thicknesses of the second amorphous silicon layer and the third amorphous silicon layer in the bilayer structure S(n) are each 20 nm or less.

4. The thin film transistor according to claim 1 or 2, characterized in that The resistivity ρ1 of the first amorphous silicon layer is less than 300 Ω·cm, and the resistivity ρ2 of the second amorphous silicon layer is less than 1×10 5 Ω·cm or more, and the resistivity ρ3 of the third amorphous silicon layer is greater than 500Ω·cm and less than 90000Ω·cm.

5. The thin film transistor according to claim 1 or 2, characterized in that The concentration C1 is 5×10 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 the following.

6. The thin film transistor according to claim 1 or 2, characterized in that The concentration C3(n) is 1.2×10 17 atoms / cm 3 Above and 4×10 19 atoms / cm 3 the following, The concentration C2(n) is greater than 0 and 1.2×10 17 atoms / cm 3 the following.

7. The thin film transistor according to claim 1 or 2, characterized in that the semiconductor layer has a polycrystalline silicon region, and the polycrystalline silicon region includes the first region, the second region, and the channel region.

8. The thin film transistor according to claim 1 or 2, characterized in that , The concentration C4 is 5×10 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 the following.

9. The thin film transistor according to claim 7, characterized in that , When viewed from the normal direction of the substrate, the semiconductor layer further includes an amorphous silicon region disposed outside the polycrystalline silicon region.

10. A thin film transistor, characterized in that , comprising: a substrate; a gate electrode, supported by the substrate; a gate insulating layer, covering the gate electrode; a semiconductor layer, which is a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including: a first region, a second region, and a channel region located between the first region and the second region; a first contact layer, disposed on the first region of the semiconductor layer; a second contact layer, disposed on the second region of the semiconductor layer; A source electrode, disposed on the first contact layer, is electrically connected to the first region via the first contact layer; A drain electrode, disposed on the second contact layer, is electrically connected to the second region via the second contact layer, The first contact layer and the second contact layer are respectively amorphous silicon layers containing n-type impurities, The amorphous silicon layer has: An upper contact region, which contacts the source electrode or the drain electrode, and the concentration of the n-type impurity is R1 or more; A concentration modulation region, which is located between the upper contact region and the semiconductor layer, and the concentration distribution of the n-type impurity in the depth direction from the source electrode or the drain electrode toward the semiconductor layer changes; and A lower contact region, which directly contacts the first region or the second region of the semiconductor layer, and the concentration of the n-type impurity in the lower contact region is R4 or more, The concentration modulation region alternately has two or more first inclined regions and second inclined regions. The first inclined region includes a portion where the concentration in the depth direction decreases from R3 to R2 within a range of 20 nm, and the second inclined region includes a portion where the concentration in the depth direction increases from R2 to R3 within a range of 20 nm, The concentrations R1, R2, and R3 satisfy the relationship of R2 < R3 < R1, The concentrations R3 and R4 satisfy the relationship of R3 < R4.

11. The thin film transistor according to claim 10, characterized in that: In the first inclined region, the concentration decreases by two or more orders of magnitude.

12. The thin film transistor according to claim 10 or 11, wherein, The concentration R1 is 4.5×10 19 atoms / cm 3 , the concentration R2 is 1.5×10 17 atoms / cm 3 , the concentration R3 is 4.5×10 17 atoms / cm 3 .

13. The thin film transistor according to claim 10 or 11, wherein, The semiconductor layer has a polycrystalline silicon region, and the polycrystalline silicon region includes the first region, the second region, and the channel region.

14. A thin film transistor, characterized in that , comprising: A substrate; A gate electrode, supported by the substrate; A gate insulating layer, covering the gate electrode; A semiconductor layer, which is a semiconductor layer disposed on the gate insulating layer, and the semiconductor layer includes: a first region, a second region, and a channel region located between the first region and the second region; A first contact layer, disposed on the first region of the semiconductor layer; A second contact layer, disposed on the second region of the semiconductor layer; A source electrode, disposed on the first contact layer, is electrically connected to the first region via the first contact layer; A drain electrode, disposed on the second contact layer, is electrically connected to the second region via the second contact layer, The first contact layer and the second contact layer respectively have a stacked structure, The stacked structure includes: a first amorphous silicon layer, which directly contacts the source electrode or the drain electrode; N double-layer structures S(n), where N is an integer of 3 or more, and n is an integer of 1 or more and N or less. The N double-layer structures S(n) are respectively composed of a second amorphous silicon layer and a third amorphous silicon layer that directly contacts the upper surface of the second amorphous silicon layer; and A fourth amorphous silicon layer, which directly contacts the first region or the second region of the semiconductor layer, When the resistivity of the second amorphous silicon layer of the double-layer structure S(n) is set to ρ2(n), the resistivity of the third amorphous silicon layer is set to ρ3(n), and the resistivity of the first amorphous silicon layer is set to ρ1, for any n, the relationship ρ2(n)>ρ3(n)>ρ1 is satisfied. When the resistivity of the fourth amorphous silicon layer is ρ4, for any n, the relationship ρ3(n)>ρ4 is satisfied.

15. The thin film transistor according to claim 14, characterized in that , the resistivity ρ1 is less than 300Ω·cm, and the resistivity ρ2 is 1×10 5 Ω·cm or more, and the resistivity ρ3 is 500Ω·cm or more and less than 90000Ω·cm.

16. The thin film transistor according to claim 14 or 15, characterized in that: The semiconductor layer has a polysilicon region, and the polysilicon region includes the first region, the second region, and the channel region.

17. The thin film transistor according to any one of claims 1, 2, 10, 11, 14 and 15, characterized in that: The thin film transistor is an etch stop type, A protective insulating layer covering the channel region of the semiconductor layer is also provided, wherein a portion of the protective insulating layer is located between the semiconductor layer and the first contact layer, and another portion of the protective insulating layer is located between the semiconductor layer and the second contact layer.

18. The thin film transistor according to any one of claims 1, 2, 10, 11, 14 and 15, characterized in that: The thin film transistor is a channel etch type, It also includes an upper insulating layer, which covers the semiconductor layer, the source electrode and the drain electrode of the thin film transistor, The upper insulating layer is in direct contact with the channel region of the semiconductor layer.

19. A display device, characterized in that ,include: A thin film transistor according to any one of claims 1 to 18; and A display area having a plurality of pixels; The thin film transistor is disposed in each of the plurality of pixels.

20. A method for manufacturing a thin film transistor, the method for manufacturing a thin film transistor according to any one of claims 1 to 9, comprising: Step (A), forming the gate, the gate insulating layer and the semiconductor layer on the substrate; Step (B), which is a step of forming a stacked film including the N double-layer structures S(n) on the semiconductor layer, wherein N is an integer greater than 1, and n is an integer greater than 1 and less than N, and the step (B) includes: step (B1), which forms a fourth amorphous silicon film containing n-type impurities at the concentration C4 so that the fourth amorphous silicon film is in contact with the semiconductor layer; step (B2), after the step (B1), a step of forming the N double-layer structures S(n), wherein each layer of the double-layer structure S(n) is formed by stacking a second amorphous silicon film and a third amorphous silicon film in the following order, wherein the second amorphous silicon film contains n-type impurities at the concentration C2(n), and the third amorphous silicon film is directly in contact with the upper surface of the second amorphous silicon film and contains n-type impurities at the concentration C3(n); step (B3), after the step (B2), forming a first amorphous silicon film containing n-type impurities at the concentration C1; Step (C), forming a conductive film on the stacked film in direct contact with the first amorphous silicon film; In step (D), the conductive film and the stacked film are patterned to form the source electrode and the drain electrode from the conductive film, and to form the first contact layer and the second contact layer from the stacked film.

21. The manufacturing method according to claim 20, characterized in that: The semiconductor layer includes a polysilicon region, In the step (B), the fourth amorphous silicon film is formed in contact with the polycrystalline silicon region.

22. A method for manufacturing a thin film transistor, which is the method for manufacturing a thin film transistor according to any one of claims 10 to 13, characterized in that: include: Step (A), forming the gate, the gate insulating layer and the semiconductor layer on the substrate; Step (B) is a step of forming an amorphous silicon film including the lower contact region, the concentration modulation region and the upper contact region on the semiconductor layer by a CVD method using an impurity-containing gas and a raw material gas containing the n-type impurity, wherein the amorphous silicon film is continuously formed by changing the ratio of the impurity-containing gas to the raw material gas and controlling the concentration of the n-type impurity in the depth direction; Step (C), forming a conductive film on the amorphous silicon film; In step (D), the conductive film and the amorphous silicon film are patterned to form the source and the drain from the conductive film, and to form the first contact layer and the second contact layer from the amorphous silicon film.

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