Non-conformal capping layer and method for forming the same

Abstract

This application discloses a non-conformal capping layer and a method for forming the same. The method includes forming a protruding structure; and forming a non-conformal film on the protruding structure using an atomic layer deposition (ALD) process. The non-conformal film includes a top portion directly above the protruding structure and a sidewall portion on a sidewall of the protruding structure. The top portion has a first thickness, and the sidewall portion has a second thickness that is less than the first thickness.

Description

Technical Field

[0001] The present disclosure generally relates to Non-conformal capping layer and method for forming the same. Background Art

[0002] Transistors are fundamental building blocks in integrated circuits. In previous developments of integrated circuits, fin field-effect transistors (FinFETs) have been developed to replace planar transistors. In the formation of a FinFET, a semiconductor fin is formed, and a dummy gate is formed on the semiconductor fin. The formation of the dummy gate may include depositing a dummy layer, such as a polysilicon layer, and then patterning the dummy layer into a dummy gate. Gate spacers are formed on the sidewalls of the dummy gate stack. The dummy gate stack is then removed to form a trench between the gate spacers. A replacement gate is then formed in the trench. Summary of the Invention

[0003] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a protruding structure; and forming a non-conformal film on the protruding structure using an atomic layer deposition (ALD) process, wherein the non-conformal film comprises: a top portion located directly above the protruding structure, wherein the top portion has a first thickness; and; a sidewall portion located on a sidewall of the protruding structure, wherein the sidewall portion has a second thickness less than the first thickness.

[0004] According to another aspect of the present disclosure, an integrated circuit structure is provided, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding above a top surface of the isolation region, wherein the isolation region is on opposite sides of the semiconductor fin; a dielectric layer on the top surface and sidewalls of the semiconductor fin; and a cap layer including a first portion directly above the semiconductor fin, wherein the cap layer comprises: a top portion overlying the dielectric layer, wherein the top portion has a first thickness; and a sidewall portion on the sidewalls of the top portion of the semiconductor fin, wherein the sidewall portion has a second thickness less than the first thickness.

[0005] According to yet another aspect of the present disclosure, an integrated circuit structure is provided, comprising: a protruding structure protruding above features on opposite sides of the protruding structure, wherein the protruding structure includes a top surface and sidewall surfaces; a dielectric capping layer having a top portion directly above the protruding structure, wherein the top portion of the dielectric capping layer has a uniform thickness, and wherein at least a bottom portion of the sidewall surface of the protruding structure has no dielectric capping layer formed thereon; and additional features in contact with: the top portion of the dielectric capping layer; and a lower portion of the sidewall surface of the protruding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1-3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8-10 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13 、 Figure 14A 、 Figure 14B and Figure 15 Perspective and cross-sectional views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET), according to some embodiments.

[0008] Figure 16 Example intermediate chemical structures in the formation of a non-conformal capping layer according to some embodiments are shown.

[0009] Figure 17 A diagram illustrating an atomic layer deposition (ALD) cycle for forming a non-conformal capping layer, according to some embodiments.

[0010] Figure 18A and Figure 18B A diagram illustrating an oxidation process for forming a non-conformal capping layer, according to some embodiments.

[0011] Figure 19 A process flow for forming a FinFET is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] According to some embodiments, a non-conformal cap layer and a method for forming the same are provided. According to some embodiments, intermediate stages of forming a non-conformal cap layer and using the non-conformal cap layer to form a fin field effect transistor (FinFET) are shown. Some variations of some embodiments are discussed. The embodiments may also be applied to other embodiments in which a non-conformal layer is to be formed, which formation may or may not be in a FinFET process. The embodiments discussed herein will provide examples to enable implementation or use of the subject matter of the present disclosure, and a person of ordinary skill in the art will readily understand the modifications that may be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figure 1-3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8-10 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13 、 Figure 14A 、 Figure 14B and Figure 15 The perspective view and cross-sectional view of the intermediate stages in the formation of FinFET according to some embodiments of the present disclosure are shown. The corresponding process is also schematically reflected in Figure 19 The process flow shown.

[0016] exist Figure 1 In the embodiment of the present invention, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, for example, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (for example, with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10, for example, a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, for example, a multi-layer substrate or a gradient substrate. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0017] Further references Figure 1 , forming a well region 22 in the substrate 20. The corresponding process is Figure 19 The process flow 400 is shown as process 402. According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (such as boron, indium, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities (such as phosphorus, arsenic, antimony, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 within the range between.

[0018] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. Figure 19The process flow 400 shown is shown as process 404. The portion of the substrate 20 between adjacent STI regions 24 is called a semiconductor strip 26. In order to form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 can be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon, or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to form a hard mask layer 30 as shown in FIG. Figure 2 A hard mask 30 is shown.

[0019] Next, patterned hard mask layer 30 is used as an etch mask to etch pad oxide layer 28 and substrate 20, and the resulting trenches in substrate 20 are then filled with dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material(s) are STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, or the like formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI regions 24 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material above the liner dielectric may include silicon oxide.

[0020] The top surface of hard mask 30 and the top surface of STI regions 24 may be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are portions of original substrate 20, and thus are made of the same material as substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are replacement strips formed by etching portions of substrate 20 between STI regions 24 to form recesses, and performing epitaxy to re-grow another semiconductor material in the recesses. Thus, semiconductor strips 26 are formed of a different semiconductor material than substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0021] refer to Figure 3 , STI region 24 is recessed. Therefore, the top of semiconductor strip 26 protrudes higher than top surface 24A of the rest of STI region 24 to form protruding fin 36. Figure 19 This is shown as process 406 in the illustrated process flow 400. This etching can be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. During the etching process, a plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, recessing of the STI regions 24 is performed using a wet etching process. The etching chemical may include, for example, HF.

[0022] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-aligned process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0023] Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 6A 、 Figure 6B 、 Figure 7A and Figure 7B 4 shows the formation of a dummy gate stack 45 according to some embodiments. Figure 4A , forming a dummy dielectric layer 38. The corresponding process is Figure 19This is shown as process 408 in the illustrated process flow 400. According to some embodiments of the present disclosure, dummy dielectric layer 38 is formed using a conformal deposition process, which may include atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like. The material of dielectric layer 38 may include silicon oxide, silicon nitride, silicon carbonitride, or the like. When using a conformal deposition process, the horizontal thickness of the horizontal portion and the vertical thickness of the vertical portion of dielectric layer 38 are equal to or substantially equal to each other, for example, differing by less than approximately 20% of the horizontal thickness. According to some embodiments, the thickness T1 of dielectric layer 38 is within a range between approximately 1 nm and approximately 10 nm. According to alternative embodiments, dielectric layer 38 is formed by oxidizing (e.g., using a thermal oxidation process) the surface portions of the protruding fins 36. The resulting dielectric layer 38 will be formed on the exposed surfaces of the protruding fins 36, but not on the top surfaces of the STI regions 24. Therefore, the dashed lines are used to indicate that some portions of dielectric layer 38 may or may not be formed on top of the STI regions 24, depending on the formation process. Figure 4B Shown as Figure 4A Reference section 4B-4B is shown.

[0024] Figure 5A FIG. 4 shows the formation of a non-conformal capping layer 40 according to some embodiments of the present disclosure. Figure 19 The process flow 400 is shown as process 410. Figure 5A As shown, non-conformal capping layer 40 is formed on dielectric layer 38 and excludes the horizontal portion directly above STI regions 24 .

[0025] Figure 5B 、 Figure 5C and Figure 5D Shown as Figure 5A As shown in the reference cross section 5B / 5C / 5D-5B / 5C / 5D, the bottom of the non-conformal capping layer 40 is at Figure 5B 、 Figure 5C and Figure 5D At different levels. Figure 5B 、 Figure 5C and Figure 5D As shown, the non-conformal capping layer 40 has a top portion 40A located directly above the protruding fin 36, and the thickness of the top portion is indicated as T2. The top portion 40A has a uniform thickness. For example, the thicknesses T2A, T2B, and T2C can be the same and vary by less than about 5% or less. The non-conformal capping layer 40 may or may not include a sidewall portion 40B on the sidewall of the protruding fin 36, which, if present, contacts the sidewall portion of the dielectric layer 38. For example, Figure 5B Sidewall portion 40B is shown extending to the bottom of protruding fin 36 . Figure 5CThe bottom end of the non-conformal capping layer 40 is shown to be at approximately the same level as the top surface of the protruding fin 36 , meaning that the sidewall portion of the non-conformal capping layer 40 is substantially absent. Figure 5D The bottom end of the non-conformal capping layer 40 is shown extending lower than the top surface of the protruding fin 36. The bottom end of the portion 40B may be located at any level between the top and bottom surfaces of the protruding fin 36. For example, the bottom end of the portion 40B may be between the top surface and an intermediate height of the protruding fin 36.

[0026] The thickness of the sidewall portion of the non-conformal capping layer 40 is Figure 5B According to some embodiments of the present disclosure, the thickness T3 is measured at the middle height of the protruding fin 36, which is between the top surface and the bottom of the protruding fin 36. According to some embodiments of the present disclosure, the thickness T2 is about peace treaty The thickness T3 is within the range of peace treaty In the range between The thickness of means that the non-conformal cap layer 40 does not extend to this intermediate height. It can be understood that when the thickness T3 (at the intermediate height of the fin 36) is , the non-conformal capping layer 40 may still extend to the sidewalls of the top portion of the protruding fin 36 (e.g. Figure 5D As shown in FIG. 3 , for example, it extends to the upper 25% of the protruding fin 36. However, the thickness of the sidewall portion 40B of the non-conformal cap layer 40 gradually decreases from top to bottom (and may decrease continuously), and eventually decreases to

[0027] The average thickness of the sidewall portion 40B of the non-conformal capping layer 40 can be expressed as T Side-Avg , and the average thickness of the top portion of the non-conformal capping layer 40 can be expressed as T Top-Avg Throughout this specification, average thickness may be determined by selecting a plurality (e.g., 5 or more) of equally spaced locations, measuring the thickness at these locations, and then calculating the average of these thicknesses. For example, Figure 5B 、 Figure 5C and Figure 5D Three equidistant positions are shown as examples, which may be used to determine T Top-Avg candidate locations. Figure 5C and Figure 5D Some equidistant positions are also shown as examples, which may be used to determine T side-Avg According to some embodiments of the present disclosure, the ratio T Side-Avg / T Top-AvgThe ratio T1-B / T1-T may be less than about 0.2 and may be in a range between about 0.05 and about 0.2. In comparison, for conformal dielectric layer 38, if the bottom portion of the sidewall portion of the dielectric layer is denoted as T1-B and the top portion of the sidewall portion of the dielectric layer is denoted as T1-T, then according to some embodiments of the present disclosure, the ratio T1-B / T1-T may be in a range between about 0.9 and about 1.0.

[0028] Figure 17 A cycle of a non-conformal ALD process for depositing a non-conformal capping layer 40 is schematically illustrated, in accordance with some embodiments. Figure 17 Three curves, A, B, and C, are included, respectively, including a precursor curve over time, a purge gas curve over time, and a plasma curve over time. The time (horizontal axis) of the precursor curve, the purge gas curve, and the plasma curve are aligned. For curve A, when the corresponding Y-axis value equals zero, it indicates that the precursor conduction has stopped. For curve B, when the corresponding Y-axis value equals zero, it indicates that the purge gas conduction has stopped. For curve C, when the corresponding Y-axis value equals zero, it indicates that the plasma generation has stopped. In the following example, the order of precursor conduction, purge gas conduction, and plasma generation will be briefly discussed.

[0029] refer to Figure 17 At time point TP1, a purge gas (curve B) is introduced into the reaction chamber. The reaction chamber is a vacuum chamber that can be evacuated and can be used to perform an ALD process. The purge gas has the function of purifying the precursor in the corresponding reaction chamber. In addition, the purge gas is used to generate plasma, which will be adsorbed on the Figure 4A and Figure 4BThe precursor on the wafer 10 shown provides energy. According to some embodiments, the purge gas includes an inert gas, which may include argon, helium, etc., or a combination thereof. The purge gas may or may not include another gas, which may have a high recombination rate (as will be discussed in detail in subsequent paragraphs), and the gas is referred to as a high recombination gas hereinafter. According to some embodiments of the present disclosure, the high recombination gas included in the purge gas may include hydrogen (H2), nitrogen (N2), or a combination thereof. Adding nitrogen can also increase the nitrogen atomic percentage in the resulting non-conformal cap layer 40. The purge gas can be continuously introduced into the reaction chamber throughout the non-conformal deposition process and simultaneously pumped out of the reaction chamber. According to some embodiments of the present disclosure, the total flow rate of the purge gas is in the range between about 50 sccm and about 6 SLM. The pressure in the reaction chamber can be in the range between about 1000 mTorr and about 8000 mTorr. The flow rate of the inert gas may be in a range between about 25 sccm and about 6 SLM, and the flow rate of the high reforming gas may be in a range between about 0 sccm and about 6 SLM, and may be in a range between about 0 sccm and about 25 sccm, or in a range between about 25 sccm and about 6 SLM. During the deposition process, the temperature of the wafer is in a range between about 50° C. and about 500° C.

[0030] According to some embodiments, the purge gas includes argon or helium and does not contain oxygen (O2). This is different from conventional PEALD because in conventional PEALD for forming oxygen-containing dielectrics, oxygen (O2) is used together with argon, and the argon decomposes the oxygen into oxygen radicals. However, in embodiments of the present disclosure, no oxygen is added, and the oxygen in the resulting non-conformal cap layer 40 is provided entirely by the precursor. The purge gas may not contain nitrogen (N2), or may include some nitrogen. Adding nitrogen has two effects. First, the recombination rate is higher than that of oxygen. Second, by adding nitrogen, the atomic percentage of nitrogen in the non-conformal cap layer 40 is increased. According to some embodiments, the flow rate ratio N2 / Ar (the flow rate of nitrogen relative to the flow rate of argon) can be less than about 0.2. In addition, a small flow rate of hydrogen (H2) can be added to improve the efficiency of breaking bonds in the precursor. For example, the flow rate ratio H2 / Ar (the flow rate of hydrogen relative to the flow rate of argon) can be less than about 0.2. During the deposition process, a small bias power can be added to improve non-conformal behavior. For example, the bias power may be in a range between approximately 0 Watts and approximately 100 Watts.

[0031] At time point TP2, the precursor begins to be conducted, as Figure 17As shown in curve A in . According to some embodiments of the present disclosure, the precursor includes a silicon-containing precursor, which may also be an amine-containing precursor and / or a CH-ligand-containing precursor. For example, the precursor may include bisdiethylaminosilane (BDEAS), diisopropylaminosilane (DIPAS), etc., or a combination thereof. The flow rate of the precursor may be in the range of about 500 sccm to about 6 SLM. The time period ΔTP2 for conducting the precursor may be longer than about 0.1 seconds and may be in the range of about 0.1 seconds to about 10 seconds. During the conduction of the precursor, the precursor is adsorbed on Figure 4A and Figure 4B A monolayer is formed on the surface of the wafer 10 shown, and excess precursor is pumped out of the reaction chamber. According to some embodiments, the monolayer covers all exposed surfaces of the wafer 10, including the protruding fins 36. It will be appreciated that if other gases such as N2, Ar, H2 are used with the precursor, the energy required to decompose these gases and adsorb them to the surface of the wafer 10 is very high, and therefore these gases will not adsorb on the surface of the wafer 10. At time point TP3, the conduction of the precursor is stopped, as shown by curve A, and the purge gas is continued. Through the continuous conduction and purging of the purge gas, excess precursor in gaseous form is removed from the reaction chamber, while the precursor adsorbed on the wafer 10 remains. The time period ΔTP3 is long enough to allow the gaseous precursor to be fully removed. According to some embodiments of the present disclosure, the time period ΔTP3 is longer than about 1 second and can range from about 1 second to about 20 seconds or longer. Longer purge times do not affect the results, but can result in reduced throughput.

[0032] After the end of the time period ΔTP3 and at time TP4, power is supplied to generate a plasma from the purge gas, as shown by curve C. The plasma causes the adsorbed precursor to react, breaking the bonds of the adsorbed precursor from the silicon atoms in the precursor to generate radicals (and ions) (e.g., carbon radicals, nitrogen radicals, hydrogen radicals, etc.) and corresponding ions. The silicon atoms remain bonded to the surface of the wafer 10. The radicals then bond again with the silicon atoms to form a single layer of dielectric, e.g., SiC, SiN, SiCN, etc. The resulting dielectric layer is non-conformal and has a thickness of 0.04mm. Figure 16 The mechanism of non-conformal dielectric formation is discussed in detail.

[0033] Since the amount of adsorbed precursor molecules is limited, the reaction is self-stopping and will terminate once the adsorbed precursor molecules are fully reacted. Therefore, the time period ΔTP4 is selected to be long enough to allow complete reaction of the adsorbed precursor molecules, but short enough so that the throughput is not affected. According to some embodiments, the time period ΔTP4 can be longer than about 0.05 seconds and can be in the range of about 0.05 seconds and about 10 seconds. The power used to generate the plasma can be in the range of about 10 watts and about 500 watts. The plasma can be generated using an inductively coupled plasma (ICP) mode, a capacitively coupled plasma (CCP) mode, etc. According to some examples, the frequency of the RF power is 13.56 MHz, but other frequencies can be used.

[0034] After the end of the time period ΔTP4, the plasma is turned off at time point TP5. According to some embodiments of the present disclosure, an elapsed time period ΔTP5 is provided, during which the purge gas is continuously turned on, while both the precursor (curve A) and the plasma (curve C) are turned off. The elapsed time period ΔTP5 ends at time point TP6. It should be understood that if another cycle of the non-conformal ALD process is to be performed, the time point TP6 is also the time point TP1 of the next ALD cycle. The non-conformal ALD cycle is thus ended. The subsequent non-conformal ALD cycle may be a repetition of the above-described non-conformal ALD cycle. The non-conformal ALD cycle may be repeated until the desired thickness T2 ( Figure 5B ). According to some embodiments of the present disclosure, the number of cycles may be between 1 and about 1000 cycles. The total number of cycles depends on the specific application of the embodiment.

[0035] According to some embodiments of the present disclosure, the total time period (ΔTP1+ΔTP5) provides time for purging unreacted radicals, ions, etc. in preparation for the next non-conformal ALD cycle. According to some embodiments of the present disclosure, the total time period (ΔTP1+ΔTP5) is between about 0.1 seconds and about 100 seconds. According to other embodiments of the present disclosure, the time period ΔTP4 can be long enough so that the total time period (ΔTP1+ΔTP5) can be reduced to zero seconds. This means that if the plasma is turned on for a long enough time (e.g., longer than about 1 second), the unreacted radicals and ions of the precursor will be completely purged when the plasma is turned on. Therefore, after the plasma is turned off, the precursor conduction for the next cycle can be started immediately.

[0036] To achieve better results without sacrificing throughput, the time periods ΔTP1, ΔTP2, ΔTP3, ΔTP4, and ΔTP5 can be optimized. For example, the time period ΔTP2 and the time period ΔTP4 can be as small as possible, for example, within a range between about 0.1 seconds and about 10 seconds, and can be close to about 0.1 seconds. The time period ΔTP2 and the time period ΔTP4 can be close to or equal to each other, for example, the absolute value of the difference (ΔTP2-ΔTP4) / ΔTP2 is less than about 0.2. On the other hand, the time periods ΔTP2 and ΔTP4 are shorter than the time periods ΔTP3 and ΔTP5, so that sufficient purification is performed within the time periods ΔTP3 and ΔTP5.

[0037] According to some embodiments, an oxidation process is performed after one or more non-conformal ALD cycles to oxidize the deposited non-conformal capping layer 40 ( Figure 4A and Figure 4B ). Thus, depending on the composition of the non-conformal capping layer 40 (which may be formed of or may include SiC, SiN, SiCN, etc.), the resulting oxidized non-conformal capping layer 40 may be formed of or may include SiOC, SiON, SiOCN, etc. According to other embodiments, the oxidation process may be skipped, and the resulting non-conformal capping layer 40 will be formed of or include SiC, SiN, SiCN, etc. It will be understood that the dielectric layer 38 and the non-conformal capping layer 40 may (or may not) include the same element selected from Si, O, C, N, etc., and that the dielectric layer 38 and the non-conformal capping layer 40 may have different compositions (with different percentages of elements), regardless of whether they include the same elements. Figure 18A and Figure 18B A curve is shown for performing an oxidation process.

[0038] According to some embodiments, when the resulting non-conformal cap layer 40 is SiCN, the atomic percentage of carbon may be in a range between about 1% and about 50%, and the atomic percentage of nitrogen may be in a range between about 1% and about 50%. When the cap layer 40 is SiOCN, the atomic percentage of oxygen may be in a range between about 1% and about 50%, the atomic percentage of carbon may be in a range between about 1% and about 50%, and the atomic percentage of nitrogen may be in a range between about 1% and about 50%.

[0039] Figure 18A A continuous oxidation process comprising a single cycle is shown. Figure 18AThe top curve in FIG18 shows the conduction of the oxidizing gas and the purge gas over time, while the bottom curve shows the plasma over time. The time in the top curve corresponds to the time in the bottom curve. According to some embodiments of the present disclosure, the oxidizing and purging gases include an oxidizing gas, which may include oxygen (O2), ozone (O3), etc. The oxidizing and purging gases may also include a carrier gas (purge gas), which may include nitrogen (N2) and / or an inert gas, such as argon, helium, etc. According to an alternative embodiment, nitrogen is used instead of oxygen, and a carrier gas may be added. Therefore, the corresponding process in FIG18 is a nitriding process rather than an oxidation process. The flow rate of the oxidizing gas may be in the range of between about 1 sccm and about 6000 sccm, and the flow rate of the carrier gas may be in the range of between about 1 sccm and about 6000 sccm. The time period of oxidation may be in the range of between about 0.1 seconds and about 100 seconds.

[0040] Figure 18B An oxidation process according to an alternative embodiment is shown. In this process, instead of keeping the plasma on all the time while conducting the oxidation and purge bodies, the plasma is turned on and off in multiple cycles. The gas flows of the oxidation and purge gases can be similar to those of the reference Figure 18A According to some embodiments, the on / off ratio may be in a range between about 0.1 and about 0.9. The total number of plasma on / off cycles may be in a range between about 5 and 10.

[0041] In such Figure 18A or Figure 18B After the single or multi-cycle oxidation process shown, the process can return to Figure 17 One or more non-conformal ALD cycles are shown. Figure 17 The process and Figure 18A (or Figure 18B ) can also form a composite cycle together, and the composite cycle can be repeated.

[0042] Figure 16 An example is shown showing the intermediate chemical structure in the formation of a non-conformal cap layer 40 when a non-conformal ALD cycle is performed on a wafer 10. This example is shown using DIPAS as an example precursor. However, the mechanism discussed is also applicable to other types of precursors, such as BDEAS. Reference numerals 112, 114, 116, 118, and 120 are used to identify the intermediate chemical structure in the formation of a non-conformal cap layer 40 when a non-conformal ALD cycle is performed on a wafer 10. Figure 16 The intermediate structures shown in FIG are to distinguish the intermediate structures generated by different stages from each other. The wafer 10 includes a base layer 110, which can be represented as Figure 4A and Figure 4B The exposed features shown include dielectric layer 38 and STI regions 24, provided that these features are exposed at the beginning of the non-conformal ALD deposition process. It should be understood that Figure 4A and Figure 4B The illustrated structure is an example, and the embodiments can be applied to other structures.

[0043] Figure 16 The initial structure in the structure 112 is referred to as structure 112. In the example shown, the base layer 110 is shown as a silicon-containing layer, which can be in the form of crystalline silicon, amorphous silicon, polycrystalline silicon, or a silicon-containing compound, including but not limited to silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, etc. According to some embodiments of the present disclosure, O-H bonds are formed at the surface of the silicon-containing layer 110, wherein these O-H bonds can be bonded to silicon atoms at the surface of the base layer 110.

[0044] With further reference to structure 112, the conductive precursor (at Figure 17 2 ), which is represented as a silicon atom bonded to two hydrogen atoms and two ligands (functional groups) represented as "L", where, when the precursor comprises DIPAS, the ligand L is a functional group having the formula N(C2H5)2. As shown in structure 112, some precursor molecules are adsorbed on the exposed wafer 10. The exposed surface can be covered with a blanket monolayer of precursor molecules. The conduction of the precursor is then stopped, and a purge gas is continuously conducted to purge the excess precursor molecules that are not adsorbed out of the reaction chamber.

[0045] Reference again Figure 16 , turn on the plasma (at Figure 17 TP4 in FIG, 1 ), and structure 114 is generated from structure 112. Assuming argon is used as the purge gas, argon ions are generated, which attack the adsorbed precursor molecules and break the bonds between OH and H and Si in the precursor molecules. As a result, the silicon atoms in the precursor molecules bond to the oxygen atoms on wafer 10. The silicon atoms may also bond to functional groups L or hydrogen atoms, as shown in the resulting structure 114.

[0046] As the plasma is generated, the functional groups L in structure 114 further break down to generate carbon radicals and ions, nitrogen radicals and ions, and hydrogen radicals and ions, and the resulting structure is shown as structure 116. These radicals and ions also form a plasma, and the plasma generation including the further decomposition of ions and radicals is referred to as plasma regeneration. The regenerated plasma includes carbon radicals (C*), nitrogen radicals (N*), hydrogen radicals (H*), and CN radicals (CN*), as shown in structure 118. The radicals and ions generated by the plasma regeneration then bond to silicon atoms and form structure 120. In the example shown, the resulting dielectric layer 40 includes SiCN, SiOCN, etc.

[0047] After forming the structure 120, repeat as Figure 16 and Figure 17The ALD cycle shown is performed to deposit multiple monolayers to form dielectric layer 40, as shown in FIG. Figure 5A and Figure 5B In the subsequent ALD cycle, the Si-C, Si-N, and Si-O bonds formed in the previous ALD cycle may be broken, and more Si atoms in the precursor introduced in the subsequent ALD cycle are bonded, subsequently forming more Si-C and Si-N bonds. Figure 16 The ALD shown is cycled until the resulting dielectric layer 40 has the desired thickness.

[0048] According to some embodiments of the present disclosure, the process is a non-conformal ALD process, and the mechanism is briefly discussed below. Figure 4B , because the plasma is concentrated at the top of the fin, the plasma and the resulting radicals are concentrated near the top of the protruding fin 36 and are less likely to appear in the trenches between the protruding fins 36 because the top is in the path of the gas flow. Therefore, carbon radicals C* and nitrogen radicals N* are more likely to bond with the open bonds of silicon atoms near the top of the fin. In comparison, if the precursor is introduced into the reaction chamber or left in the reaction chamber (except for adsorption) when the plasma is turned on, a conformal film will be formed. Depending on the precursor and process conditions, SiC, SiN or SiCN can be formed as the dielectric layer 40. C* and N* are more active than H* radicals, so the resulting dielectric layer 40 does not include hydrogen.

[0049] In order for the carbon radicals C* and nitrogen radicals N* to bond to silicon atoms, these radicals need to travel (diffuse) to the corresponding locations. However, these radicals are highly reactive and their diffusion lengths are short, and the probability of C* and N* radicals traveling from the top of the fin to the middle and bottom of the fin 36 is low. In addition, because the plasma is turned on after the excess precursor molecules are purged, there are few sources of C* and N* radicals from adsorbed precursors, and the total number of C* and N* radicals is small. The C* and N* radicals will react locally and conveniently with the silicon at the top of the fin, and will be less likely to travel to and bond to the silicon atoms at the middle and bottom of the protruding fin. As a result, the deposited dielectric layer 40 is non-conformal, as shown in FIG. Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D shown.

[0050] According to some embodiments, as shown in FIG. Figure 17As discussed, highly recombination gases such as nitrogen (N2) and / or hydrogen (H2) are provided as part of the purge gas. These gases will also be decomposed into radicals by the inert gas plasma. Highly recombination gases have a high recombination rate, which means that their radicals N* and H* are very easy to recombine, for example, to form N2 and H2 again. For example, highly recombination gases have a higher recombination rate (and diffuse a shorter distance) than oxygen radicals O*. Therefore, these gases have a short diffusion length, and their addition will amplify the non-conformal behavior and lead to a ratio T Side-Avg / T Top-Avg Even smaller.

[0051] To achieve non-conformal behavior, process conditions are also adjusted. It has been found that higher pressures of the purge gas (which may include N2) and the radicals from the adsorbed precursors produce higher recombination rates because there are more radicals available for recombination. Therefore, higher pressures lead to a more non-conformal profile of the deposited dielectric layer 40, and vice versa. On the other hand, if the pressure is too high, the quality of the dielectric layer 40 may be reduced due to the low energy carried by the radicals. According to some embodiments of the present disclosure, the pressure is controlled within a range between about 1000 mTorr and about 8000 mTorr.

[0052] Furthermore, lowering the plasma power is more beneficial for forming the non-conformal cap layer 40 because free radicals are less likely to reach the bottom of the fin and bond there. On the other hand, if the plasma power is too low (e.g., below 10 watts), the film quality may also be reduced. According to some embodiments of the present disclosure, the plasma power is controlled within a range between about 10 watts and about 500 watts.

[0053] As Figure 16 As a result of the ALD cycles shown, a single layer of dielectric layer 40 is deposited as shown in FIG. Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D The dielectric layer 40 may be formed on the top of the protruding structure shown in FIG. 1 , and may not be formed on the sidewalls of the protruding structure (particularly on the lower portion of the sidewalls) and the top of the STI region 24. In addition, the lower portion of the sidewall has a lower probability of having the dielectric layer 40 deposited thereon than the corresponding upper portion. This makes the thickness of the lower portion of the sidewall portion 40B of the dielectric layer 40 smaller and smaller (as shown in FIG. 1 ). Figure 5C and Figure 5D ), or uniform but thinner than the top portion, e.g. Figure 5B shown.

[0054] Figure 6A and Figure 6B FIG4 shows the deposition of the dummy gate electrode layer 42. Figure 19This is shown as process 412 in the illustrated process flow 400 . Figure 6B Shown Figure 6A The dummy gate electrode layer 42 may be formed of polycrystalline silicon or amorphous silicon, or may include polycrystalline silicon or amorphous silicon, and other materials may also be used. The formation process may include a deposition process followed by a planarization process. A hard mask layer 44 is then deposited on the dummy gate electrode layer 42. The corresponding process is Figure 19 This is shown as process 414 in the illustrated process flow 400. The hard mask layer 44 may be formed of or may include silicon nitride, silicon oxide, silicon oxycarbonitride, or multiple layers thereof.

[0055] Figure 7A and 7B FIG. 4 shows a patterning process for forming a dummy gate stack 45. Figure 19 This is shown as process 416 in the illustrated process flow 400 . Figure 7B Shown Figure 7A 7B-7B in FIG. According to some embodiments of the present disclosure, hard mask layer 44 is first patterned, for example, using a patterned photoresist as an etch mask. The resulting hard mask is referred to as hard mask 44′. Patterned hard mask 44′ is then used as an etch mask to etch the underlying dummy gate electrode layer 42 and dummy gate dielectric 38 to form dummy gate electrode 42′ and dummy gate dielectric 38′, respectively. This etching is performed using an anisotropic etching process.

[0056] The etching of the dummy gate electrode layer 42 (which may be formed of polysilicon) may be performed using a process gas comprising: C2F6, CF4, SO2, a mixture of (HBr, Cl2, and O2), or a mixture of HBr, Cl2, O2, and CF2. During the etching process of the dummy gate electrode layer 42, the non-conformal capping layer 40 and the dummy dielectric layer 38 are used as etch stop layers. The non-conformal capping layer 40 helps prevent etching through the dummy dielectric layer 38 during the etching of the dummy gate electrode layer 42. Otherwise, if the dielectric layer 38 is etched through, the protruding fin 36 would be severely damaged or even completely removed if the non-conformal capping layer 40 is not formed, because the protruding fin 36 may be formed of the same or similar material as the dummy gate electrode layer 42 (e.g., silicon). The thicker non-conformal capping layer 40 at the top of the protruding fin 36 provides enhanced protection for the underlying dielectric layer 38 and the protruding fin 36.

[0057] According to some embodiments, after patterning the dummy gate electrode layer 42, the exposed portion of the non-conformal capping layer 40 and the underlying portion of the dielectric layer 38 are etched, exposing the underlying protruding fins 36. According to an alternative embodiment of the present disclosure, the non-conformal capping layer 40 is etched, and the underlying portion of the dielectric layer 38 is not patterned and will be patterned after the gate spacers are formed. According to yet another alternative embodiment of the present disclosure, both the non-conformal capping layer 40 and the underlying portion of the dielectric layer 38 are not patterned and will be patterned after the gate spacers are formed.

[0058] Next, if Figure 8 As shown in FIG, a gate spacer 46 is formed on the sidewall of the dummy gate stack 45. The corresponding process is Figure 19 This is shown as process 418 in the illustrated process flow 400. According to some embodiments of the present disclosure, the gate spacers 46 are formed of dielectric material(s) such as silicon nitride, silicon carbonitride, etc., and may have a single layer structure or a multi-layer structure including multiple dielectric layers.

[0059] An etching process is then performed to etch the exposed portions of the non-conformal capping layer 40 and the underlying portions of the dielectric layer 38 (if not already patterned). Figure 19 The process flow 400 is shown as process 420. Dashed lines are used to indicate that the portion of the dielectric layer 38 and the non-conformal cap layer 40 located below the gate spacer 46 may or may not be present, depending on whether the exposed portion was etched in the previous process. The portion of the protruding fin 36 not covered by the dummy gate stack 45 and the gate spacer 46 is etched to obtain Figure 9 The structure shown. The etching can be anisotropic, so the portion of fin 36 directly below dummy gate stack 45 and gate spacer 46 is protected and not etched. According to some embodiments, the top surface of recessed semiconductor strip 26 can be lower than top surface 24A of STI region 24. Recess 50 is formed accordingly. Recess 50 includes portions located on opposite sides of dummy gate stack 45 and portions between the remaining portions of protruding fin 36.

[0060] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 50, resulting in Figure 10 The corresponding process is Figure 19In the process flow 400 shown, it is shown as process 422. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped during epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, for example, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multilayer thereof. After the groove 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and facets can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. There may be voids (air gaps) 56. According to some embodiments of the present disclosure, the formation of the epitaxial regions 54 may be completed when the top surface of the epitaxial regions 54 is still wavy, or when the top surface of the merged epitaxial regions 54 has become flat, by further growth on the epitaxial regions 54 as shown in FIG.

[0061] After the epitaxy step, the epitaxy region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted by reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxy region 54 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0062] Figure 11A FIG. 1 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. Figure 19 The process flow 400 is shown as process 424. The CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as tetraethylorthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process can be performed to make the top surfaces of the ILD 60, the dummy gate stack 45, and the gate spacers 46 flush with each other. Figure 11B Shown as Figure 11A Reference section 11B-11B is shown.

[0063] The hard mask 44', the dummy gate electrode 42', the non-conformal capping layer 40 and the dummy dielectric layer 38' are then removed, thereby forming trenches 62 between the gate spacers 46, as shown in FIG. Figure 12A and 12B shown. Figure 12B Shown as Figure 12A Reference cross section 12B-12B is shown. According to some embodiments, the Figure 7A and Figure 7B The removal of the dummy gate electrode 42' is performed using an anisotropic etching process similar to the patterning process shown. According to an alternative embodiment, the removal of the dummy gate electrode 42' is performed using a wet etching process. In the event that the dummy gate dielectric 38' is damaged, the non-conformal capping layer 40 can protect the protruding fin 36 from unwanted damage during the removal of the dummy gate electrode 42'. After the dummy gate electrode 42' is removed, the non-conformal capping layer 40 is exposed through the trench 62. The non-conformal capping layer 40 and the dielectric layer 38' are then removed, and Figure 13 The resulting structure is shown in .

[0064] Figure 14A and Figure 14B The formation of the replacement gate stack 64 and the self-aligned hard mask 80 is shown. Figure 14B Shown as Figure 14A Reference cross section 14B-14B is shown. Figure 14A and Figure 14B As shown, a replacement gate stack 64 is formed. Figure 19 The process flow 400 is shown as process 426. The gate stack 64 includes a gate dielectric 70 and a gate electrode 72. The gate dielectric 70 may include an interfacial layer (IL) 66 and a high-k dielectric layer 68 ( Figure 14B IL 66 is formed on the exposed surface of protruding fin 36 and may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation, or deposition of protruding fin 36. High-k dielectric layer 68 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and may be higher than approximately 7.0. According to some embodiments of the present disclosure, high-k dielectric layer 68 is formed using ALD, CVD, or the like.

[0065] Further references Figure 14A and Figure 14B , a gate electrode 72 is formed on the gate dielectric 70. The gate electrode 72 may include a stacked layer 74 ( Figure 14B), which may include a diffusion barrier layer (cap layer), and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride, which may (or may not) be doped with silicon. When doped with silicon, titanium nitride is sometimes also referred to as titanium silicon nitride (Ti-Si-N or TSN). The work function layer determines the work function of the gate electrode and includes at least one layer, or multiple layers formed of different materials. The specific material of the work function layer can be selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer above the TaN layer, and a TiAl layer above the TiN layer. After depositing the cap layer and the work function layer, a barrier layer may be formed, which may be another TiN layer. The barrier layer may be formed using CVD.

[0066] Next, a metal fill region 76 is deposited. The formation of the metal fill region 76 may be achieved by CVD, ALD, physical vapor deposition (PVD), etc., and the metal fill region 76 may be formed of or may include cobalt, tungsten, alloys thereof, or other metals or metal alloys.

[0067] Next, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to make the top surface of the gate stack 64 coplanar with the top surface of the ILD 60. In a subsequent process, the gate stack 64 is etched back to form a groove between the opposing gate spacers 46. Next, a hard mask 80 is formed over the replacement gate stack 64. The corresponding process is as follows. Figure 19 This is shown as process 428 in the illustrated process flow 400. According to some embodiments of the present disclosure, the formation of the hard mask 80 includes a deposition process for forming a blanket dielectric material and a planarization process for removing excess dielectric material over the gate spacers 46 and the ILD 60. The hard mask 80 may be formed of, for example, silicon nitride or other similar dielectric materials.

[0068] In the final structure, there may or may not be a remaining portion of the conformal dielectric layer 38' on the protruding fin 36, and a remaining portion of the non-conformal cap layer 40 on the conformal dielectric layer 38' directly under the gate spacer 46, as shown in FIG. Figure 14B In addition, the dielectric layer 38' and the remaining portion of the non-conformal cap layer 40 directly below the gate spacer 46 may have the same Figure 5B 、 Figure 5C and Figure 5D The same cross-sectional view is shown.

[0069] Figure 15 Some features formed in subsequent processes are shown, which may include source / drain contact plugs 84, source / drain silicide regions 86, and the lower portion of gate contact plug 82. Figure 19 The process flow 400 is shown as process 430. The process details are not discussed here. FinFET 90 is thus formed.

[0070] Embodiments of the present disclosure have several advantageous features. By forming a non-conformal capping layer, the non-conformal capping layer can provide improved protection to underlying layers / regions when performing anisotropic etching. Furthermore, the non-conformal capping layer has a very small thickness or is not formed on the sidewalls of the underlying protruding features, thus having little impact on subsequent processing.

[0071] According to some embodiments of the present disclosure, a method includes: forming a protruding structure; and forming a non-conformal film on the protruding structure using an ALD process, wherein the non-conformal film includes a top portion located directly above the protruding structure, wherein the top portion has a first thickness; and a sidewall portion on a sidewall of the protruding structure, wherein the sidewall portion has a second thickness less than the first thickness. In one embodiment, the ALD process includes a plasma-assisted ALD process, wherein the plasma is turned on during the ALD process. In one embodiment, the method further includes: forming a dummy gate electrode layer above the non-conformal film; and patterning the dummy gate electrode layer. In one embodiment, the ALD process includes a cycle, and the cycle includes: conducting a silicon-containing precursor into a reaction chamber; stopping conducting the silicon-containing precursor; purging the silicon-containing precursor; and turning on the plasma after the silicon-containing precursor is purged. In one embodiment, the purging is performed using a purge gas, and wherein the purge gas is continuously conducted into the reaction chamber during the period when the plasma is turned on. In one embodiment, the purge is performed using a purge gas, and the purge gas is continuously introduced into the reaction chamber during a time period starting from a first point in time when the conductive silicon-containing precursor is terminated to a second point in time when the plasma is turned on. In one embodiment, forming the protruding structure includes: forming a protruding semiconductor fin; and forming a dielectric layer on the protruding semiconductor fin, wherein the non-conformal film is formed on the dielectric layer. In one embodiment, a bottom end of the non-conformal film is higher than a mid-height of the protruding semiconductor fin.

[0072] According to some embodiments of the present disclosure, an integrated circuit structure includes: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding above a top surface of the isolation region, wherein the isolation region is on opposite sides of the semiconductor fin; a dielectric layer on the top surface and sidewalls of the semiconductor fin; and a capping layer including a first portion directly above the semiconductor fin, wherein the capping layer includes: a top portion overlying the dielectric layer, wherein the top portion has a first thickness; and a sidewall portion on the sidewalls of the top portion of the semiconductor fin, wherein the sidewall portion has a second thickness less than the first thickness. In one embodiment, the integrated circuit structure includes: a gate spacer including an upper portion directly above the top portion of the capping layer and a lower portion on the sidewall portion of the capping layer; and a gate stack contacting the gate spacer. In one embodiment, a bottom end of the sidewall portion of the capping layer is higher than a mid-height of the semiconductor fin. In one embodiment, a lower portion of the sidewall portion of the capping layer is thinner than a corresponding upper portion of the sidewall portion of the capping layer. In one embodiment, the thickness of the sidewall portion of the capping layer increases continuously from the lower portion to the corresponding upper portion. In one embodiment, the dielectric layer and the capping layer are formed of different materials. In one embodiment, the dielectric layer and the capping layer include the same element selected from the group consisting of Si, O, N, and C, and the dielectric layer and the capping layer have different compositions. In one embodiment, the capping layer has no horizontal portion directly above the isolation region.

[0073] According to some embodiments of the present disclosure, a structure includes: a protruding structure that protrudes higher than features located on opposite sides of the protruding structure, wherein the protruding structure includes a top surface and a sidewall surface; a dielectric cap layer having a top portion located directly above the protruding structure, wherein the top portion of the dielectric cap layer has a uniform thickness, and wherein at least a bottom portion of the sidewall surface of the protruding structure does not have the dielectric cap layer formed thereon; and additional features in contact with: the top portion of the dielectric cap layer; and a lower portion of the sidewall surface of the protruding structure. In one embodiment, the protruding structure includes an inner portion; and a conformal outer portion on the inner portion, wherein the lowest end of the dielectric cap layer is at substantially the same level as the top surface of the inner portion. In one embodiment, the inner portion includes polysilicon and the conformal outer portion includes a dielectric material. In one embodiment, the thickness of the top portion of the dielectric cap layer is about peace treaty within the range between.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0075] Example 1. A method for manufacturing a semiconductor device, comprising: forming a protruding structure; and forming a non-conformal film on the protruding structure using an atomic layer deposition (ALD) process, wherein the non-conformal film comprises: a top portion located directly above the protruding structure, wherein the top portion has a first thickness; and; a sidewall portion located on a sidewall of the protruding structure, wherein the sidewall portion has a second thickness less than the first thickness.

[0076] Example 2. The method of Example 1, wherein the ALD process comprises a plasma-assisted ALD process, wherein a plasma is turned on during the ALD process.

[0077] Example 3. The method of Example 1, further comprising: forming a dummy gate electrode layer over the non-conformal film; and patterning the dummy gate electrode layer.

[0078] Example 4. The method of Example 1, wherein the ALD process comprises a cycle, and the cycle comprises: conducting a silicon-containing precursor into a reaction chamber; stopping conducting the silicon-containing precursor; purging the silicon-containing precursor; and starting a plasma after the silicon-containing precursor is purged.

[0079] Example 5. The method of Example 4, wherein the purging is performed using a purge gas, and wherein the purge gas is continuously conducted into the reaction chamber during the plasma-on period.

[0080] Example 6. A method according to Example 4, wherein the purging is performed using a purge gas, and wherein the purge gas is continuously conducted into the reaction chamber during a time period starting from a first time point when the conduction of the silicon-containing precursor is terminated to a second time point when the plasma is turned on.

[0081] Example 7. The method of Example 1, wherein forming the protruding structure comprises: forming a protruding semiconductor fin; and forming a dielectric layer on the protruding semiconductor fin, wherein the non-conformal film is formed on the dielectric layer.

[0082] Example 8. The method of claim 7, wherein a bottom end of the non-conformal film is higher than a middle height of the protruding semiconductor fin.

[0083] Example 9. An integrated circuit structure comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding above a top surface of the isolation region, wherein the isolation region is on opposite sides of the semiconductor fin; a dielectric layer on the top surface and sidewalls of the semiconductor fin; and a cap layer comprising a first portion directly above the semiconductor fin, wherein the cap layer comprises: a top portion overlying the dielectric layer, wherein the top portion has a first thickness; and a sidewall portion on the sidewalls of the top portion of the semiconductor fin, wherein the sidewall portion has a second thickness less than the first thickness.

[0084] Example 10. The integrated circuit structure of Example 9 further includes: a gate spacer including an upper portion directly above the top portion of the cap layer and a lower portion on the sidewall portion of the cap layer; and a gate stack in contact with the gate spacer.

[0085] Example 11. The integrated circuit structure of Example 9, wherein a bottom end of the sidewall portion of the capping layer is higher than a middle height of the semiconductor fin.

[0086] Example 12. The integrated circuit structure of Example 9, wherein a lower portion of the sidewall portion of the capping layer is thinner than a corresponding upper portion of the sidewall portion of the capping layer.

[0087] Example 13. The integrated circuit structure of Example 12, wherein the thickness of the sidewall portion of the capping layer increases continuously from the lower portion to the corresponding upper portion.

[0088] Example 14. The integrated circuit structure of Example 9, wherein the dielectric layer and the capping layer are formed of different materials.

[0089] Example 15. The integrated circuit structure of Example 9, wherein the dielectric layer and the capping layer include the same element selected from the group consisting of Si, O, N, and C, and the dielectric layer and the capping layer have different compositions.

[0090] Example 16. The integrated circuit structure of Example 9, wherein the capping layer has no horizontal portion directly above the isolation region.

[0091] Example 17. An integrated circuit structure comprising: a protruding structure protruding above features on opposite sides of the protruding structure, wherein the protruding structure includes a top surface and a sidewall surface; a dielectric cap layer having a top portion located directly above the protruding structure, wherein the top portion of the dielectric cap layer has a uniform thickness, and wherein at least a bottom portion of the sidewall surface of the protruding structure does not have the dielectric cap layer formed thereon; and additional features in contact with: the top portion of the dielectric cap layer; and a lower portion of the sidewall surface of the protruding structure.

[0092] Example 18. A structure according to Example 17, wherein the protruding structure includes: an inner portion; and a conformal outer portion, on the inner portion, wherein the lowermost end of the dielectric cap layer is at substantially the same level as the top surface of the inner portion.

[0093] Example 19. The structure of Example 18, wherein the inner portion comprises polysilicon and the conformal outer portion comprises a dielectric material.

[0094] Example 20. The structure of Example 17, wherein the thickness of the top portion of the dielectric cap layer is about peace treaty within the range between.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a protruding semiconductor fin; as well as forming a dielectric layer on the protruding semiconductor fin; forming a non-conformal film on the dielectric layer using an atomic layer deposition (ALD) process, wherein the non-conformal film comprises: a top portion directly above the dielectric layer, wherein the top portion has a first thickness; and; a sidewall portion located on a sidewall of the dielectric layer, wherein the sidewall portion has a second thickness less than the first thickness, The bottom end of the non-conformal film is higher than the middle height of the protruding semiconductor fin.

2. The method according to claim 1, wherein The ALD process includes a plasma-assisted ALD process, wherein a plasma is turned on during the ALD process.

3. The method according to claim 1, further comprising: forming a dummy gate electrode layer on the non-conformal film; as well as The dummy gate electrode layer is patterned.

4. The method according to claim 1, wherein The ALD process comprises a cycle, and the cycle comprises: conducting a silicon-containing precursor into the reaction chamber; stopping conducting the silicon-containing precursor; purifying the silicon-containing precursor; and After the silicon-containing precursor is purged, the plasma is turned on.

5. The method according to claim 4, wherein The purging is performed using a purge gas, and wherein the purge gas is continuously conducted into the reaction chamber during a period when the plasma is on.

6. The method according to claim 4, wherein: The purging is performed using a purge gas, and wherein the purge gas is continuously introduced into the reaction chamber during a time period starting from a first time point at which the introduction of the silicon-containing precursor is terminated to a second time point at which the plasma is turned on.

7. An integrated circuit structure comprising: semiconductor substrates; an isolation region extending into the semiconductor substrate; a semiconductor fin protruding above a top surface of the isolation region, wherein the isolation region is on opposite sides of the semiconductor fin; a dielectric layer on the top surface and sidewalls of the semiconductor fin; and a capping layer on the dielectric layer, wherein the capping layer comprises: a top portion overlying the dielectric layer, wherein the top portion has a first thickness; and a sidewall portion on a sidewall of the dielectric layer, wherein the sidewall portion has a second thickness less than the first thickness, Wherein, a bottom end of the sidewall portion of the capping layer is higher than a middle height of the semiconductor fin.

8. The integrated circuit structure according to claim 7, further comprising: a gate spacer including an upper portion directly above the top portion of the cap layer and a lower portion on the sidewall portion of the cap layer; as well as A gate stack is in contact with the gate spacer.

9. The integrated circuit structure according to claim 7, wherein: A lower portion of the sidewall portion of the capping layer is thinner than a corresponding upper portion of the sidewall portion of the capping layer.

10. The integrated circuit structure according to claim 9, wherein: The thickness of the sidewall portion of the capping layer continuously increases from the lower portion to the corresponding upper portion.

11. The integrated circuit structure according to claim 7, wherein: The dielectric layer and the capping layer are formed of different materials.

12. The integrated circuit structure according to claim 7, wherein: The dielectric layer and the capping layer include the same element selected from the group consisting of Si, O, N, and C, and the dielectric layer and the capping layer have different compositions.

13. The integrated circuit structure according to claim 12, wherein: The dielectric layer and the cap layer include one of the following: SiC, SiN, SiCN, SiOC, SiON or SiOCN.

14. The integrated circuit structure according to claim 7, wherein: The capping layer has no horizontal portion directly above the isolation region.

15. An integrated circuit structure comprising: a protruding structure that protrudes higher than features on opposite sides of the protruding structure, wherein the protruding structure includes a top surface and sidewall surfaces, wherein the protruding structure includes: semiconductor fins; and a dielectric layer comprising a sidewall portion located on the sidewall surface of the semiconductor fin and a first top portion located directly above the top surface of the semiconductor fin; a dielectric capping layer having a second top portion directly above the first top portion of the dielectric layer and a second sidewall portion on the sidewall portion of the dielectric layer, wherein the second top portion of the dielectric capping layer has a uniform thickness, and wherein at least a bottom portion of the sidewall portion of the dielectric layer is free of the dielectric capping layer formed thereon; and Additional features, contact with: the second top portion of the dielectric cap layer; and a lower portion of the sidewall portion of the dielectric layer, The bottom end of the second sidewall portion of the dielectric cap layer is higher than the middle height of the semiconductor fin.

16. The structure according to claim 15, wherein The semiconductor fin includes polysilicon, and the dielectric layer includes a dielectric material.

17. The structure according to claim 15, wherein The thickness of the second top portion of the dielectric capping layer is in a range between 5 Å and 10 Å.

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