Fin end gate structure and method of forming the same

Abstract

The present disclosure relates to a fin end gate structure and a method for forming the same. A method includes: forming a first dummy gate stack and a second dummy gate stack simultaneously on a first portion and a second portion of a protruding fin; removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack simultaneously to form a first trench and a second trench, respectively; forming an etching mask, wherein the etching mask fills the first trench and the second trench; patterning the etching mask to remove the etching mask from the first trench; removing a first dummy gate dielectric of the first dummy gate stack, wherein the etching mask protects the second gate dielectric of the first dummy gate stack from being removed; and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

Description

Technical Field

[0001] The present disclosure generally relates to fin-end gate structures and methods of forming the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices are basic building blocks in integrated circuits. MOS devices can have a gate electrode formed from polysilicon doped with p-type or n-type impurities using a doping process such as ion implantation or thermal diffusion. The work function of the gate electrode can be tuned to the band-edge of silicon. For n-type metal oxide semiconductor (NMOS) devices, the work function can be tuned to approach the conduction band of silicon. For p-type metal oxide semiconductor (PMOS) devices, the work function can be tuned to approach the valence band of silicon. The work function of the polysilicon gate electrode can be adjusted by selecting appropriate impurities.

[0003] MOS devices with polysilicon gate electrodes exhibit carrier depletion, also known as the polysilicon depletion effect. The polysilicon depletion effect occurs when an applied electric field removes carriers from the gate region near the gate dielectric, forming a depletion layer. In n-doped polysilicon layers, the depletion layer consists of ionized, non-mobile donor sites, whereas in p-doped polysilicon layers, the depletion layer consists of ionized, non-mobile acceptor sites. The depletion effect increases the effective gate dielectric thickness, making it more difficult to form an inversion layer on the semiconductor surface.

[0004] The polysilicon depletion problem can be solved by forming a metal gate electrode, wherein the metal gate used in NMOS devices and PMOS devices can also have a band-edge work function. Therefore, the resulting metal gate includes multiple layers to meet the requirements of NMOS devices and PMOS devices.

[0005] Formation of a metal gate typically involves forming a dummy gate stack, removing the dummy gate stack to form a trench, forming a replacement gate stack including a metal gate extending into the trench, and then performing a chemical mechanical polishing (CMP) process to remove excess portions of the metal gate. Summary of the Invention

[0006] According to a first aspect of the present disclosure, a method is provided, comprising: depositing a stacked layer on a first protruding fin; patterning the stacked layer to form the following items: a first gate stack, comprising: a first gate dielectric, on a middle portion of the first protruding fin; and a first gate electrode, on the first gate dielectric; and a second gate stack, comprising: a second gate dielectric, on an end portion of the first protruding fin; and a second gate electrode, on the second gate dielectric; removing the first gate electrode and the second gate electrode to expose the first gate dielectric and the second gate dielectric, respectively; removing the first gate dielectric, wherein the second gate dielectric remains after the first gate dielectric is removed; forming a replacement gate dielectric on the middle portion of the first protruding fin; and forming a first replacement gate electrode and a second replacement gate electrode on the replacement gate dielectric and the second gate dielectric, respectively.

[0007] According to a second aspect of the present disclosure, a method is provided, comprising: simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin; simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively; forming an etching mask, wherein the etching mask fills the first trench and the second trench; patterning the etching mask to remove the etching mask from the first trench; removing the first dummy gate dielectric of the first dummy gate stack, wherein the etching mask protects the second gate dielectric of the first dummy gate stack from being removed; and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

[0008] According to a third aspect of the present disclosure, a structure is provided, comprising: an isolation region extending into a semiconductor substrate; a protruding fin between portions of the isolation region, wherein the protruding fin protrudes above the isolation region; a first gate stack comprising: a first gate dielectric on a first sidewall and a first top surface of a first portion of the protruding fin, wherein the first gate dielectric has a first thickness; and a first gate electrode on the first gate dielectric; and a second gate stack comprising: a second gate dielectric on a second sidewall and a second top surface of a second portion of the protruding fin, wherein the protruding fin terminates directly below the second gate stack and the second gate dielectric has a second thickness greater than the first thickness; and a second gate electrode on the second gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1-3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 8C and Figure 9-13 Perspective, top, and cross-sectional views are shown of intermediate stages in the formation of a fin field effect transistor (FinFET) and a fin end gate structure, according to some embodiments.

[0011] Figure 14-21 、 Figure 22A and Figure 22B Perspective, top, and cross-sectional views illustrate intermediate stages in the formation of a Gate All-Around (GAA) transistor and a fin-end gate structure, according to some embodiments.

[0012] Figure 23 A process flow for forming FinFETs and fin-end gate structures is shown, according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature relative to another element or feature(s) illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] According to some embodiments, a method for forming a fin field effect transistor (FinFET), a gate-all-around (GAA) transistor, and a fin end gate structure, and the resulting structure are provided. According to some embodiments, an intermediate stage of forming a transistor is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Transistors such as carbon network tubes (CNTs), multi-bridge channel FETs (MBCFETs), nanosheet FETs (NSFETs), nanostructured transistors, complementary (CFETs), vertical FETs (VFETs), etc., and the formation of corresponding fin end gate structures may also employ embodiments of the present disclosure. The embodiments discussed herein will provide examples of how the subject matter of the present disclosure can be performed or used, and those skilled in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] According to some embodiments of the present disclosure, a first dummy gate stack and a second dummy gate stack including dummy gate electrodes may be formed on a middle portion and an end portion of a protruding fin, respectively. The protruding fin may be a protruding semiconductor fin, or may include a stack (e.g., including a semiconductor layer and a sacrificial layer). The first dummy gate electrode and the second dummy gate electrode of the first gate stack and the second gate stack are removed to expose the first dummy gate dielectric and the second dummy gate dielectric thereunder, respectively. The first dummy gate dielectric covering the middle portion of the protruding fin is removed, while the second dummy gate dielectric covering the end portion of the protruding fin is not removed. By not removing the second dummy gate dielectric, the end portion below the protruding fin is protected from damage caused by subsequent processes, and the nearest source / drain region adjacent to the end portion of the protruding fin is protected.

[0017] Figure 1-3 、 Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 8C and Figure 9-13 The cross-sectional and perspective views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET) and a fin end structure according to some embodiments of the present disclosure. The processes shown in these figures are also schematically reflected in Figure 23 In the process flow 400 shown.

[0018] exist Figure 1 , a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, for example, a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0019] Further references Figure 1 , forming a well region 22 in the substrate 20. The corresponding process is Figure 23 The process flow 400 is shown as process 402. According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (such as boron, indium, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities (such as phosphorus, arsenic, antimony, etc.) into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 within the range between.

[0020] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. Figure 23The process flow 400 shown is shown as process 404. The portion of the substrate 20 between adjacent STI regions 24 is referred to as a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 can be formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 can be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon, or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to form a hard mask layer 30 as shown in FIG. Figure 2 A hard mask 30 is shown.

[0021] Next, patterned hard mask layer 30 is used as an etch mask to etch pad oxide layer 28 and substrate 20, followed by filling the resulting trenches in substrate 20 with dielectric material(s). A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material(s) become STI regions 24. STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner dielectric may also be a silicon oxide layer, a silicon nitride layer, or the like, deposited using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or the like. STI regions 24 also include a dielectric material overlying the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material overlying the liner dielectric may include silicon oxide.

[0022] The top surface of hard mask layer 30 and the top surface of STI regions 24 may be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are portions of original substrate 20, and thus are made of the same material as substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are replacement strips formed by etching portions of substrate 20 between STI regions 24 to form recesses, and performing epitaxy to re-grow another semiconductor material in the recesses. Thus, semiconductor strips 26 are formed of a different semiconductor material than substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0023] refer to Figure 3 , the STI region 24 is recessed so that the top portion of the semiconductor strip 26 protrudes above the top surface 24A of the remaining portion of the STI region 24 to form a protruding fin 36. Figure 23 This is shown as process 406 in the illustrated process flow 400. Etching can be performed using a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, recessing of STI regions 24 is performed using a wet etching process. The etching chemical may include, for example, HF.

[0024] In the above embodiments, the fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, a smaller pitch than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0025] refer to Figure 4A , the dummy gate stack 38 is formed to extend on the top surface and sidewalls of the (protruding) fin 36. Figure 23The process flow 400 is shown as process 408. The formation process may include depositing a stack and then patterning the stack to form a dummy gate stack 38. The dummy gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, or other materials. Each of the dummy gate stacks 38 may also include one (or more) hard mask layers 44 above the dummy gate electrode 42. The hard mask layer 44 may be formed from the dielectric layer 66, or may be formed from or include other dielectric materials, such as SiN, SiON, SiOCN, SiOC, SiO2, SiC, or the like, or multiple layers thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fin 36.

[0026] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. Figure 23 This is also shown as process 408 in the illustrated process flow 400. According to some embodiments of the present disclosure, spacer 46 is formed of dielectric material(s) such as silicon nitride, silicon carbonitride, etc., and may have a single layer structure or a multilayer structure including multiple dielectric layers.

[0027] Figure 4B A plan view of wafer 10 is shown, which includes protruding fins 36, dummy gate stacks 38, and gate spacers 46. Some of the dummy gate stacks 38 (denoted as 38A) are on the middle portion 36A of the protruding fin 36, and some other dummy gate stacks 38 (denoted as 38B) are on the end portions 36B of the protruding fin 36. The protruding fin 36 is surrounded by the STI region 24. Each of the dummy gate stacks 38B may include a first portion (e.g., the left portion shown) that covers the end portion of the protruding fin 36, and a second portion (e.g., the right portion shown) that extends beyond the protruding fin 36. According to some embodiments, the dummy gate electrodes 42 in the dummy gate stacks 38B are referred to as polysilicon on OD edge (PODE), where the term "OD" represents an active region, such as the protruding fin 36. Similarly, at the left end (not shown) of the protruding fin 36, there may also be a dummy gate stack 38B (not shown) that covers the left edge portion of the dummy gate stack 38B.

[0028] Then, an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, thereby obtaining Figure 5A The corresponding process is Figure 23This is shown as process 410 in the illustrated process flow 400. The recess can be anisotropic, so that the portion of fin 36 directly below dummy gate stack 38 and gate spacer 46 is protected and not etched. According to some embodiments, the top surface of recessed semiconductor strip 26 can be lower than top surface 24A of STI region 24. Recess 50 is formed accordingly. Recess 50 includes portions located on opposite sides of dummy gate stack 38 and a portion between the remaining portions of protruding fin 36.

[0029] Figure 5B FIG. 1 shows a plan view of the wafer 10 after forming the groove 50, wherein the portion shown corresponds to FIG. Figure 4B shown end portion, and corresponds to Figure 5A The structure shown.

[0030] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing semiconductor material in the recesses 50 (by epitaxy). Figure 6A The corresponding process is Figure 23 In the illustrated process flow 400, it is shown as process 412. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type impurities or n-type impurities can be in-situ doped during epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, for example, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multilayer thereof. After the groove 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and a small facet can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. There may be voids (air gaps) 56. According to some embodiments of the present disclosure, the formation of epitaxial regions 54 may be completed while the top surfaces of epitaxial regions 54 are still wavy, or when the top surfaces of the merged epitaxial regions 54 have become flat.

[0031] After the epitaxial growth process, the epitaxial region 54 may be further implanted with p-type impurities or n-type impurities to form source and drain regions, which may also be denoted by reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is in-situ doped with p-type impurities or n-type impurities during epitaxy, the implantation step is skipped.

[0032] Figure 6BA plan view of a portion of wafer 10 is shown, wherein the portion shown corresponds to Figure 6A The structure shown.

[0033] Figure 7A FIG. 1 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric layer (ILD) 60. Figure 23 The process flow 400 is shown as process 414. The CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process can be performed to make the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacers 46 flush with each other.

[0034] Figure 7B The cross-sectional view of three device regions 100C, 100FE and 100IO is shown. The device region 100C may be a core (logic) device region for forming a first FinFET (which may be a core (logic) FinFET). The cross-sectional view shown in the device region 100C may be viewed from Figure 6B The reference cross section 100C-100C in FIG. 1 is obtained (except that CESL 58 and ILD 60 are also in FIG. Figure 7B The device region 100FE is a device region for forming a fin end gate structure. The cross-sectional view shown in the device region 100FE can be seen from Figure 6B 6. The cross-sectional view of the structure shown in device region 10010 can be obtained by reference cross-section 100FE-100FE in FIG. 1 (except for the addition of CESL 58 and ILD 60). Device region 10010 can be a device region for forming a second FinFET (which can be an input / output (IO) FinFET). It will be appreciated that the transistors in device regions 100C and 10010 can have different gate lengths. For example, according to some embodiments, gate length GL1 can be less than gate length GL2. The cross-sectional view of the structure shown in device region 10010 can be obtained from another protruding fin 136 ( Figure 8C , similar to fin 36 ), and the cross-sectional view is obtained from the middle portion of the protruding fin 136 .

[0035] It should be understood that although the core device area and the IO device area are taken as examples, other device areas may also be considered. Figure 7BIn the embodiment, the gate dielectrics 40 in the device regions 100C, 100FE, and 100IO can be formed to share a common formation process and thus have the same thickness. The gate dielectric 40 in the device region 100C is removed in a subsequent process and is therefore a dummy gate dielectric. The gate dielectric 40 in the device region 100IO serves as the functional gate dielectric of the IO FinFET and is therefore an active gate dielectric rather than a dummy gate dielectric. Figure 7B In FIG. 4 , STI regions 24 are shown, and protruding semiconductor fins 36 and 136 protrude above top surfaces 24A of corresponding adjacent STI regions 24 .

[0036] In the formation Figure 7A and Figure 7B After the structure shown, the dummy gate stack 38 is replaced by a replacement gate, and the formation process is carried out in Figure 8A 、 Figure 8B 、 Figure 8C and Figure 9-13 To form the replacement gate, first remove the Figure 7A and Figure 7B The hard mask layer 44 and the dummy gate electrode 42 are formed as shown in FIG. Figure 8A 、 Figure 8B and Figure 8C Grooves 62 are shown. Figure 8A 4. A perspective view of the structure is shown after removing the hard mask layer 44 and the dummy gate electrode 42. Thus, the dummy gate dielectric 40 ( Figure 8C ). The corresponding process is Figure 23 This is shown as process 416 in the illustrated process flow 400 . Figure 8B A plan view of wafer 10 is shown.

[0037] like Figure 8B As shown, the gate dielectric 40 is exposed through the trench 62. At this stage, the gate dielectric 40 covers the protruding fin 36. Each gate dielectric 40 on the fin end portion 36B includes three portions, two of which are located on opposite sidewalls of the corresponding protruding fin end portion 36B and extend along the longitudinal direction (X direction) of the corresponding protruding fin end portion 36B, and the third portion extends along the lateral direction (Y direction) of the corresponding fin end portion 36B.

[0038] Figure 8C 1 shows a cross-sectional view of the device regions 100C, 100FE, and 10010 after the dummy gate electrodes are removed. Figure 8CAs shown, in device region 100FE, gate dielectric 40 at the fin end is exposed, and in the cross section shown, gate dielectric 40 also extends over the sidewalls of protruding fin end portion 36B. According to some embodiments, removal of hard mask layer 44 from device regions 100C, 100FE, and 10010 is performed in a common process, and removal of dummy gate electrode 42 from device regions 100C, 100FE, and 10010 is performed in a common process.

[0039] refer to Figure 9 , forming and patterning an etching mask 64, which may be a photoresist. The patterned etching mask 64 remains in the device regions 100PE and 100IO and is removed from the device region 100C. Figure 23 This is shown as process 418 in the illustrated process flow 400. The trenches 62 in the device regions 100PE and 100IO are filled by etching the mask 64.

[0040] Next, refer to Figure 10 , an etching process is performed to remove the dummy gate dielectric 40 in the device region 100C. Figure 23 In the illustrated process flow 400, this is shown as process 420. According to some embodiments, the etching is anisotropic. According to alternative embodiments, the etching is isotropic. According to some embodiments in which the dummy gate dielectric 40 is formed of or includes silicon oxide, a mixture of NF3 and NH3 gases, or a mixture of HF and NH3 gases, may be used. According to other embodiments in which a wet etching process is used, an HF solution or similar etchant may be used. When anisotropic etching is used, some residual portions of the dummy gate dielectric 40 may be left and overlapped by the gate spacers 46. In other embodiments, the dummy gate dielectric 40 is completely removed from the trench 62 in the device region 100C. During the etching process, the gate dielectric 40 in the device regions 100FE and 100IO is protected from etching.

[0041] After the etching process, the etch mask 64 is removed to expose the gate dielectric 40 in the device regions 100FE and 100IO again. The resulting structure is Figure 11 The corresponding process is shown in Figure 23This is shown as process 422 in the illustrated process flow 400. Since the gate spacers 46 in the device region 100C are also exposed to the etchant used to etch the dummy gate dielectric 40 in the device region 100C, the gate spacers 46 (labeled 46A) in the device region 100C can be thinned by the etchant and can be thinner than the gate spacers 46B and 46C in the device regions 100FE and 10010, respectively. According to some embodiments, the thickness difference (T2-T1) can be in a range between about 1 nm and about 2 nm, where thickness T1 is the thickness of gate spacer 46A and thickness T2 is the thickness of gate spacers 46B and 46C. The ratio (T2-T1) / T2 can be in a range between about 0.1 and about 0.3.

[0042] Next, refer to Figure 12 , forming gate stacks 72A, 72B, and 72C, which include gate dielectrics 68A, 68B, and 68C, and gate electrodes 70A, 70B, and 70C, respectively. FinFETs 74A and 74C are thereby formed, which may be core FinFETs and IO FinFETs, respectively. Gate dielectric 68A may include dielectric layer 66 and high-k dielectric layer 67A. Dielectric layer 66 is formed on the exposed surface of protruding fin portion 36A and may be formed of or may include silicon oxide. The corresponding process is Figure 23 The process flow 400 is shown as process 424. According to some embodiments, the dielectric layer 66 is an interfacial layer (IL), which may include a native oxide layer such as Figure 11 As shown. Due to the exposure of the semiconductor material to moisture and oxygen, a native oxide layer forms on the exposed surfaces of the protruding fins 36. According to some embodiments, in addition to native oxidation, dielectric layer 66 may be formed by a chemical oxidation process or a thermal oxidation process. Dielectric layer 66 may also be formed of or include other dielectric materials, such as SiN, SiON, SiOCN, SiOC, SiO2, SiC, etc. In device regions 100FE and 100IO, the original dielectric layer 40 remains.

[0043] After forming dielectric layer 66, high-k dielectric layers 67A, 67B, and 67C are formed. Figure 23This is shown as process 426 in the illustrated process flow 400. Each of the high-k dielectric layers 67A, 67B, and 67C can be formed from a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like, combinations thereof, or multiple layers thereof. According to some embodiments of the present disclosure, the high-k dielectric layers 67A, 67B, and 67C are formed using ALD, CVD, or the like. The high-k dielectric layers 67A, 67B, and 67C can be part of the same dielectric layer and formed simultaneously using the same material and having the same thickness, or formed separately using different materials and / or having different thicknesses. The dielectric layer (IL) 66 and the overlying high-k dielectric layer 67A are collectively referred to as the gate dielectric layer 68A. The dielectric layer 40 in the device region 100FE and the overlying high-k dielectric layer 67B are collectively referred to as the gate dielectric layer 68B. The dielectric layer 40 in the device region 10010 and the overlying high-k dielectric layer 67C are collectively referred to as a gate dielectric layer 68C. The high-k dielectric layers 67A, 67B, and 67C may be formed in the same deposition process(es) and may have the same thickness.

[0044] Then, gate electrodes 70A, 70B and 70C are formed. Figure 23 This is shown as process 428 in the illustrated process flow 400. According to some embodiments of the present disclosure, each of gate electrodes 70A, 70B, and 70C can have a composite structure including multiple layers. According to some embodiments, gate electrodes 70A, 70B, and 70C are formed simultaneously and share a common formation process, and therefore have the same material layers and the same thickness. According to alternative embodiments, gate electrodes 70A, 70B, and 70C can be formed in separate processes and can have the same or different structures, and have the same or different materials, and have the same or different thicknesses.

[0045] According to some embodiments, each of the gate electrodes 70A, 70B, and 70C may have a diffusion barrier layer, a work function layer on the diffusion barrier layer, a cap layer on the work function layer, and a fill metal region on the cap layer. The diffusion barrier layer may be formed of, or may include, TiN, TiSiN, or the like. The work function layer may be formed of, or may include, a material selected based on whether the corresponding FinFET formed in the device regions 100C and 100IO is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the corresponding work function layer may include an aluminum-based layer (formed of, for example, TiAl, TiAlN, TiAlC, TaAlN, or TaAlC, or including these items). When the FinFET is a p-type FinFET, the corresponding work function layer may include a TiN layer and a TaN layer. The cap layer (also referred to as a barrier layer) may be formed of, or may include, TiN, TaN, or the like. The diffusion barrier layer, the work function layer, and the cap layer may be deposited using ALD, CVD, etc. The fill metal region may be formed of or may include tungsten, cobalt, etc.

[0046] exist Figure 12 In the embodiment, the gate dielectric 66 is formed in a different process from the dielectric layer 40 in the device regions 100FE and 100IO. Since the dielectric layers 40 in the device region 100IO may be used for IO devices, they are relatively thick, for example, with a thickness T4 of about 1000nm. With In addition, the thickness of the dielectric layer 40 in the device regions 100FE and 100IO can be equal to or substantially equal to each other, for example, with a difference of less than about 20%. On the other hand, the gate dielectric 66 can be formed for the core device, and the thickness T3 is less than the thickness T4. For example, the thickness T3 can be about With The ratio T4 / T3 is related to the performance and reliability requirements of the devices in the device regions 100C and 100IO. For example, the effective oxide thickness (EOT) of the devices in the device region 100C is low to achieve a higher speed, and the thickness T3 is small, while a larger thickness T4 can improve the device reliability of the IO devices. Therefore, according to some embodiments, the ratio T4 / T3 can be in the range between about 4.0 and about 6.0.

[0047] Figure 13 A perspective view of FinFET 74A or 74C is shown. Gate contact plug 114, source / drain silicide regions 110, source / drain contact plug 112, and hard mask 116 are shown.

[0048] In the above forming process, for example, Figure 10 and Figure 11 In the process shown, when the dielectric layer 40 is removed from the device region 100C, the dielectric layer 40 is not removed from the fin end device region 100FE. Figure 12 As integrated circuits become increasingly smaller, fin end portions 36B may be damaged, for example, during a subsequent cleaning process. If fin end portions 36B are damaged, adjacent source / drain regions 54 may be damaged. Therefore, retaining dielectric layer 40 in device region 100FE serves to protect end portions 36B below protruding fins 36 and adjacent source / drain regions.

[0049] Embodiments of the present disclosure may be applied to other protruding structures and may be used to form other types of transistors (eg, nanosheet transistors, nanowire transistors, and / or gate-all-around (GAA) transistors) and corresponding fin-end gate structures. Figure 14-21 、 Figure 22A and Figure 22B Cross-sectional views of intermediate stages in the formation of GAA transistors (which may also be nanosheet transistors or nanowire transistors) and corresponding fin-end gate structures according to some embodiments of the present disclosure are shown. Unless otherwise noted, the materials and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the previous embodiments shown in the previous figures. Therefore, details about the formation processes and materials of the components shown in the previous figures can be found in the discussion of the previous embodiments.

[0050] refer to Figure 14 , forming a protruding fin 36', and forming a gate stack 38 and a gate spacer 46 on the sidewalls and top surface of the protruding fin 36'. The protruding fin 36' may include a stack layer 76, which includes a channel layer 78 (see Figure 15 ) and a sacrificial film 80. For example, the total number of channel layers 78 and the total number of sacrificial films 80 may be in a range between 1 and 10, inclusive. It is understood that although the sacrificial film 80 is shown as the top layer of the stacked layer 76 in the illustrated example embodiment, according to other embodiments, the channel layer may be the top layer of the stacked layer 76. The materials of the channel layer 78 and the sacrificial film 80 are different from each other. According to some embodiments, the channel layer 78 is formed of or includes Si, SiGe, etc. The sacrificial film 80 may be formed of or include SiGe, SiP, SiOCN, SiC, etc. The thickness of each of the channel layer 78 and the sacrificial film 80 may be about peace treaty The stacked layer 76 overlaps with the semiconductor strip 26 . Figure 14The structure shown is formed by a process similar to that of Figure 1-3 and Figure 4A The process shown is different in that Figures 1 to 3 Prior to the illustrated process, a stack of layers 76 is preformed, for example by epitaxy.

[0051] Figure 15 Shown Figure 14 The top view of the structure shown in FIG. Figure 4B is similar to the top view shown in , except that Figure 14 The protruding fin 36' replaces the Figure 4B The protruding fin 36 in the.

[0052] Then, execute Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A and Figure 7B The process shown is to form source / drain regions 54, CESL 58 and ILD 60. The resulting structure is Figure 16 , which includes cross-sectional views respectively obtained from a middle portion and an end portion of the same protruding fin 36 ′. Figure 16 100C and 100FE are cross-sectional views of the structures in the device regions 100C and 100FE, respectively. Figure 15 The reference cross sections 100C-100C and 100FE-100FE are shown. Figure 16 In the example process of forming the inner spacer 82, the inner spacer 82 is formed. Figure 5A After the fin etching process shown, the sidewalls of the sacrificial film 80 are exposed. An oxidation process is performed to oxidize the end portions of the sacrificial film 80, thereby forming oxide regions to serve as internal spacers 82. The material of the internal spacers 82 may depend on the material of the sacrificial film 80 and may include oxides of SiGe, SiP, SiOCN, SiC, etc. The width W1 of the internal spacers 82 may be approximately peace treaty within the range between.

[0053] Next, the hard mask 44 and the dummy gate electrode 42 are removed to form the trench 62, and the resulting structure is Figure 17 The gate dielectric 40 is exposed in both the device regions 100C and 100FE. Figure 18 , a patterned etch mask 64 is formed to fill the trenches 62 in the device region 100FE, while the etch mask 64 is removed from the device region 100C.

[0054] Next, the dummy gate dielectric layer 40 is removed from the device region 100C while protecting the gate dielectric layer 40 in the device region 100FE from being removed. Figure 19 The etch mask 64 is then removed and the resulting structure is shown in FIG. Figure 20 In a subsequent process, the sacrificial film 80 is removed from the middle fin portion 36A', and the resulting structure is Figure 21 . According to some embodiments, the inner spacer 82 is not removed and will remain in the final GAA transistor. The inner spacer 82 can protect the source / drain regions 54 from damage when the sacrificial film 80 is removed, and can isolate the subsequently formed gate stack from shorting with the source / drain regions 54. As a result of removing the sacrificial film 80, a space is formed between the channel layers 78.

[0055] When the sacrificial film 80 is removed, the remaining dielectric layer 40 in the trench 62 protects the corresponding fin end portion 36B' of the protruding fin from being removed. Therefore, in the final structure, the fin end portion 36B' of the protruding fin 36' remains unremoved. In addition, when the sacrificial film 80 is removed from the middle fin portion 36A', the sacrificial film 80 in the end portion 36B' is protected from removal and will remain in the final structure.

[0056] In subsequent processing, replacement gate stacks 72A and 72B are formed. Thus, GAA transistor 86 is formed. During formation, dielectric layer 66 is first formed to surround channel layer 78. This dielectric layer may include a native oxide and may be an oxide layer formed by chemical or thermal oxidation of a surface portion of channel layer 78. Gate stack 72A includes dielectric layer 66, high-k dielectric layer 67A, and gate electrode 70A. High-k dielectric layer 67A and gate electrode 70A may extend into the space between adjacent channel layers 78. Fin-end gate structure 72B includes dielectric layer 40, high-k dielectric layer 67B, and gate electrode 70B.

[0057] Figure 22B Shown from Figure 22A The reference cross section 22B-22B shown is a reference cross section obtained and illustrates the channel and gate portions of the GAA transistor 86. Additionally, a device region 10010 is also illustrated.

[0058] Embodiments of the present disclosure have several advantageous features. When removing the dummy gate dielectric from some device regions (e.g., core device regions), the dielectric layer formed on the fin ends of the protruding fins is protected from removal. The remaining dielectric layer on the fin ends of the protruding fins protects the end portions of the protruding fins from damage, and the end portions of the protruding fins can further protect the adjacent source / drain regions.

[0059] According to some embodiments of the present disclosure, a method includes: depositing a stack of layers on a first protruding fin; patterning the stack of layers to form the following: a first gate stack comprising: a first gate dielectric on a middle portion of the first protruding fin; and a first gate electrode on the first gate dielectric; and a second gate stack comprising: a second gate dielectric on an end portion of the first protruding fin; and a second gate electrode on the second gate dielectric; removing the first gate electrode and the second gate electrode to expose the first gate dielectric and the second gate dielectric, respectively; removing the first gate dielectric, wherein the second gate dielectric remains after the first gate dielectric is removed; forming a replacement gate dielectric on the middle portion of the first protruding fin; and forming a first replacement gate electrode and a second replacement gate electrode on the replacement gate dielectric and the second gate dielectric, respectively. In one embodiment, the replacement gate dielectric is formed to have a thickness less than that of the first gate dielectric. In one embodiment, removing the first gate dielectric includes: forming an etch mask to cover the second gate dielectric, wherein the etch mask protects the second gate dielectric when the first gate dielectric is removed; and removing the etch mask. In one embodiment, the method further includes: forming a third gate stack during the formation of the first gate stack, comprising: a third gate dielectric on a further middle portion of the second protruding fin; and a third gate electrode on the third gate dielectric; removing the third gate electrode to expose the third gate dielectric, wherein the third gate dielectric remains after the first gate dielectric is removed; and forming a third replacement gate electrode on the third gate dielectric. In one embodiment, the method further includes: forming an isolation region extending into the semiconductor substrate before forming the stacked layers; and forming a first protruding fin protruding above the isolation region, wherein the isolation region includes portions located on opposite sides of the first protruding fin. In one embodiment, the entire first protruding fin is semiconductor. In one embodiment, the first protruding fin includes multiple channel layers; and multiple sacrificial films, wherein the multiple channel layers and the multiple sacrificial films are alternately arranged to form another layer stack. In one embodiment, the method further includes: removing the multiple sacrificial films from the middle portion of the first protruding fin. In one embodiment, when the multiple sacrificial films are removed from the middle portion of the first protruding fin, the multiple sacrificial films in the end portions of the first protruding fin are protected from removal by the second gate dielectric.

[0060] According to some embodiments of the present disclosure, a method includes: simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin; simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively; forming an etch mask, wherein the etch mask fills the first trench and the second trench; patterning the etch mask to remove the etch mask from the first trench; removing the first dummy gate dielectric of the first dummy gate stack, wherein the etch mask protects the second gate dielectric of the first dummy gate stack from being removed; and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively. In one embodiment, the second dummy gate stack extends on a first sidewall surface, a second sidewall surface, and a third sidewall surface of the protruding fin, wherein the first sidewall surface and the second sidewall surface are along a longitudinal direction of the protruding fin, and the third sidewall surface is along a lateral direction of the protruding fin. In one embodiment, the first dummy gate dielectric includes a first silicon oxide layer having a first thickness, and forming the first replacement gate stack includes forming a second silicon oxide layer having a second thickness less than the first thickness. In one embodiment, the method further comprises: forming a source region and a drain region on opposite sides of the first dummy gate stack; and forming an additional source / drain region on one side of the second dummy gate stack, wherein the protruding fin terminates directly below the second dummy gate stack. In one embodiment, forming the etch mask comprises: dispensing photoresist.

[0061] According to some embodiments of the present disclosure, a structure includes: an isolation region extending into a semiconductor substrate; a protruding fin between portions of the isolation region, wherein the protruding fin protrudes above the isolation region; a first gate stack comprising: a first gate dielectric on a first sidewall and a first top surface of a first portion of the protruding fin, wherein the first gate dielectric has a first thickness; and a first gate electrode on the first gate dielectric; and a second gate stack comprising: a second gate dielectric on a second sidewall and a second top surface of a second portion of the protruding fin, wherein the protruding fin terminates directly below the second gate stack and the second gate dielectric has a second thickness greater than the first thickness; and a second gate electrode on the second gate dielectric. In one embodiment, the first gate dielectric comprises a first oxide layer and a first high-k dielectric layer above the first oxide layer, and the second gate dielectric comprises a second oxide layer and a second high-k dielectric layer above the second oxide layer, wherein the second oxide layer is thicker than the first oxide layer. In one embodiment, the first high-k dielectric layer and the second high-k dielectric layer are formed of the same material. In one embodiment, the ratio of the second thickness to the first thickness is in a range between approximately 4 and approximately 6. In one embodiment, the structure further includes: a source region and a drain region located on opposite sides of the first gate stack; and an additional source / drain region located on one side of the second gate stack. In one embodiment, the second gate dielectric further extends over an additional sidewall of the second portion of the protruding fin, and the additional sidewall extends in a direction perpendicular to the longitudinal direction of the protruding fin.

[0062] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0063] Example 1. A method comprising: depositing a stack of layers on a first protruding fin; patterning the stack of layers to form: a first gate stack comprising: a first gate dielectric on a middle portion of the first protruding fin; and a first gate electrode on the first gate dielectric; and a second gate stack comprising: a second gate dielectric on an end portion of the first protruding fin; and a second gate electrode on the second gate dielectric; removing the first gate electrode and the second gate electrode to expose the first gate dielectric and the second gate dielectric, respectively; removing the first gate dielectric, wherein the second gate dielectric remains after the first gate dielectric is removed; forming a replacement gate dielectric on the middle portion of the first protruding fin; and forming a first replacement gate electrode and a second replacement gate electrode on the replacement gate dielectric and the second gate dielectric, respectively.

[0064] Example 2. The method of example 1, wherein the replacement gate dielectric is formed to have a smaller thickness than the first gate dielectric.

[0065] Example 3. The method of Example 1, wherein removing the first gate dielectric comprises: forming an etch mask to cover the second gate dielectric, wherein the etch mask protects the second gate dielectric when the first gate dielectric is removed; and removing the etch mask.

[0066] Example 4. The method according to Example 1 further includes: forming a third gate stack when forming the first gate stack, the third gate stack including: a third gate dielectric on another middle portion of the second protruding fin; and a third gate electrode on the third gate dielectric; removing the third gate electrode to expose the third gate dielectric, wherein the third gate dielectric remains after the first gate dielectric is removed; and forming a third replacement gate electrode on the third gate dielectric.

[0067] Example 5. The method according to Example 1 further includes: before forming the stacked layer: forming an isolation region extending into the semiconductor substrate; and forming the first protruding fin protruding higher than the isolation region, wherein the isolation region includes a portion located on opposite sides of the first protruding fin.

[0068] Example 6. The method of example 1, wherein the entire first protruding fin is semiconductor.

[0069] Example 7. The method of Example 1, wherein the first protruding fin comprises: a plurality of channel layers; and a plurality of sacrificial films, wherein the plurality of channel layers and the plurality of sacrificial films are alternately allocated.

[0070] Example 8. The method of Example 7, further comprising removing the plurality of sacrificial films from the middle portion of the first protruding fin.

[0071] Example 9. The method of Example 8, wherein when removing the plurality of sacrificial films from the middle portion of the first protruding fin, the plurality of sacrificial films in the end portions of the first protruding fin are protected from being removed by the second gate dielectric.

[0072] Example 10. A method comprising: simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin; simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively; forming an etch mask, wherein the etch mask fills the first trench and the second trench; patterning the etch mask to remove the etch mask from the first trench; removing the first dummy gate dielectric of the first dummy gate stack, wherein the etch mask protects the second gate dielectric of the first dummy gate stack from being removed; and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

[0073] Example 11. A method according to Example 10, wherein the second dummy gate stack extends on a first sidewall surface, a second sidewall surface, and a third sidewall surface of the protruding fin, wherein the first sidewall surface and the second sidewall surface are along a longitudinal direction of the protruding fin, and the third sidewall surface is along a lateral direction of the protruding fin.

[0074] Example 12. The method of Example 10, wherein the first dummy gate dielectric comprises a first silicon oxide layer having a first thickness, and forming the first replacement gate stack comprises forming a second silicon oxide layer having a second thickness less than the first thickness.

[0075] Example 13. The method according to Example 10 further includes: forming a source region and a drain region on opposite sides of the first dummy gate stack; and forming an additional source / drain region on one side of the second dummy gate stack, wherein the protruding fin terminates at a position directly below the second dummy gate stack.

[0076] Example 14. The method of Example 10, wherein forming the etch mask comprises dispensing photoresist.

[0077] Example 15. A structure comprising: an isolation region extending into a semiconductor substrate; a protruding fin between portions of the isolation region, wherein the protruding fin protrudes above the isolation region; a first gate stack comprising: a first gate dielectric on a first sidewall and a first top surface of a first portion of the protruding fin, wherein the first gate dielectric has a first thickness; and a first gate electrode on the first gate dielectric; and a second gate stack comprising: a second gate dielectric on a second sidewall and a second top surface of a second portion of the protruding fin, wherein the protruding fin terminates directly below the second gate stack and the second gate dielectric has a second thickness greater than the first thickness; and a second gate electrode on the second gate dielectric.

[0078] Example 16. A structure according to Example 15, wherein the first gate dielectric includes a first oxide layer and a first high-k dielectric layer located above the first oxide layer, and the second gate dielectric includes a second oxide layer and a second high-k dielectric layer located above the second oxide layer, and the second oxide layer is thicker than the first oxide layer.

[0079] Example 17. The structure of Example 16, wherein the first high-k dielectric layer and the second high-k dielectric layer are formed of the same material.

[0080] Example 18. The structure of Example 16, wherein a ratio of the second thickness to the first thickness is in a range between about 4 and about 6.

[0081] Example 19. The structure of Example 15 further includes: a first gate spacer on a sidewall of the first gate stack; and a second gate spacer on a sidewall of the second gate stack, wherein the first gate spacer is thinner than the second gate spacer.

[0082] Example 20. The structure of Example 15, wherein the second gate dielectric further extends over an additional sidewall of the second portion of the protruding fin, and the additional sidewall extends in a direction perpendicular to a longitudinal direction of the protruding fin.

Claims

1. A method for forming a semiconductor device, comprising: depositing a stack of layers on the first protruding fin; The stack of layers is patterned to form the following: A first gate stack comprising: a first gate dielectric on a middle portion of the first protruding fin; and a first gate electrode on the first gate dielectric; and The second gate stack comprises: a second gate dielectric on an end portion of the first protruding fin; and a second gate electrode on the second gate dielectric; removing the first gate electrode and the second gate electrode to expose the first gate dielectric and the second gate dielectric, respectively; removing the first gate dielectric, wherein the second gate dielectric remains after the first gate dielectric is removed; forming a replacement gate dielectric on the middle portion of the first protruding fin; and A first replacement gate electrode and a second replacement gate electrode are formed on the replacement gate dielectric and the second gate dielectric, respectively.

2. The method according to claim 1, wherein: The replacement gate dielectric is formed to have a smaller thickness than the first gate dielectric.

3. The method according to claim 1, wherein: Removing the first gate dielectric includes: forming an etch mask to cover the second gate dielectric, wherein the etch mask protects the second gate dielectric when the first gate dielectric is removed; and The etching mask is removed.

4. The method according to claim 1, further comprising: When forming the first gate stack, a third gate stack is formed, and the third gate stack includes: a third gate dielectric on the other middle portion of the second protruding fin; and a third gate electrode on the third gate dielectric; removing the third gate electrode to expose the third gate dielectric, wherein the third gate dielectric remains after the first gate dielectric is removed; and A third replacement gate electrode is formed on the third gate dielectric.

5. The method according to claim 1, further comprising: Before forming the stacked layers: forming an isolation region extending into the semiconductor substrate; as well as The first protruding fin is formed to protrude higher than the isolation region, wherein the isolation region includes portions located at opposite sides of the first protruding fin.

6. The method according to claim 1, wherein: The entire first protruding fin is semiconductor.

7. The method according to claim 1, wherein: The first protruding fin comprises: a plurality of channel layers; and a plurality of sacrificial films, wherein the plurality of channel layers and the plurality of sacrificial films are alternately allocated.

8. The method according to claim 7, further comprising: The plurality of sacrificial films are removed from the middle portion of the first protruding fin.

9. The method according to claim 8, wherein: When the plurality of sacrificial films are removed from the middle portion of the first protruding fin, the plurality of sacrificial films in the end portion of the first protruding fin are protected by the second gate dielectric and are not removed.

10. A method for forming a semiconductor device, comprising: forming a first dummy gate stack and a second dummy gate stack simultaneously on the first portion and the second portion of the protruding fin; Simultaneously removing the first gate electrode of the first dummy gate stack and the second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively; forming an etching mask, wherein the etching mask fills the first trench and the second trench; patterning the etch mask to remove the etch mask from the first trench; removing a first dummy gate dielectric of the first dummy gate stack, wherein the etch mask protects a second gate dielectric of the first dummy gate stack from being removed; and A first replacement gate stack and a second replacement gate stack are formed in the first trench and the second trench, respectively.

11. The method according to claim 10, wherein: The second dummy gate stack extends on a first sidewall surface, a second sidewall surface, and a third sidewall surface of the protruding fin, wherein the first sidewall surface and the second sidewall surface are along a longitudinal direction of the protruding fin, and the third sidewall surface is along a lateral direction of the protruding fin.

12. The method according to claim 10, wherein: The first dummy gate dielectric includes a first silicon oxide layer having a first thickness, and forming the first replacement gate stack includes forming a second silicon oxide layer having a second thickness less than the first thickness.

13. The method according to claim 10, further comprising: forming a source region and a drain region on opposite sides of the first dummy gate stack; as well as An additional source / drain region is formed on one side of the second dummy gate stack, wherein the protruding fin terminates at a location directly below the second dummy gate stack.

14. The method according to claim 10, wherein: Forming the etching mask includes dispensing a photoresist.

15. A semiconductor structure comprising: an isolation region extending into the semiconductor substrate; a protruding fin between portions of the isolation region, wherein the protruding fin protrudes higher than the isolation region; A first gate stack comprising: a first gate dielectric on a first sidewall and a first top surface of a first portion of the protruding fin, wherein the first gate dielectric has a first thickness; and a first gate electrode on the first gate dielectric; and The second gate stack comprises: a second gate dielectric on second sidewalls and a second top surface of a second portion of the protruding fin, wherein the protruding fin terminates directly below the second gate stack, and the second gate dielectric has a second thickness greater than the first thickness, wherein a ratio of the second thickness to the first thickness is in a range between 4 and 6; and a second gate electrode on the second gate dielectric, The second gate stack includes a first sidewall and a second sidewall opposite to each other, the first sidewall is located directly above the second portion of the protruding fin, and the second sidewall is offset from the second portion of the protruding fin.

16. The structure according to claim 15, wherein: The first gate dielectric includes a first oxide layer and a first high-k dielectric layer over the first oxide layer, and the second gate dielectric includes a second oxide layer and a second high-k dielectric layer over the second oxide layer, and the second oxide layer is thicker than the first oxide layer.

17. The structure according to claim 16, wherein: The first high-k dielectric layer and the second high-k dielectric layer are formed of the same material.

18. The structure of claim 15, further comprising: a first gate spacer on a sidewall of the first gate stack; as well as A second gate spacer is on a sidewall of the second gate stack, wherein the first gate spacer is thinner than the second gate spacer.

19. The structure of claim 15, wherein: The second gate dielectric further extends on an additional sidewall of the second portion of the protruding fin, and the additional sidewall extends in a direction perpendicular to a longitudinal direction of the protruding fin.

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