Semiconductor Device and Method of Forming the Same

Abstract

A device includes: a semiconductor region; an interface layer located above the semiconductor region, the interface layer including a semiconductor oxide; a high-k dielectric layer located above the interface layer; a hybrid layer located above the high-k dielectric layer. The hybrid layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work function layer is located above the hybrid layer. A fill metal region is located above the work function layer. Embodiments of the present application also provide a semiconductor device and a method for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and more particularly, to semiconductor devices and methods of forming the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices are basic building blocks in integrated circuits. A MOS device may have a gate electrode formed of polysilicon doped with p-type or n-type impurities, and the p-type or n-type impurities are doped using doping processes such as ion implantation or thermal diffusion. The work function of the gate electrode can be adjusted to the band edge of silicon. For n-type metal oxide semiconductor (NMOS) devices, the work function can be adjusted to be close to the conduction band of silicon. For p-type metal oxide semiconductor (PMOS) devices, the work function can be adjusted to be close to the valence band of silicon. The adjustment of the work function of the polysilicon gate electrode can be achieved by selecting appropriate impurities.

[0003] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, which is also known as the polysilicon depletion effect. The polysilicon depletion effect occurs when the applied electric field sweeps carriers from the gate region near the gate dielectric to form a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized immobile donor sites, and in a p-doped polysilicon layer, the depletion layer includes ionized immobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult to form an inversion layer on the semiconductor surface.

[0004] The polysilicon depletion problem can be solved by forming a metal gate electrode, and the metal gate used in NMOS devices and PMOS devices can also have a work function at the band edge. Therefore, the resulting metal gate includes multiple layers to meet the requirements of NMOS devices and PMOS devices.

[0005] The formation of the metal gate generally involves depositing a metal layer and then performing a chemical mechanical polishing (CMP) process to remove the excess portion of the metal layer. The remaining portion of the metal layer forms the metal gate. Summary of the Invention

[0006] Embodiments of the present application provide a device, comprising: a semiconductor region; an interface layer located above the semiconductor region, the interface layer comprising a semiconductor oxide; a high-k dielectric layer located above the interface layer; a hybrid layer located above the high-k dielectric layer, wherein the hybrid layer comprises oxygen, a metal in the high-k dielectric layer, and an additional metal; a work function layer located above the hybrid layer; and a fill metal region located above the work function layer.

[0007] Embodiments of the present application further provide a device, including: a silicon germanium fin; a gate stack located on the silicon germanium fin, wherein the gate stack includes: an interface layer contacting the silicon germanium fin; a high-k dielectric layer located above the interface layer; a hybrid layer located above the high-k dielectric layer and contacting the high-k dielectric layer, wherein the high-k dielectric layer has a first dielectric constant, the hybrid layer has a second dielectric constant, and the second dielectric constant is greater than the first dielectric constant; and a titanium nitride layer located above the hybrid layer and contacting the hybrid layer; and source / drain regions located on the sides of the gate stack.

[0008] Embodiments of the present application also provide a method, including: forming an interface layer above a semiconductor region, wherein the interface layer includes a semiconductor oxide; depositing a high-k dielectric layer above the interface layer; depositing a barrier layer above the high-k dielectric layer; depositing a metal layer on the barrier layer; performing an annealing process when the metal layer is located above the barrier layer; and removing the metal layer.

[0009] Embodiments of the present application provide a transistor with reduced defects and a method for forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0011] Figures 1 - 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figures 11 - 18 、 Figure 23 and Figure 24 show a perspective view and a cross-sectional view of an intermediate stage in the formation of a fin field-effect transistor (FinFET) according to some embodiments;

[0012] Figure 19 and Figure 20 show a cross-sectional view of some parts of the gate stack of a FinFET according to some embodiments;

[0013] Figure 21 and Figure 22 show a cross-sectional view of an intermediate stage in the formation of the gate stack of a FinFET according to some embodiments;

[0014] Figures 25 to 30 show the results of a sample FinFET according to some embodiments;

[0015] Figure 31 and Figure 32 respectively illustrate a comparison of gate stacks of p-type and n-type transistors in accordance with some embodiments;

[0016] Figure 33 illustrates a process flow for forming a gate stack in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0018] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0019] According to various embodiments, a transistor with a replacement gate and a method of forming the same are provided. According to some embodiments, intermediate stages of the formation of a transistor are shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numerals are used to indicate like elements. In the illustrated exemplary embodiment, the formation of a fin field-effect transistor (FinFET) is used as an example to explain the concept of the present invention. Other types of transistors, such as planar transistors and gate-all-around (GAA) transistors, may also adopt the concept of the present invention. According to some embodiments of the present invention, a silicon-germanium fin is formed. An interface layer (IL) including silicon oxide and germanium oxide is formed on the silicon-germanium fin, and then a high-k dielectric layer is deposited. A metal layer is formed above the high-k dielectric layer. An annealing process is implemented. The annealing process causes oxygen atoms in the IL to diffuse into and bond with the metal in the metal layer. On the other hand, germanium atoms in the IL diffuse downward into the silicon-germanium fin. As a result, the IL becomes rich in silicon due to the removal of germanium oxide. The IL also becomes thinner, and the effective oxide thickness (EOT) of the gate dielectric decreases. The underlying germanium-containing fin becomes rich in germanium, which increases the channel mobility.

[0020] Figures 1 - 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figures 11 - 18 , Figure 23 and Figure 24 show a cross-sectional view and a perspective view of an intermediate stage in the formation of a fin field-effect transistor (FinFET) according to some embodiments of the present invention. The processes shown in these figures are also schematically reflected in Figure 33 the process flow 200 shown in.

[0021] In Figure 1In this case, a substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be a part of a wafer 10 such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as a multi-layer substrate or a gradient substrate. In some embodiments, the semiconductor material of the semiconductor substrate 20 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0022] Further referring to Figure 1 , a well region 22 is formed in the substrate 20. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 202. According to some embodiments of the present invention, the well region is an n-type well region, which is formed by implanting an n-type impurity into the substrate 20, and the n-type impurity can be phosphorus, arsenic, antimony, etc. According to other embodiments of the present invention, the well region 22 is a p-type well region, which is formed by implanting a p-type impurity into the substrate 20, and the p-type impurity can be boron, indium, etc. The resulting well region 22 can extend to the top surface of the substrate 20. The n-type or p-type impurity concentration can be equal to or less than 10 18 cm -3 , for example, in the range between about 10 17 cm -3 and about 10 18 cm -3 .

[0023] Referring to Figure 2 , an isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 can alternatively be referred to as a shallow trench isolation (STI) region. In Figure 33In the process flow 200 shown, the corresponding process is shown as process 204. The portion of the substrate 20 between adjacent STI regions 24 is referred to as a semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed by oxidizing silicon. According to some embodiments of the present invention, the pad oxide layer 28 is formed in a thermal oxidation process in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present invention, the hard mask layer 30 is formed, for example, by silicon nitride using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present invention, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, the patterned photoresist is used as an etch mask to pattern the hard mask layer 30 to form the hard mask 30 as shown in Figure 2 shown.

[0024] Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with (some) dielectric material. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove the excess portion of the dielectric material, and the remaining portion of the (some) dielectric material becomes the STI region 24. The STI region 24 may include a pad dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The pad dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc., which are formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include a dielectric material located above the pad oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the pad dielectric may include silicon oxide.

[0025] The top surface of the hard mask 30 and the top surface of the STI region 24 can be substantially flush with each other. The semiconductor strip 26 is located between adjacent STI regions 24. According to some embodiments of the present invention, the semiconductor strip 26 is a part of the original substrate 20, so the material of the semiconductor strip 26 is the same as that of the substrate 20. According to an alternative embodiment of the present invention, the semiconductor strip 26 is a replacement strip formed by etching a portion of the substrate 20 between the STI regions 24 to form a recess and performing epitaxy to regrow another semiconductor material in the recess. Therefore, the semiconductor strip 26 is formed of a semiconductor material different from that of the substrate 20. According to some embodiments, the semiconductor strip 26 is formed of a germanium-containing material such as silicon germanium. According to some embodiments, the percentage of germanium atoms in the protruding fin 36 can be in the range between about 30% and about 70%.

[0026] Reference Figure 3 , the STI region 24 is recessed so that the top of the semiconductor strip 26 protrudes above the top surface 24A of the remaining part of the STI region 24 to form a protruding fin 36. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 206. A dry etching process can be used to perform the etching, where, for example, HF3 and NH3 are used as etching gases. During the etching process, a plasma may be generated. Argon can also be included. According to an alternative embodiment of the present invention, a wet etching process is used to recess the STI region 24. The etching chemical can include, for example, HF.

[0027] According to some embodiments of the present invention, the protruding fin 36 is formed of a germanium-containing material such as silicon germanium. According to an alternative embodiment, the protruding fin 36 includes silicon and does not contain germanium. Semiconductor fins including germanium and semiconductor fins without germanium can be formed in the same wafer. For example, reference Figure 8B , in the wafer 10, there can be an n-type FinFET region 21N and a p-type FinFET region 21P where an n-type FinFET and a p-type FinFET are to be formed respectively. The protruding fin 36A can be a silicon fin (without germanium), while the protruding fin 36B can be a silicon germanium fin. In the following discussion, unless otherwise specified, the protruding fin refers to the protruding fin 36B that can be formed of silicon germanium.

[0028] In the embodiments shown above, the fins can be patterned by any suitable method. For example, one or more lithography processes including double patterning or multiple patterning processes can be used to pattern the fins. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the created pattern to have, for example, a pitch smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0029] Reference Figure 4 , a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (projecting) fins 36. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 208. The dummy gate stack 38 can include a dummy gate dielectric 40 and a dummy gate electrode 42 located above the dummy gate dielectric 40. The dummy gate electrode 42 can be formed using, for example, polysilicon and can also use other materials. Each dummy gate stack 38 can also include one (or more) hard mask layers 44 located above the dummy gate electrode 42. The hard mask layer 44 can be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 can span across a single or multiple projecting fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the projecting fins 36.

[0030] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. In Figure 33 the process flow 200 shown, the corresponding process is also shown as process 208. According to some embodiments of the present invention, the gate spacers 46 are formed of (some) dielectric materials such as silicon nitride, silicon carbonitride, etc., and can have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0031] Then, an etching process is performed to etch the portions of the projecting fins 36 not covered by the dummy gate stack 38 and the gate spacers 46, thereby obtaining Figure 5 the structure shown. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 210. The recess can be anisotropic, so that the portions of the fins 36 directly under the dummy gate stack 38 and the gate spacers 46 are protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24A of the STI region 24. A recess 50 is correspondingly formed. The recess 50 includes portions located on opposite sides of the dummy gate stack 38 and portions located between the remaining portions of the projecting fins 36.

[0032] Next, an epitaxial region (source / drain region) 54 is formed by selectively growing (by epitaxy) a semiconductor material in the recess 50, resulting in Figure 6 the structure shown. In the process flow 200 shown in Figure 33 , the corresponding process is shown as process 212. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in-situ as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present invention, the epitaxial region 54 comprises a group III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After filling the recess 50 with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally and can form facets. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. Voids (air gaps) 56 may be generated.

[0033] Figure 7A A perspective view of the structure after forming the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60 is shown. In the Figure 33 process flow 200 shown, the corresponding process is shown as process 214. The CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can comprise a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide based on materials such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as a CMP process or a mechanical polishing process, can be implemented to make the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacers 46 flush with each other.

[0034] Figure 7B shows Figure 7A reference cross-section 7B-7B in, in which the dummy gate stack 38 is shown. Next, as shown in Figure 8A , in (some) etching processes, the dummy gate stack 38 including the hard mask layer 44, the dummy gate electrode 42, and the dummy gate dielectric 40 is removed to form a trench 62 between the gate spacers 46. In Figure 33In the process flow 200 shown, the corresponding process is shown as process 216. As Figure 8B shown, the top surface and sidewalls of the protruding fin 36 are exposed to the trench 62. Figure 8B A cross-sectional view obtained from the reference section 8B-8B in Figure 8A is shown, which shows both the N-type transistor region 21N and the p-type transistor region 21P. Additionally, as previously described, the protruding fin 36 can include a silicon-containing fin 36A (which may not contain germanium) located in the n-type FinFET region 21N, and a germanium-containing fin 36B (which may include silicon germanium) located in the p-type FinFET region 21P.

[0035] Figure 9 It is shown that IL 64A and 64B are respectively formed on the protruding fins 36A and 36B through an oxidation process. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 218. According to some embodiments, the oxidation process includes a chemical oxidation process, which is implemented by contacting the wafer in a chemical solution that includes a mixture of one or more of ozone (O3) deionized (DI) water, hydrogen peroxide (H2O2), sulfuric acid (H2SO4), ammonium hydroxide (NH4OH), etc. or a combination thereof. The oxidation process can be implemented in a temperature range from room temperature (e.g., about 21 °C) to about 80 °C. According to an alternative embodiment, the oxidation process includes a thermal oxidation process, in which the wafer 10 is annealed in an oxygen-containing environment that includes oxygen (O2), ozone (O3), etc. IL64A can include silicon oxide (SiO2) and may not contain germanium oxide. IL 64B can include silicon oxide and germanium oxide (which is also referred to as silicon germanium oxide).

[0036] Next, as Figure 10A and Figure 10B shown, additional components are formed to obtain a replacement gate stack 72 filled in the trench 62 ( Figure 8A ). Figure 10B A reference cross-section 10B-10B in Figure 10A is shown. The replacement gate stack 72 includes a gate dielectric 67 and a corresponding gate electrode 70.

[0037] As Figure 10B shown, the gate dielectric 67 includes IL 64 and a high-k dielectric layer 66 formed above IL 64. In Figure 33In the process flow 200 shown, the process of forming the high-k dielectric layer 66 is shown as process 220. The high-k dielectric layer 66 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and can be higher than about 7.0, sometimes as high as 21.0 or higher. The high-k dielectric layer 66 is formed as a conformal layer and extends on the sidewalls of the protruding fins 36 and on the top surface and sidewalls of the gate spacers 46. According to some embodiments of the present invention, the high-k dielectric layer 66 is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), etc.

[0038] Further referring to Figure 10A and Figure 10B , a gate electrode 70 is formed on the gate dielectric 67. The gate electrode 70 may include a plurality of metal-containing layers 74 and a fill metal region 76. The plurality of metal-containing layers 74 may be formed as a conformal layer, and the fill metal region 76 fills the remaining part of the trenches not filled by the plurality of metal-containing layers 74. The metal-containing layer 74 may include a barrier layer, one or more work function layers above the barrier layer, and one or more metal capping layers above the work function layers. Referring to Figures 11 to 18 for a discussion of the detailed structure of the metal-containing layer 74, Figures 11 to 18 shows a gate structure for a p-type FinFET according to some embodiments.

[0039] Figure 10B Region 78 is schematically shown, which includes a portion of the fin 36, a portion of the IL 64B, a portion of the high-k dielectric layer 66, a portion of the metal-containing layer 74, and a portion of the fill metal region 76. Figures 11 to 18 Shows the formation of features extending into region 78 according to some embodiments. It should be understood that the high-k dielectric layer 66, the metal-containing layer 74, and the fill metal region 76 may include horizontal portions on top of the ILD 60 and the gate spacers 46, and these horizontal portions are removed in the planarization process to obtain Figure 10B the structure shown.

[0040] Referring to Figure 11 , the IL 64B (also referring to Figure 8B ) is located on the protruding fin. The high-k dielectric layer 66 is located above the IL 64B and contacts the IL 64B. According to some embodiments, titanium silicon nitride (TSN) 120 is formed above the high-k dielectric layer 66. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 222. The TSN layer 120 may be formed using ALD or CVD, and the TSN layer 120 may include alternately deposited TiN layers and SiN layers. Since the TiN layers and SiN layers are very thin, it may not be possible to distinguish these layers from each other, so they are combined to form the TSN layer.

[0041] Perform a post-metallization annealing (PMA) process 122. In Figure 33 the process flow 200 shown, the corresponding process is also shown as process 222. The PMA process 122 can be performed using furnace annealing, rapid annealing, etc. The temperature of the PMA process 122 can be in the range between about 600 °C and about 900 °C. The annealing duration can be in the range between about 2 seconds and about 120 seconds. The PMA process 122 can be performed using a process gas including NH3, N2, H2, O2, etc.

[0042] Figure 12 The deposition of the silicon capping layer 124 is shown. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 224. According to some embodiments, the silicon capping layer 124 is deposited using a silicon-containing precursor including silane, disilane, dichlorosilane (DCS), etc. After the deposition, a post-capping annealing (PCA) process 126 is performed. In Figure 33 the process flow 200 shown, the corresponding process is also shown as process 224. The PCA process can be performed using furnace annealing, rapid annealing, etc. The temperature of the PCA process 126 can be in the range between about 650 °C and about 1,100 °C. The annealing duration can be in the range between about 2 seconds and about 120 seconds. The PCA process 126 can be performed using a process gas including NH3, N2, H2, O2, etc.

[0043] Next, the TSN layer 120 and the silicon capping layer 124 are removed in (some) etching processes. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 226. The resulting structure is shown in Figure 13 . The deposition, annealing, and subsequent removal of the TSN layer 120 and the silicon capping layer 124 can improve the reliability and thermal stability of the high-k dielectric layer 66. According to an alternative embodiment of the present invention, the deposition, annealing, and subsequent removal of the TSN layer 120 and the silicon capping layer 124 are skipped.

[0044] Figure 14 The deposition of the barrier layer 128 and the metal layer 130 is shown. In Figure 33In the process flow 200 shown, the corresponding processes are shown as processes 228 and 230. According to some embodiments, the barrier layer 128 comprises or may be a TiN layer, a TaN layer, or a composite layer thereof. The deposition process may include CVD, ALD, etc. The metal in the metal layer 130 is selected such that it can penetrate the barrier layer 128 during annealing and can form a mixed layer with desired properties, as described in the subsequent paragraphs. The metal in the metal layer 130 is selected to be able to remove oxygen from the interface layer without creating additional vacancies in the high-k dielectric layer, so that the oxide of the selected metal layer 130 has higher stability compared to SiOx and GeOx, and lower stability compared to the high-k oxide. According to some embodiments, the metal layer 130 comprises Al, Ti, Hf, Zr, Ta, Cr, W, V, Mo, or an alloy thereof. The deposition method may include, for example, physical vapor deposition (PVD), or atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD), or chemical vapor deposition (CVD).

[0045] The thickness Tl of the barrier layer 128 is selected such that Figure 15 in the subsequent annealing process shown, the thickness Tl of the barrier layer 128 can serve to prevent excessive diffusion of the metal in the metal layer 130 into the high-k dielectric layer 66, while allowing a sufficient amount of the metal in the metal layer 130 to reach the interface between the barrier layer 128 and the high-k dielectric layer 66 to form a mixed layer. The barrier layer 128 also allows oxygen atoms in IL 64B and IL 64A to penetrate upward to reach the metal layer 130. According to some embodiments, the thickness T1 is in the range of about 5 angstroms to about 40 angstroms. If the thickness T1 is too large, for example, greater than about then the oxygen atoms cannot diffuse upward through the barrier layer 128, resulting in the defeat of the purpose of the subsequent annealing process. If the thickness T1 is too small, for example, less than about 5 angstroms, then excessive metal atoms in the metal layer 130 will diffuse downward, penetrate the barrier layer 128, and diffuse into the high-k dielectric layer 66. The diffusion of metal atoms in the high-k dielectric layer will thus adversely affect the performance of the high-k dielectric layer 66. The thickness T2 of the metal layer 130 can be in the range of about 5 angstroms to about 150 angstroms.

[0046] Figure 15 A post-deposition annealing (PDA) process 132 is shown. In Figure 33In the process flow 200 shown, the corresponding process is shown as process 232. The PDA process can be implemented using furnace annealing, rapid annealing, etc. As discussed in the subsequent paragraphs, the temperature and annealing duration are controlled to achieve the desired effect without causing adverse effects. For example, if the temperature is too high and / or the annealing duration is too long, the metal in the metal layer 130 will diffuse throughout the high-k dielectric layer 66, thereby reducing its performance, and the high-k film will also crystallize. If the temperature is too low or the annealing time is too short, the desired effect cannot be obtained. Therefore, the PDA process 132 can be implemented within a temperature range between approximately 400 °C and approximately 535 °C. The annealing duration can be within a range between approximately 15 seconds and approximately 45 seconds. The PDA process 132 can be implemented using process gases including NH3, N2, H2, O2, etc.

[0047] In the PDA process 132, the germanium oxide in IL64B decomposes in the PMOS device region 21P, while the silicon oxide in IL64A decomposes in the NMOS device region 21N. The silicon oxide in IL64B is more stable than the germanium oxide and does not decompose. This preferential decomposition of the germanium oxide in IL64B results in a decrease in the ratio of the percentage of germanium atoms to the percentage of silicon atoms in IL64B. The oxygen atoms in the decomposed germanium oxide diffuse upward into the metal layer 130 and form a metal oxide layer 136 with the bottom (or all) of the metal layer 130. For example, depending on whether the metal layer 130 contains Al, Ti, Hf, Ta, Cr, W, V, or Zr, the metal oxide layer 136 can include aluminum oxide, titanium oxide, hafnium oxide, or zirconium oxide, respectively.

[0048] In the PDA process 132, the germanium atoms in the decomposed germanium oxide diffuse downward into the top surface portion of the protruding fin 36 and form a germanium-rich layer 36-S, which forms at least a part of the channel region of the corresponding transistor. Since additional germanium atoms are added to the top surface portion of the protruding fin 36, the percentage of germanium atoms in the germanium-rich layer 36-S is higher by ΔC than the percentage of germanium atoms in the original top surface portion of the protruding fin 36, and is also higher by ΔC than the percentage of germanium atoms in the lower portion of the protruding fin 36. The atomic percentage difference ΔC can be within a range between approximately 1% and approximately 4%. The thickness T3 of the germanium-rich layer 36-S can be within a range between approximately 0.5 nm and approximately 1 nm.

[0049] Due to the decomposition of the germanium oxide and the outward diffusion of germanium atoms and oxygen atoms, the thickness of IL64B in the PMOS device region 21P decreases. Additionally, due to the decomposition of the silicon oxide and the outward diffusion of oxygen atoms, the thickness of IL64A in the NMOS device region 21N decreases. For example, before depositing the metal layer 130, IL64B or IL64A ( Figure 13) has a thickness of T4. After the PDA process 132, the thickness of one or both of IL64B and / or IL64A is reduced to T4'( Figure 15 ), which is in the range between about 25%*T4 and about 80%*T4. For example, T4 can be in the range between about 10 angstroms and about 120 angstroms, while the thickness T4' can be in the range between about 2 angstroms and about 80 angstroms. Thus, the EOT of the resulting gate dielectric is reduced.

[0050] In the PDA process 132, a hybrid layer 134 is also formed in the boundary region between the high-k dielectric layer 66 and the barrier layer 128. The hybrid layer 134 includes a metal (such as Hf) from the high-k dielectric layer 66, oxygen diffused from IL64B, a metal diffused from the metal layer 130, and a metal (such as Ti) from the barrier layer 128. The metal from the metal layer 130 can be the same as or different from (some of) the metals in the high-k dielectric layer 66, and can be the same as or different from (some of) the metals in layers 142A, 142B, 144, 146, and 148( Figure 18 ). According to some embodiments, the hybrid layer 134 includes Mx-Ti-Hf-O, where Mx is the metal in the metal layer 130. The hybrid layer 134 is a dielectric layer and can be titanium-rich, zirconium-rich, aluminum-rich, or hafnium-rich, depending on the metal in the metal layer 130. The hybrid layer 134 has some advantageous characteristics. For example, the titanium-rich and zirconium-rich hybrid layer 134 has a dielectric constant k HK higher than that of the high-k dielectric layer 66 IM , for example, the difference in k values (k IM k HK ) is greater than about 1 and can be in the range between about 1 and 8. The hybrid layer 134 has the function of preventing the overlying work function metal layer (formed subsequently) from diffusing into the high-k dielectric layer 66, thus improving the high-k film quality, leakage, and the reliability of the corresponding device. Moreover, the aluminum-rich hybrid layer 134 helps to enhance the p-type dipole and can reduce the voltage threshold of p-type transistors. The zirconium-rich hybrid layer 134 can stabilize the tetragonal phase in the high-k dielectric layer 66 and can improve the thermal stability of the high-k dielectric layer 66.

[0051] Figure 25 shows the compositional distribution of some elements in each layer according to some embodiments as Figure 15 shown. The compositional distribution is measured from a sample wafer on which the structure formed in Figure 15 is formed. For ease of understanding, example elements in each layer of the illustration are labeled. For example, the sample structure has a metal layer 130 formed by Hf and a barrier layer 128 formed by TiN. In Figure 24Among them, lines 338, 340, 342, 344, 346, 348, and 350 respectively represent the atomic percentages of Ge, Si, O, Hf, N, Ti, and Al. The percentage of Ge atoms in the Ge-rich SiGe layer 36-S (line 338) is higher than that in the SiGe protruding fin 36, so it is named Ge-rich. Correspondingly, the percentage of Si atoms in the Ge-rich SiGe layer 36-S (line 340) is lower than that in the SiGe protruding fin 36.

[0052] Figure 25 Furthermore, compared with both the Ge-rich SiGe layer 36-S and the protruding fin 36, the Ge / Si ratio of the IL layer 64B is significantly lower, which clearly indicates that Ge atoms have diffused outwards to the Ge-rich SiGe layer 36-S. It is also clearly shown that the mixed layer 134 has high atomic percentages of Hf, O, Ti, and Al.

[0053] Figure 26 Shows the atomic percentages of certain elements in the mixed layer 134, the high-k dielectric layer 66, and the IL 64B, as well as the protruding fin 36 (including the Ge-rich SiGe layer 36-S), where the X-axis represents the depth measured from the top surface of the wafer 10, and the Y-axis represents the atomic percentage. The elements are labeled. Moreover, the mixed layer 134 can also be clearly observed.

[0054] Next, etch the barrier layer 128, the metal oxide layer 136, and the metal layer 130 as Figure 15 shown, and the resulting structure is shown in Figure 16 In Figure 33 the process flow 200 shown, the corresponding process is shown as process 234. The etch chemicals can be selected according to the materials of the metal layer 130 and the barrier layer 128, and can be selected from NH4OH, HCl, HF, H3PO4, H2O2, H2O, and their combinations. For example, when the metal layer 130 includes Al, Ti, Hf, and / or Zr, and when the barrier layer 28 includes TiN, the etch chemicals can include one or both of NH4OH and HCl, and also include H2O2 and H2O. When the metal layer 130 includes Al, Ti, Hf, Ta, Cr, W, V, Mo, and / or Zr, and when the barrier layer 28 includes TaN, the etch chemicals can include a mixture of HF, NH4OH, H2O2, and H2O. After etching, the mixed layer 134 is exposed.

[0055] Figure 17 Shows the deposition of the barrier layer 142A according to some embodiments. In Figure 33In the process flow 200 shown, the corresponding process is shown as process 236. The barrier layer 142A, sometimes also referred to as an adhesion layer, can be formed of TiN, TaN, etc.

[0056] After the barrier layer 142A is formed, another deposited barrier layer 142B may (or may not) be present on the barrier layer 142A. According to other embodiments, layers 142A and 142B are not formed, and the subsequently formed work function layer 144 contacts the hybrid layer 134.

[0057] Next, also as Figure 18 shown, the work function layer 144 is formed above the barrier layer 142B (if formed). In Figure 33 the process flow 200 shown, the corresponding process is shown as process 238. The work function layer 144 determines the work function of the gate and includes at least one layer or multiple layers formed of different materials. According to some embodiments, the work function layer 144 may include a TaN layer, a TiN layer above the TaN layer, and a TiAl layer above the TiN layer. It should be understood that the work function layer may include different materials, which is also expected.

[0058] According to some embodiments of the present invention, as Figure 18 shown, a metal capping layer 146 is formed above the work function layer 144. In Figure 33 the process flow 200 shown, the corresponding process is shown as process 240. According to some embodiments, the metal capping layer 146 can be formed of a metal nitride such as TiN, and other materials such as TaN can be used. Layers 142A, 142B, 144, and 146 together correspond to Figure 10B the stack layer 74 in

[0059] Figure 18 The formation of the fill metal region 148 is shown, which corresponds to Figure 10B the fill metal region 76 in Figure 33 the process flow 200 shown, the corresponding process is shown as process 242. The stack includes the hybrid layer 134 and an overlying layer corresponding to Figure 10B the stack layer 74 in Figure 18 According to some embodiments, the fill metal region 148 is formed of tungsten or cobalt, which can be formed using ALD, CVD, etc. After the fill metal region 148 is formed, a planarization process can be performed to remove the excess of the deposited layer as Figure 10A shown, so as to obtain the gate stack 72 as Figure 10B shown.

[0060] As described above, the diffusion barrier layers 142A and 142B may or may not be formed. When the diffusion barrier layers 142A and 142B are not formed, the resulting gate stack 72 is as Figure 19 shown, where the work function layer 144 is located above the hybrid layer 134 and is in physical contact with the hybrid layer 134. According to other embodiments, the diffusion barrier layer 142B may be formed while the diffusion barrier layer 142A is not formed. The corresponding gate stack 72 is shown in Figure 20 , where the work function layer 144 is located above the diffusion barrier layer 142B and is in physical contact with the diffusion barrier layer 142B.

[0061] Figure 21 and Figure 22 show intermediate stages in the formation of the gate stack 72 according to alternative embodiments. Unless otherwise specified, the materials and formation processes of the components in these embodiments are substantially the same as those of the same components denoted by the same reference numerals in the foregoing embodiments shown in Figures 1 to 18 . Accordingly, details regarding the formation processes and materials of the components can be found in the discussion of the foregoing embodiments. Figure 21 and Figure 22 shown.

[0062] The initial steps of these embodiments are substantially the same as those in Figures 1 - 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , and Figures 11 - 15 shown. In subsequent processes, as Figure 15 shown, the metal layer 130 and the metal oxide layer 136 shown in Figure 15 are removed in an etching process, while the barrier layer 128 shown in Figure 21 is not etched. Accordingly, the corresponding etching process is referred to as a local etching process. According to some embodiments, when the metal layer 130 includes Al, Ti, Hf, Ta, Cr, W, V, Mo, and / or Zr, and when the barrier layer 128 includes TiN, the local etching chemical may include a mixture of HF, NH4OH, H2O2, and H2O. When the metal layer 130 includes Al, Ti, Hf, Ta, Cr, W, V, Mo, and / or Zr, and when the barrier layer 128 includes TaN, the etching chemical may be selected from a mixture of H2O2, H3PO4, and H2O, a mixture of NH4OH, H2O2, and H2O, a mixture of HCl, H2O2, and H2O, or a mixture of NH4OH, HCl, H2O2, and H2O. After the local etching process, as Figure 21 shown, the barrier layer 128 is retained. The barrier layer 128 is formed byFigure 18 is formed of a material similar to the diffusion barrier layer 142A and has the same function as the diffusion barrier layer 142A. Figure 22 The diffusion barrier layer 142B, work function layer 144, capping layer 146, and fill metal 148 are shown above. Similarly, the diffusion barrier layer 142B may or may not be formed.

[0063] Figure 23 The formation of the hard mask 80 according to some embodiments is shown. The formation of the hard mask 80 may include: performing an etching process to recess the gate stack 72 to form a recess between the gate spacers 46, filling the recess with a dielectric material, and then performing a planarization process such as a CMP process or a mechanical polishing process to remove the excess dielectric material. The hard mask 80 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbide nitride, etc.

[0064] Figure 24 The formation of the source / drain contact plug 82 is shown. The formation of the source / drain contact plug 82 includes: etching the ILD 60 to expose a portion of the underlying CESL 58, and then etching the exposed portion of the CESL 58 to expose the source / drain region 54. In a subsequent process, a metal layer (e.g., a Ti layer) is deposited and extended into the contact opening. A metal nitride capping layer may be performed. Then an annealing process is performed to react the metal layer with the top of the source / drain region 54 to form a silicide region 84, as Figure 24 shown. Next, either the previously formed metal nitride layer is retained without removal or the previously formed metal nitride layer is removed and then a new metal nitride layer (e.g., a titanium nitride layer) is deposited. Then a fill metal material such as tungsten, cobalt, etc. is filled into the contact opening, followed by planarization to remove the excess material, resulting in the source / drain contact plug 82. A gate contact plug (not shown) is also formed to pass through a portion of each hard mask 80 to contact the gate electrode 70. Thus, the FinFET 86 is formed, which may be connected in parallel as one FinFET.

[0065] Figure 27 The bonding energy of silicon in the PMOS device region 21P is shown. The peak of the bonding energy close to 102.8 eV represents the Si - O bond, which corresponds to the IL64B. The peak of the bonding energy close to 100 eV represents the Si - Si bond and / or Si - Ge bond, which corresponds to the channel region. The signal intensity line 152 is obtained from a first sample formed using a conventional method, in which the metal layer 130 ( Figure 15 ) is not formed, and the annealing process 132 ( Figure 15 ) is not performed. The signal intensity line 154 is obtained from a second sample formed according to some embodiments of the present invention, in which the metal layer 130 ( Figure 15), and an annealing process 132 is implemented Figure 15 ). The experimental results show that at the peak of the bonding energy close to 102.8 eV Figure 27 ), the signal intensity of line 154 is higher than that of line 152, indicating that in the IL of the second sample, the percentage of silicon atoms has increased compared to that in the first sample, which also means that the percentage of germanium atoms in IL64B has decreased due to the diffusion of germanium. At the peak of the bonding energy close to 100 eV Figure 27 ), the signal intensity of line 154 is lower than that of line 152, indicating that in the germanium-rich SiGe layer 36-S, the percentage of silicon atoms has decreased in the second sample compared to the first sample, which also means that the percentage of germanium atoms has increased in the channel.

[0066] Figure 28 and Figure 29 show the bonding energy of germanium. Close to Figure 28 33.5 eV in Figure 29 and the signal intensity of the bonding energy of 1,222 eV in Figure 28 represent Ge-O bonds, which correspond to IL64B. Close to Figure 28 30 eV in Figure 29 and the peak of the bonding energy of 1,218 eV in Figure 28 ) and 1,222 eV ( Figure 29 ), the signal intensity of line 158 is lower than that of signal intensity line 156, indicating that in the IL of the second sample, the percentage of germanium atoms has decreased, indicating fewer Ge-O bonds in IL64B, which is due to the oxygen removed from germanium oxide in the IL entering the metal layer 130 and the outward diffusion of germanium into the channel. At the peak of the bonding energy close to 30 eV ( Figure 28 ) and 1,218 eV ( Figure 29 ), the signal intensity of line 158 is higher than that of line 156, indicating an increase in the percentage of germanium atoms in the germanium-rich SiGe layer 36-S.

[0067] Figure 30 show the bonding energy of silicon in the NMOS device region 21N. The peak of the bonding energy close to 102.8 eV represents the Si-O bond, which corresponds to IL64A. The peak of the bonding energy close to 100 eV represents the Si-Si bond, which corresponds to the Si channel region. The signal intensity line 160 is obtained from the first sample formed using the conventional method, in which the metal layer 130 is not formed ( Figure 15 ), and the annealing process 132 is not implemented ( Figure 15)。The signal intensity line 162 is obtained from a second sample formed according to some embodiments of the present invention, wherein a metal layer 130 is formed ( Figure 15 ), and an annealing process 132 is implemented ( Figure 15 ). The experimental results show that at the peak of the binding energy close to 102.8 eV ( Figure 30 ), the signal intensity of line 162 is lower than that of line 160, indicating that in the IL 64A of the second sample, the percentage of silicon atoms is reduced compared to that in the first sample, which also means that the thickness of IL64A is reduced.

[0068] Figure 31 Shows a comparison of the stacking schemes of low-voltage p-type transistors, standard-voltage p-type transistors, and high-voltage p-type transistors according to some embodiments. The difference between these devices lies in whether they include diffusion barrier layers 142A (or 128) and 142B. The formation of these transistors can share a common process for forming the germanium-rich SiGe layer 64, IL 66, hybrid layer 134, and work function layer 144. In order to form the diffusion barrier layers 142A and 142B differently for different transistors, the first diffusion barrier layer 142A can be formed in all three transistor regions and then removed from the low-voltage and standard-voltage transistor regions. Next, the second diffusion barrier layer 142B can be formed in all three transistor regions and then removed from the low-voltage transistor region. The thin IL layer 64B includes silicon-rich and germanium-deficient oxides, and the work function layer 144 includes a p-type work function metal. Additionally, the germanium-rich SiGe layer 36-S is formed in all three transistor regions.

[0069] Figure 32 Shows a comparison of the stacking schemes of low-voltage n-type transistors, standard-voltage n-type transistors, and high-voltage n-type transistors according to some embodiments. The difference between these devices lies in whether they include diffusion barrier layers 142A (or 128) and 142B. The corresponding IL includes a thin silicon oxide 64A, and the work function layer includes an n-type work function metal. No germanium-rich layer is formed in the channels of all three transistor regions.

[0070] Embodiments of the present invention have some advantageous features. By forming a metal layer during the formation of the gate of an n-type transistor and annealing the metal layer, oxygen can be removed from the IL including silicon oxide. By forming a metal layer during the formation of the gate of a p-type transistor and annealing the metal layer, oxygen can be removed from the IL including silicon oxide and germanium oxide. Germanium also diffuses into the underlying channel. Thus, the amount of germanium oxide in the IL is reduced. Germanium oxide is less stable than silicon oxide and easily combines with oxygen to form germanium monoxide, which is gaseous and may evaporate, resulting in vacancies being left in the IL. Additionally, the oxygen vacancy formation energy in germanium oxide is lower compared to silicon oxide or high-k oxide. Therefore, germanium oxide in the IL causes excessive defects. Thus, the reduction of germanium oxide reduces the defects in the IL and the density of interface traps in the p-type transistor. The IL also thins in both the n-type and p-type transistors, and the EOT of the gate dielectric is reduced. The germanium diffused into the channel region enables an ideal increase in mobility in the channel for the p-type transistor. Additionally, a hybrid layer with a high-k value and other advantageous features is formed.

[0071] According to some embodiments of the present invention, a device includes: a semiconductor region; an interface layer located above the semiconductor region, the interface layer including a semiconductor oxide; a high-k dielectric layer located above the interface layer; a hybrid layer located above the high-k dielectric layer, wherein the hybrid layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal; a work function layer located above the hybrid layer; and a fill metal region located above the work function layer. In one embodiment, the additional metal is selected from the group consisting of aluminum, titanium, hafnium, zirconium, chromium, tantalum, tungsten, vanadium, molybdenum, and combinations thereof. In one embodiment, the semiconductor region includes: a lower portion including silicon germanium having a first germanium atomic percentage; and an upper portion located above and in contact with the lower portion, wherein the upper portion includes silicon germanium having a second germanium atomic percentage, and the second germanium atomic percentage is greater than the first germanium atomic percentage. In one embodiment, the upper portion has a thickness in the range between about 0.5 nm and about 1 nm. In one embodiment, the second germanium atomic percentage is greater than the first germanium atomic percentage by a difference, and the difference is in the range between about 1% and about 4%. In one embodiment, the work function layer contacts the hybrid layer. In one embodiment, the device further includes: a titanium nitride layer located between the hybrid layer and the fill metal region. In one embodiment, the interface layer, the high-k dielectric layer, the hybrid layer, the work function layer, and the fill metal region form a gate stack of a transistor.

[0072] According to some embodiments of the present invention, a device includes: a semiconductor region; an interface layer located above the semiconductor region, the interface layer including a semiconductor oxide; a high-k dielectric layer located above the interface layer; a hybrid layer located above the high-k dielectric layer, wherein the hybrid layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal; a work function layer located above the hybrid layer; and a fill metal region located above the work function layer. In one embodiment, the semiconductor region includes: a lower portion including silicon germanium having a first germanium atomic percentage; and an upper portion located above and in contact with the lower portion, wherein the upper portion includes silicon germanium having a second germanium atomic percentage, and the second germanium atomic percentage is greater than the first germanium atomic percentage. In one embodiment, a first ratio of the germanium atomic percentage to the silicon atomic percentage in the interface layer is lower than a second ratio of the germanium atomic percentage to the silicon atomic percentage in the upper portion of the semiconductor region, and is lower than a third ratio of the germanium atomic percentage to the silicon atomic percentage in the lower portion of the semiconductor region.

[0073] According to some embodiments of the present invention, a device includes: a silicon germanium fin; a gate stack located on the silicon germanium fin, wherein the gate stack includes: an interface layer in contact with the silicon germanium fin; a high-k dielectric layer located above the interface layer; a hybrid layer located above and in contact with the high-k dielectric layer, wherein the high-k dielectric layer has a first dielectric constant and the hybrid layer has a second dielectric constant, and the second dielectric constant is greater than the first dielectric constant; a titanium nitride layer located above and in contact with the hybrid layer; and source / drain regions located on sides of the gate stack. In one embodiment, the metal included in the hybrid layer is different from the metals in the high-k dielectric layer, in the gate stack, and in the overlying layer of the hybrid layer. In one embodiment, the hybrid layer includes oxygen and a metal selected from the group consisting of aluminum, titanium, hafnium, zirconium, and combinations thereof. In one embodiment, the silicon germanium fin includes: a lower portion having a first germanium atomic percentage; and an upper portion located above and in contact with the lower portion, wherein the upper portion has a second germanium atomic percentage that is higher than the first germanium atomic percentage. In one embodiment, at an interface between the lower portion and the upper portion, there is a sudden increase from the first germanium atomic percentage to the second germanium atomic percentage. In one embodiment, the silicon germanium fin, the gate stack, and the source / drain regions are part of a p-type transistor.

[0074] According to some embodiments of the present invention, a method includes: forming an interface layer over a semiconductor region, wherein the interface layer includes a semiconductor oxide; depositing a high-k dielectric layer over the interface layer; depositing a barrier layer over the high-k dielectric layer; depositing a metal layer over the barrier layer; performing an annealing process when the metal layer is over the barrier layer; and removing the metal layer. In one embodiment, a hybrid layer is formed between the barrier layer and the high-k dielectric layer by the annealing process. In one embodiment, the method further includes: removing the barrier layer; forming a work function layer after removing the barrier layer; and forming a metal-containing capping layer over the work function layer. In one embodiment, the method further includes: forming a work function layer over the barrier layer. In one embodiment, depositing the metal layer includes: depositing a metal selected from the group consisting of aluminum, titanium, hafnium, zirconium, and combinations thereof. In one embodiment, the annealing process is performed within a temperature range between about 400 °C and about 535 °C.

[0075] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor region; An interface layer located above the semiconductor region, the interface layer comprising a semiconductor oxide; A high-k dielectric layer located above the interface layer; A hybrid layer located above the high-k dielectric layer, wherein the hybrid layer comprises oxygen diffused from the interface layer, a metal in the high-k dielectric layer, and an additional metal; A work function layer located above the hybrid layer; and A fill metal region located above the work function layer.

2. The semiconductor device according to claim 1, wherein, The additional metal is selected from the group consisting of aluminum, titanium, hafnium, zirconium, chromium, tungsten, vanadium, molybdenum, and combinations thereof.

3. The semiconductor device according to claim 1, wherein, The semiconductor region comprises: A lower portion comprising silicon germanium having a first germanium atomic percentage; and An upper portion located above and in contact with the lower portion, wherein the upper portion comprises silicon germanium having a second germanium atomic percentage greater than the first germanium atomic percentage.

4. The semiconductor device according to claim 3, wherein, The upper portion has a thickness in the range between 0.5 nm and 1 nm.

5. The semiconductor device according to claim 3, wherein, The second germanium atomic percentage is greater than the first germanium atomic percentage by a difference, and the difference is in the range between 1% and 4%.

6. The semiconductor device according to claim 3, wherein, A first ratio of the germanium atomic percentage to the silicon atomic percentage in the interface layer is lower than a second ratio of the germanium atomic percentage to the silicon atomic percentage in the upper portion of the semiconductor region and lower than a third ratio of the germanium atomic percentage to the silicon atomic percentage in the lower portion of the semiconductor region.

7. The semiconductor device according to claim 1, wherein, The work function layer contacts the hybrid layer.

8. The semiconductor device according to claim 1 further comprises: A titanium nitride layer is located between the hybrid layer and the fill metal region.

9. A semiconductor device, comprising: A silicon germanium fin; A gate stack located on the silicon germanium fin, wherein the gate stack comprises: An interface layer in contact with the silicon germanium fin; A high-k dielectric layer located above the interface layer; A hybrid layer located above and in contact with the high-k dielectric layer, wherein the high-k dielectric layer has a first dielectric constant and the hybrid layer has a second dielectric constant greater than the first dielectric constant, wherein the hybrid layer is a dielectric layer and comprises oxygen diffused from the interface layer; and A titanium nitride layer located above and in contact with the hybrid layer; and source / drain regions located on sides of the gate stack.

10. The semiconductor device according to claim 9, wherein, The metal comprised in the hybrid layer is different from the metal in the high-k dielectric layer and in the gate stack and in the overlying layer of the hybrid layer.

11. The semiconductor device according to claim 9, wherein, The hybrid layer comprises a metal selected from the group consisting of aluminum, titanium, hafnium, zirconium, chromium, tungsten, vanadium, molybdenum, and combinations thereof.

12. The semiconductor device according to claim 9, wherein, The silicon germanium fin comprises: A lower portion having a first germanium atomic percentage; and An upper portion located above and in contact with the lower portion, wherein the upper portion has a second germanium atomic percentage higher than the first germanium atomic percentage.

13. The semiconductor device according to claim 12, wherein, At an interface between the lower portion and the upper portion, there is a sudden increase from the first germanium atomic percentage to the second germanium atomic percentage.

14. The semiconductor device according to claim 9, wherein The silicon germanium fin, the gate stack, and the source / drain regions are part of a p-type transistor.

15. A method of forming a semiconductor device, comprising: An interface layer is formed over the semiconductor region, wherein the interface layer comprises a semiconductor oxide; A high-k dielectric layer is deposited over the interface layer; A barrier layer is deposited over the high-k dielectric layer; A metal layer is deposited over the barrier layer; An annealing process is performed when the metal layer is over the barrier layer, wherein a hybrid layer is formed between the barrier layer and the high-k dielectric layer through the annealing process, and the hybrid layer comprises a metal diffused from the metal layer and oxygen diffused from the interface layer; and The metal layer is removed.

16. The method according to claim 15, wherein, The hybrid layer is a dielectric layer.

17. The method according to claim 15, further comprising: Removing the barrier layer; Forming a work function layer after removing the barrier layer; And Forming a metal-containing capping layer over the work function layer.

18. The method according to claim 15, further comprising: Forming a work function layer over the barrier layer.

19. The method according to claim 15, wherein, The depositing the metal layer comprises: depositing a metal selected from the group consisting of aluminum, titanium, hafnium, zirconium, chromium, tungsten, vanadium, molybdenum, and combinations thereof.

20. The method according to claim 15, wherein The annealing process is performed within a temperature range between 400 °C and 535 °C.

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