Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. A device includes: a first fin and a second fin extending from a substrate, the first fin including a first groove and the second fin including a second groove; an isolation region surrounding the first fin and surrounding the second fin; a gate stack located over the first fin and the second fin; and source / drain regions located in the first groove and the second groove, the source / drain regions being adjacent to the gate stack, wherein the source / drain regions include a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface above the first height has a second slope, the second slope being greater than the first slope.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, cellular telephones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, there is provided a semiconductor device including: a first fin and a second fin extending from a substrate, the first fin including a first groove, and the second fin including a second groove; an isolation region surrounding the first fin and surrounding the second fin; a gate stack located over the first fin and the second fin; and source / drain regions located in the first groove and the second groove, the source / drain regions being adjacent to the gate stack, wherein the source / drain regions include a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface above the first height has a second slope, the second slope being greater than the first slope.

[0005] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a first fin located above a semiconductor substrate; a second fin located above the semiconductor substrate, the second fin being adjacent to the first fin; an isolation region surrounding the first fin and the second fin; a gate structure along sidewalls of the first fin and the second fin and located above upper surfaces of the first fin and the second fin; and source / drain regions located on the first fin and the second fin, adjacent to the gate structure, the source / drain regions including a bottom surface between the first fin and the second fin, wherein the bottom surface includes a lower surface and an upper surface, wherein the lower surface is a facet of a first crystal plane, the facet of the first crystal plane extending from a bottom of the bottom surface to a facet of a second crystal plane at a first height above the isolation region, wherein the upper surface extends from the first height to an uppermost portion of the bottom surface, and wherein the upper surface includes the facet of the first crystal plane and the facet of the second crystal plane.

[0006] According to yet another embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: forming a plurality of fins protruding from a semiconductor substrate; forming an isolation region surrounding the plurality of fins; forming a gate structure above the plurality of fins; and forming an epitaxial source / drain region adjacent to the gate structure and extending above the plurality of fins, including: performing a first deposition process to deposit a first epitaxial material on the plurality of fins, wherein a bottom surface of the first epitaxial material on adjacent fins fuses at a first height above the isolation region; performing an etching process on the first epitaxial material, wherein the etching process etches the bottom surface of the first epitaxial material; and after performing the etching process, performing a second deposition process to deposit a second epitaxial material on the first epitaxial material, the epitaxial source / drain region including the first epitaxial material and the second epitaxial material, wherein after performing the second deposition process, a bottom surface of the epitaxial source / drain region between adjacent fins extends a second height above the isolation region, the second height being greater than the first height. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction Figure 1 with the following detailed description, various aspects of the present disclosure will be best understood. Note that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a FinFET device in a three-dimensional view according to some embodiments is shown.

[0009] Figure 2 、 Figure 3 、Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B and Figure 10C are cross-sectional views of intermediate stages of manufacturing a FinFET device according to some embodiments.

[0010] Figure 11 , Figure 12 , Figure 13A and Figure 13B are cross-sectional views of intermediate stages of manufacturing an epitaxial source / drain region of a FinFET device according to some embodiments.

[0011] Figure 14A and Figure 14B show a diagram of the tilt angle of the epitaxial source / drain region of a FinFET device compared to the sidewall position and a diagram of the profile of the epitaxial source / drain region of the FinFET device according to some embodiments.

[0012] Figure 15 shows a diagram of the fusion height of the epitaxial source / drain region of a FinFET device compared to the fin pitch according to some embodiments.

[0013] Figure 16 are cross-sectional views of intermediate stages of manufacturing an epitaxial source / drain region of a FinFET device according to some embodiments.

[0014] Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 22A and Figure 22B are cross-sectional views of intermediate stages of manufacturing a FinFET device according to some embodiments. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, for ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] Various embodiments provide a process for forming source / drain regions having a reduced volume and a reduced cross-sectional area. The source / drain regions may be formed by epitaxially growing a first epitaxial layer in a recess formed in a semiconductor fin, performing an etch back process, and then epitaxially growing a second epitaxial layer over the first epitaxial layer. Using the techniques described herein, adjacent source / drain regions may be formed that merge at a higher distance above the substrate, which reduces the cross-sectional area of the merged source / drain regions. A semiconductor device fabricated according to an embodiment of the present application and including source / drain regions may experience a reduced gate-to-drain capacitance (Cgd), a reduced RC delay, faster on / off switching, and increased device speed.

[0018] Figure 1Shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are provided in the substrate 50, and the fin 52 protrudes above and between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including isolation regions. Additionally, although the fin 52 is illustrated with the substrate 50 as a single, continuous material, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this case, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0019] A gate dielectric layer 92 is along the sidewalls and on top of the top surface of the fin 52, and a gate electrode 94 is on top of the gate dielectric layer 92. Source / drain regions 82 are provided on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Also shown are reference cross-sections used in the subsequent figures. Cross-section A-A is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fin 52 and, for example, in the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions of the FinFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0020] Some embodiments discussed herein are discussed in the context of FinFETs formed using a back-gate process. In other embodiments, a front-gate process may be used. Additionally, some embodiments contemplate aspects of use in planar devices such as planar FETs.

[0021] Figures 2 to 13B and Figures 16 to 22B is a cross-sectional view of an intermediate stage of manufacturing a FinFET according to some embodiments. Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A and Figure 22A are illustrated along Figure 1 the reference cross-section A-A shown, andFigure 8B , Figure 9B , Figure 10B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 20C , Figure 21B and Figure 22B are illustrated along a similar cross - section B - B as shown in Figure 1 . Figure 10C , Figure 11 , Figure 12 , Figure 13A , Figure 13B and Figure 16 are illustrated along a reference cross - section C - C as shown in Figure 1 .

[0022] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor - on - insulator (SOI) substrate, etc., which can be doped (e.g., using p - type or n - type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multi - layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium indium phosphide arsenide; or combinations thereof.

[0023] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form n - type devices, such as NMOS transistors, such as n - type FinFETs. The region 50P can be used to form p - type devices, such as PMOS transistors, such as p - type FinFETs. The region 50N can be physically separated from the region 50P (as shown by a divider 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the region 50N and the region 50P.

[0024] In Figure 3In, fins 52 are formed in substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. In some embodiments, fins 52 having a width WF between about 5 nm and about 30 nm can be formed. In some embodiments, fins 52 having a pitch PF between about 10 nm and about 40 nm can be formed.

[0025] The fins 52 can be patterned by any suitable method. For example, one or more lithography processes (including double-patterning or multi-patterning processes) can be used to pattern the fins 52. Generally, double-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing patterns to be created with a pitch, for example, smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) can be retained over the fins 52.

[0026] In Figure 4 In, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, etc. or a combination thereof, and can be formed by: high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material (e.g., an oxide)), etc. or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner (not shown) can first be formed along the surfaces of the substrate 50 and the fins 52. Thereafter, a fill material as described above can be formed over the liner.

[0027] In Figure 5In this process, a removal process is applied to the insulating material 54 to remove the excess insulating material 54 over the fins 52. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc. can be utilized. The planarization process exposes the fins 52 such that the top surfaces of the fins 52 and the insulating material 54 are flush after the planarization process is completed. In embodiments where a mask is retained on the fins 52, the planarization process can expose the mask or remove the mask such that the mask or the top surfaces of the fins 52 and the insulating material 54 are flush respectively after the planarization process is completed.

[0028] In Figure 6 this process, the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in regions 50N and 50P protrude between adjacent STI regions 56. Additionally, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof as shown. The top surface of the STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 56 can be recessed using an acceptable etching process (e.g., an etching process selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fins 52)). For example, oxide removal can be used, which uses, for example, dilute hydrofluoric (dHF) acid.

[0029] Regarding Figures 2 to 6 the processes described above are just one example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form fins. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fins 52. For example, Figure 5 the fins 52 in this process can be recessed, and a material different from the fins 52 can be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 include the recessed material and the epitaxially grown material disposed over the recessed material. In further embodiments, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. Then, a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments where a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material can be in-situ doped during growth, which can avoid prior and subsequent implantations, although in-situ doping and implantation doping can be used together.

[0030] Further, it may be advantageous to epitaxially grow a material different from that in region 50N (e.g., NMOS region) in region 50P (e.g., PMOS region). In various embodiments, the upper portion of fin 52 may be formed of silicon germanium (Si x Ge 1-x , where x may range from 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0031] In addition, in Figure 6 , appropriate wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0032] In embodiments having different well types, different implantation steps for regions 50N and 50P may be implemented using a photoresist or other mask (not shown). For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, e.g., the PMOS region. The photoresist may be formed by using a spin coating technique and may be patterned using acceptable lithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may act as a mask to substantially prevent the n-type impurity from being implanted into region 50N, e.g., the NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc. implanted into the region at a concentration equal to or less than 10 18 cm -3 (e.g., between about 10 16 cm -3 and about 10 18 cm -3 ). After implantation, the photoresist is removed, e.g., by an acceptable ashing process.

[0033] After the implantation into region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurity implantation can be performed in region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity can be boron, boron fluoride, indium, etc. with a concentration implanted into the region equal to or less than 10 18 cm -3 (e.g., between about 10 16 cm -3 and about 10 18 cm -3 ). After the implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0034] After the implantation into regions 50N and 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, in-situ doping of the grown epitaxial fin material can be performed during growth, which can avoid implantation, although in-situ doping and implant doping can be used together.

[0035] In Figure 7In [the figure], a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group including the following: amorphous silicon, polysilicon (polycrystalline silicon), polysilicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 can be made of other materials having a high etch selectivity from the etching of the isolation region. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed on the regions 50N and 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 60 is shown covering only the fin 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 56 and extends between the dummy gate layer 62 and the STI region 56.

[0036] Figures 8A to 13B and Figures 16 to 22B Various additional steps for manufacturing an exemplary device are shown. These figures show features in either of the regions 50N and 50P. For example, the structures shown in these figures can be applicable to both the regions 50N and 50P. The differences (if any) in the structures of the regions 50N and 50P are described in the text accompanying each figure.

[0037] In Figure 8A and Figure 8B In [the figure], the mask layer 64 (see Figure 7 ) can be patterned using acceptable lithography and etching techniques to form a mask 74. Then, the pattern of the mask 74 can be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by acceptable etching techniques to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0038] Furthermore, in Figure 8A and Figure 8BIn [the above], the gate seal spacer 80 can be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching can form the gate seal spacer 80. The gate seal spacer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0039] After forming the gate seal spacer 80, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In embodiments having different device types, similar to the implants discussed above in Figure 6 [the above], a mask such as photoresist can be formed over the region 50N while exposing the region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the exposed fins 52 in the region 50P. Then the mask can be removed. Subsequently, a mask such as photoresist can be formed over the region 50P while exposing the region 50N, and an appropriate type (e.g., n-type) of impurity can be implanted into the exposed fins 52 in the region 50N. Then the mask can be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration ranging from about 10 15 cm -3 to about 10 19 cm -3 . Annealing can be used to repair implantation damage and activate the implanted impurities.

[0040] In Figure 9A and Figure 9B [the above], the gate spacer 86 is formed on the gate seal spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, etc. The gate spacer 86, the gate seal spacer 80, the dummy gate 72, and the mask 74 can be collectively referred to as the "dummy gate structure" herein.

[0041] Note that the above disclosure generally describes the processes for forming the spacers and the LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86, resulting in an "L-shaped" gate seal spacer), spacers may be formed and removed, etc. Additionally, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region of the n-type device may be formed before forming the gate seal spacer 80, while the LDD region of the p-type device may be formed after forming the gate seal spacer 80.

[0042] Figures 10A to 13B Illustrated are various steps for forming the epitaxial source / drain regions 82 in the fin 52 according to some embodiments. Figure 10C 、 Figure 11 、 Figure 12 and Figure 13A -B are illustrated along the reference cross-section C-C shown. For clarity, Figure 1 certain dimensions or ratios of the features shown in Figures 10C to 13B may be different from those shown in other figures. The epitaxial source / drain regions 82 in the region 50N (e.g., the NMOS region) may be formed by masking the region 50P (e.g., the PMOS region) and etching in the region 50N to form a recess 77 in the fin 52. Then, the epitaxial source / drain regions 82 in the region 50N are epitaxially grown in the recess 77. The epitaxial source / drain regions 82 in the region 50P (e.g., the PMOS region) may be formed by masking the region 50N (e.g., the NMOS region) and etching in the region 50P to form a recess 77 in the fin 52. Then, the epitaxial source / drain regions 82 in the region 50P are epitaxially grown in the recess 77. The epitaxial source / drain regions 82 may be formed using multiple deposition and etching processes, which will be described in more detail below.

[0043] Figure 10A 、 Figure 10B and Figure 10CAn etching is shown to form a groove 77 in the source / drain regions of the fin 52. The groove 77 can be formed by etching using any acceptable etching process (e.g., a dry etching process (e.g., RIE, NBE, etc.)) or a wet etching process (e.g., tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.) or a combination thereof). The etching process can be anisotropic. In some embodiments, the material of the gate spacer 86 and / or the gate seal spacer 80 is maintained on the STI region 56 between adjacent fins 52 (not shown in the figure). In some embodiments, the groove 77 extends into the fin 52 below the top surface of the STI region 56. In other embodiments, after the groove 77 is formed, a portion of the fin 52 protrudes from the STI region 56. The STI region 56 between adjacent fins 52 can be flush as shown, or can have a convex or concave surface. In Figures 10C to 13B , the position of the channel region 58 of the fin 52 under the dummy gate structure (e.g., the channel region 58 that is not etched to form the groove 77) is shown for reference.

[0044] Turning to Figure 11 , according to some embodiments, a first deposition process is performed to form an epitaxial region 81 in the groove 77. The epitaxial region 81 can be epitaxially grown using a suitable process such as CVD, metalorganic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc. or a combination thereof. For example, the first deposition process can include a process performed at a pressure of about 5 Torr to about 300 Torr or at a temperature of about 500 °C to about 800 °C. In some embodiments, the first deposition process can include gases and / or precursors such as SiH4, DCS, Si2H6, GeH4, PH3, AsH3, B2H6, HCl, etc. or a combination thereof. The gases and / or precursors can flow into the processing chamber at a rate between about 10 sccm and about 2000 sccm. The first deposition process can be performed over a period of time between about 50 seconds and about 3000 seconds. Other deposition processes or process parameters can be used.

[0045] The epitaxial region 81 can include any acceptable material, e.g., suitable for an n-type FinFET or a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial region 81 in the region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. If the fin 52 is silicon, the epitaxial region 81 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial region 81 can have a surface that protrudes from the corresponding surface of the fin 52 and can have a facet.

[0046] As shown Figure 11 in FIG. 2, the epitaxial materials formed in adjacent fins 52 may fuse to form a continuous epitaxial region 81. An air gap 79 may be formed between and under the epitaxial materials (formed on the adjacent fins 52). In some embodiments where the epitaxial region 81 is fused, the air gap 79 may have a "fusion height" HM1 above the STI region 56, which is between about 5 nm and about 50 nm. During a first deposition process, the surface of the epitaxial material may have facets with various crystal orientations. For example, the surface near the top of the channel region 58 and the surface near the bottom of the channel region 58 may have {111} facets. Other surfaces may have other facets, such as {110} facets, or may have a combination of facets, such as a combination of {111} facets and {110} facets, or other facets. In some embodiments, a higher HCl flow rate during the deposition process may result in surfaces with {100} facets, surfaces with {100} facets, and / or surfaces with {111} facets having more similar growth rates. Thus, increasing the flow rate of HCl during the deposition process may promote the growth of surfaces having a combination of {100} facets, {110} facets, and / or {111} facets.

[0047] In some cases, during the first deposition process, the epitaxial region 81 grows laterally from each fin 52, where the growth boundary is substantially determined by the formation of {111} facets. In other words, the shape of the epitaxial region 81 is substantially determined by the {111} facets, and the maximum size (e.g., volume or cross-sectional area) of the epitaxial region 81 is substantially determined by the {111} facets. As an illustrative example, Figure 11 FIG. 3 shows the {111} facets that substantially define the growth boundary of the epitaxial region 81, represented by the dashed contour labeled "{111}". Due to the growth of the facets, the shape and size of the epitaxial region 81 are substantially restricted within this dashed contour. Thus, the growth of the epitaxial region 81 may be "facet-limited".

[0048] During the first deposition process, the epitaxial material may initially form a lower {111} facet near the bottom of the channel region 58 and an upper {111} facet near the top of the channel region 58. As the first deposition process continues, the epitaxial material grows along these upper and lower {111} facets, where the lateral growth rate is greatly reduced beyond the intersection of the upper and lower {111} facets. In this way, the maximum lateral growth of the epitaxial material may be approximately defined by the upper and lower {111} facets. In Figure 11Among them, the points that approximately define the lateral growth boundary of the epitaxial region 81 by the {111} facet are represented as points "LP". The LP points can have a height HL between about 20 nm and about 50 nm above the STI region 56, which can depend on the depth of the trench 77 or the height of the exposed portion of the fin 52. In some cases, after the growth of the epitaxial region 81 reaches the LP points defined by the {111} facets, the growth rate of the epitaxial region 81 may be significantly reduced. In some cases, the height HL can be about half of the height of the trench 77, or can be about half of the height HF of the epitaxial region 82 (see Figure 13B ). The maximum lateral width of the epitaxial material can be approximately determined by the distance between the opposing LP points, and in some embodiments, the distance between the opposing LP points can be between about 40 nm and about 100 nm. In the case where adjacent fins 52 are close enough (e.g., having a small enough pitch PF) such that the epitaxial material grown on the adjacent fins 52 has overlapping {111} facets, the epitaxial material can fuse together into a continuous epitaxial region 81. The bottom surface of the epitaxial material as the {111} facet fuses at a height HM0 above the STI region, which is approximately defined by the intersection of the {111} facets and may depend on the pitch PF. In some embodiments, the height HM0 can be between about 10 nm and about 60 nm.

[0049] In some embodiments, the first deposition process stops before the lateral growth of the epitaxial region 81 reaches the point LP. In this way, the epitaxial region 81 can be formed with regions having surfaces with different crystal orientations. For example, as Figure 11 shown, the lower region 83A near the bottom of the channel region 58 and the upper region 83B near the top of the channel region 58 can have surfaces including {111} facets. In Figure 11 , this is also shown by the lower region 83A and the upper region 83B, and the lower region 83A and the upper region 83B have surfaces along the dashed line contour "{111}" indicating the growth-limiting {111} facets. The surface between the lower region 83A and the upper region 83B, such as Figure 11 the surface of the intermediate region 83C shown in, can have other facets such as {110} facets, or can have a combination of facets such as a combination of {111} facets and {110} facets, or other facets. As Figure 11As shown, the epitaxial material on each fin 52 can be separate or can be fused into a continuous epitaxial region 81. Additionally, by stopping the first deposition process in this manner, an epitaxial region 81 with a smaller cross-sectional area can be formed, which can reduce the parasitic capacitance (e.g., Cgd) of the FinFET device, as will be described in more detail below. In some embodiments, the first deposition process is stopped before the facets growing along the bottom surface of the epitaxial material fuse (e.g., at height HM0). In these embodiments, the epitaxial material can fuse at a height HM1 greater than height HM0.

[0050] In Figure 12 , according to some embodiments, an etch-back process is performed on the epitaxial region 81. The etch-back process can include, for example, an anisotropic dry etching process. The etch-back process can include a variety of gases and / or precursors, such as HCl, GeH4, SiH4, etc. or combinations thereof. The process gas can flow into the processing chamber at a rate of from about 20 sccm to about 3000 sccm. The etch-back process can include a process temperature in the range from about 600 °C to about 800 °C, and can include a process pressure in the range from about 3 Torr to about 300 Torr. The etch-back process can be performed over a time period between about 1 second and about 300 seconds (e.g., about 50 seconds).

[0051] In some embodiments, the characteristics of the etch-back process are controlled such that a surface having {110} facets is etched at a higher rate than a surface having {111} facets. For example, the etch-back process may include gases and / or precursors such as HCl, Cl2, H2, N2, etc. or combinations thereof. The etch-back process may include a process pressure between 5 Torr and about 300 Torr, or a process temperature between about 600 °C and about 800 °C. In some embodiments, the ratio of the etch rate of the {111} facets to the etch rate of the {110} facets can be controlled by controlling the process temperature of the etch-back process. In some cases, the {111} facets and the {110} facets may have different activation energies for the etch reaction of the etch-back process, and controlling the process temperature can increase or decrease the etch rate ratio due to the difference in activation energy. In some embodiments, the etch-back process etches the {110} facets at a rate that is at least about 4 times greater than the {111} facets. Thus, compared to the etch-back process etching the lower region 83A or the upper region 83B, the etch-back process can etch the intermediate region 83C more, and thus can etch more in the lateral direction. In this way, the intermediate region 83C can have a flatter (e.g., less rounded or more vertical) profile after the etch-back process. In some cases, after the etch-back process, the lower region 83A and the upper region 83B have surfaces that are substantially {111} facets, and the intermediate region 83C has a surface that includes {111} and {110} facets. In some cases, the lower region 83A is etched less than the upper region 83B, as Figure 12 shown.

[0052] In some embodiments, the epitaxial material on the fin 52 becomes unfused by the etch-back process. In other embodiments, as Figure 12As shown, after the etch-back process, the epitaxial material remains fused as the epitaxial region 81. In some embodiments, due to the etch-back process, the fusion height HM1 of the air gap 79 can increase. For example, after the etch-back process, the fusion height HM2 of the air gap 79 above the STI region 56 can be between about 10 nm and about 60 nm, and this fusion height HM2 can be higher than the height HM1 of the air gap 79 before the etch-back process. In this way, the etch-back process can reduce the total cross-sectional area of the epitaxial region 81, which can include increasing the fusion height of the fused epitaxial material in the epitaxial region 81. In some cases, epitaxial material with a small or incomplete fusion region can allow the gas-phase etchant to more easily reach the bottom side of the epitaxial region 81 (e.g., adjacent to the air gap 79), and allow an increase in the etching of the bottom side of the epitaxial region 81. Additionally, since the unbiased gas-phase etchant can more easily reach the bottom side of the epitaxial region 81, the use of the anisotropic etch-back process as described above can allow an increase in the etching of the bottom side of the epitaxial region 81.

[0053] In Figure 13A and Figure 13B According to some embodiments, a second deposition process is performed to deposit epitaxial material on the epitaxial region 81 to form the epitaxial region 82. Figure 13A and Figure 13B show the same cross-sectional view, and for clarity, the features are individually labeled on each figure. The epitaxial material of the epitaxial region 82 can be epitaxially grown using a suitable process such as CVD, MOCVD, MBE, LPE, VPE, SEG, etc. or a combination thereof. The epitaxial material deposited on the epitaxial region 81 can include materials similar to those deposited during the first deposition process described above. For example, the second deposition process can include a process performed at a pressure of about 5 Torr to about 300 Torr or at a process temperature of about 500 °C to about 800 °C. In some embodiments, the second deposition process can include gases and / or precursors such as SiH4, DCS, Si2H6, GeH4, PH3, AsH3, B2H6, HCl, etc. or a combination thereof. The gases and / or precursors can flow into the processing chamber at a rate between about 10 sccm and about 2000 sccm. The second deposition process can be performed over a time period between about 50 seconds and about 3000 seconds. Other deposition processes or process parameters can be used. The epitaxial material deposited by the second deposition process can be similar to or different from the epitaxial material deposited by the first deposition process, for example, having a different semiconductor composition or having different doping. The epitaxial region 82 can have a surface that protrudes from the corresponding surface of the fin 52 and can have facets.

[0054] As Figure 13AAs shown in FIG. -B, the epitaxial material is deposited over the epitaxial region 81 and between the fins 52 such that the epitaxial region 82 is a continuous region. In some cases, the growth rate of the epitaxial material between the fins 52 can be greater than the growth rate of the epitaxial material on other surfaces, especially in cases where the epitaxial material is fused. The epitaxial region 82 can have a substantially flat top surface, or the top surface can be concave, convex, or "wavy". In some embodiments, the epitaxial material deposited by the second deposition process can have facets with various crystal orientations. For example, the lower region 85A of the epitaxial region 82 can have a surface substantially having {111} facets. In some embodiments, the lower region 85A can extend at a height HSA between about 5 nm and about 60 nm. In some embodiments, the upper region 85B of the epitaxial region 82 can have a surface substantially having {111} facets. In some embodiments, the upper region 85B can extend at a height HSB between about 0 nm and about 30 nm. In some cases, an epitaxial region 81 with a small or incomplete fusion region can allow precursors to more easily reach the bottom side of the epitaxial region 81 (e.g., adjacent to the air gap 79), and thus can allow some epitaxial material to be deposited on the bottom side of the epitaxial region 81. In some cases, some epitaxial material can be deposited near the bottom of the lower region 85A.

[0055] In some embodiments, the intermediate region 85C of the epitaxial region 82 located between the lower region 85A and the upper region 85B has a surface including {110} facets. The intermediate region 85C can also include a combination of {110} facets and {111} facets, or other facets. The surface of the lower region 85A deviates from the {111} facets at the boundary between the lower region 85A and the intermediate region 85C, which can be, for example, at or near the height HSA. Figure 13A An example boundary point between the lower region 85A and the intermediate region 85C, i.e., the "slope turning point" STP, is shown. In some embodiments, the intermediate region 85C can have a greater sidewall slope than the sidewall slope of the lower region 85A and / or the sidewall slope of the upper region 85B. The position of the STP on the epitaxial region 82 (e.g., the height HSA) can be controlled by controlling the parameters of the first deposition process, the etch-back process, and / or the second deposition process. In some embodiments, the length of the {111} facets in the lower region 85A can depend on the amount of {111} facet material deposited by the first deposition process and / or the amount of {111} facet material deposited by the second deposition process. For example, performing the first deposition process and / or the second deposition process for a longer duration can grow more {111} facet material in the lower region 85A, thereby increasing the height HSA of the STP. As another example, performing the etch-back process for a longer duration can etch more material of the lower region 83A (seeFigure 12 ), and thus the height HSA of the STP can be reduced.

[0056] In some cases, once the epitaxial region 82 has significantly merged, the growth rate of the epitaxial material on the bottom side of the epitaxial region 82 can be greatly reduced. In this way, the position of the STP can be approximately determined by the merging of the epitaxial region 82. In some cases, if the growth rate of the {111} facet is lower than the growth rate of the {110} facet, the boundary during the growth of the epitaxial material 81 is mainly determined by the surface with the {111} facet. In this case, the relatively slow growth rate of the {111} facet can cause the position of the STP to be closer to the merging point MP (described in more detail below), and the HSA is thus relatively high. In some cases, the growth rate of the {111} facet with a growth rate closer to that of the {110} facet may cause the position of the STP to be far from the merging point MP, and the HSA is thus relatively low. In this way, the position of the STP and the height of the HSA can be controlled by controlling the relative growth rates of the {111} facet and the {110} facet (e.g., the ratio of the growth rates). These are examples, and the position or height HSA of the STP can be controlled by controlling different parameters or different combinations of parameters.

[0057] The techniques described herein can reduce the total cross-sectional area of the epitaxial region 82. By reducing the total cross-sectional area of the epitaxial region 82, the gate-to-drain capacitance (Cgd) of the FinFET device can be reduced, which can improve the performance of the FinFET device. For example, the RC delay of the FinFET device can be reduced, and the response speed of the FinFET device can be increased. In some embodiments, the cross-sectional area of the epitaxial region 82 can be reduced to between about 5% and about 60% of the cross-sectional area limited by the maximum facet shown by the dashed contour labeled "{111}". In some embodiments, the cross-sectional area limited by the maximum facet can be between about 1000 nm 2 and about 6000 nm 2 and the cross-sectional area of the epitaxial region 82 can be between about 500 nm 2 and about 5000 nm 2 Other cross-sectional areas of the epitaxial region 82 are possible.

[0058] In some embodiments, by controlling a first deposition process, a re-etch process, and a second deposition process, the cross-sectional area of the epitaxial region 82 can be reduced by reducing the lateral width of the epitaxial region 82. For example, the lateral width of the epitaxial region 82 can be reduced to between about 5% and about 70% of the lateral width of the maximum facet limit (e.g., between opposite LP points). In some embodiments, the lateral width of the epitaxial region 82 can be between about 40 nm and about 80 nm, but other lateral widths can be achieved. Additionally, the cross-sectional area of the epitaxial region 82 can be reduced by increasing the height of the air gap 79. For example, after the second deposition process, the air gap 79 can have a merged height HMP above the STI region 56 that is between about 15 nm and about 60 nm. By increasing the height HMP, the cross-sectional area of the epitaxial region 82 is reduced, and the capacitance Cgd can be correspondingly reduced. In some cases, the height of the air gap 79 can be closer to the top surface of the epitaxial region 82 than the STI region 56 in the vertical direction. In some embodiments, the second deposition process deposits epitaxial material on a portion of the bottom side of the epitaxial region 81 such that the height HMP is less than the height HM2 (see Figure 12 ). In other embodiments, the second deposition process does not deposit epitaxial material on a portion of the bottom side of the epitaxial region 81 such that the height HMP is substantially the same as the height HM2 (see Figure 12 ). In some embodiments, the height HMP can be greater than the height HM1 (see Figure 11 ). In some embodiments, the merged height HMP can be greater than the merged height HM0 of the facet limit. For example, the height HMP can be greater than the height HM0 by about 3 nm to about 15 nm. In some embodiments, the height HMP can be greater than the height HL, but in other embodiments, the height HMP can be approximately equal to or less than the height HL. Other dimensions, heights, or relative heights are also possible.

[0059] Turning to Figure 13B , points on the sidewalls of the air gap 79 are marked for reference. Point P0 indicates the bottom point of the epitaxial region 82, point STP indicates the "slope turning point" as described above, and point MP indicates the "merged point" at the top of the air gap 79. Additionally, point M0 indicates the "merged point" of the cross-sectional area of the facet limit (shown by the dashed contour labeled "{111}"). As Figure 13B shows, M0 and MP are laterally located approximately midway between adjacent fins 52. In some embodiments, a first vertical distance from the top surface of the epitaxial region 82 to MP is less than half of a second vertical distance from the top surface of the epitaxial region 82 to the STI region 56.

[0060] Due to the difference in the facets between the lower region 85A and the middle region 85C, the sidewall slope of the epitaxial region 82 changes at or near the "slope turning point" STP. As an illustrative example, Figure 14A For Figure 13B the points P0, STP, MP, and M0 shown illustrate the relationship between the tilt angle and the sidewall position. The sidewall of the epitaxial region 82 from P0 to STP in the lower region 85A has a tilt angle A0 of approximately 54.7°, corresponding to the crystal plane of the {111} facet. In the middle region 85C, from STP to MP, the sidewall has a tilt angle A1, which can be an angle between approximately 54.7° and approximately 90°, such as approximately 78°. The sidewall from STP to MP can have more than one tilt angle or can have a varying tilt angle, and the transition between the tilt angles near STP can be abrupt or gradual. Figure 14B A diagram showing the profile of the epitaxial region 82, corresponding to a part of the cross-sectional view from Figure 13B the P0 shown to the fusion at 1 / 2PF. The profile of the epitaxial region 82 from P0 to STP corresponds to the crystal plane of the {111} facet. If the profile between P0 and 1 / 2PF also follows the {111} plane, the profile would follow a straight line from STP to M0 and have a corresponding tilt angle of approximately 54.7°. However, due to the change in slope near STP, the slope of the profile between STP and the fusion point MP is greater. Figure 14B A diagram shows an abrupt change in the profile slope at STP, but the profile change can be gradual or curved. As an illustrative example, Figure 14B four possible fusion points MP1, MP2, MP3, and MP4 are shown, each with an increasingly larger profile slope from STP. The techniques described herein allow the profile slope between STP and the fusion point (e.g., MP1, MP2, MP3, or MP4) to be greater than the slope corresponding to the {111} facet, and thus a higher fusion point can be formed. For example, the profile slope from STP to MP3 is greater than the profile slope from STP to MP1, and thus the fusion point MP3 is higher than the fusion point MP1, and both are higher than the fusion point M0. In this way, the shape and slope of the epitaxial region can be controlled to increase the fusion height of the epitaxial region. As shown in Figure 13B and Figure 14A -B, the middle region 85C has a larger tilt angle than the lower region 85A, and thus MP is higher than M0.

[0061] By controlling the parameters of the first deposition process, the second deposition process, and the etch-back process, the sidewall positions of the tilt angle A1 and the slope turning point STP can be controlled, and the height HMP of the merge point MP can be controlled. For example, as previously described, the first deposition process and / or the second deposition process can be controlled to reduce the formation of facets in the upper and lower regions, or the etch-back process can be controlled by etching the {110} facets at a rate greater than that of the {111} facets to increase the tilt angle A1. Other examples are possible. Additionally, as previously described, controlling the temperature during the deposition of the epitaxial material can control the relative growth rates of the {111} and {110} facets, which can control the position of the STP, the position of the MP, or the facet ratio that determines the tilt angle A1. The position of the MP can also be determined by controlling the position of the STP, controlling the tilt angle A1, or selecting a specific fin pitch PF. As an illustrative example, Figure 15 shows the range of possible merge heights HMP for an epitaxial region 82 with a given fin pitch PF. For facet-limited growth, the merge height HMP is limited to the heights within region 151, where the merge height HMP is equal to the height HM0, and the maximum merge height HMP is the height HL. Using the techniques described herein, the formation of the epitaxial region 82 can be controlled to have any merge height HMP within region 153, which includes the heights within region 151. As shown, the techniques described herein allow for greater design flexibility for the epitaxial region ⑧2, including reducing the cross-sectional area.

[0062] In some embodiments, the epitaxial region 82 can be formed of merged epitaxial material grown in more than two fins 52. Figure 16 An example multi-fin embodiment is shown, but the epitaxial region 82 can be formed over more or fewer fins 52 than shown. The techniques described herein can be used to reduce the cross-sectional area of the epitaxial region 82 in this and other multi-fin embodiments. It should be noted that other techniques for controlling the slope turning point STP and / or increasing the merge height HMP to reduce the cross-sectional area of the epitaxial region 82 can be used, including but not limited to performing additional deposition processes or etch-back processes.

[0063] In some embodiments, as Figure 13A shown in -B, the spacer etch used to form the gate spacer 86 can be adjusted to remove spacer material to allow the material grown epitaxially to extend to the surface of the STI region 56. In other embodiments, the gate spacer 86 is formed to cover a portion of the sidewalls of the fins 52 that extends above the STI region 56, thereby preventing epitaxial growth on these portions. The epitaxial source / drain regions 82 and / or the fins 52 can be implanted with dopants to form the source / drain regions, which is similar to the process previously discussed for forming lightly doped source / drain regions and then annealing. The source / drain regions can have a doping concentration of about 10 19cm -3 about 10 21 cm -3 The impurity concentration between. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in-situ during growth.

[0064] Figure 17A and Figure 17B In, a first interlayer dielectric (ILD) 88 is deposited over the structure. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 86. The CESL 87 can include a dielectric material having an etch rate different from that of the material overlying the first ILD 88, such as silicon nitride, silicon oxide, silicon oxynitride, etc. In some embodiments, the air gap 79 remains empty (e.g., without the first ILD 88 or the CESL 87). In other embodiments, the first ILD 88 or the CESL 87 can be deposited within the air gap 79.

[0065] In Figure 18A and Figure 18B In, a planarization process, such as CMP, can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72 and portions of the gate seal spacer 80 and the gate spacers 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate seal spacer 80, the gate spacers 86, and the first ILD 88 are flush. Thus, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0066] In Figure 19A and Figure 19BIn [the structure], the dummy gate 72 and the mask 74 (if any) are removed in one or more etching steps to form a groove 90. The portion of the dummy dielectric layer 60 within the groove 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the groove 90. In some embodiments, the dummy dielectric layer 60 is removed from the groove 90 in a first region (e.g., the core logic region) of the die and remains in the groove 90 in a second region (e.g., the input / output region) of the die. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each groove 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, when etching the dummy gate 72, the dummy dielectric layer 60 may be used as an etch stop layer. Then, the dummy dielectric layer 60 may optionally be removed after removing the dummy gate 72.

[0067] In Figure 20A and Figure 20B [the structure], a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 20C FIG. [the figure number] shows Figure 20B a detailed view of the region 89. The gate dielectric layer 92 is conformally deposited within the groove 90, e.g., on the top surface and sidewalls of the fin 52, and on the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multi-layer thereof. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The method of forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy dielectric layer 60 remains within the groove 90, the gate dielectric layer 92 includes the material of the dummy dielectric layer 60 (e.g., SiO2).

[0068] The gate electrode 94 is deposited respectively on top of the gate dielectric layer 92 and fills the remaining portion of the groove 90. The gate electrode 94 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, and combinations or multi-layers thereof. For example, although a single-layer gate electrode 94 is shown in Figure 20Bshown, but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and fill material 94C, as Figure 20C shown. After filling the trench 90, a planarization process (e.g., CMP) may be performed to remove the excess portions of the material of the gate electrode 94 and the gate dielectric layer 92 that are above the top surface of the ILD 88. Thus, the remaining portions of the material of the gate electrode 94 and the gate dielectric layer 92 form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0069] The formation of the gate dielectric layer 92 in regions 50N and 50P may occur simultaneously such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 may occur simultaneously such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by different processes such that the gate dielectric layer 92 may be different materials, and / or the gate electrode 94 in each region may be formed by different processes such that the gate electrode 94 may be different materials. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0070] In Figure 21A and Figure 21B a second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD and PECVD. According to some embodiments, prior to forming the second ILD 108, the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is recessed to form a trench directly over the gate stack and between opposing portions of the gate spacer 86, as Figure 21A and Figure 21B shown. A gate mask 96 including one or more dielectric materials (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the trench, followed by a planarization process to remove the excess portions of the dielectric material that extend above the first ILD 88. The subsequently formed gate contact 110 (see Figure 22A -B) passes through the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0071] In Figure 22A and Figure 22BIn some embodiments, the gate contact 110 and the source / drain contact 112 are formed to penetrate through the second ILD 108 and the first ILD 88. The opening of the source / drain contact 112 is formed to penetrate through the first ILD 88 and the second ILD 108, and the opening of the gate contact 110 is formed to penetrate through the second ILD 108 and the gate mask 96. The openings can be formed using acceptable lithography and etching techniques. Liners and conductive materials such as diffusion barrier layers, adhesion layers, etc. are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove the excess material from the surface of the second ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contact 112 and the gate contact 110 can be formed in different processes or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 110 can be formed in a different cross-section, which can avoid short-circuiting of the contacts.

[0072] The described embodiments can provide advantages. For example, the techniques described herein can allow adjacent source / drain epitaxial regions of a FinFET device to merge from a location farther away from the substrate, which can reduce the total cross-sectional area of the merged source / drain epitaxial regions. Additionally, the merged epitaxial source / drain regions can be formed to have fewer faceted surfaces, which reduces the cross-sectional area relative to merged epitaxial source / drain regions having larger facets or faceting limitations. Reducing the area of the merged epitaxial source / drain regions in this manner can reduce the parasitic capacitance (e.g., Cgd) between the gate stack and the epitaxial source / drain regions, which can allow for improved device speed (e.g., faster on / off switching speed in a ring oscillator device, etc.), reduced RC delay effects, or reduced other performance issues due to parasitic capacitance. In some embodiments, the epitaxial source / drain regions are formed by first growing a first epitaxial layer, then performing a etch-back process to increase the merge height, and then growing a second epitaxial layer.

[0073] According to some embodiments of the present disclosure, a device includes: a first fin and a second fin extending from a substrate, the first fin including a first groove and the second fin including a second groove; an isolation region surrounding the first fin and surrounding the second fin; a gate stack located over the first fin and the second fin; and source / drain regions located in the first groove and the second groove, the source / drain regions being adjacent to the gate stack, wherein the source / drain regions include a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface above the first height has a second slope, the second slope being greater than the first slope. In an embodiment, the first portion of the bottom surface has a {111} crystal plane. In an embodiment, the second slope is between 54.7° and 90°. In an embodiment, a first vertical distance from a top surface of the source / drain region to the bottom surface is less than half of a second vertical distance from the top surface of the source / drain region to a bottom of the first groove. In an embodiment, a top surface of the source / drain region extending over the first fin and the second fin is flat. In an embodiment, the second portion of the bottom surface includes facets of at least two different crystal planes. In an embodiment, the source / drain regions further include opposing sidewalls, wherein below the first height, the sidewalls are facets of a {111} crystal plane. In an embodiment, an upper sidewall of the source / drain region extending from a second height above the isolation region to the top surface of the source / drain region is a facet of a {111} crystal plane, wherein the second height is higher than the first height. In an embodiment, between the first height and the second height, the sidewall includes a surface having a third slope, the third slope being greater than the first slope.

[0074] According to some embodiments of the present disclosure, a structure includes: a first fin located above a semiconductor substrate; a second fin located above the semiconductor substrate, the second fin being adjacent to the first fin; an isolation region surrounding the first fin and the second fin; a gate structure along sidewalls of the first fin and the second fin and located above upper surfaces of the first fin and the second fin; and source / drain regions located on the first fin and the second fin, adjacent to the gate structure, the source / drain regions including a bottom surface between the first fin and the second fin, wherein the bottom surface includes a lower surface and an upper surface, wherein the lower surface is a facet of a first crystal plane, the facet of the first crystal plane extending from a bottom of the bottom surface to a facet of a second crystal plane at a first height above the isolation region, wherein the upper surface extends from the first height to a topmost portion of the bottom surface, wherein the upper surface includes a facet of the first crystal plane and a facet of the second crystal plane. In an embodiment, the structure includes an air gap located between the first fin and the second fin, defined by the bottom surface. In an embodiment, the topmost portion of the bottom surface is closer in a vertical direction to a top surface of the source / drain region than to the isolation region. In an embodiment, the upper surface has a greater sidewall slope than the lower surface. In an embodiment, the source / drain region includes a sidewall surface from the second fin, opposite to the first fin, wherein a first portion of the sidewall surface extending from the bottom surface of the source / drain region is a facet of the first crystal plane. In an embodiment, a second portion of the sidewall surface extending from the top surface of the source / drain region is a facet of the first crystal plane. In an embodiment, a third portion of the sidewall surface between the first portion and the second portion includes a facet of the first crystal plane and a facet of the second crystal plane.

[0075] According to some embodiments of the present disclosure, a method includes: forming fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; forming a gate structure above the fins; and forming an epitaxial source / drain region adjacent to the gate structure and extending above the fins, including: performing a first deposition process to deposit a first epitaxial material on the fins, wherein a bottom surface of the first epitaxial material on adjacent fins fuses at a first height above the isolation region; performing an etching process on the first epitaxial material, wherein the etching process etches the bottom surface of the first epitaxial material; and after performing the etching process, performing a second deposition process to deposit a second epitaxial material on the first epitaxial material, the epitaxial source / drain region including the first epitaxial material and the second epitaxial material, wherein after performing the second deposition process, a bottom surface of the epitaxial source / drain region between adjacent fins extends a second height above the isolation region, the second height being greater than the first height. In an embodiment, the etching process etches a {110} surface at a rate greater than that of a {111} surface. In an embodiment, after performing the second deposition process, a surface of the epitaxial source / drain region extending from the isolation region to a third height is a {111} facet, wherein the third height is less than the first height. In an embodiment, the etching process reduces a lateral width of the first epitaxial material.

[0076] The foregoing has outlined the features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations to the present disclosure without departing from the spirit and scope of the present disclosure.

[0077] Example 1 is a semiconductor device, comprising: a first fin and a second fin extending from a substrate, the first fin including a first groove, and the second fin including a second groove; an isolation region surrounding the first fin and surrounding the second fin; a gate stack located above the first fin and the second fin; and source / drain regions located in the first groove and the second groove, the source / drain regions being adjacent to the gate stack, wherein the source / drain regions include a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface above the first height has a second slope, the second slope being greater than the first slope.

[0078] Example 2 is the device of Example 1, wherein the first portion of the bottom surface has a {111} crystal plane.

[0079] Example 3 is the device of Example 1, wherein the second slope is between 54.7° and 90°.

[0080] Example 4 is the device of Example 1, wherein a first vertical distance from a top surface of the source / drain region to the bottom surface is less than half of a second vertical distance from the top surface of the source / drain region to a bottom of the first groove.

[0081] Example 5 is the device of Example 1, wherein a top surface of the source / drain region extending above the first fin and the second fin is flat.

[0082] Example 6 is the device of Example 1, wherein the second portion of the bottom surface includes a plurality of facets of at least two different crystal planes.

[0083] Example 7 is the device of Example 1, wherein the source / drain region further includes opposing sidewalls, wherein below the first height, the sidewalls are facets of a {111} crystal plane.

[0084] Example 8 is the device described in Example 7, wherein an upper sidewall of the source / drain region extending from a second height above the isolation region to a top surface of the source / drain region is a facet of a {111} crystal plane, and wherein the second height is higher than the first height.

[0085] Example 9 is the device described in Example 8, wherein between the first height and the second height, the sidewall includes a surface having a third slope, and the third slope is greater than the first slope.

[0086] Example 10 is a semiconductor structure, including: a first fin located above a semiconductor substrate; a second fin located above the semiconductor substrate, the second fin being adjacent to the first fin; an isolation region surrounding the first fin and the second fin; a gate structure along sidewalls of the first fin and the second fin and located above upper surfaces of the first fin and the second fin; and source / drain regions located on the first fin and the second fin and adjacent to the gate structure, the source / drain regions including a bottom surface located between the first fin and the second fin, wherein the bottom surface includes a lower surface and an upper surface, wherein the lower surface is a facet of a first crystal plane, the facet of the first crystal plane extending from a bottom of the bottom surface to a facet of a second crystal plane at a first height above the isolation region, wherein the upper surface extends from the first height to an uppermost portion of the bottom surface, and wherein the upper surface includes the facet of the first crystal plane and the facet of the second crystal plane.

[0087] Example 11 is the structure described in Example 10, including an air gap located between the first fin and the second fin and defined by the bottom surface.

[0088] Example 12 is the structure described in Example 10, wherein an uppermost portion of the bottom surface is closer in a vertical direction to a top surface of the source / drain region than to the isolation region.

[0089] Example 13 is the structure described in Example 10, wherein the upper surface has a greater sidewall slope than the lower surface.

[0090] Example 14 is the structure described in Example 10, wherein the source / drain region includes a sidewall surface from the second fin and opposite to the first fin, and wherein a first portion of the sidewall surface extending from a bottom surface of the source / drain region is a facet of the first crystal plane.

[0091] Example 15 is the structure described in Example 14, wherein a second portion of the sidewall surface extending from a top surface of the source / drain region is a facet of the first crystal plane.

[0092] Example 16 is the structure described in Example 15, wherein a third portion of the sidewall surface between the first portion and the second portion includes facets of the first crystal plane and facets of the second crystal plane.

[0093] Example 17 is a method for forming a semiconductor structure, comprising: forming a plurality of fins protruding from a semiconductor substrate; forming an isolation region surrounding the plurality of fins; forming a gate structure over the plurality of fins; and forming an epitaxial source / drain region adjacent to the gate structure and extending over the plurality of fins, comprising: performing a first deposition process to deposit a first epitaxial material on the plurality of fins, wherein bottom surfaces of the first epitaxial material on adjacent fins merge at a first height above the isolation region; performing an etching process on the first epitaxial material, wherein the etching process etches the bottom surfaces of the first epitaxial material; and after performing the etching process, performing a second deposition process to deposit a second epitaxial material on the first epitaxial material, the epitaxial source / drain region comprising the first epitaxial material and the second epitaxial material, wherein after performing the second deposition process, a bottom surface of the epitaxial source / drain region between adjacent fins extends a second height above the isolation region, the second height being greater than the first height.

[0094] Example 18 is the method described in Example 17, wherein the etching process etches a {110} surface at a rate greater than that of a {111} surface.

[0095] Example 19 is the method described in Example 17, wherein after performing the second deposition process, a surface of the epitaxial source / drain region extending from the isolation region to a third height is a {111} facet, wherein the third height is less than the first height.

[0096] Example 20 is the method described in Example 17, wherein the etching process reduces a lateral width of the first epitaxial material.

Claims

1. A semiconductor device, comprising: a first fin and a second fin extending from a substrate, the first fin including a first groove, and the second fin including a second groove; an isolation region surrounding the first fin and surrounding the second fin; a gate stack located above the first fin and the second fin; and source / drain regions located in the first groove and the second groove, the source / drain regions adjacent to the gate stack, wherein the source / drain regions include a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface above the first height has a second slope, the second slope being greater than the first slope, wherein a topmost portion of the bottom surface is closer in a vertical direction to a top surface of the source / drain regions rather than to the isolation region.

2. The device according to claim 1, wherein The first portion of the bottom surface has a {111} crystal plane.

3. The device according to claim 1, wherein The second slope is between 54.7° and 90°.

4. The device according to claim 1, wherein, A first vertical distance from the top surface of the source / drain regions to the bottom surface is less than half of a second vertical distance from the top surface of the source / drain regions to a bottom of the first groove.

5. The device according to claim 1, wherein, A top surface of the source / drain regions extending above the first fin and the second fin is flat.

6. The device according to claim 1, wherein The second portion of the bottom surface includes a plurality of facets of at least two different crystal planes.

7. The device according to claim 1, wherein The source / drain regions further include opposing sidewalls, wherein below the first height, the sidewalls are facets of a {111} crystal plane.

8. The device according to claim 7, wherein, An upper sidewall of the source / drain regions extending from a second height above the isolation region to the top surface of the source / drain regions is a facet of a {111} crystal plane, wherein the second height is higher than the first height.

9. The device according to claim 8, wherein Between the first height and the second height, the sidewalls include a surface having a third slope, the third slope being greater than the first slope.

10. A semiconductor structure, comprising: a first fin located above a semiconductor substrate; a second fin located above the semiconductor substrate, the second fin adjacent to the first fin; an isolation region surrounding the first fin and the second fin; a gate structure along sidewalls of the first fin and the second fin and located above upper surfaces of the first fin and the second fin; and source / drain regions located on the first fin and the second fin, adjacent to the gate structure, the source / drain regions including a bottom surface located between the first fin and the second fin, wherein the bottom surface includes a lower surface and an upper surface, wherein the lower surface is a facet of a first crystal plane extending from a bottom of the bottom surface to a second crystal plane of a facet at a first height above the isolation region, wherein the upper surface extends from the first height to a topmost portion of the bottom surface, wherein the upper surface includes the facet of the first crystal plane and the facet of the second crystal plane.

11. The structure according to claim 10 includes an air gap, which is located between the first fin and the second fin and is defined by the bottom surface.

12. The structure according to claim 10, wherein, The uppermost part of the bottom surface is closer to the top surface of the source / drain region in the vertical direction than to the isolation region.

13. The structure according to claim 10, wherein, The upper surface has a larger sidewall slope than the lower surface.

14. The structure according to claim 10, wherein The source / drain region includes a sidewall surface from the second fin, opposite to the first fin, wherein a first portion of the sidewall surface extending from the bottom surface of the source / drain region is a facet of the first crystal plane.

15. The structure according to claim 14, wherein, A second portion of the sidewall surface extending from the top surface of the source / drain region is a facet of the first crystal plane.

16. The structure according to claim 15, wherein, A third portion of the sidewall surface between the first portion and the second portion includes facets of the first crystal plane and facets of the second crystal plane.

17. A method for forming a semiconductor structure includes: forming a plurality of fins protruding from a semiconductor substrate; forming an isolation region surrounding the plurality of fins; forming a gate structure over the plurality of fins; and forming an epitaxial source / drain region adjacent to the gate structure and extending over the plurality of fins, including: performing a first deposition process to deposit a first epitaxial material on the plurality of fins, wherein the bottom surface of the first epitaxial material on adjacent fins merges at a first height above the isolation region; performing an etching process on the first epitaxial material, wherein the etching process etches the bottom surface of the first epitaxial material; and after performing the etching process, performing a second deposition process to deposit a second epitaxial material on the first epitaxial material, the epitaxial source / drain region including the first epitaxial material and the second epitaxial material, wherein after performing the second deposition process, the bottom surface of the epitaxial source / drain region between adjacent fins extends a second height above the isolation region, and the second height is greater than the first height.

18. The method according to claim 17, wherein, The etching process etches the {110} surface at a rate greater than the {111} surface.

19. The method according to claim 17, wherein, After performing the second deposition process, the surface of the epitaxial source / drain region extending from the isolation region to a third height is a {111} facet, wherein the third height is less than the first height.

20. The method according to claim 17, wherein The etching process reduces the lateral width of the first epitaxial material.

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