Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is provided. The three-dimensional semiconductor memory device includes: first semiconductor patterns that are vertically separated from each other on a substrate, each first semiconductor pattern including a first end portion and a second end portion that are separated from each other, and a first side surface and a second side surface that are separated from each other to connect the first end portion and the second end portion; a first source / drain region and a second source / drain region that are disposed in each first semiconductor pattern and are adjacent to the first end portion and the second end portion, respectively; a channel region that is located in each first semiconductor pattern and is between the first source / drain region and the second source / drain region; a first word line that is adjacent to the first side surface and the channel region and extends vertically; and a gate insulating layer that is disposed between the first word line and the first side surface. The gate insulating layer may extend to be disposed between the first source / drain regions.

Description

[0001] Korean Patent Application No. 10-2019-0135889, filed on Oct. 29, 2019, with the Korean Intellectual Property Office and entitled "Three-Dimensional Semiconductor Memory Device" is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a three-dimensional semiconductor memory device having an increased integration density. BACKGROUND ART

[0003] In order to meet consumers' demands for excellent performance and low price, semiconductor devices with higher integration density are required. In the case of semiconductor devices, since the integration density of semiconductor devices is an important factor determining product price, an increase in integration density is particularly required. In the case of two-dimensional semiconductor devices or planar semiconductor devices, since the integration density of two-dimensional semiconductor devices or planar semiconductor devices is mainly determined by the area occupied by a unit memory cell, the integration density is greatly affected by the level of fine pattern formation technology. However, the extremely expensive process equipment required to increase pattern fineness places practical limitations on increasing the integration density of two-dimensional semiconductor devices or planar semiconductor devices. To overcome this limitation, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed. SUMMARY OF THE INVENTION

[0004] According to an embodiment, a three-dimensional semiconductor memory device may include: a first semiconductor pattern, a first source / drain region, a second source / drain region, a channel region, a first word line, and a gate insulating layer. The first semiconductor pattern may be vertically stacked on a substrate and may be separated from each other. Each first semiconductor pattern may include a first end portion and a second end portion separated from each other and a first side surface and a second side surface separated from each other to connect the first end portion to the second end portion. The first source / drain region and the second source / drain region may be provided in each first semiconductor pattern and may be respectively provided adjacent to the first end portion and the second end portion. The channel region may be provided in each first semiconductor pattern and may be provided between the first source / drain region and the second source / drain region. The first word line may be adjacent to the first side surface of the first semiconductor pattern and the channel region and may extend in a first direction perpendicular to the top surface of the substrate. The gate insulating layer may be disposed between the first word line and the first side surface of the first semiconductor pattern. The gate insulating layer may extend to be disposed between the first source / drain regions.

[0005] According to an embodiment, a three-dimensional semiconductor memory device may include a first semiconductor pattern and a second semiconductor pattern disposed on a substrate and spaced apart from each other in a first direction, a first word line disposed between the first semiconductor pattern and the second semiconductor pattern and adjacent to the first semiconductor pattern, a second word line disposed between the first semiconductor pattern and the second semiconductor pattern and adjacent to the second semiconductor pattern, and a shield line disposed between the first word line and the second word line and electrically disconnected from the first word line and the second word line.

[0006] According to an embodiment, a three-dimensional semiconductor memory device may include an interlayer insulating layer and a semiconductor pattern alternately stacked on a substrate, and a word line penetrating the semiconductor pattern and the interlayer insulating layer and adjacent to the substrate. The word line may include a word line portion and a protruding portion, the word line portion extending vertically from the top surface of the substrate, and the protruding portion protruding from the side surface of the word line portion toward the interlayer insulating layer and spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Features will become apparent to those of ordinary skill in the art by describing exemplary embodiments in detail with reference to the drawings.

[0008] Figure 1 A circuit diagram of a cell array of a three-dimensional semiconductor memory device according to an embodiment is shown.

[0009] Figure 2 A perspective view of a three-dimensional semiconductor memory device according to an embodiment is shown.

[0010] Figure 3A A plan view of a three-dimensional semiconductor memory device according to an embodiment is shown.

[0011] Figure 3B A cross-sectional view taken along lines A-A', B-B', and C-C' is shown. Figure 3A is shown.

[0012] Figure 3C A perspective view of a portion “P1” of Figure 3B is shown.

[0013] Figure 4A , Figure 5A and 7A to 12A are plan views of stages in a process of manufacturing the three-dimensional semiconductor memory device in Figure 3A .

[0014] Figure 4B , Figure 5B and FIG. 7B to FIG. 12B respectively show cross-sectional views taken along lines A-A', B-B', and C-C' of Figure 4A , Figure 5A and 7A to 12A .

[0015] Figure 6 shows a cross-sectional view of a process for manufacturing a three-dimensional semiconductor memory device Figure 3B in

[0016] FIG. 13A to FIG. 13E shows a perspective view of a three-dimensional semiconductor memory device according to an embodiment.

[0017] Fig.14A shows a plan view of a three-dimensional semiconductor memory device according to an embodiment.

[0018] Fig. 14B shows a cross-sectional view taken along Fig.14A lines A-A', B-B', and C-C'.

[0019] Fig. 14C shows a perspective view of a part (e.g., Fig. 14B "P2") of a three-dimensional semiconductor memory device according to an embodiment.

[0020] FIG. 15A to FIG. 19A shows a process for manufacturing Fig.14A a three-dimensional semiconductor memory device in a stage of the process.

[0021] FIG. 15B to FIG. 19B Respectively show cross-sectional views taken along FIG. 15A to FIG. 19A lines A-A', B-B', and C-C'.

[0022] FIG. 20A to FIG. 20C shows a perspective view of a part of a three-dimensional semiconductor memory device according to an embodiment.

[0023] Fig.21 shows a cross-sectional view of a process for manufacturing Fig. 20A or Fig. 20B a three-dimensional semiconductor memory device.

[0024] Fig. 22 shows a perspective view of a part of a three-dimensional semiconductor memory device according to an embodiment.

[0025] Fig.23A and Fig. 23B shows a cross-sectional view of a stage in a process for manufacturing Fig. 22 a three-dimensional semiconductor memory device.

[0026] Fig.24A and Fig. 24B shows a perspective view of a three-dimensional semiconductor memory device according to an embodiment.

[0027] Fig.25A and Fig.25B shows a process for manufacturing Fig.24A or Fig. 24B Cross-sectional views of stages in the process of a three-dimensional semiconductor memory device.

[0028] Fig.26A Shows cross-sectional views along Fig.14A lines A-A', B-B' and C-C' of

[0029] Fig.26B Shows Fig.26A a perspective view of part "P3" of

[0030] Fig. 27 Shows Fig.26A cross-sectional views of the process of manufacturing a three-dimensional semiconductor memory device of

[0031] Figures 28 to 37 Shows a perspective view of a three-dimensional semiconductor memory device according to an embodiment.

[0032] Figures 38 to 41 Shows a perspective view of a three-dimensional semiconductor memory device according to an embodiment.

[0033] Fig.42 and Fig.43 Shows a perspective view of a three-dimensional semiconductor memory device according to an embodiment.

[0034] Fig.44 and Fig.45 Shows a perspective view of a three-dimensional semiconductor memory device according to an embodiment.

[0035] Fig.46 Shows a perspective view of a part of a three-dimensional semiconductor memory device according to an embodiment.

[0036] Fig.47A Shows Fig.46 a plan view of the process of manufacturing a three-dimensional semiconductor memory device of

[0037] Fig.47B Shows cross-sectional views along Fig.47A lines A-A', B-B' and C-C' of

[0038] Fig.48A Shows a plan view of a three-dimensional semiconductor memory device according to an embodiment.

[0039] Fig.48B Shows cross-sectional views along Fig.48A lines A-A', B-B' and C-C' of

[0040] Fig.48C Shows Fig.48B a perspective view of the word lines in

[0041] Fig.49A and Fig.50A shows a plan view of stages in a process of manufacturing a three-dimensional semiconductor memory device. Fig.48A in

[0042] Fig.49B and 50B shows cross-sectional views taken along lines A-A', B-B', and C-C' of Fig.49A and Fig.50A respectively. Detailed Description

[0043] Figure 1 is a circuit diagram schematically showing a cell array of a three-dimensional semiconductor memory device according to an embodiment.

[0044] Referring to Figure 1 , the cell array of the three-dimensional semiconductor memory device may include a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged to be separated from each other along a second direction D2, for example.

[0045] Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. In an embodiment, each memory cell MC may be disposed between a corresponding one of the word lines WL in the word lines WL and a corresponding one of the bit lines BL in the bit lines BL.

[0046] The bit lines BL may be conductive patterns (e.g., metal lines) disposed above a substrate or vertically separated from the substrate. The bit lines BL may extend in a first direction D1. In each sub-cell array SCA, the bit lines BL may be separated from each other in a vertical direction (e.g., a third direction D3) perpendicular to the top surface of the substrate.

[0047] The word lines WL may be conductive patterns (e.g., metal lines) extending in the vertical direction (i.e., the third direction D3). In each sub-cell array SCA, the word lines WL may be separated from each other in the first direction D1.

[0048] Each memory cell MC may include a memory cell transistor MCT and a data storage element DS. The gate of the memory cell transistor MCT may be connected to the word line WL, and the source of the memory cell transistor MCT may be connected to the bit line BL. The data storage element DS may be a capacitor, and the drain of the memory cell transistor MCT may be connected to the capacitor.

[0049] Figure 2 is a perspective view showing a three-dimensional semiconductor memory device according to an embodiment.

[0050] Referring to Figure 1 and Figure 2 and referring to Figure 1One of the described sub-unit arrays SCA can be disposed on the substrate 1 ( Figure 2 ). For example, the substrate 1 can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0051] Specifically, the semiconductor pattern SP can be disposed on the substrate 1 and separated from each other in a first direction D1 and a third direction D3 that cross each other. Each of the semiconductor patterns SP can be a strip pattern extending in a second direction D2 that crosses the first direction D1 and the third direction D3. The first direction D1 and the second direction D2 can be parallel to the top surface of the substrate 1. The third direction D3 can be perpendicular to the top surface of the substrate 1. Each of the semiconductor patterns SP can include a first end E1 and a second end E2 that are separated from each other. For example, as Figure 2 shown, the first end E1 and the second end E2 can be opposite surfaces of the semiconductor pattern SP that are separated from each other in the second direction D2. In addition, each of the semiconductor patterns SP can include a first side surface SW1 and a second side surface SW2, each of the first side surface SW1 and the second side surface SW2 connecting the first end E1 to the second end E2, and the first side surface SW1 and the second side surface SW2 being separated from each other in the first direction D1, for example. The semiconductor pattern SP can be formed of at least one of, for example, silicon and germanium, or include at least one of, for example, silicon and germanium.

[0052] Each of the semiconductor patterns SP can include a first source / drain region SD1 adjacent to the first end E1, a second source / drain region SD2 adjacent to the second end E2, and a channel region CH disposed between the first source / drain region SD1 and the second source / drain region SD2. Each of the first source / drain region SD1 and the second source / drain region SD2 can be an impurity region formed by doping the semiconductor pattern SP with an impurity. In an embodiment, the channel region CH can be doped with an impurity. For example, the first source / drain region SD1 and the second source / drain region SD2 can be doped to have a first conductivity type, and the channel region CH can be doped to have a second conductivity type different from the first conductivity type.

[0053] The bit lines BL can be stacked on the substrate 1 and separated from each other in the third direction D3. The bit lines BL can extend in the first direction D1. The first ends E1 of the semiconductor patterns SP at the same level can be connected to corresponding ones of the bit lines BL. For example, the first ends E1 of the semiconductor patterns SP can face and contact corresponding side surfaces of the bit lines BL.

[0054] The data storage element DS can be respectively connected to the second end portion E2 of the semiconductor pattern SP. The data storage element DS can be a memory element for storing data. Each of the data storage elements DS can be, for example, a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a memory element using a variable resistance material (e.g., a phase change material). In an embodiment, each of the data storage elements DS can be a capacitor.

[0055] The first word line WL1 can be disposed near the first side surface SW1 of the semiconductor pattern SP. The second word line WL2 can be disposed near the second side surface SW2 of the semiconductor pattern SP. The first word line WL1 and the second word line WL2 can extend from the top surface of the substrate 1 in the third direction D3. Each of the first word lines WL1 can be separated from the corresponding one of the second word lines WL2, and the channel region CH of each semiconductor pattern SP is disposed between each of the first word lines WL1 and the corresponding one of the second word lines WL2.

[0056] The gate insulating layer Gox can be disposed between each of the first word line WL1 and the second word line WL2 and the semiconductor pattern SP (e.g., Figure 2 and FIG. 3A to FIG. 3B the thick black line in). The gate insulating layer Gox can be a single-layer or multi-layer structure and can be formed of, for example, at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride, or include, for example, at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the high-k dielectric material can include, for example, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0057] The bit line BL and each of the first word line WL1 and the second word line WL2 can be formed of a conductive material or include a conductive material. For example, the conductive material can be a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0058] The bit line BL can be the bit line BL described with reference to Figure 1 The first word line WL1 can correspond to the word line WL described with reference to Figure 1 The second word line WL2 can be used as a back gate electrode for controlling the movement of charges in the channel region CH. An insulating layer can be disposed between the bit lines BL and between the semiconductor patterns SP. The word lines WL1 and WL2 can be electrically disconnected from the substrate 1.

[0059] Figure 3A is a plan view showing a three-dimensional semiconductor memory device according to an embodiment. Figure 3B is a cross-sectional view showing cross-sections along lines A-A', B-B', and C-C' of Figure 3A the same. Figure 3C is a perspective view showing a portion “P1” of Figure 3B the same.

[0060] Referring to FIG. 3A to FIG. 3C , the substrate 1 may be formed of or include a semiconductor material. For example, the substrate 1 may be a single-crystalline silicon wafer or a silicon-on-insulator (SOI) wafer.

[0061] Semiconductor patterns SP separated from each other may be stacked on the substrate 1. As described with reference to Figure 2 , each of the semiconductor patterns SP may include a first end portion E1, a second end portion E2, a first side surface SW1, and a second side surface SW2. A first source / drain region SD1, a second source / drain region SD2, and a channel region CH may be provided in each of the semiconductor patterns SP.

[0062] A first word line WL1 and a second word line WL2 may extend from the top surface of the substrate 1 in a third direction D3. The first word line WL1 may be adjacent to the first side surface SW1 of the semiconductor pattern SP, and the second word line WL2 may be adjacent to the second side surface SW2 of the semiconductor pattern SP. The first word line WL1 may be separated from the second word line WL2, and the channel region CH may be disposed between the first word line WL1 and the second word line WL2. A first recessed region RC1 may be formed in the substrate 1, and the first word line WL1 and the second word line WL2 may be partially inserted into the first recessed region RC1.

[0063] The gate insulating layer Gox can be disposed between each of the first word line WL1 and the second word line WL2 and the semiconductor pattern SP. The gate insulating layer Gox can extend and can be disposed between the semiconductor patterns SP. For example, the gate insulating layer Gox can extend between the semiconductor patterns SP adjacent to each other along the third direction D3. In addition, the gate insulating layer Gox can be set to fill the space between the semiconductor patterns SP (e.g., between the semiconductor patterns SP adjacent to each other along the third direction D3), thereby constituting the first interlayer insulating layer IL1. In other words, the first interlayer insulating layer IL1 can be a part of the gate insulating layer Gox. The gate insulating layer Gox can extend to cover a plurality of semiconductor patterns SP. The gate insulating layer Gox can be continuous between each of the first word line WL1 and the second word line WL2 and the semiconductor pattern SP. The side surfaces of the first word line WL1 and the second word line WL2 in contact with the gate insulating layer Gox can have an uneven structure. Since the first word line WL1 and the second word line WL2 are adjacent to the top surface and the bottom surface of the semiconductor pattern SP, the channel controllability through the first word line WL1 and the second word line WL2 can be improved. Therefore, the reliability of the three-dimensional semiconductor memory device can be improved.

[0064] The gate insulating layer Gox can extend and can be disposed between the bottom surface of the first recessed region RC1 and each of the first word line WL1 and the second word line WL2. At least one of a high-k dielectric pattern, a work function control pattern, a ferroelectric pattern, a diffusion barrier pattern, and a charge storage pattern can be disposed between each of the first word line WL1 and the second word line WL2 and the gate insulating layer Gox. The high-k dielectric pattern can be formed of at least one of metal oxides (e.g., hafnium oxide and aluminum oxide) having a dielectric constant higher than that of the silicon oxide layer, or can include at least one of metal oxides (e.g., hafnium oxide and aluminum oxide) having a dielectric constant higher than that of the silicon oxide layer. The diffusion barrier pattern can include a metal nitride layer, e.g., a tungsten nitride layer, a titanium nitride layer, and a tantalum nitride layer. The charge storage pattern can include, for example, a silicon nitride layer or a polysilicon layer.

[0065] The second interlayer insulating layer IL2 and the semiconductor layer 5 may be alternately stacked on the edge region of the substrate 1. The second interlayer insulating layer IL2 may be formed of a material different from or the same as the gate insulating layer Gox, or may include a material different from or the same as the gate insulating layer Gox. Each of the semiconductor layers 5 may be located at the same level as a corresponding one of the semiconductor patterns SP. Compared with the second interlayer insulating layer IL2, the side surfaces of the semiconductor layers 5 may protrude toward the word lines WL1 and WL2. For example, the semiconductor layers 5 may extend beyond the second interlayer insulating layer IL2 in the direction facing the corresponding word line among the word lines WL1 and WL2. The first interlayer insulating layer IL1 may extend into the region between the semiconductor layers 5 and may be in direct contact with the second interlayer insulating layer IL2, for example.

[0066] The first end portion E1 of the semiconductor pattern SP may be in contact with the bit line BL. Each of the second interlayer insulating layers IL2 may be disposed between the bit lines BL. The bit lines BL may extend in the first direction D1. The bit lines BL may be in contact with the insulating isolation pattern SL. The insulating isolation pattern SL may be in contact with the side surfaces of the bit lines BL and the side surfaces of the second interlayer insulating layers IL2. When observed in a plan view, as Figure 3A shown, the insulating isolation pattern SL may also be a linear pattern having a linear shape or a curved shape extending in the first direction D1, for example.

[0067] The second end E2 of the semiconductor pattern SP may be in contact with the data storage electrode SE, respectively. The data storage electrode SE may have a letter "C" shaped cross section. The data storage electrode SE may have a hollow cup shape or a cylindrical shape. The data storage electrode SE may be conformally covered with a dielectric layer DL. The dielectric layer DL may extend to contact the side surface of the first interlayer insulating layer IL1 disposed between the semiconductor patterns SP. The dielectric layer DL may be covered with a plate electrode PE. The data storage electrode SE, the dielectric layer DL, and the plate electrode PE may constitute a data storage element DS, for example, a capacitor. Each of the data storage electrode SE and the plate electrode PE may be formed of a conductive material or include a conductive material. The conductive material may be one of a doped semiconductor material (for example, doped silicon, doped silicon germanium, etc.), a conductive metal nitride (for example, titanium nitride, tantalum nitride, etc.), a metal material (for example, tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (for example, tungsten silicide, cobalt silicide, titanium silicide, etc.). The dielectric layer DL may be formed of or include at least one of silicon oxide, metal oxides (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide), and perovskite dielectric materials (e.g., SrTiO3 (STO), (Ba, Sr)TiO3 (BST), BaTiO3, PZT, and PLZT).

[0068] The first insulating gap filling pattern 7 may be disposed between adjacent data storage electrodes in the data storage electrode SE and between the data storage electrode SE and the semiconductor layer 5. The second insulating gap filling pattern 11 may be disposed between the first word line WL1 and the second word line WL2. The third insulating gap filling pattern 13 may be disposed between the first word line WL1 and the second word line WL2 and the bit line BL, between the second insulating gap filling pattern 11 and the bit line BL, and between the gate insulating layer Gox and the bit line BL. The fourth insulating gap filling pattern 15 may be disposed between the first word line WL1 and the second word line WL2 and the first insulating gap filling pattern 7. Each of the first to fourth insulating gap filling patterns 7, 11, 13, and 15 may be independently formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may have a single-layer structure or a multi-layer structure. The semiconductor layer 5 may be disposed to include an end portion forming a step structure. The bit line BL may be disposed to include an end portion forming a step structure.

[0069] Figure 4A , Figure 5A as well as 7A to 12Ais a plan view showing a process of manufacturing a three-dimensional semiconductor memory device having a planar structure shown in Figure 3A . The cross-sectional views of the three-dimensional semiconductor memory device taken along lines A-A', B-B' and C-C' shown in Figure 4B , Figure 5B and FIG. 7B to FIG. 12B are cross-sectional views respectively showing the cross-sections of the three-dimensional semiconductor memory device taken along lines A-A', B-B' and C-C' of Figure 4A , Figure 5A and 7A to 12A . Figure 6 is a cross-sectional view showing a stage (e.g., between the stage of Figure 3B and the stage of Figure 5B ) in the process of manufacturing the three-dimensional semiconductor memory device shown in Figure 7B .

[0070] Referring to Figure 4A and Figure 4B , a sacrificial layer 3 and a semiconductor layer 5 can be alternately stacked on a substrate 1 to form a preliminary stacked structure PT. The semiconductor layer 5 can be formed of a semiconductor material (e.g., silicon) or include a semiconductor material (e.g., silicon). The sacrificial layer 3 can be formed of a material having an etching selectivity with respect to the semiconductor layer 5 or include a material having an etching selectivity with respect to the semiconductor layer 5. For example, the sacrificial layer 3 can be formed of at least one of, for example, silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride, or include at least one of, for example, silicon germanium, silicon oxide, silicon nitride, and silicon oxynitride. The preliminary stacked structure PT can be etched to form a first hole H1 and a first groove G1, and the first hole H1 and the first groove G1 expose the substrate 1 and are separated from each other. The first holes H1 can be separated from each other in a first direction D1. The first grooves G1 can be separated from each other in the first direction D1. The first grooves G1 can be separated from the first holes H1 in a second direction D2. During the etching of the preliminary stacked structure PT, the upper portion of the substrate 1 can be etched to form a first recessed region RC1. A first insulating gap-fill pattern 7 can be formed in the first groove G1, and the forming step of the first insulating gap-fill pattern 7 can include: forming an insulating layer to fill the first groove G1 and anisotropically etching the insulating layer.

[0071] Referring to Figure 5A and Figure 5B , an isotropic etching process can be performed to partially remove the sacrificial layer 3 exposed through the first hole H1. As a result, a first region R1 can be formed to expose the top surface and the bottom surface of the semiconductor layer 5, and a sacrificial pattern 3a can be left on the edge region of the substrate 1. When the sacrificial layer 3 is partially removed, the first insulating gap-fill pattern 7 and the sacrificial pattern 3a can prevent the preliminary stacked structure PT from tilting or collapsing. The sacrificial pattern 3a can be a part of the sacrificial layer 3. The side surface of the sacrificial pattern 3a can also be exposed through the first region R1.

[0072] Referring to Figure 6 , a thermal oxidation process or a deposition process may be performed to form a gate insulating layer Gox on the exposed surface of the semiconductor layer 5. Here, the gate insulating layer Gox may be formed to have a thickness sufficient to fill the first region R1 between the semiconductor layers 5. In the case where the gate insulating layer Gox is formed by a thermal oxidation process, the etching damage in the semiconductor layer 5 can be repaired. This makes it possible to prevent leakage current from occurring during the operation of the three-dimensional semiconductor memory device and improve the reliability of the three-dimensional semiconductor memory device. The gate insulating layer Gox between the semiconductor layers 5 may be referred to as the first interlayer insulating layer IL1. The first interlayer insulating layer IL1 may be in contact with the sacrificial pattern 3a. The gate insulating layer Gox may also be formed on the surface of the substrate 1. The gate insulating layer Gox may also be formed on the bottom surface and the side surface of the first recessed region RC1. The gate insulating layer Gox in the first hole H1 may have an uneven profile near the semiconductor layer 5 and between the semiconductor layers 5. The word line layer 9 may be conformally formed on the gate insulating layer Gox. The word line layer 9 may be formed of at least one of conductive materials.

[0073] Referring to Fig. 7A and Figure 7B , an anisotropic etching process may be performed on the word line layer 9 and the gate insulating layer Gox to form a preliminary word line pattern 9a and the gate insulating layer Gox in the first hole H1. For example, an anisotropic etching process may be performed to remove the portions of the gate insulating layer Gox and the word line layer 9 located on the topmost semiconductor layer in the semiconductor layer 5 and on the bottom of the first recessed region RC1, for example, to expose the top surface of the topmost semiconductor layer 5 and a part of the substrate 1 in the first recessed region RC1. In this case, the preliminary word line pattern 9a and the gate insulating layer Gox may remain in the first hole H1. When observed in a plan view, the preliminary word line pattern 9a may have a closed-loop shape. Thereafter, a second insulating gap filling pattern 11 may be formed in the first hole H1 to be in contact with the preliminary word line pattern 9a.

[0074] Referring to Fig. 7A , Figure 7B , Fig. 8A and Figure 8B , the second hole H2 and the third hole H3 separated from each other may be formed by removing the portions of the preliminary stacked structure PT adjacent to the preliminary word line pattern 9a and by removing portions of the preliminary word line pattern 9a and the gate insulating layer Gox. The third hole H3 may be located, for example, along the second direction D2 between the first hole H1 and the first groove G1. The second hole H2 may be separated from the third hole H3, and the second insulating gap filling pattern 11 may be disposed between the second hole H2 and the third hole H3. For example, in Fig. 8AIn a top view, the second hole H2 can be partially superimposed on the first hole H1. For example, in Fig. 8A 's top view, the third hole H3 can be partially superimposed on the first hole H1 and the first groove G1. As a result of forming the second hole H2 and the third hole H3, the preliminary word line pattern 9a (e.g., the preliminary word line pattern 9a has an annular shape in Fig. 7A 's top view) can be divided into a first word line WL1 and a second word line WL2 that are separated from each other (e.g., Fig. 8A 's top view). The third insulating gap filling pattern 13 and the fourth insulating gap filling pattern 15 can be formed by filling the second hole H2 and the third hole H3 with an insulating layer. The second insulating gap filling pattern 11 can be partially etched by an etching process.

[0075] Referring to Fig. 8A 、 Figure 8B 、 Fig. 9A and Fig. 9B , the preliminary stacked structure PT adjacent to the third insulating gap filling pattern 13 can be etched to form a second groove G2. When observed in a plan view, the second groove G2 can have a line shape extending in the first direction D1. The second groove G2 can expose the top surface of the lowermost sacrificial pattern in the sacrificial pattern 3a.

[0076] Referring to Fig. 9A 、 Fig. 9B 、 Fig. 10A and Fig. 10B , the semiconductor layer 5 exposed through the second groove G2 can be partially removed to form a second recessed region RC2. The second recessed region RC2 can expose the side surface of the third insulating gap filling pattern 13. An ion implantation process can be performed to form a first source / drain region SD1 in the semiconductor layer 5 adjacent to the second recessed region RC2. A conductive layer can be deposited to fill the second recessed region RC2, and then the conductive layer can be anisotropically etched to form a bit line BL in the second recessed region RC2.

[0077] After that, the sacrificial pattern 3a exposed through the second groove G2 can be removed to evacuate the region between the bit lines BL. A second interlayer insulating layer IL2 can be deposited to fill the region between the bit lines BL, and then the second interlayer insulating layer IL2 can be anisotropically etched to form a second interlayer insulating layer IL2 between the bit lines BL. In an embodiment, during this process, all the sacrificial patterns 3a can be replaced with the second interlayer insulating layer IL2. In some embodiments, part of the sacrificial pattern 3a can be left. The left part of the sacrificial pattern 3a can be replaced with the second interlayer insulating layer IL2 in a subsequent process, which will be referred to Fig.11A and Fig. 11BDescription. An insulating isolation layer may be deposited to fill the second groove G2, and then the insulating isolation layer may be anisotropically etched to form an insulating isolation pattern SL in the second groove G2.

[0078] Referring to Fig.11A and Fig. 11B , the first insulating gap-fill pattern 7, the semiconductor layer 5 adjacent to the first insulating gap-fill pattern 7, and the second interlayer insulating layer IL2 disposed between the semiconductor layers 5 may be etched to form a third groove G3. The third groove G3 may have a line shape extending in the first direction D1. In Fig. 10A and 10B , in the case where the sacrificial pattern 3a remains after the process of

[0079] Referring to Fig.11A , 11B , 12A and 12B, the semiconductor layer 5 exposed through the third groove G3 may be partially removed by an isotropic etching process to form a third recessed region RC3 and a semiconductor pattern SP. The third recessed region RC3 may be set to expose the top surface and the bottom surface of the second interlayer insulating layer IL2 and the side surface of the first insulating gap-fill pattern 7. An ion implantation process may be performed to form a second source / drain region SD2 in the semiconductor pattern SP.

[0080] After Fig. 12A , Fig. 12B , Figure 3A and Figure 3B , an isotropic etching process may be performed to etch the side surface of the first insulating gap-fill pattern 7 exposed through the third recessed region RC3, and as a result of the isotropic etching process, the third recessed region RC3 may have an increased width. A conductive layer may be deposited to conformally fill the third recessed region RC3, and then the conductive layer may be anisotropically etched to form a data storage electrode SE. As Figure 3B shown in

[0081] In this embodiment, since the gate insulating layer Gox is used to form the first interlayer insulating layer IL1, an additional process of forming the first interlayer insulating layer IL1 may be omitted and the overall manufacturing process may be simplified.

[0082] FIG. 13A to FIG. 13E is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0083] Referring to Fig.13A , the gate insulating layer Gox can be disposed between the channel region CH and each of the first word line WL1 and the second word line WL2. For example, the gate insulating layer Gox can extend only along the channel region CH without overlapping with the first source / drain region SD1 and the second source / drain region SD2. The gate insulating layer Gox can be disposed between the channel regions CH of the semiconductor pattern SP, for example, along the third direction D3 between adjacent channel regions CH. The gate insulating layers Gox respectively surrounding the semiconductor pattern SP may not be connected to each other and may be separated from each other by the air gap region AG, for example, along the third direction D3. The gate insulating layer Gox can extend into the region between the first source / drain regions SD1 of the semiconductor pattern SP, thereby constituting the first interlayer insulating layer IL1. The air gap region AG can be formed in the first interlayer insulating layer IL1. Due to the presence of the air gap region AG, it may be possible to reduce the interference between adjacent channel regions CH in the channel region CH. Fig.13A The gate insulating layer Gox in the embodiment of Figure 3C can be thinner than the gate insulating layer Gox in the previous embodiment of FIG. 3A to FIG. 3C . Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment can have substantially the same features as those described with reference to Figure 6 . The three-dimensional semiconductor memory device of Fig.13A can be manufactured by forming the gate insulating layer Gox to a reduced thickness in the step of

[0084] and performing subsequent process steps. Fig. 13B In an alternative example shown in Fig. 13B , the first word line WL1 and the second word line WL2 can extend into the region between the semiconductor patterns SP to contact each other. In other words, the first word line WL1 and the second word line WL2 can be connected to form a single object serving as the word line WL. Fig.13A The gate insulating layer Gox in the embodiment of FIG. 3A to FIG. 3C can be thinner than the gate insulating layer Gox in the previous embodiment of

[0085] . The gate insulating layer Gox can include a portion disposed between the first source / drain regions SD1 of the semiconductor pattern SP and constituting the first interlayer insulating layer IL1. In addition, the second interlayer insulating layer IL2 can also be disposed between the first source / drain regions SD1 to contact the first interlayer insulating layer IL1. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment can have substantially the same features as those described with reference to Fig. 13C . Fig. 13BA structure that is basically the same. In this structure, the air gap region AG can be referred to as a void. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment can have features that are basically the same as those described with reference to Fig. 13B The features described are basically the same. In Fig. 13B Or Fig. 13C In, the channel region CH of the semiconductor pattern SP is surrounded by the word line WL, and the channel controllability can be increased.

[0086] In Fig.13D In the alternative example shown, Fig.13A The air gap region AG of can be filled with the second interlayer insulating layer IL2. The second interlayer insulating layer IL2 can be formed of the same or different material as the gate insulating layer Gox, or include the same or different material as the gate insulating layer Gox.

[0087] In Fig.13E In the alternative example shown, only the second interlayer insulating layer IL2 can be disposed between the first source / drain regions SD1 of the semiconductor pattern SP, and except for this, Fig.13E The structure of can be basically the same as the structure of Fig.13D The structure of.

[0088] The three-dimensional semiconductor memory device of can be manufactured by using or modifying the manufacturing method described with reference to FIG. 3A to FIG. 12B The three-dimensional semiconductor memory device of can be manufactured by using or modifying the manufacturing method described with reference to FIG. 13B to FIG. 13E The three-dimensional semiconductor memory device of.

[0089] Fig.14A Is a plan view showing a three-dimensional semiconductor memory device according to an embodiment. Fig. 14B Is a cross-sectional view showing a cross-section of the three-dimensional semiconductor memory device taken along lines A-A', B-B' and C-C' of Fig.14A The three-dimensional semiconductor memory device taken along lines A-A', B-B' and C-C' of. Fig. 14C Is a perspective view showing a part (e.g., Fig. 14B "P2") of the three-dimensional semiconductor memory device according to an embodiment.

[0090] With reference to FIG. 14A to FIG. 14C The semiconductor pattern SP and the interlayer insulating layer IL can be alternately stacked on the central region of the substrate 1. The semiconductor layer 5 and the interlayer insulating layer IL can be alternately stacked on the edge region of the substrate 1. Each pair of the semiconductor layer 5 and the semiconductor pattern SP at the same height can have the same thickness and can be formed of the same material.

[0091] As described with reference to Figure 2 Each of the semiconductor patterns SP can include a first end E1, a second end E2, a first side surface SW1 and a second side surface SW2. The first source / drain region SD1, the second source / drain region SD2 and the channel region CH can be provided in each of the semiconductor patterns SP.

[0092] The first word line WL1 and the second word line WL2 can extend from the top surface of the substrate 1 in the third direction D3. The first word line WL1 can be adjacent to the first side surface SW1 of the semiconductor pattern SP, and the second word line WL2 can be adjacent to the second side surface SW2 of the semiconductor pattern SP. The first word line WL1 can be separated from the second word line WL2, and the channel region CH is disposed between the first word line WL1 and the second word line WL2.

[0093] The gate insulating layers Gox can be respectively disposed between the semiconductor pattern SP and each of the first word line WL1 and the second word line WL2. The gate insulating layers Gox can be separated from each other. The diffusion barrier layer BM can be disposed between the gate insulating layers Gox and each of the first word line WL1 and the second word line WL2 and between the first interlayer insulating layer IL1 and each of the first word line WL1 and the second word line WL2. The diffusion barrier layer BM can include a metal nitride layer, for example, a tungsten nitride layer, a titanium nitride layer, and a tantalum nitride layer. At least one of a charge storage layer, a ferroelectric layer, a variable resistance layer, and a work function control layer can be disposed between the gate insulating layers Gox and each of the first word line WL1 and the second word line WL2. In this embodiment, the gate insulating layers Gox may not extend into the region between the semiconductor patterns SP. The interlayer insulating layer IL may not be part of the gate insulating layers Gox. The interlayer insulating layer IL and the gate insulating layers Gox can be independently formed by different processes and can include the same material or different materials.

[0094] The side surfaces of the semiconductor pattern SP can be aligned with the side surfaces of the interlayer insulating layer IL. Compared with the side surfaces of the interlayer insulating layer IL, the side surfaces of the gate insulating layers Gox can protrude toward the first word line WL1 and the second word line WL2. The side surfaces of the first word line WL1 and the second word line WL2 that are in contact with the diffusion barrier layer BM can have an uneven shape.

[0095] The first interlayer insulating gap filling pattern 12 can be disposed between the first word line WL1 and the second word line WL2 adjacent to each other. The second interlayer insulating gap filling pattern 14 can be disposed between the bit line BL and the first word line WL1 and the second word line WL2. The third interlayer insulating gap filling pattern 16 can be disposed between the data storage element DS and the first word line WL1 and the second word line WL2. Each of the first interlayer insulating gap filling pattern to the third interlayer insulating gap filling patterns 12, 14, and 16 can be formed of at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride, or include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment can have substantially the same features as those described with reference to Figure 3A and Figure 3B description.

[0096] FIG. 15A to FIG. 19A is a plan view showing a process of manufacturing a three-dimensional semiconductor memory device having a planar structure as shown in Fig.14A . FIG. 15B to FIG. 19B are cross-sectional views respectively showing cross-sections of the three-dimensional semiconductor memory device taken along lines A-A', B-B', and C-C' of FIG. 15A to FIG. 19A .

[0097] Referring to Fig.15A and Fig. 15B , an interlayer insulating layer IL and a semiconductor layer 5 can be alternately stacked on a substrate 1 to form a preliminary stacked structure PT. The semiconductor layer 5 can be formed of a semiconductor material (e.g., silicon, germanium, silicon germanium, and indium gallium zinc oxide (IGZO)). The interlayer insulating layer IL can be formed of an insulating material having an etching selectivity with respect to the semiconductor layer 5. For example, the interlayer insulating layer IL can be formed of at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0098] The preliminary stacked structure PT can be etched to form first grooves G1 exposing the substrate 1. The first grooves G1 can be spaced apart from each other in a first direction D1. During the etching of the preliminary stacked structure PT, an upper portion of the substrate 1 can be etched to form a first recessed region RC1.

[0099] Referring to Fig.16A and Fig. 16B , a thermal oxidation process can be performed to form a gate insulating layer Gox on the exposed surfaces of the semiconductor layer 5, respectively. The gate insulating layer Gox may not be formed on the exposed surface of the interlayer insulating layer IL. Since the gate insulating layer Gox is formed by the thermal oxidation process, etching damage of the semiconductor layer 5 can be repaired, and this enables improvement of the reliability of the three-dimensional semiconductor memory device. A diffusion barrier layer BM and a word line layer can be sequentially formed on the substrate 1, and then, an anisotropic etching process can be performed to form a preliminary word line pattern 9a and expose the bottom surface of the first recessed region RC1. An insulating layer can be deposited on the substrate 1 and the insulating layer can be anisotropically etched to form a first interlayer insulating gap-fill pattern 12 filling the first grooves G1.

[0100] Referring to Fig.17A and Fig. 17B, the first word line WL1 and the second word line WL2 separated from each other can be formed by at least etching a preliminary word line pattern 9a in the first groove G1. Here, the first interlayer insulating gap filling pattern 12, the diffusion barrier layer BM, and the gate insulating layer Gox can be etched in the first groove G1. An insulating layer can be deposited, and then an etch-back process can be performed on the insulating layer to form the second interlayer insulating gap filling pattern 14 and the third interlayer insulating gap filling pattern 16. The second interlayer insulating gap filling pattern 14 and the third interlayer insulating gap filling pattern 16 fill the first groove G1 and are separated from each other.

[0101] Referring to Fig.18A and Fig.18B , the preliminary stacked structure PT adjacent to the second interlayer insulating gap filling pattern 14 can be etched to form a second groove G2. The semiconductor layer 5 exposed through the second groove G2 can be partially removed, and an ion implantation process can be performed to form a first source / drain region SD1 in the semiconductor layer 5. A conductive layer can be deposited, and then the conductive layer can be anisotropically etched to form a bit line BL. An insulating isolation layer can be deposited to fill the second groove G2, and then the insulating isolation layer can be anisotropically etched to form an insulating isolation pattern SL in the second groove G2. The third interlayer insulating gap filling pattern 16, the semiconductor layer 5 adjacent to the third interlayer insulating gap filling pattern 16, and the interlayer insulating layer IL disposed between the semiconductor layers 5 can be etched to form a third groove G3. The third groove G3 can have a line shape extending in a first direction D1.

[0102] Referring to Fig.19A and Fig.19B , the semiconductor layer 5 exposed through the third groove G3 can be partially removed by an isotropic etching process to form a third recessed region RC3 and a semiconductor pattern SP. The third recessed region RC3 can expose the top surface and the bottom surface of the interlayer insulating layer IL and the side surface of the third interlayer insulating gap filling pattern 16. An ion implantation process can be performed to form a second source / drain region SD2 in the semiconductor pattern SP.

[0103] Thereafter, the isotropic etching process described with reference to Fig.19A , Fig.19B , Fig.14A and Fig. 14B can be performed to laterally etch the side surface of the third interlayer insulating gap filling pattern 16 exposed through the third recessed region RC3. As a result of the isotropic etching process, the third recessed region RC3 can have an increased width. A conductive layer can be conformally deposited, and then the conductive layer can be anisotropically etched to form a data storage electrode SE. Thereafter, a dielectric layer DL and a plate electrode PE constituting the data storage element DS (e.g., a capacitor) can be formed.

[0104] FIG. 20A to FIG. 20C is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0105] Referring to Fig. 20A , the semiconductor pattern SP according to the present embodiment may have a first width WT1 in a first direction D1, and the interlayer insulating layer IL may have a second width WT2 in the first direction D1. The first width WT1 may be smaller than the second width WT2. In other words, compared with the side surfaces of the semiconductor pattern SP, the side surfaces of the interlayer insulating layer IL may protrude toward the first word line WL1 and the second word line WL2. The gate insulating layer Gox may be continuously disposed between each of the first word line WL1 and the second word line WL2 and the semiconductor pattern SP and between each of the first word line WL1 and the second word line WL2 and the interlayer insulating layer IL, and may have a substantially constant thickness. The diffusion barrier layer BM may be disposed between the gate insulating layer Gox and each of the first word line WL1 and the second word line WL2. The gate insulating layer Gox and the diffusion barrier layer BM may have a concavo-convex structure. Each of the first word line WL1 and the second word line WL2 may include a protruding portion extending toward the semiconductor pattern SP. The diffusion barrier layer BM may be omitted. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment may have features substantially the same as those described with reference to Fig.14A and Fig. 14B .

[0106] In Fig. 20B the alternative example shown, the gate insulating layers Gox according to the present embodiment may be separated from each other. The gate insulating layer Gox may be disposed only between each of the first word line WL1 and the second word line WL2 and the semiconductor pattern SP. The side surfaces of the gate insulating layer Gox may be aligned with the side surfaces of the interlayer insulating layer IL. The diffusion barrier layer BM may be in contact with both the interlayer insulating layer IL and the gate insulating layer Gox. The first word line WL1 and the second word line WL2 may not include protruding portions. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment may have features substantially the same as those described with reference to Fig. 20A .

[0107] In Fig. 20CIn the optional example shown, the semiconductor pattern SP may have a first width WT1 in the first direction D1, and the interlayer insulating layer IL may have a second width WT2 in the first direction D1. The first width WT1 may be greater than the second width WT2. In other words, compared with the side surfaces of the interlayer insulating layer IL, the side surfaces of the semiconductor pattern SP may protrude toward the first word line WL1 and the second word line WL2. The gate insulating layer Gox may be continuously disposed between each of the first word line WL1 and the second word line WL2 and the semiconductor pattern SP and between each of the first word line WL1 and the second word line WL2 and the interlayer insulating layer IL, and may have a substantially constant thickness. The portions of the first word line WL1 and the second word line WL2 between the semiconductor patterns SP may protrude toward the interlayer insulating layer IL. The side surfaces of the first word line WL1 and the second word line WL2 adjacent to the gate insulating layer Gox may have an uneven structure. Since the first word line WL1 and the second word line WL2 are adjacent to the side surfaces of the semiconductor pattern SP and the top and bottom surfaces of the semiconductor pattern SP, the channel controllability through the first word line WL1 and the second word line WL2 may be improved. This enables improvement of the reliability of the three-dimensional semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment may have features substantially the same as those described with reference to Fig. 20A The features are substantially the same.

[0108] Fig.21 is a cross-sectional view showing the process of manufacturing Fig. 20A or the three-dimensional semiconductor memory device of 20B.

[0109] Referring to Fig.21 , an isotropic etching process may be performed on a structure having a cross-section A-A' identical to the cross-section A-A' shown in Fig. 15B to laterally etch the semiconductor layer 5 and partially expose the top and bottom surfaces of the interlayer insulating layer IL. As a result, the first groove G1 may have an increased width, and the first recessed region RC1 may have an increased depth. Thereafter, a deposition process (e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD)) may be performed to form the gate insulating layer Gox to a uniform thickness, and then, the subsequent process steps described with reference to FIG. 16A to FIG. 19B may be performed to obtain the structure shown in Fig. 20A . Optionally, a thermal oxidation process may be performed to form the gate insulating layer Gox only on the exposed surface of the semiconductor layer 5, and then the subsequent process steps described with reference to FIG. 16A to FIG. 19B may be performed to obtain the structure shown in Fig. 20B .

[0110] Fig. 20C The semiconductor device of may be manufactured by the following manufacturing process. An isotropic etching process may be performed on a structure having a cross-section A-A' identical to the cross-section A-A' shown in Fig. 15BThe structure of cross-section A-A' that is the same as cross-section A-A' shown in the figure performs an isotropic etching process to laterally etch the interlayer insulating layer IL and partially expose the top and bottom surfaces of the semiconductor layer 5. After that, a deposition process can be performed to form the gate insulating layer Gox with a uniform thickness, and then the subsequent process steps described with reference to FIG. 16A to FIG. 19B can be performed to obtain Fig. 20C the structure shown in the figure.

[0111] Fig. 22 is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0112] With reference to Fig. 22 , each of the semiconductor patterns SP according to the present embodiment may include a top surface US and a bottom surface BS. The top surface US and the bottom surface BS may have a non-flat (e.g., circular) shape. The top surface US and the bottom surface BS may protrude in the upward and downward directions, respectively. The first interlayer insulating layer IL1 may be disposed between the semiconductor patterns SP, respectively. The side surfaces of the semiconductor patterns SP may be aligned with the side surfaces of the first interlayer insulating layer IL1. The side surfaces of the semiconductor patterns SP and the side surfaces of the first interlayer insulating layer IL1 may be covered with the gate insulating layer Gox. The side surfaces of the gate insulating layer Gox may be covered with the diffusion barrier layer BM. The diffusion barrier layer BM may be in contact with the first word line WL1 and the second word line WL2. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment may have substantially the same features as those described with reference to Fig. 20A .

[0113] Fig.23A and Fig. 23B are cross-sectional views showing the process of manufacturing Fig. 22 the three-dimensional semiconductor memory device.

[0114] As Figure 5B shown in the figure, the sacrificial layer 3 can be partially removed through the first hole H1 to form the first region R1 and leave the sacrificial pattern 3a. Next, as Fig.23A shown in the figure, an isotropic etching process can be performed on the resulting structure having a cross-section substantially the same as the cross-section of Figure 5B , so that the corners of the semiconductor layer 5 can be rounded.

[0115] Next, with reference to Fig. 23B , an insulating layer can be deposited on the substrate 1 and the insulating layer can be anisotropically etched to form the first interlayer insulating layer IL1 in the first region R1 or between the semiconductor layers 5. After that, the gate insulating layer Gox, the diffusion barrier layer BM, and the word line layer can be conformally deposited on the substrate 1, and then the gate insulating layer Gox, the diffusion barrier layer BM, and the word line layer can be anisotropically etched. Next, the process steps described with reference to 7A to 12B The described process steps for manufacturing Fig. 22 a three-dimensional semiconductor memory device.

[0116] Fig.24A and Fig. 24B is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0117] Referring to Fig.24A and Fig. 24B , a first interlayer insulating layer IL1 can be disposed between the channel regions CH of the semiconductor pattern SP, and a second interlayer insulating layer IL2 can be disposed between the first source / drain regions SD1 of the semiconductor pattern SP. As Fig.24A shown in Fig. 24B , the interface at a specific height between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 can be adjacent to the top edge portions of the word lines WL1 and WL2. In the alternative example shown in Fig. 22 , the first interlayer insulating layer IL1 can protrude beyond the region between the word lines WL1 and WL2. The top and bottom surfaces of the semiconductor pattern SP can be flat. The first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 can include the same material or different materials. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment can have substantially the same features as those described with reference to Fig.24A and Fig. 24B . In the three-dimensional semiconductor memory device of

[0118] Fig.25A and Fig.25B , the materials and positions of the first interlayer insulating layer IL1 and the materials and positions of the second interlayer insulating layer IL2 can be adjusted to optimize the performance of the three-dimensional semiconductor memory device. For example, the first interlayer insulating layer IL1 can be formed of an insulating material having a dielectric constant lower than that of the second interlayer insulating layer IL2, and in this case, it can be possible to reduce the interference problem between the semiconductor patterns SP. In addition, the second interlayer insulating layer IL2 can be formed of an insulating material having a mechanical strength higher than that of the first interlayer insulating layer IL1, and in this case, it can be possible to prevent crack problems from occurring in the three-dimensional semiconductor memory device.

[0118] Fig.25A and Fig.25B are cross-sectional views showing the process of manufacturing Fig.24A or Fig. 24B a three-dimensional semiconductor memory device.

[0119] As Figure 5B shown in Fig.25A shown in Figure 5BAn insulating layer is deposited on the structure and the insulating layer can be anisotropically etched to form a first interlayer insulating layer IL1 in the first region R1 or between the semiconductor layers 5. Thereafter, as Fig.25B shown in Fig.25A , a gate insulating layer Gox and a diffusion barrier layer BM can be sequentially deposited by a deposition process to conformally cover Figure 5B the structure. Then, a word line layer can be deposited on the gate insulating layer Gox. Thereafter, an etching process step can be performed on the word line layer to form a first word line WL1 and a second word line WL2. According to Fig.24A the removal amount of the sacrificial layer 3 in the removal step, the semiconductor device can have Fig. 24B or

[0120] Fig.26A is a cross-sectional view showing the cross-section of a three-dimensional semiconductor memory device taken along the lines A-A', B-B' and C-C' of Fig.14A . Fig.26B is a perspective view showing Fig.26A the partial "P3" of

[0121] Referring to Fig.26A and Figure 26B , an air gap region AG can be provided between the semiconductor patterns SP and between the semiconductor layers 5. In this structure, the air gap region AG can be referred to as an "empty space". The air gap region AG can expose the top and bottom surfaces of the semiconductor pattern SP and the top and bottom surfaces of the semiconductor layer 5. The air gap region AG can extend into the region between the bit lines BL to expose the top and bottom surfaces of the bit lines BL. As shown in the cross-section A-A' of Figure 26A , a second interlayer insulating layer IL2 can be disposed between the edge portions of the semiconductor layer 5. As shown in the cross-section C-C' of Figure 26A , a second interlayer insulating layer IL2 can be disposed between the edge portions of the semiconductor pattern SP. Referring to Figure 26B , the side surfaces of the second interlayer insulating gap filling pattern 14 can be exposed through the air gap region AG. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment can have features substantially the same as those described with reference to Figure 14A and Figure 14B . Due to the air gap region AG, it is possible to reduce the parasitic capacitance between the semiconductor patterns SP and between the first word line WL1 and the second word line WL2 and reduce the interference between electrical signals.

[0122] Figure 27 is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device having a Figure 26A cross-sectional structure.

[0123] Referring to Figure 27 , it is possible to start fromFigure 18B The structure completely removes the interlayer insulating layer IL exposed through the third groove G3 to form an air gap region AG. Here, the gate insulating layer Gox, the first word line WL1 and the second word line WL2, and the first interlayer insulating gap filling pattern to the third interlayer insulating gap filling patterns 12, 14, and 16 can prevent the preliminary stacked structure PT from tilting or collapsing. Return to reference Figure 26A , the second interlayer insulating layer IL2 can be formed to close the entrance of the air gap region AG, and in an embodiment, the second interlayer insulating layer IL2 can be formed by a deposition method having poor step coverage characteristics or can be formed of an insulating material. Thereafter, subsequent processes can be performed.

[0124] Figures 28 to 37 is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0125] Reference Figure 28 , the interlayer insulating layer IL can include a first insulating layer L1 and a second insulating layer L2. The first insulating layer L1 and the second insulating layer L2 can be formed of different materials. The first insulating layer L1 can cover the side surfaces of the gate insulating layer Gox, the top and bottom surfaces of the semiconductor pattern SP, and the side surfaces of the second interlayer insulating gap filling pattern 14. When observed in a cross-section parallel to the first direction D1, the first insulating layer L1 can be in a hollow closed-loop shape. The second insulating layer L2 can fill the space between the semiconductor patterns SP. The three-dimensional semiconductor memory device can be formed by forming the air gap region AG to have the Figure 27 structure shown, thinly forming the first insulating layer L1 to conformally cover the air gap region AG, filling the air gap region AG with the second insulating layer L2, and then performing subsequent processes. Figure 28 three-dimensional semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment can have substantially the same features as those described with reference to Figure 26B the description.

[0126] In Figure 29In the alternative example shown, the interlayer insulating layer IL may include a first insulating layer L1, a second insulating layer L2, and a third insulating layer L3. The second insulating layer L2 may be formed of a material different from that of the first insulating layer L1 and the third insulating layer L3, or may include a material different from that of the first insulating layer L1 and the third insulating layer L3. The first insulating layer L1 may cover the side surfaces of the gate insulating layer Gox, the top and bottom surfaces of the semiconductor pattern SP, and the side surfaces of the second interlayer insulating gap-fill pattern 14. When observed in a cross-section parallel to the first direction D1, the first insulating layer L1 may be in a hollow closed-loop shape. The third insulating layer L3 may be provided to fill the space between the semiconductor patterns SP. The second insulating layer L2 may be disposed between the first insulating layer L1 and the third insulating layer L3. Except for additionally forming the third insulating layer L3, the process of manufacturing Figure 29 the three-dimensional semiconductor memory device may be similar to the process for Figure 28 the semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment may have substantially the same features as those described with reference to Figure 28 the features.

[0127] In Figure 30 the alternative example shown, the interlayer insulating layer IL may include a first insulating layer L1 and an air gap region AG. Figure 30 the three-dimensional semiconductor memory device may be manufactured by omitting the process of forming the second insulating layer L2 from the process for Figure 28 the three-dimensional semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment may have substantially the same features as those described with reference to Figure 28 the features.

[0128] In Figure 31 the alternative example shown, the interlayer insulating layer IL may include a first insulating layer L1 and a second insulating layer L2. The first insulating layer L1 may cover the side surfaces of the gate insulating layer Gox and the side surfaces of the second interlayer insulating gap-fill pattern 14, but may not cover the top surface of the semiconductor pattern SP. The second insulating layer L2 may fill the space between the semiconductor patterns SP. By partially recessing the side surface of the first interlayer insulating layer IL1 in the structure of Figure 25A , depositing the first insulating layer L1, anisotropically etching the first insulating layer L1 to leave the first insulating layer L1 on the first interlayer insulating layer IL1, and then performing subsequent processes to manufacture Figure 31 the three-dimensional semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to this embodiment may have substantially the same features as those described with reference to Figure 28 the features.

[0129] In Figure 32In the alternative example shown, the interlayer insulating layer IL may include a first insulating layer L1 and a second insulating layer L2. The first insulating layer L1 may be formed on the top and bottom surfaces of the semiconductor pattern SP. The second insulating layer L2 may fill the space between the semiconductor patterns SP. It may be manufactured by oxidizing the top and bottom surfaces of the semiconductor layer 5 in the structure of Figure 27 to form the first insulating layer L1, filling the space between the semiconductor patterns SP with the second insulating layer L2, and then performing subsequent processes to manufacture Figure 32 the three-dimensional semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment may have substantially the same features as those described with reference to Figure 28

[0130] In Figure 33 the alternative example shown, the interlayer insulating layer IL may include a first insulating layer L1 and an air gap region AG. It may be manufactured by omitting the process of forming the second insulating layer L2 from the process of manufacturing Figure 31 the three-dimensional semiconductor memory device to manufacture Figure 33 the three-dimensional semiconductor memory device. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment may have substantially the same features as those described with reference to Figure 31

[0131] In Figures 34 to 37 the alternative example shown, the air gap region AG may be provided in the interlayer insulating layer IL. As shown in Figure 34 , the air gap region AG may have a circular cross-section. In an embodiment, as shown in Figure 35 , the air gap region AG may have an elliptical cross-section extending in a first direction D1. In an embodiment, as shown in Figure 36 , the air gap region AG may have an elliptical cross-section extending in a third direction D3. In an embodiment, as shown in Figure 37 , the air gap region AG may extend in the first direction D1 and may expose the side surface of the gate insulating layer Gox.

[0132] In the three-dimensional semiconductor memory device described with reference to Figures 3A to 37 , the structure of the interlayer insulating layer IL may be variously changed to implement various three-dimensional semiconductor memory devices having desired characteristics.

[0133] Figures 38 to 41 is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0134] Referring to Figure 38 ​​, the unit stack structure UST may include an interlayer insulating layer IL and a semiconductor pattern SP that are sequentially and alternately stacked. A first word line WL1 and a second word line WL2 may be respectively disposed adjacent to two side surfaces of the unit stack structure UST and may extend in a third direction. An upper width WT3 of the first word line WL1 and the second word line WL2 measured in a second direction D2 may be larger than a lower width WT4 of the first word line WL1 and the second word line WL2 measured in the second direction D2. An upper width WT5 of the unit stack structure UST measured in a first direction D1 may be substantially equal to or similar to a lower width WT6 of the unit stack structure UST measured in the first direction D1. The widths of the first word line WL1 and the second word line WL2 may increase as the distance from the top surface of the substrate 1 increases.

[0135] In Figure 39 In the alternative example shown, an upper width WT3 of the first word line WL1 and the second word line WL2 measured in a second direction D2 may be smaller than a lower width WT4 of the first word line WL1 and the second word line WL2 measured in the second direction D2. An upper width WT5 of the unit stack structure UST measured in a first direction D1 may be substantially equal to or similar to a lower width WT6 of the unit stack structure UST measured in the first direction D1. The widths of the first word line WL1 and the second word line WL2 may decrease as the distance from the top surface of the substrate 1 increases.

[0136] In Figure 40 In the alternative example shown, an upper width WT3 of the first word line WL1 and the second word line WL2 measured in a second direction D2 may be larger than a lower width WT4 of the first word line WL1 and the second word line WL2 measured in the second direction D2. An upper width WT5 of the unit stack structure UST measured in a first direction D1 may be smaller than a lower width WT6 of the unit stack structure UST measured in the first direction D1. The widths of the first word line WL1 and the second word line WL2 may increase as the distance from the top surface of the substrate 1 increases. A width of the lowermost semiconductor pattern in the semiconductor pattern SP measured in the first direction D1 may be different from a width of the uppermost semiconductor pattern in the semiconductor pattern SP measured in the first direction D1.

[0137] In Figure 41In the alternative example shown, the upper width WT3 of the first word line WL1 and the second word line WL2 measured in the second direction D2 may be smaller than the lower width WT4 of the first word line WL1 and the second word line WL2 measured in the second direction D2. The upper width WT5 of the unit stack structure UST measured in the first direction D1 may be smaller than the lower width WT6 of the unit stack structure UST measured in the first direction D1. The widths of the first word line WL1 and the second word line WL2 may decrease as the distance from the top surface of the substrate 1 increases.

[0138] Figures 38 to 41 The relationship between the pattern widths in the three-dimensional semiconductor memory device of Figure 4B and Figure 8B can be determined by the process conditions of the anisotropic etching process in

[0139] Figure 42 and Figure 43 is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0140] Referring to Figure 42 , the bit line BL may have a first thickness TH1. The first end E1 of the semiconductor pattern SP in contact with the bit line BL may have the first thickness TH1. The second end E2 of the semiconductor pattern SP opposite to the first end E1 may have a second thickness TH2. The first thickness TH1 may be larger than the second thickness TH2. The thickness of the semiconductor pattern SP may decrease as the distance from the first end E1 increases in the direction toward the first word line WL1 and the second word line WL2. The interlayer insulating layer IL may have a third thickness TH3 at a position adjacent to the bit line BL. The interlayer insulating layer IL may have a fourth thickness TH4 at a position adjacent to the second end E2. The third thickness TH3 may be smaller than the fourth thickness TH4. The three-dimensional semiconductor memory device of Figure 27 can be manufactured by etching a part of the semiconductor layer 5 in the step of Figure 42 and performing subsequent processes.

[0141] In Figure 43 the alternative example shown, the interlayer insulating layer IL may have a third thickness TH3 at a position adjacent to the bit line BL. The interlayer insulating layer IL may have a fourth thickness TH4 at a position adjacent to the second end E2. The third thickness TH3 may be larger than the fourth thickness TH4. The bit line BL may have a fifth thickness TH5 at a position separated from the first end E1 of the semiconductor pattern SP. The bit line BL may have a sixth thickness TH6 at a position in contact with the first end E1 of the semiconductor pattern SP. The fifth thickness TH5 may be smaller than the sixth thickness TH6. The three-dimensional semiconductor memory device of Figure 10BIn the step of thickly forming the first interlayer insulating layer IL1 or the second interlayer insulating layer IL2 and performing subsequent processes to fabricate Figure 43 a three-dimensional semiconductor memory device.

[0142] Figure 44 and Figure 45 is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0143] Referring to Figure 44 , a first end portion E1 of the semiconductor pattern SP may be in contact with the bit line BL, and a second end portion E2 of the semiconductor pattern SP may be in contact with the data storage electrode SE. The data storage electrode SE may have a hollow cylindrical shape. An internal space of the data storage electrode SE may be conformally covered with a dielectric layer DL and may be filled with a plate electrode PE. The bit line BL may have a fifth thickness TH5 at a position separated from the first end portion E1. The data storage electrode SE may have a seventh thickness TH7 at a position in contact with the second end portion E2. The seventh thickness TH7 may be larger than the fifth thickness TH5. It may be fabricated by removing a part of the interlayer insulating layer IL by an isotropic etching process in the step of Figure 19B and performing subsequent processes to fabricate Figure 44 a three-dimensional semiconductor memory device.

[0144] In Figure 45 the optional example shown, when measured in the first direction D1, the bit line BL may have a seventh width WT7 at a position separated from the first end portion E1. When measured in the first direction D1, the data storage electrode SE may have an eighth width WT8. The eighth width WT8 may be larger than the seventh width WT7.

[0145] Figure 46 is a perspective view showing a part of a three-dimensional semiconductor memory device according to an embodiment.

[0146] Referring to Figure 46, the shield line SPT can be disposed between a first word line WL1 and a second word line WL2 adjacent to each other. The shield line SPT can be formed of at least one of metallic materials (such as tungsten, copper, and aluminum), or include at least one of metallic materials (such as tungsten, copper, and aluminum). The shield line SPT can include a polysilicon layer doped with impurities. The shield line SPT can be formed of a conductive material, or include a conductive material. The shield line SPT can be electrically disconnected (or insulated) from the first word line WL1 and the second word line WL2 through a first interlayer insulating gap filling pattern 12. The shield line SPT can be applied with a ground voltage or a voltage of 0V. The shield line SPT can suppress or reduce the electrical interference problem between the first word line WL1 and the second word line WL2 adjacent to each other. The side surface of the shield line SPT can be aligned with the side surface of the first word line WL1, the side surface of the second word line WL2, and the side surface of the first interlayer insulating gap filling pattern 12. The shield line SPT, the first word line WL1, the second word line WL2, and the first interlayer insulating gap filling pattern 12 can be parallel to a second direction D2 and can have the same width W9.

[0147] Figure 47A is a plan view showing a process of manufacturing Figure 46 a three-dimensional semiconductor memory device. Figure 47B is a cross-sectional view showing a cross-section of the three-dimensional semiconductor memory device taken along Figure 47A lines A-A', B-B', and C-C' of

[0148] Referring to Figure 47A and Figure 47B , a gate insulating layer Gox, a diffusion barrier layer BM, and a word line layer can be formed to conformally cover a first groove G1 formed to have the structure shown in Figure 15A and Figure 15B , and an anisotropic etching process can be performed to form a preliminary word line pattern 9a and expose a central region of the bottom surface of the first recessed region RC1. A first interlayer insulating gap filling pattern 12 can be formed to cover the inner surface of the preliminary word line pattern 9a and expose the central region of the bottom surface of the first recessed region RC1. Thereafter, a shielding layer SPTL in contact with the first interlayer insulating gap filling pattern 12 can be formed to fill the first groove G1. Next, during the process of etching the preliminary word line pattern 9a to form word lines WL1 and WL2 (for example, see Figure 17A and Figure 17B ), the shielding layer SPTL can be etched together with the preliminary word line pattern 9a to form the shield line SPT.

[0149] Figure 48A is a plan view showing a three-dimensional semiconductor memory device according to an embodiment. Figure 48B is a view showing along Figure 48ACross-sectional views of a three-dimensional semiconductor memory device taken along lines A-A', B-B', and C-C'. Figure 48C Shows a perspective view of a word line according to an embodiment Figure 48B of a word line.

[0150] Referring to Figures 48A to 48C , the word line WL can penetrate the channel region CH of the semiconductor pattern SP and the interlayer insulating layer IL disposed between the channel regions CH. The gate insulating layer Gox can be disposed between the word line WL and the semiconductor pattern SP and between the word line WL and the interlayer insulating layer IL. The word line WL can include a word line portion WLL and a word line protruding portion WLP. The word line portion WLL extends from the top surface of the substrate 1 in the third direction D3, and the word line protruding portion WLP protrudes from the side surface WLS of the word line portion WLL toward the interlayer insulating layer IL and is spaced apart from each other. When observed in a plan view, the word line portion WLL can have a circular shape (e.g., see Figure 48A ) or an oval, square, or rectangular shape. When observed in a plan view, as shown in Figure 48A or 48C, the word line protruding portion WLP can have an annular shape. In the cross-section A-A' of Figure 48B , the word line WL can have a tenth width WT10 at the height of the semiconductor pattern SP and can have an eleventh width WT11 larger than the tenth width WT10 at the height of the interlayer insulating layer IL.

[0151] As shown in Figure 48A , the insulating gap filling pattern 18 can be disposed between the semiconductor patterns SP in the first direction D1. Except for the above differences, the three-dimensional semiconductor memory device according to the present embodiment can have substantially the same features as those described with reference to Figures 3A to 3C . Since the word line WL has the word line protruding portion WLP, the channel controllability can be improved.

[0152] Figure 49A and Figure 50A Sequentially show the processes of manufacturing a three-dimensional semiconductor memory device having a planar structure as shown in Figure 48A in a plan view. Figure 49B and Figure 50B Are cross-sectional views of a three-dimensional semiconductor memory device taken along lines A-A', B-B', and C-C' of Figure 49A and Figure 50A respectively.

[0153] Referring to Figure 49A and Figure 49B , the first groove G1 can be formed to have the same as Figure 15A and Figure 15BThe same structure as shown. The first groove G1 can be filled with the insulating gap filling pattern 18. The preliminary stacked structure PT between the insulating gap filling patterns 18 can be etched to form a fourth hole H4 exposing the top surface of the substrate 1. The fourth hole H4 can be formed to be separated from the insulating gap filling pattern 18.

[0154] Referring to Figure 49A , Figure 49B , Figure 50A and Figure 50B , an isotropic etching process can be performed to partially remove the interlayer insulating layer IL exposed through the fourth hole H4. Then, a gate insulating layer Gox can be conformally formed, and a word line WL can be formed by filling the fourth hole H4 with a conductive layer. Except for the above differences, the manufacturing process according to this embodiment can have substantially the same features as the above process.

[0155] The embodiments described with reference to Figures 2 to 50B can be combined. For example, Figure 46 the shielding line SPT can be provided between adjacent word lines among the first word line WL1 and the second word line WL2 in the embodiment of Figures 3A to 45 or between adjacent word lines among the word lines WL in the embodiment of Figure 48A . The width relationship and thickness relationship described with reference to Figures 38 to 45 can be applied to the embodiments described with reference to Figures 3A to 37 as well as Figure 46 and Figure 48A . In the embodiment of Figures 38 to 48B , the interlayer insulating layer IL can have the same structure as one of the structures described with reference to Figures 3A to 37 .

[0156] In a three-dimensional semiconductor memory device according to an embodiment, the interlayer insulating layer can be provided in various structures, and this enables diversification of the performance of the three-dimensional semiconductor memory device. In addition, the word line can be provided adjacent to the top surface and the bottom surface of the semiconductor pattern to improve the channel controllability performance. Therefore, the reliability of the three-dimensional semiconductor memory device can be improved.

[0157] Example embodiments have been disclosed herein. Although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art at the time of filing this application, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: A first semiconductor pattern, the first semiconductor patterns being vertically stacked on a substrate and spaced apart from each other in a vertical direction, each first semiconductor pattern comprising: a first end and a second end, spaced apart from each other; and a first side surface and a second side surface, spaced apart from each other, each of the first side surface and the second side surface connecting the first end to the second end; A first source / drain region and a second source / drain region, located in each first semiconductor pattern, the first source / drain region and the second source / drain region being adjacent to the first end and the second end, respectively; A channel region, located in each first semiconductor pattern, the channel region being between the first source / drain region and the second source / drain region; A first word line, adjacent to the first side surface and the channel region of the first semiconductor pattern, the first word line extending in a vertical direction perpendicular to the top surface of the substrate; and A gate insulating layer, located between the first word line and the first side surface of the first semiconductor pattern, the gate insulating layer extending between the first source / drain regions of adjacent first semiconductor patterns, wherein the gate insulating layer fills the space between the adjacent first semiconductor patterns, and a side surface of the first word line in contact with the gate insulating layer has a concavo-convex structure.

2. The three-dimensional semiconductor memory device according to claim 1, the three-dimensional semiconductor memory device further comprising an air gap region between the adjacent first semiconductor patterns to expose the gate insulating layer.

3. The three-dimensional semiconductor memory device according to claim 1, wherein A part of the first word line extends between the adjacent first semiconductor patterns.

4. The three-dimensional semiconductor memory device according to claim 3, wherein, The first word line includes a gap between the adjacent first semiconductor patterns.

5. The three-dimensional semiconductor memory device according to claim 1, the three-dimensional semiconductor memory device further comprising an interlayer insulating layer between the adjacent first semiconductor patterns, the interlayer insulating layer being in contact with the gate insulating layer and formed of a material different from that of the gate insulating layer.

6. The three-dimensional semiconductor memory device according to claim 1, the three-dimensional semiconductor memory device further comprising: A second semiconductor pattern, the second semiconductor patterns being vertically stacked on the substrate, spaced apart from each other, and spaced apart from the first semiconductor patterns, the second semiconductor patterns respectively including a third side surface adjacent to the first side surface of the first semiconductor pattern; A second word line, adjacent to the third side surface of the second semiconductor pattern, the second word line extending in a vertical direction perpendicular to the top surface of the substrate; and A shielding line, located between the first word line and the second word line, the shielding line being spaced apart from the first word line and the second word line.

7. The three-dimensional semiconductor memory device according to claim 6, wherein, The first word line, the second word line, and the shielding line are parallel to the vertical direction and have the same width.

8. The three-dimensional semiconductor memory device according to claim 1, wherein, An upper width of the first word line measured in a first direction is different from a lower width of the first word line measured in the first direction, the first direction being parallel to the top surface of the substrate.

9. The three-dimensional semiconductor memory device according to claim 8, wherein, A width of the lowermost first semiconductor pattern among the first semiconductor patterns measured in a second direction is different from a width of the uppermost first semiconductor pattern among the first semiconductor patterns measured in the second direction, the second direction being parallel to the top surface of the substrate and different from the first direction.

10. The three-dimensional semiconductor memory device according to claim 1, wherein, In each first semiconductor pattern, a first end portion has a first thickness, a second end portion has a second thickness, and the first thickness and the second thickness are different in a vertical direction.

11. The three-dimensional semiconductor memory device according to claim 1, wherein the three-dimensional semiconductor memory device further includes bit lines respectively contacting the first end portions of the first semiconductor patterns, and the bit lines extend in a second direction parallel to the top surface of the substrate. Among them, Each bit line has a first thickness at a position contacting the first end portion and has a second thickness different from the first thickness at a position spaced apart from the first end portion.

12. The three-dimensional semiconductor memory device according to claim 1, wherein the three-dimensional semiconductor memory device further includes data storage electrodes respectively contacting the second end portions of the first semiconductor patterns, and a thickness of the data storage electrodes is different from a thickness of the first semiconductor patterns.

13. A three-dimensional semiconductor memory device, the three-dimensional semiconductor memory device comprising: At least one first semiconductor pattern and at least one second semiconductor pattern, located on a substrate, the at least one first semiconductor pattern and the at least one second semiconductor pattern being separated from each other in a first direction; A first word line, located between the at least one first semiconductor pattern and the at least one second semiconductor pattern, the first word line being adjacent to the at least one first semiconductor pattern; A second word line, located between the at least one first semiconductor pattern and the at least one second semiconductor pattern, the second word line being adjacent to the at least one second semiconductor pattern; And A shielding line, located between the first word line and the second word line, the shielding line being insulated from the first word line and the second word line, Wherein, the at least one first semiconductor pattern includes a plurality of first semiconductor patterns stacked on the substrate and separated from each other, and the three-dimensional semiconductor memory device further includes a gate insulating layer covering top surfaces, bottom surfaces and side surfaces of the plurality of first semiconductor patterns. Wherein, the gate insulating layer fills a space between adjacent first semiconductor patterns among the plurality of first semiconductor patterns, and a side surface of the first word line contacting the gate insulating layer has an uneven structure.

14. The three-dimensional semiconductor memory device according to claim 13, wherein, Each of the first word line, the second word line and the shielding line extends from the top surface of the substrate in a vertical direction, and side surfaces of the shielding line are aligned with side surfaces of the first word line and the second word line.

15. The three-dimensional semiconductor memory device according to claim 13, wherein, Each of the plurality of first semiconductor patterns includes a first end portion and a second end portion separated from each other, The three-dimensional semiconductor memory device further includes: A first source / drain region and a second source / drain region, located in each of the plurality of first semiconductor patterns, the first source / drain region and the second source / drain region being adjacent to the first end portion and the second end portion respectively; A channel region, located in each of the plurality of first semiconductor patterns, the channel region being between the first source / drain region and the second source / drain region; A first interlayer insulating layer, located between channel regions of the plurality of first semiconductor patterns; and The second interlayer insulating layer is located between the first source / drain regions or the second source / drain regions of the plurality of first semiconductor patterns, and the first interlayer insulating layer includes a material different from that of the second interlayer insulating layer.

16. The three-dimensional semiconductor memory device according to claim 13, wherein, The three-dimensional semiconductor memory device further includes a space between adjacent first semiconductor patterns among the plurality of first semiconductor patterns, and the space exposes the top surface and the bottom surface of the first semiconductor pattern.

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