Amplitude Shift Keying Demodulation for Wireless Chargers

Abstract

The present invention relates to "Amplitude Shift Keying Demodulation for a Wireless Charger." A power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample and hold (S&H) circuit having an input coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal having the same frequency, wherein the first control signal is configured to alternately turn the first switch on and off, the second control signal is configured to alternately turn the second switch on and off, and the third control signal determines a sampling time of the first S&H circuit and has a first predetermined delay from a first edge of the first control signal.

Description

Technical Field

[0001] The present invention relates generally to wireless charging circuits and, in particular embodiments, to circuits and methods for demodulating amplitude shift keying (ASK) modulated signals in wireless charging systems. Background Art

[0002] Wireless charging has become an increasingly popular charging technology. Sometimes referred to as inductive charging, wireless charging uses an electromagnetic field to transfer power between a power transmitter and a power receiver. Power is transmitted to an electrical device through inductive coupling, which can then use the power to charge a battery or operate the device. Inductive chargers use a first induction coil to generate an alternating electromagnetic field from the transmitter and a second induction coil to receive power from the electromagnetic field. The second induction coil converts the power back into an electric current, which can then be used to charge a battery or directly power an electrical device. When the two induction coils are in close proximity, they form a transformer.

[0003] Various industry standards have recently been developed to enable communication between power transmitters and power receivers. For example, in some standards, amplitude shift keying (ASK) modulation is used for in-band communication between power receivers and power transmitters. Current hardware for ASK demodulation is often bulky. Furthermore, ASK demodulation for in-band communication is challenging due to in-band noise. There is a need in the art for compact hardware designs for ASK demodulation that can achieve high demodulation accuracy for wireless power systems. Summary of the Invention

[0004] In some embodiments, a power transmitter includes: a first switch and a second switch, wherein the first switch and the second switch are connected at a first node, wherein the second switch is configured to be coupled between a power source and the first node, and wherein the first switch is configured to be coupled between the first node and a reference voltage node; a coil, wherein a first end of the coil is coupled to the first node, and a second end of the coil is configured to be coupled to the reference voltage node; a timing control circuit, wherein the timing control circuit is configured to generate a first control signal coupled to a first control terminal of the first switch, and the timing control circuit is configured to generate a second control signal coupled to a second control terminal of the second switch, wherein the first control signal and the second control signal is configured to turn on the first switch while the second switch is turned off, and the first control signal and the second control signal are configured to turn off the first switch while the second switch is turned on, wherein the first switch and the second switch are configured to be alternately turned on and off at the same switching frequency; a first sample and hold (S&H) circuit coupled to the first node; and a second S&H circuit coupled to the second end of the coil, wherein the timing control circuit is further configured to generate a third control signal and a fourth control signal, wherein the third control signal enables the first S&H circuit to sample at the switching frequency; and the fourth control signal enables the second S&H circuit to sample at the switching frequency.

[0005] In some embodiments, a method of operating a power transmitter includes: generating, by a timing control circuit of the power transmitter, first and second control signals; providing the first and second control signals to first control terminals of a first switch and second control terminals of a second switch, respectively, wherein the first control signal alternately switches the first switch on and off at a first switching frequency, wherein the second control signal alternately switches the second switch on and off at the first switching frequency, wherein the first and second switches are connected at a first node, the first switch is coupled between the first node and electrical ground, and the second switch is coupled between a power supply and the first node; generating, by the timing control circuit, third and fourth control signals, wherein the third control signal has a first predetermined delay from a first edge of the first control signal, and the fourth control signal has a second predetermined delay from a second edge of the second control signal; controlling operation of a first sample and hold (S&H) circuit using the third control signal, wherein an input of the first sample and hold circuit is coupled to the first node; and controlling operation of a second S&H circuit using the fourth control signal, wherein an input of the second S&H circuit is coupled to a second end of a coil, wherein the first end of the coil is coupled to the first node, and the second end of the coil is coupled to electrical ground via a capacitor.

[0006] In some embodiments, a power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample and hold circuit, wherein an input of the first sample and hold circuit is coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal, wherein the first control signal, the second control signal, and the third control signal have the same frequency, wherein the first control signal is configured to alternately turn on and off the first switch, the second control signal is configured to alternately turn on and off the second switch, and the third control signal determines a sampling time of the first S&H circuit, wherein the third control signal has a first predetermined delay from a first edge of the first control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present invention will become apparent from the description and drawings, as well as from the claims. In the drawings, like reference numerals generally represent like components throughout the various views, and for the sake of brevity, they will generally not be re-described. For a more complete understanding of the present invention, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0008] Figure 1 A schematic diagram of a wireless power system in one embodiment is shown;

[0009] Figure 2 A schematic diagram illustrating another wireless power system in one embodiment is shown;

[0010] Figure 3 A schematic diagram of a power transmitter in one embodiment is shown;

[0011] Figure 4 An embodiment of the present invention is shown. Figure 3 Timing diagram of sampling the current and voltage of the power transmitter;

[0012] Figure 5 A schematic diagram of a power transmitter in one embodiment is shown;

[0013] Figure 6A A schematic diagram of a power transmitter in one embodiment is shown;

[0014] Figure 6B shows a schematic diagram of a voltage divider in some embodiments;

[0015] Figure 6C A schematic diagram illustrating a resistor-capacitor (RC) filter in some embodiments is shown;

[0016] Figure 7 An embodiment of the present invention is shown. Figure 6A Timing diagram of sampling the current and voltage of the power transmitter;

[0017] Figure 8 Another embodiment is shown for Figure 6A Timing diagram of sampling the current and voltage of the power transmitter;

[0018] Figure 9 Another embodiment is shown for Figure 6A Timing diagram of sampling the current and voltage of the power transmitter;

[0019] Figure 10 Another embodiment is shown for Figure 6A Timing diagram of sampling the current and voltage of the power transmitter;

[0020] Figure 11 A block diagram illustrating a power transmitter with a parallel ASK demodulation path in some embodiments; and

[0021] Figure 12 A flow chart illustrating a method for operating a power transmitter in some embodiments is shown. DETAILED DESCRIPTION

[0022] The making and using of the presently preferred embodiments will be discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific circumstances. The specific embodiments discussed are merely illustrative of specific ways to make and use the present invention and do not limit the scope of the invention. Throughout the discussion herein, unless otherwise indicated, identical or similar numbers in different figures represent identical or similar components.

[0023] The present invention will be described with respect to exemplary embodiments in a specific context, namely, circuits and methods for demodulating ASK modulated signals in a wireless power system.

[0024] Figure 1 A schematic diagram of a wireless power system 100 in one embodiment is shown. In the discussion herein, a wireless power system may also be referred to as a wireless charging system. It should be noted that for simplicity, not all features of the wireless power system 100 are shown.

[0025] like Figure 1As shown, wireless power system 100 includes a power transmitter 110 and a power receiver 120. Power transmitter 110 includes an alternating current (AC) power source 111, a capacitor 113, and a coil 115. AC power source 111 provides a high-frequency (e.g., several hundred kilohertz) AC current to the power transmitter circuit. Coil 115 enters series resonance with capacitor 113 and generates a time-varying electromagnetic field due to the applied AC current.

[0026] Still refer to Figure 1 , the power receiver 120 includes a coil 125, a capacitor 123, a rectifier 142 (including diodes D1, D2, D3 and D4) and a capacitor 129. When the power transmitter 110 charges the power receiver 120, the coil 125 is electromagnetically coupled to the coil 115 and enters into series resonance with the capacitor 123, so that power is transmitted from the power transmitter 110 to the power receiver 120. The rectifier 142 rectifies the AC voltage from the resonant network (the resonant network includes the coil 125 and the capacitor 123 coupled in series) into a direct current (DC) voltage. The capacitor 129 can be used as a low-pass filter to filter out the AC component in the output DC voltage from the rectifier 142, and the capacitor 129 is generally referred to as a storage capacitor. Although in Figure 1 A full-bridge rectifier is shown in FIG, but any suitable rectifier may be used, such as a half-bridge rectifier.

[0027] also, Figure 1 Regulator 127 is shown, which regulates (e.g., down-converts, up-converts, and / or stabilizes) the output voltage from rectifier 142 and sends the regulated voltage to load 131 (e.g., a battery to be charged or the input of a battery charger). In some embodiments, regulator 127 is omitted. In some embodiments, AC power source 111 and load 131 are considered external components connected to wireless power system 100 and are therefore not part of wireless power system 100.

[0028] Figure 1Also shown are a capacitor 141 coupled to a switch SCmod and a resistor 143 coupled to a switch SRmod for ASK modulation. In a wireless power system, it may be advantageous for a power transmitter to transfer an appropriate amount of energy to a power receiver and ensure that the receiver has a device to communicate power requirements to the transmitter. Industry standards, such as the Qi standard developed by the Wireless Power Consortium (WPC), enable a power receiver to communicate with a power transmitter via in-band communication and use ASK modulation to transmit communication signals (also known as transmission data). For example, to send a bit "1", the control circuit of the power receiver 120 can generate a control signal to turn on the switch SCmod (or SRmod) within a predetermined time period (e.g., 500ms). Similarly, to send a bit "0", the switch SCmod (or SRmod) is turned off within a predetermined time period. As defined by the standard, the polarity for transmitting bits "1" and "0" can be reversed.

[0029] Turning the switch SCmod (or SRmod) on or off changes the impedance of the power receiver 120, which causes changes on the power transmitter side through electromagnetic coupling. For example, modulation on the power receiver side (also known as the secondary side) (e.g., opening and closing the switch) can cause changes in the current, voltage, and / or frequency observed on the power transmitter side (also known as the primary side). By detecting changes on the power transmitter side (e.g., current changes, voltage changes, and / or frequency changes), the ASK modulated signal transmitted on the power receiver side can be detected and demodulated. ASK modulation can be performed by opening / closing the switch SCmod, the switch SRmod, or both switches SCmod and SRmod.

[0030] Figure 2 FIG2 shows a schematic diagram of another wireless power system 200 in one embodiment. Figure 1 The wireless power system 100 is similar to that in FIG. Figure 2 The rectifier 142 in the embodiment is formed by switches S1, S2, and S3, and S3 replaces Figure 1 . The switches S1, S2, S3, and S4 may be any suitable switches, such as transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)). The control circuit of the power receiver 120 may generate control signals coupled to control terminals (e.g., gates) of the switches. As will be readily understood by those skilled in the art, the control signals are configured to turn on switches S1 and S2 when switches S3 and S4 are off, and to turn on switches S3 and S4 when switches S1 and S2 are off. When a switch (e.g., S1, S2, S3, or S4) is on, a low impedance path is formed between the load path terminals (e.g., drain / source terminals) of the switches, and current flows through the load path terminals.

[0031] exist Figure 1 and Figure 2 In the example of , the power transmitter 110 can be a wireless charging station (e.g., a charging pad or charging device), and the power receiver 120 can be a mobile device (e.g., a mobile phone). However, the power receiver 120 can be designed to include additional circuitry so that the power receiver can also be used as a power transmitter to provide charging capabilities. Such a power receiver can be referred to as a combined Tx / Rx power device. For example, a mobile phone can be designed as a combined Tx / Rx power device so that it can not only be charged by a wireless charging station in Rx mode, but can also charge another mobile phone as a wireless charging station in Tx mode. Due to the space limitations of mobile devices, the combined Tx / Rx device should be compact for easy integration. In addition, reliable ASK demodulation should be achieved. The embodiments disclosed herein achieve the above requirements.

[0032] Figure 3 FIG2 shows a schematic diagram of a full-bridge power transmitter 300 in one embodiment. In the embodiment shown, the power transmitter 300 is an equivalent schematic diagram of a combined Tx / Rx power device in Tx mode, and Figure 2 The power receiver 120 in FIG is an equivalent schematic diagram of a combined Tx / Rx power device in Rx mode. Note that for clarity, Figure 3 Not all features of the power transmitter 300 are shown. Figure 3 The battery 145 shown in FIG. 3 can be considered an external component connected to the power supply node Vbat rather than a part of the power transmitter 300 .

[0033] like Figure 3 As shown, the power transmitter 300 includes coils L coupled in series (in Figure 2 In the figure, there is a coil 125) and a capacitor C (in Figure 2 The switches S1, S2, S3 and S4 form a full bridge. The switch S1 is coupled between the node AC1 and the power supply node Vbat, which is connected to the positive terminal of the battery 145 (which may be a Figure 2 Regulator 127 in FIG. 1 is coupled in series with load 131. Switch S4 is coupled between node AC1 and a reference voltage node (e.g., connected to electrical ground). Switch S3 is coupled between power supply node Vbat and node AC2. Switch S2 is coupled between the reference voltage node and node AC2.

[0034] The control circuit of the power transmitter 300 generates control signals to turn on and off switches S1, S2, S3, and S4 to generate a positive or negative voltage between node AC1 and node AC2. In the discussion herein, the voltage between node AC1 and node AC2 is represented as V(AC1, AC2), where a positive value of V(AC1, AC2) indicates that the voltage on node AC1 is higher than the voltage on node AC2, and vice versa. For example, the control signal can turn on switches S1 and S2 (while turning off switches S3 and S4) to generate positive V(AC1, AC2), and then can turn on switches S3 and S4 (while turning off switches S1 and S2) to generate negative V(AC1, AC2). The above process is repeated at a switching frequency, so that the DC voltage of the battery 145 becomes an AC voltage, and a time-varying electromagnetic field is generated through the coil L for transferring energy to the power receiver, which can have the same Figure 1 or Figure 2 The power receiver 120 in FIG. 1 may have the same or similar structure as the power receiver 120 in FIG. The power receiver may communicate with the power transmitter 300 via ASK modulation. Figure 4 A timing control signal is shown, which is used to detect the amplitude changes of the current and voltage in the power transmitter 300 due to the ASK modulation on the power receiver side.

[0035] Figure 4 An embodiment of the present invention is shown. Figure 3 The timing diagram of the current and voltage sampling of the power transmitter. Figure 4 In the diagram, the x-axis represents time and the y-axis represents the amplitude of various signals. Figure 4 In the example (and subsequent example timing diagrams), the resonant frequency of the power transmitter (e.g., 300) is determined by the capacitance of the capacitor C and the inductance of the coil L, and the resonant frequency is less than the switching frequency of the power transmitter. The switching frequency can be calculated as the switching period T of the switching control signal (e.g., see Figure 4 and Figure 7 For example, the resonant frequency of the power transmitter 300 may be approximately 80 KHz, and the switching frequency of the power transmitter 300 may be between approximately 95 KHz and approximately 200 KHz.

[0036] exist Figure 4, curve 410 shows the voltage signal V(AC1, AC2) over time. Note that V(AC1, AC2) is determined by the control signal for turning on and off switches S1, S2, S3, and S4, and therefore, the state of the control signal can be derived from the voltage signal V(AC1, AC2). Therefore, the voltage V(AC1, AC2) can also be called a switch control signal. Curves 420 and 430 show the current I(L) flowing through the coil L and the nodes P and N (see FIG. 1 ) when the switching frequency of the power transmitter 300 is 160 kHz. Figure 3 For comparison, curves 440 and 450 show the current I(L) and the voltage V(P, N) when the switching frequency of the power transmitter 300 is 95 KHz.

[0037] Figure 4 Further shown are sampling control signals 401 and 403, which are Figure 4 , are shown as arrows to indicate the timing of sampling the current I(L) and voltage V(P, N), respectively. Sampling control signals 401 and 403 may be any suitable control signals, such as the rising edges of clock signals 404A and 404B, respectively. For simplicity, the subsequent figures illustrate the sampling control signals (e.g., 701 / 703, 801 / 803, and 901 / 903) as arrows, and it should be understood that the arrows indicate, for example, the positions of the rising edges of the respective clock signals. The sampled values ​​of the current I(L) and / or the sampled values ​​of the voltage V(P, N) are then sent to the ASK demodulation circuit to detect the digital data (e.g., zero or one) sent by the power receiver.

[0038] Since the ASK demodulation circuit demodulates the transmitted ASK signal by detecting the amplitude changes of the current and / or voltage, it is advantageous to sample the current I(L) and / or voltage V(P, N) at or near their respective peak values ​​to improve noise immunity and reduce demodulation errors. It should be noted that sampling near the peak values ​​of the current or voltage signal may be sufficient for ASK demodulation because ASK demodulation may respond to the difference between the sampled values ​​(rather than the absolute value) for demodulation.

[0039] exist Figure 4In the example shown, the sampling instant for current I(L) (see sampling control signal 401) occurs once per switching period T, at the end of each low state of V(AC1, AC2) (e.g., when V(AC1, AC2) is negative). In other words, the sampling frequency of current I(L) is the same as the switching frequency of the power transmitter, and each sampling instant precedes the corresponding rising edge of V(AC1, AC2) by a predetermined duration. Therefore, the sampling instant for current I(L) is also said to have a predetermined negative delay t1 (t1<0) from the corresponding rising edge of voltage signal V(AC1, AC2). Here, the corresponding rising (or falling) edge refers to the most recent rising (or falling) edge.

[0040] Similarly, the sampling frequency of the voltages V(P, N) is the same as the switching frequency of the power transmitter, and the sampling instants of the voltages V(P, N) have a predetermined delay t2 (t2>0) from the corresponding rising edge of the voltage signals V(AC1, AC2). Therefore, there is a predetermined delay (e.g., t2-t1, where t1 is a negative value) between the sampling control signals 401 and 403. In some embodiments with a switching frequency between approximately 95 kHz and approximately 200 kHz, the magnitude (e.g., absolute value) of the delay t1 is between approximately 0 μs and approximately 1 μs, and the magnitude of the delay t2 is between approximately 0.2 μs and approximately 1.5 μs. Because the sampling control signals 401 and 403 have the same frequency as the switching frequency and have a fixed relationship (e.g., delay) with the switching control signal, the sampling control signals 401 and 403 are said to be synchronized with the switching control signal.

[0041] Figure 5 A schematic diagram of a half-bridge power transmitter 400 in one embodiment is shown. In the embodiment shown, the power transmitter 400 is an equivalent schematic diagram of a combined Tx / Rx power device in Tx mode and may be similar to the power transmitter 300, but with some modifications to the half-bridge configuration. For example, the power transmitter 400 may be configured to be connected to the power supply 300 by removing the power supply 300. Figure 3 switches S1 and S4, and by Figure 3 The node AC1 in the power transmitter 400 is directly connected to the electrical ground to form the power transmitter 400. The control circuit of the power transmitter 400 is also modified to generate the control signals for the remaining switches S2 and S3. Figure 5 The switches T2 and T1 in the Figure 3 Note that for clarity, the switches S3 and S2 in Figure 5 Not all features of the power transmitter 400 are shown.

[0042] exist Figure 5In the embodiment of the present invention, the power transmitter 400 includes a switch T1 coupled between a node N (also a node AC2) and a reference voltage node Vref (e.g., electrical ground), and includes a switch T2 coupled between a power supply node Vbat and the node N. In addition, the power transmitter 400 includes a coil L and a capacitor C, which are coupled in series between the node N and electrical ground. A first end of the coil L is coupled to the node N, and a second end of the coil L is coupled to the capacitor C.

[0043] Figure 6A FIG1 shows a schematic diagram of a power transmitter 500 in one embodiment that generates current and voltage samples for ASK demodulation. The power transmitter 500 may be a more detailed diagram of the power transmitter 400 or may be provided by a power transmitter 500. Figure 5 The power transmitter 400 is formed by adding additional circuitry to generate samples of the current I(L) and the voltage V(P, N) for ASK demodulation of data transmitted from the electromagnetically coupled power receiver.

[0044] exist Figure 6A In the embodiment of the present invention, power transmitter 500 includes a timing control circuit 405, also referred to as a control circuit. Power transmitter 500 also includes driver circuits 407A and 407B coupled between timing control circuit 405 and switches T1 and T2, respectively. Driver circuits 407A and 407B can be any suitable driver circuit known in the art. In some embodiments, driver circuits 407A and 407B are omitted, and the switch control signals from timing control circuit 405 are coupled directly to the control terminals of switches T1 and T2.

[0045] The timing control circuit 405 is digital hardware that is configured to generate a control signal (eg, a digital clock signal) for turning on and off the switches T1 and T2 at a switching frequency. The timing control circuit 405 is also configured to generate a current sampling control signal I sample And the voltage sampling control signal V sample , which respectively indicate the time when the current I(L) and voltage V(P, N) are sampled. As discussed below, the current sampling control signal I sample And the voltage sampling control signal V sample Therefore, the delay circuit 511 with the predetermined delay is coupled to the current sampling control signal I sample And the voltage sampling control signal V sample The details of the control signal generated by the timing control circuit 405 will be referred to below. Figure 7-10 Have a discussion.

[0046] Figure 6AA filter 505 is shown coupled between node N and a sample and hold (S&H) circuit 507. When current in coil L flows through switch T1, the voltage drop across the load path terminals of switch T1 serves as an image of (e.g., a value proportional to) the current value I(L). In other words, switch T1 also serves as a sensing device for current I(L). Filter 505 can be a simple resistor-capacitor (RC) filter (e.g., see FIG. 1 ). Figure 6C ), or other suitable low-pass analog filters. In some embodiments, the filter 505 is not permanently connected to the node N, but a switch may be coupled between the node N and the filter 505, and the switch may be turned on or off by a control signal so that the filter 505 can be disconnected from the node N at an appropriate time. For example, when the node N is high (e.g., has a high voltage), the filter 505 can be disconnected from the node N, so that the filter 505 does not detect the node N to avoid saturation or excessive voltage. The bandwidth of the filter 505 can be determined by the switching frequency to ensure that the in-band signal passes while suppressing out-of-band noise. For example, the bandwidth of the filter 505 can be hundreds of kilohertz wide. The current sampling control signal Is ample Control the sampling time of the S&H circuit 507. sample At each instant indicated, the S&H circuit 507 samples the current value I(L) and holds the sampled value. In some embodiments, the output of the S&H circuit 507 may be sent directly to an analog-to-digital converter (ADC) for conversion to a digital signal. In other embodiments, the output of the S&H circuit 507 may be sent to signal conditioning hardware before being converted to a digital signal by the ADC. After the ADC conversion, further digital signal processing, such as ASK demodulation and error correction decoding, may be performed to decode the message sent from the power receiver to the power transmitter.

[0047] Figure 6A Further shown is a voltage divider 513 coupled to node P. The voltage divider may be a simple resistor based voltage divider (e.g., see Figure 6B ), or it may be another suitable voltage divider, such as a switched capacitor voltage divider, in which case high frequency noise should be filtered out before the voltage is divided by the switched capacitor voltage divider. In some embodiments, the voltage divider 513 is not permanently connected to the node P and is therefore coupled to the node P by, for example, a switch that can be turned on and off by a control signal at appropriate times. The output of the voltage divider 513 is sent to the filter 515, which is a low-pass analog filter that is the same as or similar to the filter 505. The output of the filter 515 is sent to the input of the S&H circuit 517. The sampling control signal V sample Control the sampling time of the S&H circuit 517. sampleAt each instant of time indicated, the S&H circuit 517 samples the image of the voltage value V(P, N) and holds the sampled value. In some embodiments, the output of the S&H circuit 517 may be sent directly to an analog-to-digital converter (ADC) for conversion to a digital signal. In other embodiments, the output of the S&H circuit 517 may be sent to signal conditioning hardware before being converted to a digital signal by the ADC. After the ADC conversion, further digital signal processing, such as ASK demodulation and error correction decoding, may be performed to decode the message sent from the power receiver to the power transmitter.

[0048] exist Figure 6A In the example shown, two S&H circuits 507 and 517 are used to sample the current value I(L) and the voltage value V(P, N). This allows ASK demodulation to be performed using different signals in multiple demodulation / decoding paths, thereby improving robustness and accuracy. In other embodiments, to reduce hardware cost, only one of the S&H circuits 507 and 517 and its associated components (e.g., filters and voltage dividers, if necessary) is used to provide a sampled value of the current I(L) or a sampled value of the voltage V(P, N).

[0049] Figure 7 An embodiment of the present invention is shown. Figure 6A The timing diagram of sampling the current and voltage of the power transmitter 500. Figure 7 In FIG, curves 710 and 720 respectively show the gate control voltages V(G2) and V(G1) (also referred to as switch control signals) generated by the timing control circuit 405 to turn on and off the switches T2 and T1. Figure 7 In the example, it is assumed that a logic high voltage turns on switches T1 and T2, and a logic low voltage turns on switches T1 and T2. It is noted that the gate control voltages V(G1) and V(G2) are non-overlapping drive signals. In other words, when V(G1) is high (e.g., switch T1 is turned on), V(G2) is low (e.g., switch T2 is turned off); when V(G2) is high (e.g., switch T2 is turned on), V(G1) is low (e.g., switch T1 is turned off). Curve 730 shows the voltage V(AC1, AC2). Curves 740 and 750 show the current I(L) and the voltage V(P, N). In Figure 7 The current sampling control signal I represented by the arrow sample (See reference numeral 701) and the voltage sampling control signal V sample (See reference numeral 703 ), which indicate that the current I(L) and the voltage V(P, N) are sampled by the S&H circuits (eg, 507 , 517 ), respectively.

[0050] like Figure 7 As shown, the current sampling control signal I sample And the voltage sampling control signal Vsample It has the same frequency as the switch control signal and is synchronized with the switch control signal. Figure 7 In the example, the current sampling control signal I sample has a predetermined delay t1 (t1≤0) from the corresponding falling edge of the gate control voltage V(G1), and the voltage sampling control signal V sample There is a predetermined delay t2 (t2>0) starting from the corresponding rising edge of the gate control voltage V(G2). Figure 7 The dashed line A in FIG shows the falling edge of the gate control voltage V(G1), and the dashed line B shows the rising edge of the gate control voltage V(G2). In some embodiments where the switching frequency is between about 95 kHz and about 200 kHz, the magnitude (e.g., absolute value) of the delay t1 is between about 0 μs and about 1 μs, and the magnitude of the delay t2 is between about 0.2 μs and about 1.5 μs. Since the timing control circuit 405 generates the gate control voltages V(G1) and V(G2), it knows where the rising and falling edges of each gate control voltage are. Since the current sampling control signal I sample And the voltage sampling control signal V sample With a predetermined delay (eg, t1, t2) from the rising or falling edge of the corresponding gate control signal, it is simple for the timing control circuit 405 to generate the current sampling control signal I sample And the voltage sampling control signal V sample .

[0051] Figure 7 The current sampling control signal I sample And the voltage sampling control signal V sample are non-limiting examples. Other options are possible and are fully intended to be included within the scope of this disclosure. Figure 8-10 The current sampling control signal I sample And the voltage sampling control signal V sample Additional examples of .

[0052] Figure 8 Another embodiment is shown for Figure 6A A timing diagram illustrating the sampling of current and voltage of power transmitter 500. In some embodiments, the characteristics of the amplitude of current I(L) and voltage V(P, N) due to ASK modulation depend at least in part on the switching frequency used and are known (e.g., they can be measured and stored in a table in memory). Therefore, the sampling times of current I(L) and voltage V(P, N) can be adjusted according to the switching frequency to obtain better ASK demodulation results. Figure 8 The adjusted sampling time for a high switching frequency of 160 KHz and a low switching frequency of 95 KHz is shown (e.g., from Figure 7 Two examples of example adjustments).

[0053] Figure 8 The curve in is similar to Figure 7 Curves 840 and 850 show the current I(L) and voltage V(P, N) when the switching frequency is 160KHz. sample (See reference numeral 801) is adjusted to have a predetermined delay t1=0 starting from (and therefore corresponding to) the corresponding falling edge of the gate control signal V(G1), while the voltage sampling control signal V sample (See reference numeral 803 ) with a predetermined delay t2 ( t2 > 0) starting from the corresponding rising edge of the gate control signal V( G2 ).

[0054] Still refer to Figure 8 , curves 860 and 870 show the current I(L) and voltage V(P, N) at a switching frequency of 95KHz. sample (See reference numeral 801) with a predetermined delay t1 (t1<0) from the corresponding falling edge of the gate control signal V(G1), while the voltage sampling control signal V sample (See reference numeral 803) has been adjusted to have a predetermined delay t2 (t2-0) starting from the corresponding rising edge of the gate control signal V(G2). In some embodiments where the switching frequency is between about 95 kHz and about 200 kHz, the magnitude (e.g., absolute value) of the delay t1 is between about 0 μs and about 1 μs, and the magnitude of the delay t2 is between about 0.1 μs and about 1.5 μs.

[0055] Figure 9 Another embodiment is shown for Figure 6A The timing diagram of sampling the current and voltage of the power transmitter 500. Figure 9 In the current sampling control signal I sample (See reference numeral 901) with a predetermined delay t1 (t1<0) from the corresponding rising edge of the gate control signal V(G1), while the voltage sampling control signal V sample (See reference numeral 903) with a predetermined delay t2 (t2>0) from the corresponding rising edge of the gate control signal V(G2). Figure 9 In the current sampling control signal I sample And the voltage sampling control signal V sample The ADC only needs to convert samples into digital data approximately every half switching period T. Figure 7 and 8 Current sampling control signal Is in ampleAnd voltage sampling control signal Vsa mple Compared to the closed examples, Figure 9 The embodiment relaxes the requirement on ADC speed.

[0056] In another embodiment (not shown), the current sampling control signal I sample has a predetermined delay t1 (t1<0) from the corresponding falling edge of the gate control signal V(G1), while the voltage sampling control signal V sample has a predetermined delay t2 (t2>0) starting from the corresponding falling edge of the gate control signal V(G2). In yet another embodiment (not shown), the current sampling control signal I sample has a predetermined delay t1 (t1<0) from the corresponding rising edge of the gate control signal V(G1), and the voltage sampling control signal V sample There is a predetermined delay t2 (t2>0) starting from the corresponding falling edge of the gate control signal V(G2).

[0057] Figure 10 Another embodiment is shown for Figure 6A The timing diagram of sampling the current and voltage of the power transmitter 500. The current sampling control signal I sample And the voltage sampling control signal V sample The sampling instants indicated are chosen similarly to Figure 7 However, in Figure 10 In each switching cycle, before the corresponding falling edge of the gate control signal V(G1), the current I(L) is sampled multiple times by the S&H circuit 507 (and converted into multiple digital samples by the ADC circuit). In addition, after the corresponding rising edge of the gate control signal V(G2), the voltage V(P, N) is sampled multiple times by the S&H circuit 517 (and converted into multiple digital samples by the ADC circuit). In other words, Figure 10 In the example of FIG, multiple samples of the current I(L) and multiple samples of the voltage V(P, N) are obtained in each cycle of the switch control signal (e.g., each switching cycle). The corresponding multiple samples can be processed by digital processing techniques to further improve the ASK demodulation results and provide robustness against noise in the digital samples. For example, filtering techniques such as a simple averaging process or a more advanced filtering process can be used to improve the ASK demodulation performance. Those skilled in the art will readily appreciate that the above description of the ASK demodulation performance is not limited to the following examples: Figure 10 The multi-sampling method discussed in the example can also be applied to other embodiments, such as Figure 8 Example of .

[0058] Figure 11A block diagram of a power transmitter 600 with a parallel ASK demodulation path in some embodiments is shown. Figure 11 The power transmitter 600 in the embodiment may be Figure 6A A more detailed diagram of the power transmitter 500 in FIG. 1 is available, or can be viewed by clicking on the Figure 6A The power transmitter 500 in FIG. 1 is formed by adding additional circuits.

[0059] exist Figure 11 In the example of FIG. 5 , the power transmitter 600 includes an analog block 610, which may be Figure 6A The power transmitter 500 in FIG. The analog block 610 provides three sensing points 601, 603, and 605 for respectively sensing the changes of current (e.g., I(L)), voltage (e.g., V(P, N)), and frequency (e.g., the phase of the frequency or equivalent switching frequency) on the power transmitter side. Figure 6A In an embodiment where power transmitter 500 in FIG. 5 is used as analog block 610, the output of S&H circuit 507 provides a sensing point for sensing current, and the output of S&H circuit 517 provides a sensing point for sensing voltage. For frequency sensing, a suitable sensing method such as that disclosed in U.S. Patent Application No. 20160372934 may be used. U.S. Patent Application No. 20160372934 is incorporated herein by reference.

[0060] like Figure 11 As shown, the current, voltage, and phase observations are converted into digital samples by the ADC circuit 607 and processed in the digital domain in three parallel signal processing paths to demodulate and decode the message sent by the power receiver. In other words, the power transmitter 600 uses different sensed observations (e.g., current, voltage, and phase) in three different signal processing paths to demodulate and decode the data sent from the power receiver.

[0061] exist Figure 11 In the embodiment, each signal processing path includes a digital filter 611, a demodulation circuit 613, and a decoder 615. The digital filter 611 can remove out-of-band noise. The demodulation circuit 613 can perform ASK demodulation to recover the transmitted data. The decoder 615 can perform error correction decoding and / or error detection on the data generated by the demodulation circuit 613. A suitable error detection method such as a parity check or a cyclic redundancy check (CRC) can be used to determine which signal processing path produces a valid decoding result. The selector 617 selects the output of the signal processing path with the valid decoding result as the final output.

[0062] Redundancy is provided by decoding the transmitted data using three different signal processing paths. Studies have shown that the amount of change in current, voltage, and frequency on the power transmitter side depends on many factors, such as the topology of the power transmitter / power receiver, the impedance of the power transmitter / power receiver, the coupling factor between the coils of the power transmitter and the power receiver, etc. As a result, under certain conditions (e.g., load conditions, switching frequency), ASK modulation on the power receiver side may cause the amount of change in current, voltage, or frequency on the power transmitter side to be insignificant, which may cause difficulties for ASK demodulation. However, it is impossible for current, voltage, and frequency to have insignificant changes at the same time. Therefore, by demodulating the ASK signal using all three sensed observations (e.g., current, voltage, frequency), at least one of the signal processing paths may be able to correctly recover the data sent by the power receiver.

[0063] Figure 12 A flow chart of a method for operating a power transmitter in some embodiments is shown. It should be understood that Figure 12 The embodiment methods shown are merely examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated: Figure 12 The steps shown.

[0064] refer to Figure 12 At step 1210, a timing control circuit of the power transmitter generates a first control signal and a second control signal. At step 1020, the first control signal and the second control signal are provided to a first control terminal of a first switch and a second control terminal of a second switch, respectively, wherein the first control signal alternately switches the first switch on and off at a first switching frequency, and wherein the second control signal alternately switches the second switch on and off at the first switching frequency, wherein the first switch and the second switch are connected at a first node, the first switch is coupled between the first node and electrical ground, and the second switch is coupled between a power supply and the first node. At step 1030, the timing control circuit generates a third control signal and a fourth control signal, wherein the third control signal has a first predetermined delay from a first edge of the first control signal, and the fourth control signal has a second predetermined delay from a second edge of the second control signal. At step 1040, the operation of a first sample and hold (S&H) circuit is controlled using the third control signal, wherein an input of the first S&H circuit is coupled to the first node. In step 1050, operation of a second S&H circuit is controlled using a fourth control signal, wherein an input of the second S&H circuit is coupled to a second end of the coil, wherein a first end of the coil is coupled to the first node and a second end of the coil is coupled to electrical ground through a capacitor.

[0065] Embodiments can achieve advantages. For example, by using a sample and hold circuit and a synchronized sampling control signal, cycle-by-cycle detection of the current envelope and the voltage envelope can be achieved, which allows for a simple, compact circuit system for ASK demodulation and is easily integrated into a mobile device. Cycle-by-cycle detection naturally provides high-pass behavior (e.g., real-time cycle-by-cycle detection) for quickly detecting changes in peak (or near-peak) voltage or peak (or near-peak) current. The sample and hold method naturally suppresses the switching frequency. The output of the disclosed power transmitter (e.g., the output of the S&H circuit) can be converted to digital data by an ADC and can be processed by digital hardware or software to demodulate / decode the transmitted data. Various digital signal processing methods can be used to further enhance the accuracy and robustness of the demodulation.

[0066] Example embodiments of the present invention are summarized here. Other embodiments are apparent from the entire specification and claims herein.

[0067] Example 1. In one embodiment, a power transmitter includes: a first switch and a second switch, wherein the first switch and the second switch are connected at a first node, wherein the second switch is configured to be coupled between a power source and the first node, and the first switch is configured to be coupled between the first node and a reference voltage node; a coil, wherein a first end of the coil is coupled to the first node, and a second end of the coil is configured to be coupled to the reference voltage node; a timing control circuit, wherein the timing control circuit is configured to generate a first control signal coupled to a first control terminal of the first switch, and configured to generate a second control signal coupled to a second control terminal of the second switch, wherein The first control signal and the second control signal are configured to turn on the first switch while the second switch is turned off, and are configured to turn off the first switch while the second switch is turned on, wherein the first switch and the second switch are configured to be alternately turned on and off at the same switching frequency; a first sample and hold (S&H) circuit coupled to the first node; and a second S&H circuit coupled to the second end of the coil, wherein the timing control circuit is further configured to generate a third control signal and a fourth control signal, wherein the third control signal enables the first S&H circuit to sample at the switching frequency, and the fourth control signal enables the second S&H circuit to sample at the switching frequency.

[0068] Example 2. The power transmitter of Example 1, wherein there is a predetermined delay between the third control signal and the fourth control signal.

[0069] Example 3. The power transmitter of Example 2, wherein the third control signal and the fourth control signal are synchronized with the first control signal and the second control signal.

[0070] Example 4. The power transmitter of Example 1, wherein the third control signal is generated with a first predetermined delay from a first edge of the first control signal, and the fourth control signal is generated with a second predetermined delay from a second edge of the second control signal.

[0071] Example 5. The power transmitter of example 4, wherein the first predetermined delay has a negative value and the second predetermined delay has a positive value.

[0072] Example 6. The power transmitter of Example 5, wherein the first edge is a falling edge of the first control signal or a rising edge of the first control signal.

[0073] Example 7. The power transmitter of Example 6, wherein the second edge is a rising edge of the second control signal or a falling edge of the second control signal.

[0074] Example 8. The power transmitter of Example 1, wherein the power transmitter further comprises a capacitor coupled in series with the coil, wherein a resonant frequency of the power transmitter is determined by a capacitance of the capacitor and an inductance of the coil, wherein the resonant frequency is lower than the switching frequency.

[0075] Example 9. The power transmitter of Example 1, wherein the power transmitter further comprises: a first driver circuit coupled between the first output of the timing control circuit and the first control terminal of the first switch; and a second driver circuit coupled between the second output of the timing control circuit and the second control terminal of the second switch.

[0076] Example 10. The power transmitter of Example 1, further comprising: a first filter coupled between the first node and the first S&H circuit; and a second filter coupled between the second end of the coil and the second S&H circuit.

[0077] Example 11. The power transmitter of Example 10, wherein the first filter and the second filter are low pass filters.

[0078] Example 12. The power transmitter of Example 11, further comprising a voltage divider coupled between the second filter and the second end of the coil.

[0079] Example 13. In one embodiment, a method of operating a power transmitter includes: generating, by a timing control circuit of the power transmitter, first and second control signals; providing the first and second control signals to a first control terminal of a first switch and a second control terminal of a second switch, respectively, wherein the first control signal alternately switches the first switch on and off at a first switching frequency, wherein the second control signal alternately switches the second switch on and off at the first switching frequency, wherein the first and second switches are connected at a first node, the first switch is coupled between the first node and electrical ground, and the second switch is coupled between a power supply and the first node; generating, by the timing control circuit, third and fourth control signals, wherein the third control signal has a first predetermined delay from a first edge of the first control signal, and the fourth control signal has a second predetermined delay from a second edge of the second control signal; controlling operation of a first sample and hold circuit using the third control signal, wherein an input of the first sample and hold circuit is coupled to the first node; and controlling operation of a second sample and hold circuit using the fourth control signal, wherein an input of the second sample and hold circuit is coupled to a second end of a coil, wherein the first end of the coil is coupled to the first node, and the second end of the coil is coupled to electrical ground via a capacitor.

[0080] Example 14. The method of Example 13, wherein the third control signal and the fourth control signal have a frequency equal to the first switching frequency, wherein the first predetermined delay has a negative value and the second predetermined delay has a positive value.

[0081] Example 15. The method of Example 14, wherein the first edge of the first control signal is a falling edge or a rising edge.

[0082] Example 16. The method of Example 15, wherein the second edge of the second control signal is a rising edge or a falling edge.

[0083] Example 17. The method of Example 14, wherein a resonant frequency of an LC tank circuit including the coil and the capacitor is lower than the first switching frequency.

[0084] Example 18. In one embodiment, a power transmitter includes: a first switch coupled between a first node and a reference voltage node; a second switch configured to be coupled between a power supply and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample and hold (S&H) circuit, wherein an input of the first S&H circuit is coupled to the first node; and a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal, wherein the first control signal, the second control signal, and the third control signal have the same frequency, wherein the first control signal is configured to alternately turn on and off, the second control signal is configured to alternately turn on and off the second switch, and the third control signal determines a sampling time of the first S&H circuit, wherein the third control signal has a first predetermined delay from a first edge of the first control signal.

[0085] Example 19. The power transmitter of Example 18, further comprising a second S&H circuit, wherein an input of the second S&H circuit is coupled to a second node between the coil and the capacitor, wherein the timing control circuit is further configured to generate a fourth control signal having the same frequency as the third control signal, wherein the fourth control signal determines a sampling time of the second S&H circuit, wherein the fourth control signal has a second predetermined delay from a second edge of the second control signal.

[0086] Example 20. The power transmitter of Example 19, wherein the first predetermined delay has a negative value and the second predetermined delay has a positive value.

[0087] Example 21. The power transmitter of Example 20, wherein each of the first edge and the second edge is a falling edge or a rising edge.

[0088] Example 22. The power transmitter of Example 20, further comprising: a first amplitude shift keying (ASK) demodulation circuit coupled to the output of the first S&H circuit; and a second ASK demodulation circuit coupled to the output of the second S&H circuit.

[0089] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art by reference to the description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. A power transmitter, comprising: a first switch and a second switch, wherein the first switch and the second switch are connected at a first node, wherein the second switch is configured to be coupled between a power supply and the first node, and the first switch is configured to be coupled between the first node and a reference voltage node; a coil, wherein a first end of the coil is coupled to the first node and a second end of the coil is configured to be coupled to the reference voltage node; a timing control circuit, wherein the timing control circuit is configured to generate a first control signal coupled to a first control terminal of the first switch, and the timing control circuit is configured to generate a second control signal coupled to a second control terminal of the second switch, wherein the first control signal and the second control signal are configured to turn on the first switch while the second switch is turned off, and the first control signal and the second control signal are configured to turn off the first switch while the second switch is turned on, wherein the first switch and the second switch are configured to be alternately turned on and off at the same switching frequency; a first sample and hold circuit coupled to the first node; as well as a second sample and hold circuit coupled to the second end of the coil, wherein the timing control circuit is further configured to generate a third control signal and a fourth control signal, wherein the third control signal enables the first sample and hold circuit to sample at the switching frequency; And the fourth control signal enables the second sample and hold circuit to perform sampling at the switching frequency. 2 . The power transmitter according to claim 1 , wherein there is a predetermined delay between the third control signal and the fourth control signal. 3 . The power transmitter of claim 2 , wherein the third control signal and the fourth control signal are synchronized with the first control signal and the second control signal. 4 . The power transmitter of claim 1 , wherein the third control signal is generated with a first predetermined delay from a first edge of the first control signal, and the fourth control signal is generated with a second predetermined delay from a second edge of the second control signal. 5 . The power transmitter of claim 4 , wherein the first predetermined delay has a negative value and the second predetermined delay has a positive value. 6 . The power transmitter according to claim 5 , wherein the first edge is a falling edge of the first control signal or a rising edge of the first control signal. 7 . The power transmitter according to claim 6 , wherein the second edge is a rising edge of the second control signal or a falling edge of the second control signal.

8. The power transmitter of claim 1 , wherein the power transmitter further comprises a capacitor coupled in series with the coil, wherein a resonant frequency of the power transmitter is determined by a capacitance of the capacitor and an inductance of the coil, wherein the resonant frequency is lower than the switching frequency.

9. The power transmitter of claim 1 , wherein the power transmitter further comprises: a first driver circuit coupled between a first output of the timing control circuit and the first control terminal of the first switch; as well as A second driver circuit is coupled between a second output of the timing control circuit and the second control terminal of the second switch.

10. The power transmitter of claim 1 , further comprising: a first filter coupled between the first node and the first sample and hold circuit; as well as A second filter is coupled between the second end of the coil and the second sample and hold circuit. The power transmitter of claim 10 , wherein the first filter and the second filter are low-pass filters. 12 . The power transmitter of claim 11 , further comprising a voltage divider coupled between the second filter and the second end of the coil.

13. A method of operating a power transmitter, the method comprising: generating a first control signal and a second control signal by a timing control circuit of the power transmitter; providing the first control signal and the second control signal to a first control terminal of a first switch and a second control terminal of a second switch, respectively, wherein the first control signal alternately switches the first switch on and off at a first switching frequency, wherein the second control signal alternately switches the second switch on and off at the first switching frequency, wherein the first switch and the second switch are connected at a first node, the first switch is coupled between the first node and electrical ground, and the second switch is coupled between a power supply and the first node; generating, by the timing control circuit, a third control signal and a fourth control signal, wherein the third control signal has a first predetermined delay from a first edge of the first control signal, and the fourth control signal has a second predetermined delay from a second edge of the second control signal; controlling the operation of a first sample and hold circuit using the third control signal, wherein an input of the first sample and hold circuit is coupled to the first node; as well as The operation of a second sample and hold circuit is controlled using the fourth control signal, wherein an input of the second sample and hold circuit is coupled to a second end of a coil, wherein a first end of the coil is coupled to the first node and a second end of the coil is coupled to electrical ground via a capacitor. 14 . The method of claim 13 , wherein the third control signal and the fourth control signal have a frequency equal to the first switching frequency, wherein the first predetermined delay has a negative value and the second predetermined delay has a positive value. The method according to claim 14 , wherein the first edge of the first control signal is a falling edge or a rising edge. The method according to claim 15 , wherein the second edge of the second control signal is a rising edge or a falling edge. 17 . The method of claim 14 , wherein a resonant frequency of an LC tank circuit including the coil and the capacitor is lower than the first switching frequency.

18. A power transmitter comprising: a first switch coupled between the first node and a reference voltage node; a second switch configured to be coupled between a power source and the first node; a coil and a capacitor coupled in series between the first node and the reference voltage node; a first sample and hold circuit, wherein an input of the first sample and hold circuit is coupled to the first node; as well as a timing control circuit configured to generate a first control signal, a second control signal, and a third control signal, wherein the first control signal, the second control signal, and the third control signal have the same frequency, wherein the first control signal is configured to alternately turn on and off the first switch, the second control signal is configured to alternately turn on and off the second switch, and the third control signal determines a sampling time of the first sample and hold circuit, wherein the third control signal has a first predetermined delay from a first edge of the first control signal.

19. The power transmitter of claim 18 , further comprising a second sample and hold circuit, wherein an input of the second sample and hold circuit is coupled to a second node between the coil and the capacitor, wherein the timing control circuit is further configured to generate a fourth control signal, the fourth control signal having the same frequency as the third control signal, wherein the fourth control signal determines a sampling time of the second sample and hold circuit, wherein the fourth control signal has a second predetermined delay from a second edge of the second control signal.

20. The power transmitter of claim 19, wherein the first predetermined delay has a negative value and the second predetermined delay has a positive value. 21 . The power transmitter of claim 20 , wherein each of the first edge and the second edge is a falling edge or a rising edge.

22. The power transmitter of claim 20, further comprising: a first amplitude shift keying demodulation circuit coupled to the output of the first sample and hold circuit; as well as A second amplitude shift keying demodulation circuit is coupled to the output of the second sample and hold circuit.

Images