Semiconductor device with separated active regions and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device with separated active regions and a manufacturing method thereof. The semiconductor device includes a substrate, a plurality of isolation islands, a source region and a drain region. The substrate includes a first active region, a second active region and a plurality of separated active regions. The plurality of separated active regions are connected to the first active region and the second active region, and are alternately arranged with the plurality of separated isolation islands. The gate structure includes a main body and a plurality of extensions. The main body is arranged on a portion of the first active region. A plurality of extensions are connected to the main body and extend from the main body to the plurality of isolation islands. The source region and the drain region are respectively located in the substrate of the first active region and the second active region.

Description

Technical Field

[0001] The invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] High-voltage (HV) transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), can function as high-voltage switches in high-voltage switching regulators and power management integrated circuits (ICs). To handle the high voltages involved in these and other high-voltage applications, it is desirable for the high-voltage transistors to have high breakdown voltage and low on-resistance. Summary of the invention

[0003] Embodiments of semiconductor devices having isolated active regions and methods of making such devices are described, wherein the semiconductor devices can achieve high breakdown voltage and low on-resistance.

[0004] An embodiment of the present invention provides a semiconductor device, comprising a substrate, a plurality of isolation islands, a gate structure, a source region and a drain region. The substrate comprises a first active region, a second active region and a plurality of separated active regions. The plurality of separated active regions extend in a first direction and are arranged in a second direction, are located between the first active region and the second active region, and are connected to the first active region and the second active region respectively. A plurality of isolation islands are located in the substrate and are alternately arranged with the plurality of separated active regions in the second direction. A gate structure is located on the substrate. The gate structure comprises a main body and a plurality of extensions. The main body extends in the second direction and is arranged on a portion of the first active region. The plurality of extensions are connected to the main body, extend from the main body to the plurality of isolation islands in the first direction, and are alternately arranged with the plurality of separated active regions in the second direction. The source region is located in the substrate of the first active region. The drain region is located in the substrate of the second active region.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps. An isolation structure is formed in a substrate, the isolation structure comprising a plurality of isolation islands, the isolation structure defining a first active region, a second active region, and a plurality of separated active regions between the first active region and the second active region in the substrate, wherein the plurality of separated active regions extend in a first direction, are respectively connected to the first active region and the second active region, and are alternately arranged with the plurality of isolation islands in the second direction. A gate structure is formed on the substrate. The gate structure comprises a main body and a plurality of extensions. The main body extends in the second direction and is arranged on a portion of the first active region. The plurality of extensions are connected to the main body, extend from the main body toward the first direction to the plurality of isolation islands, and are alternately arranged with the plurality of separated active regions in the second direction. A source region is formed in the substrate of the first active region. A drain region is formed in the substrate of the second active region.

[0006] The semiconductor device according to the embodiment of the present invention can achieve high breakdown voltage and low on-resistance.

[0007] The details of one or more disclosed embodiments are set forth in the accompanying drawings and the description below. Other features, embodiments, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A top view of a semiconductor device having separated active regions is shown in accordance with one or more embodiments.

[0009] Figure 1B Show Figure 1A Enlarged view of region R in the middle.

[0010] Figure 2A for Figure 1B Sectional view of tangent line II'.

[0011] Figure 2B for Figure 1B Sectional view of the tangent line II-II'.

[0012] FIG. 3A to FIG. 3E is a top view illustrating an exemplary manufacturing method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0013] FIG. 4A to FIG. 4E It is shown that FIG. 3A to FIG. 3E Sectional view along the median line III-III'.

[0014] Figure 4F It is shown that Figure 3E Section view along the median line IV-IV'.

[0015] Figure 5 It is a drain electrical property curve diagram of the present invention and a known semiconductor device.

[0016] [Description of Reference Symbols] 10: semiconductor device

[0017] 100: Substrate

[0018] 102: n-type deep well region

[0019] 104: Isolation Structure

[0020] 106: n-type doped drift region

[0021] 108: n-type well region

[0022] 109: Drift Zone

[0023] 110: p-well region

[0024] 112: Gate dielectric layer

[0025] 114: Gate electrode

[0026] 116: Gap wall

[0027] 118: Gate structure

[0028] 118L: Long

[0029] 118S: Short section

[0030] 120: n+ drain region

[0031] 122: n+ source region

[0032] 124: p+ body contact region

[0033] 126: Blocking Department

[0034] 130: Metal silicide layer

[0035] A1: First active area

[0036] A2: Second active area

[0037] AA: Active Area

[0038] D: Horizontal distance

[0039] D1: First direction

[0040] D2: Second direction

[0041] IOI: Isolation Island

[0042] O1, O2: Open

[0043] P1: Main body

[0044] P2: Extension

[0045] R: Region

[0046] SSA: Separation of active areas C1, C1', C2, C2', C3, C4: Curve

[0047] L1, L2, L3, L4: Length

[0048] II', II-II', III-III, IV-IV': tangent DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0050] An embodiment of the present invention provides a semiconductor device. The semiconductor device is, for example, a high voltage transistor device with high breakdown voltage and low on-resistance. The high voltage transistor device has a separated active region for separating an isolation structure between a source region and a drain region into a plurality of isolated islands.

[0051] The technology disclosed herein can optimize the on-resistance and breakdown voltage of a high voltage transistor device without the need for an additional mask (e.g., a photoresist mask). The high voltage transistor device can be fabricated by a standard process, such as a triple well process, a bipolar-complementary metal-oxide-semiconductor (CMOS)-double-diffusedmetal-oxide-semiconductor (DMOS), BCD process, a non-epitaxially-grown layer (non-EPI) process with a triple well process or a twin well process, and / or a single poly or double poly process. The high voltage transistor device can be a low-side switch metal oxide semiconductor (MOS) transistor, a high-side switch MOS transistor, a fully isolated switch MOS transistor, or a high voltage low surface field (RESURF) LDMOS transistor. The high voltage transistor may be an n-channel metal oxide semiconductor (NMOS) transistor, a p-channel metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor (CMOS) transistor. The technology may be applied to any suitable structure, any suitable process, and / or any suitable operating voltage. In addition to high voltage devices, the technology may also be used for direct current (DC) applications and / or low voltage applications.

[0052] The technology can be applied to any suitable transistor device in any suitable substrate. For illustrative purposes only, some examples in the following description are related to an n-channel laterally diffused (LD) metal oxide semiconductor field effect transistor (or LDMOS transistor) as a type of high voltage transistor. The n-channel LDMOS transistor can be located in a p-type semiconductor substrate, or alternatively, can be located in a p-type epitaxial layer formed on a substrate. Some examples in the following description are related to the production of a single transistor by a manufacturing process, or the formation of multiple transistors at the same time. In addition, in the following description, the p-type can be, for example, doped with boron or boron fluoride (BF2) dopants; the n-type can be, for example, doped with phosphorus or arsenic dopants.

[0053] Figure 1A A top view of an exemplary semiconductor device having separated active regions according to one or more embodiments is shown. Figure 1B Show Figure 1A Enlarged view of region R in the middle. Figure 2A for Figure 1B Sectional view of tangent line II'. Figure 2B for Figure 1B The cross-sectional view of the tangent line II-II'. Figure 1A The two high voltage (HV) transistor devices share a source region, however, the high voltage transistor device of the present invention is not limited thereto.

[0054] Please refer to Figure 1A , Figure 1B , Figure 2A and Figure 2B The semiconductor device 10 is, for example, a high voltage transistor device. The high voltage transistor device may be an LDNMOS transistor or a drain extended NMOS transistor. The semiconductor device 10 is formed in a p-type semiconductor substrate 100. The p-type semiconductor substrate 100 may be a p-type silicon wafer or a p-type epitaxial layer formed on a substrate. The p-type semiconductor substrate 100 may have 10 14 cm -3 Up to 10 16 cm -3 The p-type doping concentration.

[0055] In one embodiment, the semiconductor device 10 is configured to be completely isolated from the substrate 100 so that a bias voltage can be applied independently. The semiconductor device 10 may include an n-type doped buried layer (NBL) 102 and an n-type well region 108. The n-type deep well region 102 is also called an n-type doped buried layer. The n-type well region 108 is also called a first well region. The n-type deep well region 102 is configured to provide vertical isolation; the n-type well region 108 is configured to provide lateral isolation. In one embodiment, the n-type deep well region 102 may have 10 16 cm -3 Up to 10 19 cm -3 The high voltage n-type well region 108 may have an n-type doping concentration of 10 15 cm -3 Up to 10 18 cm -3 The n-type doping concentration.

[0056] An isolation structure 104 is formed in the p-type semiconductor substrate 100. The isolation structure 104 electrically isolates the semiconductor device 10 from other transistor devices and devices formed on the p-type semiconductor substrate 100. The isolation structure 104 is, for example, a shallow trench isolation (STI) or a thick field oxide (FOX) layer. The isolation structure 104 may include a single layer or multiple layers. The material of the isolation structure 104 includes silicon oxide, silicon nitride, or a combination thereof. The isolation structure 104 defines an active area AA in the substrate 100. The active area AA includes a first active area A1, a second active area A2, and a plurality of separated active areas SSA located between the first active area A1 and the second active area A2. The first active area A1 and the second active area A2 extend along the second direction D2 and are arranged in parallel along the first direction D1. The plurality of separated active areas SSA extend along the first direction D1, connect the first active area A1 and the second active area A2, and are arranged along the second direction D2. In addition, the separated active area SSA also separates the isolation structure 104 between the first active area A1 and the second active area A2 into a plurality of isolation islands 101. The plurality of separated active areas SSA and the plurality of isolation islands 101 alternate with each other along the second direction D2. In some embodiments, the top views of the first active area A1, the second active area A2, the separated active area SSA, and the isolation islands 101 are, for example, rectangular. The length L1 in the first direction of the first active area A1 is, for example, greater than the length L2 in the first direction of the second active area A2.

[0057] In the semiconductor substrate 100, a p-type doping concentration (eg, 10 16 cm -3 Up to 10 18 cm -3 ) is implanted and diffused into a p-well region 110. The p-well region 110 is also called a second well region. The p-well region 110 partially overlaps with the first active region A1. A heavily doped p+ body contact region 124 (e.g., having 10 19 cm -3 Up to 10 21 cm -3 The p-type doping concentration) and the heavily doped n+ source region 122 (e.g., having 10 19 cm -3 Up to 10 21 cm -3The p+ body contact region 124 may be further from the gate structure 118 (described in detail below) than the n+ source region 122. The p-well region 110 may extend laterally beyond the p+ body contact region 124 and the n+ source region 122, and extend vertically below the p+ body contact region 124 and the n+ source region 122. The p+ body contact region 124 and the n+ source region 122 are in direct electrical contact with each other.

[0058] In the p-type substrate 100, a higher n-type doping concentration (e.g., 10 16 cm -3 Up to 10 18 cm -3 ) is implanted and diffused with an n-type doping drifting (NDD) region (or doped region) 106. The isolation island 101 is located in the n-type doped drift region 106. The n-type doped drift region 106 can extend laterally toward the gate structure 118, and partially overlap with the first active region A1, but is laterally separated from the p-well region 110. The n-type doped drift region 106 also extends toward the second active region A2, so that the separated active region SSA and the second active region A2 completely overlap with it. The second active region A2 of the n-type doped drift region 106 contains a heavily doped n+ drain region 120 (for example, having 10 19 cm -3 Up to 10 21 cm -3 The n+ drain region 120 may be more heavily doped than the n-type doped drift region 106 .

[0059] The gate structure 118 is disposed on the substrate 100 between the n+ source region 122 and the n+ drain region 120 .

[0060] The gate structure 118 includes a gate dielectric layer 112, a gate electrode 114, and a spacer 116. The gate dielectric layer 112 may include silicon oxide (SiO2) or a high dielectric constant dielectric material (e.g., a high dielectric constant greater than the dielectric constant (3.9) of silicon oxide (SiO2)). The gate electrode 114 partially covers the p-well region 110 and the n-type doped drift region 106. The gate electrode 114 is separated from the semiconductor substrate 100, the p-well region 110, and the n-type doped drift region 106 by the gate dielectric layer 112. The gate electrode 114 may include doped polysilicon (poly) disposed on the gate dielectric layer 112. The spacer 116 is located on the sidewall of the gate electrode 114. The spacer 116 may be a single layer or a multilayer, for example, including silicon oxide, silicon nitride, or a combination thereof.

[0061] Please refer to Figure 1B, the gate structure 118 is, for example, in a comb shape. The gate structure 118 covers a portion of the first active area A1 and a portion of the isolation structure 104. In some embodiments, the gate structure 118 includes a main body P1 and a plurality of extensions P2. The main body P1 extends in the second direction D2, covering a portion of the first active area A1, so that the first active areas A1 on both sides of the main body P1 are exposed. The extensions P2 extend in the first direction D1 and connect the main body P1. Each extension P2 covers a portion of the first active area A1 and a portion of the isolation island IOI. The plurality of extensions P2 and the plurality of separated active areas SSA are alternately arranged in the second direction D2.

[0062] On the other hand, the gate structure 118 includes a plurality of long portions 118L and a plurality of short portions 118S. The plurality of long portions 118L and the plurality of short portions 118S alternate with each other in the second direction D2. The long portion 118L has a length L3 in the first direction D1; the short portion 118S has a length L4 in the first direction D1. The length L4 is equal to the length of the main portion P1 in the first direction D1. The length L3 is equal to the sum of the length of the main portion P1 in the first direction D1 and the length of the extension portion P2 in the first direction D1.

[0063] Please refer to Figure 2A , one side of the short portion 118S of the gate structure 118 exposes the n+ source region 122 and the p+ body contact region 124. The short portion 118S covers a portion of the p-well region 110, the substrate 100, and the first portion of the n-type doped drift region 106. The surface of the p-well region 110 and the substrate 100 covered by the short portion 118S serves as a channel region. One side of the short portion 118S of the gate structure 118 exposes the second portion of the n-type doped drift region 106 and the n+ drain region 120. There is no isolation structure in the n-type doped drift region 106, which can provide a low on-resistance for the semiconductor device 10.

[0064] The gate electrode 114 of the short portion 118S adjoins the n+ source region 122 at one end and extends over the first portion of the n-type doped drift region 106 at the other end. The second portion of the n-type doped drift region 106 (from the other end of the gate electrode 114 to the n+ drain region 120) adjoins the first portion of the n-type doped drift region 106 and has a lateral distance D. The second portion of the n-type doped drift region 106 can be regarded as a drift region 109 for charge carriers to move from the n+ source region 122 to the n+ drain region 120. The on-resistance of the semiconductor device 10 is associated with the doping concentration of the drift region 109 (i.e., the concentration of the n-type doped drift region 106) and the lateral distance D. The higher the doping concentration of the drift region 109, the lower the on-resistance; the longer the lateral distance D, the higher the on-resistance.

[0065] Please refer to Figure 2B, one side of the long portion 118L of the gate structure 118 exposes the n+ source region 122 and the p+ body contact region 124. The long portion 118L covers a portion of the p-well region 110, the substrate 100, and a portion of the isolation island 101. The p-well region 110 and the surface of the substrate 100 covered by the long portion 118L serve as a channel region. One side of the long portion 118L of the gate structure 118 exposes another portion of the isolation island 101 and the n+ drain region 120. The configuration of the isolation island 101 can provide a high breakdown voltage for the semiconductor device 10.

[0066] The blocking portion (PRO) 126 is formed on the substrate 100, covering a plurality of separated active regions SSA and a plurality of isolation islands IOI, exposing the first active region A1 and the second active region A2. In some embodiments, the blocking portion 126 covers the n-type doped drift region 106 and the isolation islands IOI, exposing the p+ body contact region 124, the n+ source region 122, the gate structure 118, and the n+ drain region 120. In other embodiments, the blocking portion 126 also covers a portion of the long portion 118L and a portion of the short portion 118S of a portion of the gate structure 118. The blocking portion 126 can be a single layer or a multilayer. The material of the blocking portion 126 includes silicon oxide, silicon nitride, or a combination thereof.

[0067] The metal silicide layer 130 is formed on the p+ body contact region 124, the n+ source region 122, the gate structure 118, and the n+ drain region 120 that are not covered by the barrier 126. The metal silicide layer 130 may include cobalt silicide, titanium nitride / titanium silicide, titanium nitride / titanium / cobalt silicide, polycrystalline cobalt silicide, or titanium nitride / titanium polycrystalline silicide, titanium nitride / titanium / cobalt polycrystalline silicide.

[0068] The embodiment of the present invention can optimize the on-resistance and breakdown voltage of the semiconductor device 10 by changing and designing the length and width of the separated active region SSA and the plurality of isolation islands IOI and the doping concentration of the drift region 109. For example, increasing the doping concentration of the drift region 109, shortening the length of the separated active region SSA in the first direction D1, or increasing the length ratio of the separated active region SSA and the isolation island IOI in the second direction D2 can reduce the on-resistance of the semiconductor device 10. Conversely, the breakdown voltage of the semiconductor device 10 can be increased.

[0069] FIG. 3A to FIG. 3E is a top view illustrating an exemplary manufacturing method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4A to FIG. 4E It is shown that FIG. 3A to FIG. 3E Sectional view along the median line III-III'. Figure 4F It is shown that Figure 3E Section view along the median line IV-IV'.

[0070] Please refer to Figure 3A and Figure 4A , an n-type deep well region 102 is formed in the substrate 100. The substrate 100 is, for example, a p-type semiconductor substrate, such as a p-type silicon substrate. The n-type deep well region 102 is formed by, for example, forming an ion implantation mask on the substrate 100, and then performing an ion implantation process to implant n-type dopants into the substrate 100. Thereafter, the implantation mask is removed.

[0071] Next, an isolation structure 104 is formed in the substrate 100. The isolation structure 104 includes a plurality of isolation islands 101. The method for forming the isolation structure 104 is, for example, a shallow trench isolation method. The steps of the shallow trench isolation method are as follows. A plurality of trenches are formed in the substrate 100 by photolithography and etching processes. Afterwards, an insulating material is formed on the substrate 100 and in the trenches. Then, a planarization process is performed by chemical mechanical polishing or back etching to remove the insulating material on the substrate 100. The insulating material includes silicon oxide, silicon nitride or a combination thereof formed by chemical vapor deposition or thermal oxidation. The isolation structure 104 defines an active area AA in the substrate 100. The active area AA includes a first active area A1, two second active areas A2 and a plurality of separated active areas SSA. The first active area A1 is located between the two second active areas A2. The separated active areas SSA are respectively located between the first active area A1 and the second active area A2.

[0072] Please refer to Figure 3B and Figure 4B , an n-type doped drift region 106, an n-type well region 108, and a p-well region 110 are formed in the substrate 100 above the n-type deep well region 102. The doping concentration of the n-type well region 108 may be the same as, slightly higher than, or slightly lower than the doping concentration of the n-type deep well region 102. An implantation mask may be formed on the substrate 100 for the n-type well region 108 and the p-well region 110, and then an ion implantation process is performed to implant n-type dopants and p-type dopants into the substrate 100, respectively. Thereafter, the implantation mask is removed. The n-type well region 108 partially overlaps with the second active region A2, a plurality of separated active regions SSA, and the isolation structure 104. The n-type well region 108 may be in a ring shape, and the bottom surface of the n-type well region 108 is deeper than the bottom surface of the isolation structure 104, and is adjacent to the top surface of the n-type deep well region 102. Therefore, the n-type well region 108 and the n-type deep well region 102 may enclose an independent region, and the transistor device formed in the independent region may be completely isolated from the substrate 100 so that a bias voltage can be applied independently.

[0073] Please refer to Figure 3B and Figure 4B, the doping concentration of the n-type doped drift region 106 can be slightly higher than the doping concentration of the n-type well region 108. The n-type doped drift region 106 can be formed with an implantation mask on the substrate 100, and then an ion implantation process is performed to implant n-type dopants into the substrate 100. Afterwards, the implantation mask is removed. The implantation mask has two openings O1. The opening O1 exposes part of the first active region A1, and exposes a plurality of separated active regions SSA, a plurality of isolation islands IOI, two second active regions A2, and a portion of the isolation structure 104 adjacent to the second active region A2. Therefore, the n-type doped drift region 106 partially overlaps with the first active region A1, completely overlaps with the plurality of separated active regions SSA, a plurality of isolation islands IOI, and the two second active regions A2, and partially overlaps with the n-type well region 108 and the isolation structure 104. The n-type doped drift region 106 extends vertically downward from the surface of the substrate 100 until its bottom surface is adjacent to the top surface of the n-type deep well region 102 (such as Figure 3B The n-type doped drift region 106 surrounds and covers the plurality of isolation islands 101.

[0074] The doping concentration of the p-well region 110 is slightly higher than the doping concentration of the substrate 100. An implantation mask can be formed on the substrate 100 for the p-well region 110, and then an ion implantation process is performed to implant n-type dopants into the substrate 100. Afterwards, the implantation mask is removed. The implantation mask has an opening O2. The opening O2 exposes part of the central area of ​​the first active region A1. The n-type doped drift region 106 partially overlaps with the first active region A1 and is laterally separated from the p-well region 110. The p-well region 110 extends vertically downward from the surface of the substrate 100, but its bottom surface is not adjacent to the top surface of the n-type deep well region 102, but is separated vertically. For the sake of simplicity in the drawing, Figure 3C and Figure 3D The p-well region 110 and the opening O2 will no longer be shown.

[0075] Please refer to Figure 3C and Figure 4C , two gate structures 118 are formed on the substrate 100. The gate structure 118 includes a gate dielectric layer 112, a gate electrode 114, and a spacer 116. The gate structure 118 is formed by, for example, forming a gate dielectric material layer and a gate electrode material layer on the substrate 100, and then patterning the gate dielectric material layer and the gate electrode material layer through photolithography and etching processes. After that, a spacer material layer is formed, and then an anisotropic etching process is performed on the spacer material layer. The gate structure 118 is, for example, in a comb shape (such as Figure 3C118). The gate structure 118 includes a plurality of long portions 118L and a plurality of short portions 118S alternating with each other in the second direction D2. The plurality of long portions 118L and the plurality of short portions 118S of the gate structure 118 cover a portion of the p-well region 110, a portion of the n-type doped drift region 106, and a portion of the plurality of isolation islands 101. A portion of the isolation island 101 is covered by the long portion 118L, and another portion of the isolation island 101 is exposed by the long portion 118L of the gate structure 118. The isolation island 101 is not covered by the short portion 118S of the gate structure 118.

[0076] Please refer to Figure 3C and Figure 4C , a p+ body contact region 124 and an n+ source region 122 are formed in the first active region A1, and an n+ drain region 120 is formed in the two second active regions A2. The doping concentration of the p+ body contact region 124 is higher than the doping concentration of the p-well region 110. The doping concentrations of the n+ source region 122 and the n+ drain region 120 are higher than the doping concentration of the n-type doped drift region 106. The p+ body contact region 124, the n+ source region 122, and the n+ drain region 120 can be respectively formed on the substrate 100 with an implantation mask, and then an ion implantation process is performed to implant p-type or n-type dopants into the substrate 100. Thereafter, the implantation mask is removed. The n+ source region 122 and the n+ drain region 120 can be formed at the same time.

[0077] Please refer to Figure 3D and Figure 4D , a blocking portion (PRO) 126 is formed on the substrate 100 to cover a portion of the gate structure 118, the n-type doped drift regions 106 in the plurality of separated active regions SSA, and the plurality of isolation islands 101, and expose another portion of the gate structure 118, the p+ body contact region 124 and the n+ source region 122 in the first active region A1, and the n+ drain region 120 in the second active region A2. In some embodiments, the blocking portion 126 does not cover the gate electrode 114 (not shown) of the gate structure 118.

[0078] Please refer to Figure 3E , Figure 4E and Figure 4F , a self-aligned silicidation process is performed to form a metal silicide layer 130 on the gate electrode 114 , the p+ body contact region 124 , the n+ source region 122 and the n+ drain region 120 .

[0079] Figure 5 It is a drain electrical property curve diagram of the present invention and a known semiconductor device.

[0080] Please refer to Figure 5The semiconductor device of the present invention has smooth drain saturation current curves C1, C2, C3, and C4. The saturation current curves C1' and C2' of conventional semiconductor devices are quite steep. Figure 5 It can be seen that, compared with the prior art, the semiconductor device of the present invention has a smoother saturation current curve.

[0081] In the embodiment of the present invention, by forming a plurality of separated active areas SSA connecting the first active area and the second active area, the current at the short portion of the gate electrode can flow through the drift region of low resistance in the separated active area SSA in a shorter path, thereby reducing the on-resistance of the transistor device. According to experiments, the on-resistance of the known semiconductor device is about 14 ohm-square millimeter, and the on-resistance of the semiconductor device of the present invention can be reduced to 9.4 ohm-square millimeter.

[0082] In addition, by disposing a plurality of isolation islands IOI between the first active region and the second active region, the transistor device can be maintained at a predetermined breakdown voltage.

[0083] In addition, the long portion of the gate electrode extends onto a plurality of isolation islands IOI, and can function as a partial field plate to make the electric field uniform.

[0084] Therefore, the embodiment of the present invention can optimize the on-resistance and breakdown voltage of the transistor device by separating the active area SSA and the length and width of multiple isolation islands IOI, the length of the gate electrode, and the change and design of the doping concentration of the drift region without adding additional masks and processes.

[0085] Although the present invention may describe many details, however, these details should not be understood as limitations on the claims of the claimed invention or the content that may be claimed, but only as descriptions of the features that are unique to a particular embodiment. Certain features of the present invention described in the context of each separate embodiment may also be implemented in a single embodiment in combination. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although the above may describe each feature as working in certain combinations and even initially claimed to be so, one or more features in the claimed combination may be removed from the combination in some cases, and the claimed combination may become a sub-combination or a variation of the sub-combination. Similarly, although the operations are depicted in a particular order in the drawings, this should not be understood as a requirement that these operations should be performed in the particular order shown or in a sequential order, or that all described operations should be performed to achieve the desired result.

[0086] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device comprising: Substrate, comprising: The first active region; a second active region; and A plurality of separated active regions extending in the first direction and arranged in the second direction, located between the first active region and the second active region, and respectively connected to the first active region and the second active region; a plurality of isolation islands, located in the substrate and arranged alternately with the plurality of separated active regions in the second direction; A gate structure is located on the substrate, and the gate structure includes: a main body portion extending in the second direction and disposed on a portion of the first active area; A plurality of extension portions connected to the main body portion, extending from the main body portion in the first direction to the plurality of isolation islands, and arranged alternately with the plurality of separated active regions in the second direction; a source region located in the substrate of the first active region; and A drain region is located in the substrate of the second active region. The semiconductor device according to claim 1 , wherein the gate structure is in a comb shape.

3. The semiconductor device according to claim 1, wherein the gate structure comprises a plurality of long portions and a plurality of short portions alternating with each other, the plurality of long portions and a plurality of separated active regions alternating with each other and covering a portion of the plurality of isolation islands, and the plurality of short portions not covering a portion of the plurality of isolation islands.

4. The semiconductor device according to claim 1, further comprising: A doped region is located in the substrate, wherein the plurality of isolation islands and the drain region are located in the doped region, and the gate structure covers a portion of the doped region.

5. The semiconductor device according to claim 4, further comprising: A first well region is located in the substrate, wherein the first well region partially overlaps with the doped region, and the drain region and part of the plurality of isolation islands are located in the first well region; A second well region is located in the substrate, wherein the second well region and the first well region have different conductivity types, and the source region is located in the second well region, and the main body of the gate structure covers a portion of the second well region; as well as The doped buried layer is located in the substrate, extends from below the first well region to below the second well region, and is electrically connected to the first well region.

6. The semiconductor device according to claim 1, further comprising: a barrier layer covering the plurality of separated active regions between the main body of the gate structure and the drain region, and covering a portion of the substrate of the first active region; as well as The metal silicide layer is located on the source region, the drain region and the gate structure.

7. A method for manufacturing a semiconductor device, comprising: An isolation structure is formed in a substrate, wherein the isolation structure includes a plurality of isolation islands, and the isolation structure defines a first active region, a second active region, and a plurality of separated active regions between the first active region and the second active region in the substrate, wherein the plurality of separated active regions extend in a first direction, are respectively connected to the first active region and the second active region, and are alternately arranged with the plurality of isolation islands in a second direction; A gate structure is formed on the substrate, wherein the gate structure comprises: a main body portion extending in the second direction and disposed on a portion of the first active area; A plurality of extension portions connected to the main body portion, extending from the main body portion in the first direction to the plurality of isolation islands, and arranged alternately with the plurality of separated active regions in the second direction; forming a source region in the substrate of the first active region; and A drain region is formed in the substrate in the second active region. 8 . The method for manufacturing a semiconductor device according to claim 7 , further comprising forming a doped region in the substrate, wherein the plurality of isolation islands and the drain region are located in the doped region, and the gate structure covers a portion of the doped region.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising: forming a doped buried layer in the substrate; forming a first well region in the substrate, wherein the first well region is connected to the doped buried layer and partially overlaps with the doped region, and the drain region is located in the first well region; A second well region is formed in the substrate, wherein the second well region and the first well region have different conductivity types, and the source region is located in the second well region, and the main body of the gate structure covers a portion of the second well region.

10. The method for manufacturing a semiconductor device according to claim 7, further comprising: forming a barrier layer on the substrate to cover the plurality of separated active regions and a portion of the first active region on the substrate between the main portion of the gate structure and the drain region; as well as A metal silicide layer is formed on the source region, the drain region and the main body of the gate structure.

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