Control Circuit for Inverter

Abstract

The present invention discloses a control circuit for an inverter, which comprises: an input acquisition circuit including M switches under test, a plurality of resistors, and M signal detection output terminals; a priority encoder including M encoding input terminals respectively coupled to the M signal detection output terminals and N encoding output terminals, wherein the priority encoder assigns a unique and corresponding N-bit code to each encoding input terminal, the encoding input terminals have priorities, and when the encoding input terminal with a higher priority is at an effective level, the encoding output terminal outputs the N-bit code corresponding to the encoding input terminal with a higher priority; and a digital signal processor, which knows the on and / or off states of the switches under test by receiving the N-bit codes output by the priority encoder. In this way, the resources of the digital signal processor DSP of the inverter are released, and the IO interfaces of the digital signal processor DSP of the inverter are saved.

Description

Technical Field

[0001] The present invention relates to the field of inverters, and more particularly to a control circuit for an inverter.

Background Art

[0002] The development of an inverter needs to comply with certain safety specifications. One of the safety specifications is as follows: for the inputs from multiple predetermined buttons of the inverter, it is required that the inverter makes corresponding responses. In the prior art, in order to comply with this safety specification, the digital signal processor (DSP) of the inverter directly receives the inputs of these predetermined buttons, which requires integrating multiple analog-to-digital converters inside the DSP, with complex logic, and wasting the resources of the DSP and the I / O (input / output) interfaces.

[0003] Therefore, it is necessary to provide a new improved solution to overcome the above problems.

Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a control circuit for an inverter, which has simple logic, low cost, releases the resources of the digital signal processor (DSP) of the inverter, and saves the I / O interfaces of the digital signal processor (DSP) of the inverter.

[0005] To solve the above problems, according to one aspect of the present invention, the present invention provides a control circuit for an inverter, which includes: an input acquisition circuit, which includes M inspected switches, a plurality of resistors, and M signal detection output terminals, wherein the signal on one signal detection output terminal can reflect whether the corresponding inspected switch is turned on; a priority encoder, which includes M encoding input terminals respectively coupled to the M signal detection output terminals and N encoding output terminals, wherein M is greater than N, and both M and N are positive integers greater than or equal to 1, and the priority encoder assigns a unique corresponding N-bit code to each encoding input terminal, and the encoding input terminals have priorities. When the encoding input terminal with a higher priority is at an effective level, the encoding output terminals output the N-bit code corresponding to the encoding input terminal with a higher priority; a digital signal processor, which has N input terminals respectively connected to the N encoding output terminals, and learns the on and / or off states of the inspected switches by receiving the N-bit codes output by the priority encoder.

[0006] Compared with the prior art, in the present invention, the cooperation of the input acquisition circuit and the priority encoder is used to realize the recognition and detection of the actions of the input buttons, with simple logic, low cost, releasing the resources of the digital signal processor (DSP) of the inverter, and saving the I / O interfaces of the digital signal processor (DSP) of the inverter.

[0007] Regarding other objects, features, and advantages of the present invention, they will be described in detail in the specific embodiments below with reference to the accompanying drawings.

Description of the Drawings

[0008] The present invention will be more easily understood in conjunction with the accompanying drawings and the following detailed description, where the same reference numerals correspond to the same structural components, and:

[0009] Figure 1 is a schematic structural diagram of a control circuit for an inverter in an embodiment of the present invention;

[0010] Figure 2 is Figure 1 a circuit diagram of an input acquisition circuit in an embodiment of

[0011] Figure 3 is Figure 1 a schematic structural diagram of a priority encoder in

[0012] Figure 4 is Figure 3 a truth table of a priority encoder in

[0013] Figure 5 is Figure 3 a function table of each port of a priority encoder in

[0014] Figure 6 is a circuit diagram of a level conversion circuit in the present invention.

Detailed Embodiments

[0015] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0016] As used herein, "an embodiment" or "embodiments" means that the specific features, structures, or characteristics related to the embodiments can be included in at least one implementation of the present invention. The phrase "in an embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it have to be a separate or alternative embodiment that is mutually exclusive with other embodiments. The terms "a plurality" and "several" in the present invention mean two or more. The term "and / or" in the present invention means "and" or "or".

[0017] The present invention provides a control circuit for an inverter, which has a simple logic, low cost, releases the resources of the digital signal processor (DSP) of the inverter, and saves the I / O interface of the digital signal processor (DSP) of the inverter.

[0018] Figure 1 is a schematic structural diagram of a control circuit 100 for an inverter in an embodiment of the present invention. As shown in Figure 1As shown, the control circuit 100 includes an input acquisition circuit 110, a priority encoder 120, and a digital signal processor 130.

[0019] The input acquisition circuit 110 includes M switches under test, a plurality of resistors, and M signal detection output terminals. The signal on one of the signal detection output terminals can reflect whether the corresponding switch under test is conducting. The priority encoder 120 includes M encoding input terminals respectively coupled to the M signal detection output terminals and N encoding output terminals, where M is greater than N, and both M and N are positive integers greater than or equal to 1. The priority encoder assigns a unique and corresponding N-bit code to each encoding input terminal. The encoding input terminals have priorities. When the encoding input terminal with a higher priority is at an effective level, the encoding output terminals output the N-bit code corresponding to the encoding input terminal with the higher priority. The digital signal processor 130 has N input terminals respectively connected to the N encoding output terminals, and learns the on and / or off states of the switches under test by receiving the N-bit codes output by the priority encoder. Herein, the effective level can be a low level or a high level, and the effective level is set as needed. When all the encoding input terminals are at an invalid level, the priority encoder 120 outputs a predetermined N-bit code. In the present invention, the priority encoder 120 is sometimes simply referred to as the encoder.

[0020] Since the digital signal processor 130 does not directly detect whether the external switches under test are on or off, but the input acquisition circuit 110 and the priority encoder 120 cooperate to acquire the detection signals, this saves the resources of the digital signal processor 130 and saves the IO (input / output) interfaces of the inverter DSP (digital signal processor) chips. At the same time, the structure of the priority encoder 120 is very simple. The signals output by the input acquisition circuit 110 can be directly recognized by the priority encoder 120. The input acquisition circuit 110 does not have an analog-to-digital converter, and only by connecting resistors, the signal acquisition function can be realized, and the cost is very low.

[0021] After the digital signal processor 130 knows which switch under test is conducting, the digital signal processor 130 can output corresponding instructions to respond to the conduction of this switch under test. The content about how to make a response and what kind of response to make is not within the scope of discussion of the present invention, and it can be implemented by using various existing technologies. The present invention focuses on how the digital signal processor 130 can learn which switch under test is triggered and conducting in a simpler, more reliable, and optimized scheme.

[0022] Figure 2 For Figure 1 the circuit diagram of the input acquisition circuit 110 in one embodiment. As Figure 2As shown, the input acquisition circuit 110 includes:

[0023] A plurality of switches to be tested S5, S6, S7, S8, S9, S0;

[0024] Resistors R1, R2, R3, R4, R5, R6,

[0025] Signal detection output terminals DRM1 / 5, DRM2 / 6, DRM3 / 7, DRM4 / 8, COM LOAD / 0-1, COM LOAD / 0-2;

[0026] A voltage comparator LM2903;

[0027] The power supply terminal is connected to the signal detection output terminal DRM1 / 5 through the resistor R5, and the signal detection output terminal DRM1 / 5 is grounded through the switch to be tested S5;

[0028] The power supply terminal is connected to the signal detection output terminal DRM2 / 6 through the resistor R4, and the signal detection output terminal DRM2 / 6 is grounded through the switch to be tested S6;

[0029] The power supply terminal is connected to the signal detection output terminal DRM3 / 7 through the resistor R3, and the signal detection output terminal DRM3 / 7 is grounded through the switch to be tested S7;

[0030] The power supply terminal is connected to the signal detection output terminal DRM4 / 8 through the resistor R2, and the signal detection output terminal DRM4 / 8 is grounded through the switch to be tested S8;

[0031] The power supply terminal is connected to the signal detection output terminal COM LOAD / 0-1 through the resistor R1, and the signal detection output terminal COM LOAD / 0-1 is grounded through the switch to be tested S9 and the resistor R6 in sequence;

[0032] The switch to be tested S0 is in parallel with the resistor R6;

[0033] The connection terminal of the resistor R1 and the switch to be tested S9 is also denoted as the connection terminal COM LOAD / 0. The connection terminal COM LOAD / 0 is connected to the first input terminal of the voltage comparator LM2903. The second input terminal of the voltage comparator is a predetermined reference voltage REF. The output terminal of the voltage comparator LM2903 is the signal detection output terminal COM LOAD / 0-2.

[0034] Continue to refer to Figure 2, the input acquisition circuit further includes control switches S1 - S4. The signal detection output terminal DRM1 / 5 is grounded through the control switch S1 and the resistor R6 in sequence, the signal detection output terminal DRM2 / 6 is grounded through the control switch S2 and the resistor R6 in sequence; the signal detection output terminal DRM3 / 7 is grounded through the control switch S3 and the resistor R6 in sequence; the signal detection output terminal DRM4 / 8 is grounded through the control switch S4 and the resistor R6 in sequence.

[0035] It can be seen that at this time M = 6. In one embodiment, R1 = 3.7K, R2 = 200K, R3 = 200K, R4 = 200K, R5 = 200K, R6 = 15K. The predetermined reference voltage can be 4V. When the voltage at the first input terminal of the voltage comparator LM2903 is lower than 4V, a high level is output, that is, COM LOAD / 0 - 2 is at a high level. At this time, it indicates that S9 is conducting and working normally. When the voltage at the first input terminal of the voltage comparator LM2903 is higher than 4V, a low level is output, that is, COM LOAD / 0 - 2 is at a low level. At this time, it indicates that S9 is disconnected. The signals of the signal detection output terminals DRM1 / 5, DRM2 / 6, DRM3 / 7, DRM4 / 8, COM LOAD / 0 - 1, and COMLOAD / 0 - 2 are respectively used to reflect the conduction and disconnection of the switches under test S5, S6, S7, S8, S0, and S9.

[0036] Figure 3 is Figure 1 the schematic structural diagram of the priority encoder 120 in Figure 4 is Figure 3 the truth table of the priority encoder 120 in Figure 5 is Figure 3 the function table of each port of the priority encoder in Figure 3-5 As shown, the encoding input terminals 1 - 6 of the priority encoder 120 are respectively connected to the signal detection output terminals DRM1 / 5, DRM2 / 6, DRM3 / 7, DRM4 / 8, COM LOAD / 0 - 1, and COM LOAD / 0 - 2. Among them, the priorities of the encoding input terminals 1 - 6 increase in sequence, the priority of the encoding input terminal 6 is the highest, and the priority of the encoding input terminal 1 is the lowest. At this time, N is 3, and the N encoding output terminals of the priority encoder are respectively denoted as A0, A1, A2, and they are respectively coupled to the three input terminals OP1, OP2, and OP3 of the digital signal processor. It can be seen that the priorities of the switches under test S5, S6, S7, S8, S0, and S9 increase from low to high.

[0037] In some embodiments, the high level of the signal output by the priority encoder 120 is 5V, while the high level of the signal received by the digital signal processor 130 is 3.3V, and the two do not match. To solve this problem, the control circuit 100 further includes a level conversion circuit. The encoding output terminal of the priority encoder 120 is connected to the input terminal of the digital signal processor 130 through the level conversion circuit, and the level conversion circuit converts the 5V level signal into a 3.3V level signal. Figure 6 This is the circuit diagram of the level conversion circuit in the present invention. The level conversion circuit includes resistors R41, R42, R43 and a switching transistor M1, and their connection relationship is as Figure 5 .

[0038] Please refer to Figure 2 , a plurality of switches under test S5, S6, S7, S8, S9, S0, and control switches S1 - S4 are respectively marked as S5DRM5, S6 DRM6, S7 DRM7, S8 DRM8, etc., and are sometimes referred to as DRM5(S5), DRM6(S6), DRM7(S7), DRM8(S8), etc. in the following text.

[0039] Next, the specific principle of the present invention will be introduced in combination with some specific parameters.

[0040] The following classification is for different states of the switches under test DRM5 - DRM9(S5 - S9) and the switch under test DRM0(S0), and is divided into two cases: normal operation and abnormal operation:

[0041] 1: Normal operation is when the switch under test DRM9(S9) is closed and DRM0(S0) is open. The following is the change of the DRM1 / 5 level in the state of DRM5(S5 closed), as shown in the following table:

[0042]

[0043] Therefore, the signal detection output terminal DRM1 / 5 only needs to judge two states of 0V and greater than 4V to identify whether DRM5(S5) is closed or open. Similarly, the signal detection output terminals DRM2 / 6, DRM3 / 7, and DRM4 / 8 all need to judge two states of 0V and greater than 4V.

[0044] 2: During abnormal operation, DRM9(S9) is open and DRM0(S0) is closed. For the level of COM LOAD / 0, the following 3 levels need to be simultaneously identified to judge the states of DRM0(S0) and DRM9(S9).

[0045] DRM9(S9) is closed and DRM0(S0) is open (this state does not need to be identified normally)

[0046] DRM9 (S9) is closed and DRM0 (S0) is closed

[0047] DRM9 (S9) is open and DRM0 (S0) is open

[0048] As shown in the following table

[0049]

[0050] According to the requirements of safety specifications, it is necessary to identify the open state of DRM9 (S9) and the closed state of DRM0 (S0). Therefore, it is necessary to identify the levels at three states of the signal COM LOAD / 0, namely 0V, 4V, and 5V.

[0051] When DRM5 (S5) is closed, the state is 0V. For an encoder with active low, the output can recognize this low level. When DRM5 (S5) is open and any one of the switches DRM0 - DRM4 (S0 - S4) is closed simultaneously, the level is 4V or 5V. At this time, the state does not need to be recognized and the original state output is maintained. At this time, the encoder also defaults that the state is high level and does not perform recognition. The same principle applies to DRM6 - DRM8 (S6 - S8).

[0052] At this time, for the abnormal states of DRM0 (S0) or DRM9 (S9), since all three states of COM LOAD / 0 need to be recognized at this time, 2 input ports are used for the encoder to recognize these 3 states, such as interfaces 5 and 6 in the above "truth table".

[0053] When working normally, DRM0 (S0) is open and DRM9 (S9) is closed. At this time, the level of COM LOAD / 0 - 1 is 4V ± 0.1V and does not need to be recognized.

[0054] When DRM0 (S0) is closed and DRM9 (S9) is closed, the level of COM LOAD / 0 - 1 is 0V. The 5th port of the encoder corresponds to a low level and the encoder recognizes L. The output truth table is L H L;

[0055] When DRM0 (S0) is open and DRM9 (S9) is open, the level of COMLOAD / 0 - 1 is 5V. The state at this time is recognized by adding the 6th port with the highest priority of the encoder.

[0056] As Figure 2, the voltage comparator LM2903 is used to identify the voltage at the connection terminal COMLOAD / 0. When the voltage at COMLOAD / 0 is less than or equal to 4V, the output of the voltage comparator LM2903 is high. At this time, the 6th port of the encoder is at a high level of 5V and is not recognized. When the voltage is greater than 4V, the output of the voltage comparator LM2903 is low, and COM LOAD / 0 - 2 is set to a low level of 0V. At this time, the 6th port of the encoder 120 is L, and the recognized state is L L H. The switch state of DRM9(S9) is set to the highest priority level at this time.

[0057] Scheme verification

[0058] a. Verification of the output state of the priority encoder after DRM9(S9) is closed and then disconnected

[0059] According to the above principle, when DRM9(S9) is closed and the others are all disconnected, the outputs AO, A1, A2 are H, H, H.

[0060] Through actual testing, it is verified that the outputs AO, A1, A2 are all at a high level of 5V, meeting this logic. When DRM9(S9) is closed, by calculating the voltage - dividing resistors, the voltage of DRMO at this time is 4V, and the measured value is 3.94V. The encoder defaults to high - level effective and meets the requirements. When DRM9(S9) changes from closed to open, the outputs AO, A1, A2 are H, L, L;

[0061] b. Verification of the output state of the priority encoder after DRM9(S9) is closed and DRM0(S0) is disconnected

[0062] According to the principle, when DRM9(S9) is closed and the others are all disconnected, the outputs AO, A1, A2 are H, H, H.

[0063] Through actual testing, it is verified that the outputs AO, A1, A2 are all at a high level of 5V, meeting this logic. When DRM9(S9) is closed and DRM0(S0) changes from disconnected to connected, DRM0 pulls low, and the outputs AO, A1, A2 are L, H, L;

[0064] c. Verification of the output state of the priority encoder when DRM9(S9) is closed, DRM8(S8) is disconnected and then re - connected

[0065] According to the principle, when DRM9(S9) is closed and the others are all disconnected, the outputs AO, A1, A2 are H, H, H.

[0066] Through actual testing, it is verified that the outputs AO, A1, A2 are all at a high level of 5V. When DRM9(S9) is closed and DRM8(S8) changes from disconnected to connected, DRM8 pulls low, and the outputs AO, A1, A2 are L, H, H;

[0067] d. Verification of the output status of the priority encoder when DRM9 (S9) is closed, DRM7 (S7) is opened and then closed again

[0068] According to the principle, when DRM9 (S9) is closed and others are all open, the outputs AO, A1, and A2 are H, H, H.

[0069] Through actual tests, it is verified that the outputs AO, A1, and A2 are all at the high level of 5V. When DRM9 (S9) is closed and DRM7 (S7) changes from open to closed, DRM7 is set low, and the outputs AO, A1, and A2 are H, L, H;

[0070] e. Verification of the output status of the priority encoder when DRM9 (S9) is closed, DRM6 (S6) is opened and then closed again

[0071] According to the principle, when DRM9 (S9) is closed and others are all open, the outputs AO, A1, and A2 are H, H, H.

[0072] Through actual tests, it is verified that the outputs AO, A1, and A2 are all at the high level of 5V. When DRM9 (S9) is closed and DRM6 (S6) changes from open to closed, DRM6 is set low, and the outputs AO, A1, and A2 are L, L, H;

[0073] e. Verification of the output status of the priority encoder when DRM9 (S9) is closed, DRM5 (S5) is opened and then closed again

[0074] According to the principle, when DRM9 (S9) is closed and others are all open, the outputs AO, A1, and A2 are H, H, H.

[0075] Through actual tests, it is verified that the outputs AO, A1, and A2 are all at the high level of 5V. When DRM9 (S9) is closed and DRM5 (S5) changes from open to closed, DRM5 is set low, and the outputs AO, A1, and A2 are H, H, L.

[0076] In the present invention, words such as "connected", "linked", "joined", "connected" indicating electrical connection, without special explanation, mean direct or indirect electrical connection. The "coupled" in this article refers to indirect or direct electrical connection, and the indirect connection can be electrically connected through one or more electrical components (such as resistors, capacitors, inductors, etc.).

[0077] The above description has fully disclosed the specific embodiments of the present invention. It should be noted that any changes made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims of the present invention. Correspondingly, the scope of the claims of the present invention is not limited to the foregoing specific embodiments.

Claims

1. A control circuit for an inverter, characterized in that, It includes: An input acquisition circuit, which includes M switches under test, multiple resistors, and M signal detection output terminals. The signal on one signal detection output terminal can reflect whether the corresponding switch under test is conducting; A priority encoder, which includes M coding input terminals and N coding output terminals respectively coupled to the M signal detection output terminals, where M is greater than N, and both M and N are positive integers greater than or equal to 1. The priority encoder assigns a unique and corresponding N-bit code to each coding input terminal. The coding input terminals have priorities. When the coding input terminal with a higher priority is at an effective level, the coding output terminal outputs the N-bit code corresponding to the coding input terminal with a higher priority; A digital signal processor, which has N input terminals respectively connected to the N coding output terminals, and knows the on and / or off states of the switches under test by receiving the N-bit codes output by the priority encoder; The input acquisition circuit includes: Multiple switches under test S5, S6, S7, S8, S9, S0; Resistors R1, R2, R3, R4, R5, R6, Signal detection output terminals DRM1 / 5, DRM2 / 6, DRM3 / 7, DRM4 / 8, COM LOAD / 0-1, COM LOAD / 0-2; A voltage comparator; The power supply terminal is connected to the signal detection output terminal DRM1 / 5 through the resistor R5, and the signal detection output terminal DRM1 / 5 is grounded through the switch under test S5; The power supply terminal is connected to the signal detection output terminal DRM2 / 6 through the resistor R4, and the signal detection output terminal DRM2 / 6 is grounded through the switch under test S6; The power supply terminal is connected to the signal detection output terminal DRM3 / 7 through the resistor R3, and the signal detection output terminal DRM3 / 7 is grounded through the switch under test S7; The power supply terminal is connected to the signal detection output terminal DRM4 / 8 through the resistor R2, and the signal detection output terminal DRM4 / 8 is grounded through the switch under test S8; The power supply terminal is connected to the signal detection output terminal COM LOAD / 0-1 through the resistor R1, and the signal detection output terminal COMLOAD / 0-1 is grounded through the switch under test S9 and the resistor R6 in sequence; The switch under test S0 is in parallel with the resistor R6; The connection terminal of the resistor R1 and the switch under test S9 is also denoted as the connection terminal COM LOAD / 0. The connection terminal COM LOAD / 0 is connected to one input terminal of the voltage comparator, and the other input terminal of the voltage comparator is a predetermined reference voltage. The output terminal of the voltage comparator is the signal detection output terminal COM LOAD / 0-2.

2. The control circuit according to claim 1, wherein The input acquisition circuit further includes control switches S1-S4, The signal detection output terminal DRM1 / 5 is grounded through the control switch S1 and the resistor R6 in sequence, The signal detection output terminal DRM2 / 6 is grounded through the control switch S2 and the resistor R6 in sequence; The signal detection output terminal DRM3 / 7 is grounded through the control switch S3 and the resistor R6 in sequence; The signal detection output terminal DRM4 / 8 is grounded through the control switch S4 and the resistor R6 in sequence.

3. The control circuit according to claim 1, characterized in that, The encoding input terminals 1-6 of the priority encoder are respectively coupled to the signal detection output terminals DRM1 / 5, DRM2 / 6, DRM3 / 7, DRM4 / 8, COM LOAD / 0-1, and COM LOAD / 0-2. Among them, the priorities of the encoding input terminals 1-6 increase in sequence, the priority of the encoding input terminal 6 is the highest, and the priority of the encoding input terminal 1 is the lowest. N is 3. The N encoding output terminals of the priority encoder are respectively denoted as A0, A1, and A2, and they are respectively coupled to the three input terminals OP1, OP2, and OP3 of the digital signal processor.

4. The control circuit according to claim 1, wherein It further includes a level conversion circuit. The encoding output terminal of the priority encoder is connected to the input terminal of the digital signal processor through the level conversion circuit.

Images