Array substrate and reflective display panel

Abstract

The application discloses an array substrate and a reflective display panel, and belongs to the technical field of display. The array substrate comprises a substrate, a plurality of data lines and a plurality of sub-pixels on the substrate. Each sub-pixel can comprise a reflective pixel electrode and a TFT. The orthogonal projection of the pixel electrode in each sub-pixel on the substrate is in intersection with the orthogonal projections of the first electrode, the first data line and the second data line, so that the area of the orthogonal projection of the plurality of pixel electrodes on the substrate in the array substrate is large, and the display effect of the reflective display panel in which the array substrate is located is good.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a reflective display panel. BACKGROUND

[0002] With the development of display technology, various display panels have emerged. Among them, the reflective display panel can display images without setting a backlight.

[0003] The reflective display panel generally can include: an array substrate and a color film substrate arranged oppositely, and a liquid crystal layer located in the array substrate and the color film substrate. The array substrate can include: a substrate, and a plurality of pixel electrodes located on the substrate, the pixel electrode is made of a metal material with light reflection. In this way, the plurality of pixel electrodes can reflect ambient light, so that the reflective display panel can display images without setting a backlight.

[0004] However, the area of the orthogonal projection of the pixel electrode on the substrate in the current array substrate is small, which will affect the display effect of the reflective display panel. SUMMARY

[0005] Embodiments of the present application provide an array substrate and a reflective display panel. The technical solution can solve the problem of poor display effect of the current reflective display panel, and the technical solution is as follows:

[0006] In one aspect, an array substrate is provided, comprising:

[0007] a substrate, a plurality of data lines and a plurality of sub-pixels located on the substrate, each of the sub-pixels comprising: a reflective pixel electrode and a thin film transistor, a first pole of the thin film transistor being connected with one of the data lines, and a second pole of the thin film transistor being connected with the pixel electrode;

[0008] The data lines include first data lines and second data lines, the first data lines being connected with the first poles of the thin film transistors in the sub-pixels, and the second data lines being connected with the first poles of the thin film transistors in the sub-pixels adjacent to the sub-pixels;

[0009] Among them, on the substrate, the orthogonal projection of the pixel electrode in the sub-pixel and the orthogonal projection of the first pole of the thin film transistor in the sub-pixel and the first data line connected with the first pole exist a first overlapping area, and the orthogonal projection of the second data line exists a second overlapping area.

[0010] Optionally, a portion of the pixel electrode corresponding to the first overlap area and the first electrode and the portion of the first data line corresponding to the first overlap area form a first parasitic capacitance, and a portion of the pixel electrode corresponding to the second overlap area and the portion of the second data line corresponding to the second overlap area form a second parasitic capacitance, and the first parasitic capacitance has a capacitance value equal to that of the second parasitic capacitance.

[0011] Optionally, the first electrode and the second electrode of the thin film transistor are disposed in the same layer as the plurality of data lines and are made of the same material.

[0012] The area of the first overlap area on the substrate, in which the orthogonal projection of the pixel electrode overlaps the orthogonal projection of the first electrode and the first data line, is a first area.

[0013] The area of the second overlap area on the substrate, in which the orthogonal projection of the pixel electrode overlaps the orthogonal projection of the second data line, is a second area.

[0014] The first area is equal to the second area.

[0015] Optionally, the plurality of sub-pixels are arranged into a plurality of columns along a first direction and a plurality of rows along a second direction, and the data line extends along the second direction on the substrate as a whole.

[0016] The plurality of sub-pixels include a first sub-pixel and a second sub-pixel located in the same row and adjacent to each other, and the data line has a first portion extending into the first sub-pixel and covered by a pixel electrode in the first sub-pixel, and a second portion extending into the second sub-pixel and covered by a pixel electrode in the second sub-pixel, the orthogonal projection of the first portion on the substrate is located in the first overlap area in the first sub-pixel, and the orthogonal projection of the second portion on the substrate is located in the second overlap area in the second sub-pixel.

[0017] Optionally, the data line includes a plurality of straight line extensions and a plurality of curved line extensions connected in sequence, and each curved line extension has an opening.

[0018] The plurality of straight line extensions are located between a first sub-pixel column and a second sub-pixel column, the first sub-pixel column is a column of sub-pixels including the first sub-pixel, and the second sub-pixel column is a column of sub-pixels including the second sub-pixel; the first portion includes at least one curved line extension, the second portion includes at least one curved line extension, and the direction of the opening of the curved line extension in the first portion is opposite to the direction of the opening of the curved line extension in the second portion.

[0019] Optionally, the data line comprises: a plurality of first linear extension parts and a plurality of second linear extension parts connected in sequence, and the plurality of first linear extension parts and the plurality of second linear extension parts are staggered one by one, and the extension directions of any two connected first linear extension parts and second linear extension parts intersect.

[0020] The plurality of sub-pixels are arranged in a plurality of columns, and on the substrate, in the same data line, the projection of one of the first linear extension parts overlaps the projection of a pixel electrode in a first sub-pixel column, and the projection of the other first linear extension part overlaps the projection of a pixel electrode in a second sub-pixel column.

[0021] On the substrate, the projection of the second linear extension part in the data line overlaps the projection of the pixel electrode in the first sub-pixel column and the projection of the pixel electrode in the second sub-pixel column, respectively.

[0022] The first sub-pixel column is a column of sub-pixels containing the first sub-pixels, and the second sub-pixel column is a column of sub-pixels containing the second sub-pixels.

[0023] The extension directions of the plurality of first linear extension parts are parallel to the second direction, and the extension directions of the plurality of second linear extension parts are parallel to the first direction.

[0024] Optionally, in the same data line, one of the first linear extension parts is connected to the first electrode of a thin film transistor in the first sub-pixel column, and on the substrate, the projection of one of the first linear extension parts overlaps the projections of two adjacent pixel electrodes in the first sub-pixel column, respectively, and on the substrate, the projection of the other first linear extension part is located within the projection of a pixel electrode in the second sub-pixel column and is spaced apart from the projection of the thin film transistor.

[0025] Optionally, on the substrate, the pixel electrode covers the thin film transistor connected thereto and covers part of the data line connected thereto, and covers part of the data line of an adjacent sub-pixel.

[0026] Optionally, the pixel electrode is rectangular, the data line extends along a direction as a whole and is covered by the pixel electrode of the same column of sub-pixels, and the data line has a part extending to an adjacent sub-pixel through a part of the pixel electrode, and the part extending to the adjacent sub-pixel is covered by the pixel electrode of the adjacent sub-pixel.

[0027] Optionally, on the substrate, the data line is a straight line extending along the column direction in a sub-pixel connected with the data line, and is a whole line extending along the column direction and partially a straight line, a curve or a polygonal line in an adjacent sub-pixel; the extending parts in two sub-pixels are connected by a connecting line; or,

[0028] The data line is a curve or a polygonal line extending along the column direction in a sub-pixel connected with the data line, and is a whole line extending along the column direction and partially a straight line, a polygonal line or a curve in an adjacent sub-pixel; the extending parts in two sub-pixels are connected by a connecting line.

[0029] Optionally, the pixel electrodes in the plurality of sub-pixels are arranged in an array, and distances between any two adjacent pixel electrodes in the first direction or the second direction are equal.

[0030] Optionally, the first electrode comprises a U-shaped structure, the second electrode comprises a strip-shaped structure, and one end of the second electrode is located in the U-shaped structure and the other end is connected with the pixel electrode.

[0031] Optionally, the array substrate further comprises a first auxiliary electrode connected with the second electrode, a second auxiliary electrode located on a side of the first auxiliary electrode away from the pixel electrode, and a first insulating layer located between the first auxiliary electrode and the second auxiliary electrode.

[0032] The orthographic projection of the first auxiliary electrode overlaps the orthographic projection of the second auxiliary electrode on the substrate.

[0033] Optionally, the first auxiliary electrode is arranged in the same layer as the first electrode and the second electrode and is made of the same material; and the second auxiliary electrode is arranged in the same layer as the gate electrode of the thin film transistor and is made of the same material.

[0034] In another aspect, a reflective display panel is provided, comprising:

[0035] Oppositely arranged array substrate and color film substrate, and a liquid crystal layer between the array substrate and the color film substrate, the array substrate being the array substrate described above.

[0036] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0037] The array substrate comprises a substrate, and a plurality of data lines and a plurality of sub-pixels on the substrate. Each sub-pixel can comprise a reflective pixel electrode and a TFT. The pixel electrode in each sub-pixel has a projection on the substrate, which is in intersection with the projections of the first electrode, the first data line and the second data line, so that the area of the projection of the plurality of pixel electrodes on the substrate in the array substrate is large, thereby improving the display effect of the reflective display panel in which the array substrate is located. When the reflective display panel uses a column inversion mode for display, the polarities of the voltages loaded on the first data line and the second data line are opposite. Under the action of the first parasitic capacitor and the second parasitic capacitor, the pulling effect of the first data line and the second data line on the sub-pixel voltage loaded on the pixel electrode can be positively and negatively cancelled, and will not affect the display of the reflective display panel. In this way, the area of the projection of the plurality of pixel electrodes on the substrate in the array substrate can be improved without affecting the display effect of the reflective display panel, and the display effect of the reflective display panel can be ensured to be good. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0039] Figure 1 is a top view of a common array substrate;

[0040] Figure 2 is a top view of an array substrate provided by an embodiment of the present application;

[0041] Figure 3 is Figure 2 is a schematic view of the film layer of the array substrate at A-A';

[0042] Figure 4 is a top view of another array substrate provided by an embodiment of the present application;

[0043] Figure 5 is a top view of still another array substrate provided by an embodiment of the present application;

[0044] Figure 6 is a top view of yet another array substrate provided by an embodiment of the present application;

[0045] Figure 7 is a top view of an array substrate provided by another embodiment of the present application;

[0046] Figure 8 isFigure 7 A film layer structure schematic diagram of the array substrate at A-A';

[0047] Figure 9 An equivalent circuit diagram of a sub-pixel in a reflective display panel;

[0048] Figure 10 A top view of another array substrate provided by another embodiment of the present application;

[0049] Figure 11 A film layer structure schematic diagram of a reflective display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0051] Please refer to Figure 1 , Figure 1 is a top view of a common array substrate at present. The array substrate can include a substrate 01, and a plurality of data lines 02, a plurality of gate lines 03 and a plurality of sub-pixels 04 on the substrate 01. Each sub-pixel 04 can include a pixel electrode 041 and a thin film transistor (English: Thin Film Transistor; abbreviated: TFT) 042. The TFT 042 can include a first electrode 0421, a second electrode 0422 and a gate electrode 0423. The first electrode 0421 can be connected with a data line 02, the second electrode 0422 can be connected with the pixel electrode 041, and the gate electrode 0423 can be connected with a gate line 03. When the array substrate needs to be arranged in a reflective display panel, the pixel electrode 041 in the array substrate needs to be made of a metal material with light reflection property.

[0052] Since the display effect of the reflective display panel is positively correlated with the area of the orthogonal projection of the plurality of pixel electrodes 041 in the array substrate on the substrate 01. Therefore, in order to improve the display effect of the reflective display panel at present, it is necessary to increase the area of the orthogonal projection of the plurality of pixel electrodes 041 in the array substrate on the substrate 01. However, after increasing the area of the orthogonal projection of the plurality of pixel electrodes 041 on the substrate 01, the orthogonal projection of the pixel electrode 041 will overlap with the orthogonal projection of the data line 02 on the substrate 01. In this way, the part of the pixel electrode 041 overlapping with the data line 02 will generate a parasitic capacitance, resulting in the phenomenon of crosstalk failure of the array substrate, which will seriously affect the display effect of the reflective display panel where the array substrate is located.

[0053] Please refer to Figure 2 , Figure 2is a top view of an array substrate provided by an embodiment of the present application. The array substrate 000 can include:

[0054] a substrate 100, a plurality of data lines 200 and a plurality of sub-pixels 300 on the substrate 100.

[0055] Each sub-pixel 300 can include a reflective pixel electrode 301 and a TFT 302. The TFT 302 has a first pole 3021 and a second pole 3022. It should be noted that the first pole 3021 in the TFT 302 in the embodiment of the present application refers to one of the source and the drain in the TFT 302, and the second pole 3022 in the TFT 302 refers to the other of the source and the drain in the TFT 302.

[0056] The first pole 3021 of the TFT 302 in each sub-pixel 300 can be connected with a data line 200, and the second pole 3022 of the TFT 302 in each sub-pixel 300 can be connected with the pixel electrode 301 in the sub-pixel 300.

[0057] In the present application, the plurality of data lines 200 in the array substrate 000 includes a first data line 200a and a second data line 200b. The first data line 200a is connected with the first pole 3021 of the TFT 302 in the sub-pixel 300, and the second data line is connected with the first pole 3021 of the TFT 302 in the sub-pixel 300 adjacent to the sub-pixel 300. That is, the first data line 200a and the second data line 200b are two adjacent data lines in the plurality of data lines 200.

[0058] In the present application, the plurality of data lines 200 in the array substrate 000 includes a first data line 200a and a second data line 200b. The first data line 200a is connected with the first pole 3021 of the TFT 302 in the sub-pixel 300, and the second data line is connected with the first pole 3021 of the TFT 302 in the sub-pixel 300 adjacent to the sub-pixel 300. That is, the first data line 200a and the second data line 200b are two adjacent data lines in the plurality of data lines 200.

[0059] In the embodiment of the present application, the pixel electrode 301 and the data line 200 are insulated. Therefore, in each sub-pixel 300, the portion of the pixel electrode 301 corresponding to the first overlap area S1 and the portion of the first pole 3021 and the first data line 200a corresponding to the first overlap area S1 connected with each other can form a first parasitic capacitance Cdp1 (not labeled in the figure). Figure 2 In each sub-pixel 300, the portion of the pixel electrode 301 corresponding to the second overlap area S2 and the portion of the second data line 200b corresponding to the second overlap area S2 form a second parasitic capacitance Cdp2 (not labeled in the figure). Figure 2 In each sub-pixel 300, the portion of the pixel electrode 301 corresponding to the second overlap area S2 and the portion of the second data line 200b corresponding to the second overlap area S2 form a second parasitic capacitance Cdp2 (not labeled in the figure).

[0060] For more clearly showing the structure of the parasitic capacitance in the sub-pixel 300, please refer to Figure 3 , Figure 3 is Figure 2 A schematic diagram of the film layers of the array substrate at A-A' is shown.

[0061] In some embodiments, the first parasitic capacitance Cdp1 in the sub-pixel 300 has a capacitance value equal to that of the second parasitic capacitance Cdp2.

[0062] In other embodiments, the first parasitic capacitance Cdp1 in the sub-pixel 300 has a capacitance value not equal to that of the second parasitic capacitance Cdp2.

[0063] In the embodiments of the present application, the pixel electrode of one sub-pixel completely covers a part of the data line of the sub-pixel, and the pixel electrode of the adjacent sub-pixel covers another part of the data line.

[0064] In the embodiments of the present application, when the orthogonal projection of the pixel electrode 301 in the sub-pixel 300 on the substrate 100 overlaps with the orthogonal projections of the first electrode 3021 and the first data line 200a and the second data line 200b in the sub-pixel 300, the area of the orthogonal projection of the plurality of pixel electrodes 301 on the substrate 100 in the array substrate 000 can be increased, so that the display effect of the reflective display panel in which the array substrate 000 is located is better. Moreover, when the reflective display panel displays in the column inversion mode, the polarities of the voltages loaded on the first data line 200a and the second data line 200b are opposite. In this way, when the first parasitic capacitance Cdp1 in the sub-pixel 300 has a non-zero capacitance value and the second parasitic capacitance Cdp2 has a non-zero capacitance value, the pulling effect of the first data line 200a and the second data line 200b on the sub-pixel voltage loaded on the pixel electrode 301 can be partially or completely offset under the action of the first parasitic capacitance Cdp1 and the second parasitic capacitance Cdp2, and the influence of the data line on the display of the reflective display panel can be reduced or eliminated.

[0065] In summary, the array substrate provided by the embodiments of the present application includes a substrate, and a plurality of data lines and a plurality of sub-pixels located on the substrate. Each sub-pixel can include a reflective pixel electrode and a TFT. The orthogonal projection of the pixel electrode in each sub-pixel on the substrate overlaps with the orthogonal projections of the first electrode, the first data line and the second data line, so that the area of the orthogonal projection of the plurality of pixel electrodes on the substrate in the array substrate is larger, and thus the display effect of the reflective display panel in which the array substrate is located is better.

[0066] And, when the reflective display panel displays in the column inversion mode, the polarities of the voltages loaded by the first data line and the second data line are opposite. Thus, when the capacitance values of the first parasitic capacitance and the second parasitic capacitance in each sub-pixel are non-zero or non-zero and equal, the pulling effects of the first data line and the second data line on the sub-pixel voltage loaded by the pixel electrode can be partially or completely offset, and the impact on the display of the reflective display panel is reduced. Thus, the area of the orthogonal projection of the plurality of pixel electrodes in the array substrate on the substrate can be increased without affecting the display effect of the reflective display panel, and the display effect of the reflective display panel is ensured to be good.

[0067] The following describes the case that the capacitance value of the first parasitic capacitance Cdp1 and the capacitance value of the second parasitic capacitance Cdp2 in the sub-pixel 300 are the same or approximately the same.

[0068] In the embodiment of the present application, as shown in Figure 2 and Figure 3 The first electrode 3021 and the second electrode 3022 of the TFT 302 in each sub-pixel 300 in the array substrate 000 can be disposed in the same layer as the plurality of data lines 200 in the array substrate 000. The materials of the first electrode 3021, the second electrode 3022 and the data lines 200 are the same. Thus, the first electrode 3021, the second electrode 3022 and the data lines 200 are formed by one patterning process.

[0069] In this case, the distance between the pixel electrode 301 and the data line 200 is the same as the distance between the pixel electrode 301 and the first electrode 3021. Assuming that the area of the first overlap region S1 in which the orthogonal projection of the pixel electrode 301 overlaps with the orthogonal projection of the first electrode 3021 and the first data line 200a connected to each other is a first area, and the area of the second overlap region S2 in which the orthogonal projection of the pixel electrode 301 overlaps with the orthogonal projection of the second data line 200b is a second area. Then, since the capacitance value of the capacitor is related to the relative area of the two capacitor plates and the distance between the two capacitor plates. Therefore, when the first electrode 3021 and the second electrode 3022 of the TFT 302 are disposed in the same layer as the plurality of data lines 200, it is only necessary to ensure that the first area is equal to the second area, that is, to ensure that the capacitance value of the first parasitic capacitance Cdp1 in the sub-pixel 300 is equal to the capacitance value of the second parasitic capacitance Cdp2.

[0070] In the embodiment of the present application, as shown in Figure 4 , the first electrode 3021 and the second electrode 3022 of the TFT 302 in each sub-pixel 300 in the array substrate 000 can be disposed in the same layer as the plurality of data lines 200 in the array substrate 000. The materials of the first electrode 3021, the second electrode 3022 and the data lines 200 are the same. Thus, the first electrode 3021, the second electrode 3022 and the data lines 200 are formed by one patterning process. Figure 4is another top view of an array substrate provided by an embodiment of the present application. A plurality of sub-pixels 300 in the array substrate 000 can be arranged as a plurality of columns along a first direction x and as a plurality of rows along a second direction y. The first direction x is the row direction of the plurality of sub-pixels 000, and the second direction y is the column direction of the plurality of sub-pixels 300. The first direction x is perpendicular to the second direction y. Each data line 200 in the array substrate 000 extends along the second direction y on the substrate 100 as a whole.

[0071] The plurality of sub-pixels 300 includes a first sub-pixel 300a and a second sub-pixel 300b located in the same row and adjacent to each other. The first sub-pixel 300a and the second sub-pixel 300b can be any two adjacent sub-pixels in any row. Assuming that a column of sub-pixels containing the first sub-pixel 300a is a first sub-pixel column, and a column of sub-pixels containing the second sub-pixel 300b is a second sub-pixel column. Then, the data line 200 located between the first sub-pixel column and the second sub-pixel column has a first portion 200c extending into the first sub-pixel 300a and covered by the pixel electrode 301 in the first sub-pixel 300a, and a second portion 200d extending into the second sub-pixel 300b and covered by the pixel electrode 301 in the second sub-pixel 300b. The orthogonal projection of the first portion 200c on the substrate 100 is located in a first overlap area S1 in the first sub-pixel 300a; the orthogonal projection of the second portion 200d on the substrate 100 is located in a second overlap area S2 in the second sub-pixel 300b.

[0072] It should be noted that the first portion 200c in the data line 200 is connected to the first electrode 3021 of the TFT 302, and the second portion 200d in the data line 200 is not connected to the TFT 302. The orthogonal projection of the second portion 200d on the substrate 100 completely overlaps the second overlap area S2.

[0073] In this case, the orthogonal projection of each data line 200 on the substrate 100 overlaps the orthogonal projection of the pixel electrodes 301 in the two columns of sub-pixels adjacent to the data line 200, respectively. Correspondingly, the orthogonal projection of the pixel electrode 301 in each column of sub-pixels on the substrate 100 overlaps the orthogonal projection of the two data lines 200 adjacent to the column of sub-pixels, respectively.

[0074] In the present application, the first portion 200c and the second portion 200d in the data line 200 have various structures, and embodiments of the present application will be described schematically by taking the following two optional implementation manners as examples.

[0075] In the first optional implementation manner, as shown in Figure 5 Figure 5 ​is a top view of another array substrate provided by an embodiment of the present application. Each data line 200 in the array substrate 000 can include a plurality of straight line extending portions 201 and a plurality of curved line extending portions 202 connected in sequence. Each curved line extending portion 202 has an opening. In the present application, the extending direction of each straight line extending portion 201 is parallel to the second direction y, and the extending direction of each curved line extending portion 202 is the direction of an arc. The plurality of straight line extending portions 201 and the plurality of curved line extending portions 202 can be arranged alternately. It should be noted that the plurality of curved line extending portions 202 in the data line 200 have two types of curved line extending portions 202, and the structures of the two types of curved line extending portions 202 are the same, and only the directions of the openings are different.

[0076] In the present application, the plurality of straight line extending portions 201 in the data line 200 can be located between the first sub-pixel column and the second sub-pixel column.

[0077] The first portion 200c of the data line 200 includes at least one curved line extending portion 202. The second portion 200d of the data line 200 includes at least one curved line extending portion 202. It should be noted that when the first portion 200c includes a plurality of curved line extending portions 202, the directions of the openings of the plurality of curved line extending portions 202 are consistent. Similarly, when the second portion 200d includes a plurality of curved line extending portions 202, the directions of the openings of the plurality of curved line extending portions 202 are consistent. Moreover, the direction of the opening of the curved line extending portion 202 in the first portion 200c is opposite to the direction of the opening of the curved line extending portion 202 in the second portion 200c. For example, the direction of the opening of the curved line extending portion 202 in the first portion 200c is toward the second sub-pixel 300b, and the direction of the opening of the curved line extending portion 202 in the second portion 200d is toward the first sub-pixel 300a.

[0078] In the present embodiment, the first portion 200c in the data line 200 needs to be connected with the first electrode 3021 of the TFT 302. Therefore, in order to ensure that the capacitance value of the first parasitic capacitance Cdp1 in any sub-pixel 300 is equal to the capacitance value of the second parasitic capacitance Cdp2, it is necessary to ensure that the number of the curved line extending portions 202 in the first portion 200c is less than the number of the curved line extending portions 202 in the second portion 200d.

[0079] There are two cases for the arrangement mode of the straight line extending portion 201 located between the first sub-pixel 300a and the second sub-pixel 300b:

[0080] In the first case, the orthogonal projection of the straight extension 201 on the substrate 100 is arranged apart from the orthogonal projection of the pixel electrode 301 in the first sub-pixel 300a, and is arranged apart from the orthogonal projection of the pixel electrode 301 in the second sub-pixel 300b. In this case, in order to ensure that the capacitance value of the first parasitic capacitance Cdp1 in any sub-pixel 300 is equal to the capacitance value of the second parasitic capacitance Cdp2, it is necessary to ensure that the distance between the straight extension 201 and the first sub-pixel 300a, and the distance between the straight extension 201 and the second sub-pixel 300b are equal.

[0081] In the second case, the orthogonal projection of the straight extension 201 on the substrate 100 overlaps the orthogonal projection of the pixel electrode 301 in the first sub-pixel 300a, and overlaps the orthogonal projection of the pixel electrode 301 in the second sub-pixel 300b. In this case, in order to ensure that the capacitance value of the first parasitic capacitance Cdp1 in any sub-pixel 300 is equal to the capacitance value of the second parasitic capacitance Cdp2, the area of the orthogonal projection of the straight extension 201 and the pixel electrode 301 in the first sub-pixel 300a on the substrate 100, and the area of the orthogonal projection of the straight extension 201 and the pixel electrode 301 in the second sub-pixel 300b on the substrate 100 are equal.

[0082] In the second alternative implementation, as shown in FIG. 2B, Figure 6 Figure 6 is another top view of an array substrate provided by an embodiment of the present application. Each data line 200 in the array substrate 000 includes a plurality of first straight extensions 203 and a plurality of second straight extensions 204 connected to each other in sequence. The plurality of first straight extensions 203 and the plurality of second straight extensions 204 are arranged alternately one by one, and the extension directions of any two connected first straight extension 203 and second straight extension 204 intersect.

[0083] For example, the extension directions of the plurality of first straight extensions 203 in the data line 200 are the same, and the extension directions of the plurality of second straight extensions 204 in the data line 200 are the same. The extension direction of the first straight extension 203 is parallel to the second direction y, and the extension direction of the second straight extension 204 is parallel to the first direction x. In the same data line 200, any two adjacent second straight extensions 204 and the first straight extension 203 located between the two second straight extensions 204 can form a bending structure with an opening. In this way, in the same data line 200, a plurality of bending structures can be formed by the plurality of second straight extensions 204 and the plurality of first straight extensions 203, and the directions of the openings of any two adjacent bending structures are opposite.

[0084] ​In this embodiment, on the substrate 100, among any two adjacent first straight line extensions 203 of the same data line 200, the orthographic projection of one first straight line extension 203 overlaps with the orthographic projection of the pixel electrode 301 in the first sub-pixel column, and the orthographic projection of the other first straight line extension 203 overlaps with the orthographic projection of the pixel electrode 301 in the second sub-pixel column. Furthermore, on the substrate 100, the orthographic projection of each second straight line extension 204 of the data line 200 overlaps with the orthographic projections of the pixel electrode 301 in the first and second sub-pixel columns, respectively.

[0085] For example, in any two adjacent first straight line extensions 203 of the same data line 200, one first straight line extension 203 can be connected to the first electrode 3021 of the TFT 302 in the first sub-pixel column, and on the substrate 100, the orthographic projection of this one first straight line extension 203 overlaps with the orthographic projections of two adjacent pixel electrodes 301 in the first sub-pixel column. On the substrate 100, the orthographic projection of the other first straight line extension 203 is located within the orthographic projection of a pixel electrode 301 in the second sub-pixel column, and is spaced apart from the orthographic projection of the TFT 302. Thus, the data line 200 is connected to the sub-pixel 300 in the first sub-pixel column through the first straight line extension 203 in the data line 200, but the data line 200 is not connected to the sub-pixel 300 in the second sub-pixel column.

[0086] In this case, the first portion 200c of the data line 200 includes a portion of two first straight extensions 203 and a portion of two second straight portions 204; the second portion 200d of the data line 200 includes the entirety of one first straight extension 203 and a portion of the two second straight portions 204.

[0087] Optional, such as Figure 7 As shown, Figure 7 This is a top view of an array substrate provided in another embodiment of this application. On the substrate 100, the orthographic projection of the TFT 302 in each sub-pixel 300 lies within the orthographic projection of the pixel electrode 301 in that sub-pixel 300. In this way, the area of ​​the orthographic projection of the plurality of pixel electrodes 301 in the array substrate 000 onto the substrate 100 can be further increased. It should be noted that... Figure 7 Based on the structure of the data lines in the array substrate Figure 6 The data line shown is used as an example for illustrative purposes.

[0088] In this embodiment, the array substrate 000 may further include multiple gate lines 400 located on the substrate 100. Each sub-pixel 300's TFT 302 in the array substrate 000 also includes a gate 3023, which can be connected to a gate line 400. For example, the gate line 400 may be disposed on the same layer as the gate 3023, and the material of the gate line 400 may be the same as the material of the gate 3023. Thus, the gate line 400 and the gate 3023 can be formed in a single patterning process.

[0089] Optional, such as Figure 7 and Figure 8 As shown, Figure 8 yes Figure 7 The diagram shows the film structure of the array substrate at A-A'. The array substrate 000 may further include: a first auxiliary electrode 500 connected to the second electrode 3022 of the TFT 302, a second auxiliary electrode 600 located on the side of the first auxiliary electrode 500 away from the pixel electrode 301, and a first insulating layer 700 located between the first auxiliary electrode 500 and the second auxiliary electrode 600.

[0090] In this application, the orthographic projections of the first auxiliary electrode 500 and the second auxiliary electrode 600 overlap on the substrate 100. Since the first auxiliary electrode 500 can be electrically connected to the pixel electrode 301 via the second electrode 3022, when power is applied, the electrode of the first auxiliary electrode 500 is at the same potential as that of the pixel electrode 301. Thus, the first auxiliary electrode 500 and the second auxiliary electrode 600 can form a storage capacitor Cst, which can maintain the stability of the voltage applied to the pixel electrode 500.

[0091] It should be noted that the number of first auxiliary electrodes 500 and second auxiliary electrodes 600 in the array substrate 000 can both be multiple, and the multiple first auxiliary electrodes 500, multiple second auxiliary electrodes 600, and multiple pixel electrodes 301 correspond one-to-one. On the substrate 100, the orthographic projection of each pixel electrode 301 overlaps with the orthographic projection of the corresponding first auxiliary electrode 500 and the orthographic projection of the corresponding second auxiliary electrode 600, and the orthographic projections of the first auxiliary electrode 500 and the second auxiliary electrode 600 are located within the orthographic projection of the corresponding pixel electrode 301.

[0092] In the present application, the first auxiliary electrode 500 can be arranged in the same layer as the first electrode 3021 and the second electrode 3022 of the TFT 302, and the materials are the same. That is, the first auxiliary electrode 500 and the first electrode 3021 and the second electrode 3022 are formed by the same patterning process. The second auxiliary electrode 500 can be arranged in the same layer as the gate electrode 3023 of the TFT 302, and the materials are the same. That is, the second auxiliary electrode 500 and the gate electrode 3023 are formed by the same patterning process. In this way, the manufacturing process of the array substrate is effectively simplified.

[0093] Optionally, the array substrate 000 can further include a common electrode line 800 electrically connected to each row of the second auxiliary electrode 600. The common electrode line 800 can be arranged in the same layer as the second auxiliary electrode 500, and the materials are the same. That is, the common electrode line 800 and the second auxiliary electrode 500 are formed by the same patterning process. The common electrode line 500 can be electrically connected to the common electrode in the liquid crystal display panel in which the array substrate 000 is located, so that the potential of the second auxiliary electrode 500 is the same as that of the common electrode in the case of power-on.

[0094] In the embodiment of the present application, the first electrode 3021 of the TFT 302 in each sub-pixel 300 includes a U-shaped structure, the second electrode 3022 includes a strip-shaped structure, one end of the second electrode 3022 is located in the U-shaped structure in the first electrode 3021, and the other end is electrically connected to the pixel electrode 301. For example, the TFT 302 in each sub-pixel 300 further includes an active layer 3024, which is respectively connected to the first electrode 3021 and the second electrode 3022, and the active layer 3024 is arranged in insulation with the gate electrode 3023, for example, the active layer 3024 and the gate electrode 3023 have a first insulating layer 700 therebetween. When the first electrode 3021 of the TFT 302 includes a U-shaped structure, and the second electrode 3022 includes a strip-shaped structure extending into the U-shaped structure, the channel region of the active layer 3024 is a U-shaped channel region. It should be noted that the channel region of the active layer 3024 refers to the region of the active layer 3024 between the region where the active layer 3024 contacts the first electrode 3021 and the region where the active layer 3024 contacts the second electrode 3022. When the channel region of the active layer 3024 is a U-shaped channel region, since the U-shaped channel region has a large aspect ratio, the TFT 302 can withstand a higher breakdown voltage, and the service life of the array substrate 000 can be improved.

[0095] It should be noted that, as Figure 8As shown, the array substrate further comprises a second insulating layer 900 between the pixel electrode 301 and the second electrode 3022. The second insulating layer 900 has a via hole 900a, through which the pixel electrode 301 can be electrically connected to the other end of the second electrode 3022.

[0096] In the embodiments of the present application, as shown in Figure 7 As shown, the orthographic projection of one gate line 400 on the substrate 100 overlaps with the orthographic projection of the pixel electrode 301 in one row of sub-pixels 300. In this way, the area of the orthographic projection of the plurality of pixel electrodes 301 in the array substrate 000 on the substrate 100 is further increased.

[0097] In this case, the size of the area of the orthographic projection of the plurality of pixel electrodes 301 in the array substrate 000 on the substrate 100 is only related to the process precision when the array substrate 000 is manufactured. Theoretically, the distance between any two adjacent pixel electrodes 301 can be infinitely reduced, and the ratio of the area of the orthographic projection of the plurality of pixel electrodes 301 on the substrate 100 to the area of the side of the substrate 100 close to the pixel electrode 301 can theoretically approach 100%, and thus the area of the orthographic projection of the plurality of pixel electrodes 301 on the substrate 100 is large, which greatly improves the display effect of the reflective display panel. For example, the plurality of pixel electrodes 301 in the plurality of sub-pixels 300 are arranged in an array, and the distance between any two adjacent pixel electrodes 301 in the first direction x or the second direction y is equal.

[0098] It should be noted that, Figure 7 For example, as shown in

[0099] For example, as shown in Figure 9 For example, as shown in Figure 9This is an equivalent circuit diagram of a sub-pixel in a reflective display panel. In each sub-pixel 300, the first electrode of a TFT 302 is connected to a data line 200, the second electrode of a TFT 302 is connected to a pixel electrode, and the gate of a TFT 302 is connected to a gate line 400. This pixel electrode can be equivalent to a liquid crystal capacitor Clc with the common electrode Vcom in the reflective display panel, and the pixel electrode can form a storage capacitor Cst with the common electrode line. The TFT 302 can respond to the gate drive signal provided by the gate line 400 to output a data signal from the data line 200 connected to it to the pixel electrode, thereby charging the pixel electrode and creating a potential difference between the pixel electrode and the common electrode Vcom. The liquid crystal molecules located between the pixel electrode and the common electrode Vcom can be deflected under the action of this potential difference, thereby controlling the light emission of the sub-pixel.

[0100] like Figure 9 As shown, in each sub-pixel 300, the pixel electrode can generate a first parasitic capacitance Cdp1 with the interconnected first data line and first electrode, and the pixel electrode can also generate a second parasitic capacitance Cdp2 with the second data line. When the capacitance value of the first parasitic capacitance Cdp1 is equal to the capacitance value of the second parasitic capacitance Cdp2, the first parasitic capacitance Cdp1 and the second parasitic capacitance Cdp2 will not affect the display of the reflective display panel.

[0101] like Figure 9 As shown, in each sub-pixel 300, when the orthographic projection of the pixel electrode in that sub-pixel overlaps with the orthographic projection of the gate to which the sub-pixel is connected on the substrate, a parasitic capacitance Cgs is generated between the pixel electrode and the gate line. When the potential on the gate line 200 changes, due to the coupling effect of the parasitic capacitance Cgs, the potential of the pixel electrode connected to the gate line 200 is pulled, causing it to deviate from the set potential. Because the potential of the pixel electrode changes, while the potential of the common electrode Vcom is generally constant, the potential difference between the pixel electrode and the common electrode changes, ultimately leading to abnormal deflection of the liquid crystal molecules. This causes flickering in the reflective display panel, resulting in poor display quality.

[0102] During the charging process of the pixel electrode, under the influence of parasitic capacitance Cgs, the potential charged to the pixel electrode undergoes a certain degree of jump at both the initial and final stages of charging. Furthermore, the actual potential charged to the pixel electrode ultimately deviates from the set potential. The potential difference ΔVp between this actual potential and the set potential can satisfy the following:

[0103]

[0104] Wherein, VGH is the high voltage of the gate, and VGL is the low voltage of the gate. According to the formula, it can be seen that the larger the parasitic capacitance Cgs is, the larger the ΔVp is. ΔVp is a key factor affecting the picture quality. If ΔVp is too large, the risks of flicker and residual image caused by the difference in brightness between positive and negative frames will increase.

[0105] To this end, as Figure 10 shown, Figure 10 is another top view of an array substrate provided by another embodiment of the present application. In the array substrate 000, the normal projection of the gate line 400 connected by the gate 3023 of the TFT 302 in the nth row of sub-pixels is arranged to be spaced from the normal projection of the pixel electrode 301 in the nth row of sub-pixels and to overlap the normal projection of the pixel electrode 301 in the (n+1)th row of sub-pixels. In this way, the gate line 400 connected by the gate 3023 of the TFT 302 in the nth row of sub-pixels forms a parasitic capacitance with the pixel electrode 301 in the (n+1)th row of sub-pixels, but does not form a parasitic capacitance with the pixel electrode 302 in the nth row of sub-pixels. Since the nth row of sub-pixels and the (n+1)th row of sub-pixels need to be charged in sequence during display, the gate line 400 connected by the gate 3023 of the TFT 302 in the nth row of sub-pixels forms a parasitic capacitance with the pixel electrode in the (n+1)th row of sub-pixels, which does not affect the (n+1)th row of sub-pixels that are being charged. This effectively reduces the probability of flicker when the array substrate 000 is used in a reflective display panel to display a picture, and further improves the display effect of the reflective display panel.

[0106] Optionally, any two adjacent data lines 200 in the array substrate 000 are used to load voltages of opposite polarities. In this way, the reflective display panel in which the array substrate 000 is used displays in column inversion mode, effectively avoiding the aging of liquid crystal molecules in the reflective display panel. In other optional implementation manners, the reflective display panel can also display in point inversion mode. The embodiments of the present application do not limit this.

[0107] Optionally, the material of the pixel electrode 302 in the above embodiment includes a metal material having a reflective property. For example, the material of the pixel electrode 302 can include a metal material such as aluminum, silver, or an alloy.

[0108] In some embodiments, on the substrate, the pixel electrode covers the thin film transistor connected thereto and covers part of the data line connected thereto, and covers part of the data line of the adjacent sub-pixel.

[0109] In some embodiments, the pixel electrode is rectangular, the data line extends in one direction as a whole and is covered by the pixel electrodes of the sub-pixels in the same column, the data line has a portion extending to an adjacent sub-pixel through a part of the pixel electrode, and the portion extending to the adjacent sub-pixel is covered by the pixel electrode of the adjacent sub-pixel.

[0110] In some embodiments, on the substrate, the data line extends in the column direction within the sub-pixel connected with the data line, extends in the column direction within the adjacent sub-pixel, and the extending parts within the two sub-pixels are connected by the connecting line; or,

[0111] the data line is a straight line extending in the column direction within the sub-pixel connected with the data line, extends in the column direction as a whole and is a curve or a polyline in part within the adjacent sub-pixel, and the extending parts within the two sub-pixels are connected by the connecting line; or,

[0112] the data line is a curve or a polyline extending in the column direction within the sub-pixel connected with the data line, extends in the column direction as a whole and is a straight line, a polyline or a curve in part within the adjacent sub-pixel, and the extending parts within the two sub-pixels are connected by the connecting line.

[0113] In summary, the array substrate provided by the embodiments of the present application comprises: a substrate, and a plurality of data lines and a plurality of sub-pixels on the substrate. Each sub-pixel can comprise: a reflective pixel electrode and a TFT. The orthogonal projection of the pixel electrode in each sub-pixel on the substrate intersects with the orthogonal projections of the first electrode, the first data line and the second data line, so that the area of the orthogonal projection of the plurality of pixel electrodes on the substrate in the array substrate is larger, thereby making the display effect of the reflective display panel in which the array substrate is located better. Moreover, when the reflective display panel displays in the column inversion mode, the polarities of the voltages loaded by the first data line and the second data line are opposite. In this way, when the capacitance values of the first parasitic capacitance and the second parasitic capacitance in each sub-pixel are equal, the pulling effects of the first data line and the second data line on the sub-pixel voltage loaded by the pixel electrode can be positively and negatively cancelled out, and will not affect the display of the reflective display panel. In this way, the area of the orthogonal projection of the plurality of pixel electrodes on the substrate in the array substrate can be increased without the display effect of the reflective display panel being affected by the parasitic capacitance, and the display effect of the reflective display panel can be ensured to be better.

[0114] The embodiments of the present application also provide a reflective display panel, as shown in Figure 11 , Figure 11 is a schematic diagram of a film layer structure of a reflective display panel provided by the embodiments of the present application. The reflective display panel can comprise:

[0115] The array substrate 000 and the color filter substrate 001 are oppositely arranged, and a liquid crystal layer 003 is located between the array substrate 000 and the color filter substrate 002. The array substrate 000 can be the array substrate in the above embodiments, for example, the array substrate 000 can be Figure 2 Or Figure 4 The array substrate shown in the figure.

[0116] In the present application, when the common electrode is located on the color filter substrate 002, the reflective display panel is a twisted nematic (TN) type display panel.

[0117] The present application also provides a display device, which can include the above-mentioned reflective display panel. Optionally, the display device can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer or navigator.

[0118] It should be noted that in the drawings, the size of the layers and regions can be exaggerated for clarity. It will also be understood that when a component or layer is referred to as being "on" another component or layer, it can be directly on the other component or layer, or intervening layers can also be present. In addition, it will also be understood that when a component or layer is referred to as being "under" another component or layer, it can be directly under the other component or layer, or one or more intervening layers or components can also be present. In addition, it will also be understood that when a layer or component is referred to as being "between" two layers or components, it can be the only layer or component between the two layers or components, or one or more intervening layers or components can also be present. Similar reference numerals indicate similar components throughout the specification.

[0119] In the present application, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "a plurality of" refers to two or more, unless otherwise explicitly limited.

[0120] The above description is only optional embodiments of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate, characterized by, The application relates to a display panel, comprising: a substrate; a first insulating layer, a plurality of data lines, a plurality of sub-pixels, a plurality of first auxiliary electrodes and a plurality of second auxiliary electrodes on the substrate, each of the sub-pixels comprising a reflective pixel electrode and a thin film transistor, the first electrode of the thin film transistor being connected with one of the data lines, and the second electrode of the thin film transistor being connected with the pixel electrode; the first auxiliary electrode is electrically connected with the pixel electrode through the second electrode, the second auxiliary electrode is located on the side of the first auxiliary electrode away from the pixel electrode, and the first insulating layer is located between the first auxiliary electrode and the second auxiliary electrode; on the substrate, the orthogonal projection of the first auxiliary electrode and the orthogonal projection of the second auxiliary electrode overlap, and the orthogonal projection of the first auxiliary electrode and the orthogonal projection of the second auxiliary electrode are both located in the orthogonal projection of the corresponding pixel electrode; the data lines comprise first data lines and second data lines, the first data lines are connected with the first electrodes of the thin film transistors in the sub-pixels, and the second data lines are connected with the first electrodes of the thin film transistors in the sub-pixels adjacent to the sub-pixels; on the substrate, the orthogonal projection of the pixel electrode in the sub-pixel and the orthogonal projection of the first electrode of the thin film transistor in the sub-pixel and the first data line connected with the first electrode form a first overlapping area, and the orthogonal projection of the second data line forms a second overlapping area; the first overlapping area comprises the overlapping area of the orthogonal projection of the pixel electrode and the orthogonal projection of the first electrode and the overlapping area of the orthogonal projection of the pixel electrode and the orthogonal projection of the first data line; the part of the pixel electrode corresponding to the first overlapping area and the part of the first electrode and the first data line connected with each other and corresponding to the first overlapping area form a first parasitic capacitor, and the part of the pixel electrode corresponding to the second overlapping area and the part of the second data line corresponding to the second overlapping area form a second parasitic capacitor, and the capacitance of the first parasitic capacitor is equal to the capacitance of the second parasitic capacitor.

2. The array substrate of claim 1, wherein, the first electrode and the second electrode of the thin film transistor are arranged in the same layer as the plurality of data lines and are made of the same material; on the substrate, the area of the first overlapping area where the orthogonal projection of the pixel electrode and the orthogonal projection of the first electrode and the first data line connected with each other overlap is a first area; on the substrate, the area of the second overlapping area where the orthogonal projection of the pixel electrode and the orthogonal projection of the second data line overlap is a second area; the first area is equal to the second area.

3. The array substrate of claim 1, wherein, the plurality of sub-pixels are arranged into a plurality of columns along a first direction and a plurality of rows along a second direction, and the data lines extend along the second direction on the substrate as a whole. The plurality of sub-pixels includes first and second sub-pixels located in the same row and adjacent to each other, the data line has a first portion extending into the first sub-pixel and covered by a pixel electrode in the first sub-pixel, and a second portion extending into the second sub-pixel and covered by a pixel electrode in the second sub-pixel, a projection of the first portion on the substrate is located in the first overlap region in the first sub-pixel, and a projection of the second portion on the substrate is located in the second overlap region in the second sub-pixel.

4. The array substrate of claim 3, wherein, The data line comprises a plurality of straight line extensions and a plurality of curved line extensions connected in sequence, each of the curved line extensions has an opening; The plurality of straight line extensions are located between a first sub-pixel column and a second sub-pixel column, the first sub-pixel column is a column of sub-pixels including the first sub-pixel, and the second sub-pixel column is a column of sub-pixels including the second sub-pixel; The first portion includes at least one of the curved line extensions, the second portion includes at least one of the curved line extensions, and the direction of the opening of the curved line extension in the first portion is opposite to the direction of the opening of the curved line extension in the second portion.

5. The array substrate of claim 3, wherein, The data line comprises a plurality of first straight line extensions and a plurality of second straight line extensions connected in sequence, and the plurality of first straight line extensions and the plurality of second straight line extensions are staggered one by one, and the extension directions of any two connected first straight line extensions and second straight line extensions intersect; The plurality of sub-pixels are arranged in a plurality of columns, on the substrate, in the same data line, the projection of one of the first straight line extensions overlaps the projection of the pixel electrode in the first sub-pixel column, and the projection of the other of the first straight line extensions overlaps the projection of the pixel electrode in the second sub-pixel column; On the substrate, the projection of the second straight line extension in the data line overlaps the projection of the pixel electrode in the first sub-pixel column and the projection of the pixel electrode in the second sub-pixel column, respectively; The first sub-pixel column is a column of sub-pixels including the first sub-pixel, and the second sub-pixel column is a column of sub-pixels including the second sub-pixel; The extension directions of the plurality of first straight line extensions are parallel to the second direction, and the extension directions of the plurality of second straight line extensions are parallel to the first direction.

6. The array substrate of claim 5, wherein, In the same data line, one of the first straight line extensions is connected to the first electrode of the thin film transistor in the first sub-pixel column, and on the substrate, the projection of one of the first straight line extensions overlaps the projections of two adjacent pixel electrodes in the first sub-pixel column, respectively, and on the substrate, the projection of the other of the first straight line extensions is located in the projection of one pixel electrode in the second sub-pixel column and is spaced apart from the projection of the thin film transistor.

7. The array substrate of claim 1, wherein, The pixel electrode covers the thin film transistor connected thereto and part of the data line connected thereto, and covers part of the data line of the adjacent sub-pixel.

8. The array substrate of claim 7, wherein, The pixel electrode is rectangular, the data line extends in one direction as a whole and is covered by the pixel electrodes of the sub-pixels in the same column, and the data line has a part extending to the adjacent sub-pixel through a part of the pixel electrode, and the part extending to the adjacent sub-pixel is covered by the pixel electrode of the adjacent sub-pixel.

9. The array substrate of claim 8, wherein, The data line is a straight line extending in the column direction in the sub-pixel connected with the data line, and extends in the column direction as a whole and is partially a straight line, a curve or a broken line in the adjacent sub-pixel; the extending parts in two sub-pixels are connected by a connecting line; or, The data line is a curve or a broken line extending in the column direction in the sub-pixel connected with the data line, and extends in the column direction as a whole and is partially a straight line, a broken line or a curve in the adjacent sub-pixel; the extending parts in two sub-pixels are connected by a connecting line.

10. The array substrate of claim 8, wherein, Each pixel electrode in the plurality of sub-pixels is arranged in an array, and the distance between any two adjacent pixel electrodes is equal in the first direction or the second direction. The plurality of sub-pixels are arranged into multiple columns in the first direction and multiple rows in the second direction, and the data line extends in the second direction as a whole on the substrate.

11. The array substrate according to any one of claims 3 to 10, wherein, The first electrode comprises a U-shaped structure, the second electrode comprises a strip-shaped structure, one end of the second electrode is located in the U-shaped structure, and the other end of the second electrode is connected with the pixel electrode.

12. The array substrate of claim 1, wherein, The first auxiliary electrode is arranged in the same layer and is made of the same material as the first electrode and the second electrode; and the second auxiliary electrode is arranged in the same layer and is made of the same material as the gate electrode of the thin film transistor.

13. A reflective display panel, characterized by The array substrate comprises: An array substrate and a color film substrate arranged oppositely, and a liquid crystal layer between the array substrate and the color film substrate, the array substrate is the array substrate in any one of claims 1 to 12.

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