Interrupt processing method, interrupt manager, electronic device, and computer readable medium

Abstract

The present disclosure provides an interrupt processing method, comprising: when IPI request information is written into an inter-processor interrupt IPI request information area, a predetermined interrupt request is generated according to the IPI request information, the IPI request information carries the identifier of at least one target virtual central processing unit vCPU, wherein the storage space of the current IPI interrupt manager includes at least one IPI request information area, the IPI request information area corresponds to a virtual machine, and the physical address of the IPI request information area is mapped to the corresponding virtual machine through a memory mapping input and output MMIO; the predetermined interrupt request is sent to an interrupt controller, so that the interrupt controller sends the predetermined interrupt request to each of the target vCPUs. The present disclosure also provides an interrupt processing method, an IPI interrupt manager, an electronic device, and a computer-readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to an interrupt processing method, an interrupt processing method, an IPI interrupt manager, an electronic device, and a computer-readable medium. Background Art

[0002] Virtualization supports running multiple logical hosts (virtual machines) on one physical host, thereby achieving features such as secure isolation and high utilization. A virtual machine can have multiple virtual central processing units (vCPUs) to provide better operating performance. In order to support synchronization between multiple vCPUs, the operating system requires virtualization to provide an inter-processor interrupt (IPI, Inter-Processor Interrupts) mechanism. The IPI mechanism allows one vCPU to send interrupts to multiple vCPUs, which can generally perform operations such as address translation buffer (TLB, Translation Lookaside Buffer) refresh and cross-CPU function calls. It is an important operating mechanism of the operating system.

[0003] However, IPI virtualization operates at a low efficiency. Summary of the invention

[0004] The embodiments of the present disclosure provide an interrupt processing method, an interrupt processing method, an IPI interrupt manager, an electronic device, and a computer-readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides an interrupt processing method, including:

[0006] When the inter-processor interrupt IPI request information is written into the IPI request information area, a predetermined interrupt request is generated according to the IPI request information, the IPI request information carries an identifier of at least one target virtual central processing unit vCPU, wherein the storage space of the current IPI interrupt manager includes at least one IPI request information area, the IPI request information area corresponds to a virtual machine, and the IPI request information area is mapped to the corresponding virtual machine through a memory mapped input and output MMIO;

[0007] The predetermined interrupt request is sent to an interrupt controller, so that the interrupt controller sends the predetermined interrupt request to each of the target vCPUs.

[0008] In a second aspect, an embodiment of the present disclosure provides an interrupt processing method, including:

[0009] When a vCPU initiates an IPI request, the IPI request information is written into an IPI request information area in the storage space of the IPI interrupt manager corresponding to the virtual machine to which the vCPU initiating the IPI request belongs, wherein the IPI request information carries an identifier of at least one target vCPU, wherein the storage space of the IPI interrupt manager includes at least one IPI request information area, and the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO;

[0010] When the target vCPU receives a predetermined interrupt request, an IPI processing operation is called to process the predetermined interrupt request.

[0011] In a third aspect, an embodiment of the present disclosure provides an IPI interrupt manager, including:

[0012] one or more processors;

[0013] A storage device stores one or more programs thereon, and when the one or more programs are executed by the one or more processors, the one or more processors implement the interrupt handling method provided in the first aspect of the embodiment of the present disclosure.

[0014] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including:

[0015] one or more processors;

[0016] A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the interrupt processing method provided in the first aspect of the embodiment of the present disclosure and / or the interrupt processing method provided in the second aspect;

[0017] One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

[0018] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the interrupt handling method provided in the first aspect of the embodiment of the present disclosure and / or the interrupt handling method provided in the second aspect.

[0019] In the disclosed embodiment, the IPI request information area in the storage space of the IPI interrupt manager is mapped to the corresponding virtual machine through the memory mapping input and output MMIO. When the vCPU sends an IPI interrupt, the vCPU can directly write the IPI interrupt request information into the corresponding IPI request information area without exiting the Guest state; the IPI interrupt manager converts the IPI interrupt into a predetermined interrupt that can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state. Based on the hardware interrupt virtualization function provided by the CPU, the IPI interrupt can be directly injected into the target vCPU without the target vCPU exiting the Guest state. Therefore, in the disclosed embodiment, during the process of the vCPU sending the IPI interrupt request information and injecting the IPI interrupt into the target vCPU, the virtual machine does not need to exit the Guest state, which reduces the performance loss caused by the virtualization exit and improves the virtualization operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of existing IPI virtualization;

[0021] Figure 2 This is a flow chart of an interrupt processing method according to an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram of IPI virtualization in an embodiment of the present disclosure;

[0023] Figure 4 It is a flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0024] Figure 5 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0025] Figure 6 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0026] Figure 7 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0027] Figure 8 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0028] Fig. 9 This is a flow chart of an interrupt processing method according to an embodiment of the present disclosure;

[0029] Fig.10 It is a flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0030] Fig.11A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0031] Fig.12 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0032] Fig.13 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0033] Fig.14 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure;

[0034] Fig.15 A flowchart of some steps in another interrupt processing method in an embodiment of the present disclosure

[0035] Fig.16 A schematic diagram of a storage space of an IPI interrupt manager in an embodiment of the present disclosure;

[0036] Fig.17 This is a schematic diagram of IPI virtualization in an embodiment of the present disclosure;

[0037] Fig.18 It is a block diagram of an IPI interrupt manager in an embodiment of the present disclosure;

[0038] Fig.19 is a block diagram of a composition of an electronic device in an embodiment of the present disclosure;

[0039] Fig. 20 The present invention is a block diagram of a computer-readable medium in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the interrupt processing method, interrupt processing method, IPI interrupt manager, electronic device, and computer-readable medium provided by the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0041] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0042] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0043] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0046] Figure 1 FIG. 1 is a schematic diagram of existing IPI virtualization. Figure 1 As shown, when the vCPU sends an IPI interrupt, the interrupt controller can be operated directly; or the virtual machine manager (VMM) can be notified through the VP method, and then the VMM checks the target vCPUs of the IPI interrupt and sends the IPI interrupt one by one. The inventor of the present disclosure has found that the above methods of sending IPI interrupts will cause the virtual machine (VM) to exit the Guest mode and switch to the Host mode.

[0047] In another existing IPI virtualization technology, when the vCPU sends an IPI interrupt, the host is notified of multiple IPI interrupt information of the virtual machine at one time. The inventor of the present disclosure has found that in this existing IPI virtualization technology, although the number of times the VM exits the Guest state is reduced, there is still at least one Guest state exit during the notification process.

[0048] The inventor of the present disclosure believes that a large amount of state saving and switching work needs to be performed when a virtual machine exits, and the saved state needs to be restored when entering the virtualization state again. Therefore, the existing IPI virtualization technology has a large performance loss.

[0049] In view of this, firstly, refer to Figure 2 , the present disclosure provides an interrupt processing method, including:

[0050] In step S110, when the inter-processor interrupt IPI request information is written into the IPI request information area, a predetermined interrupt request is generated according to the IPI request information, the IPI request information carries an identifier of at least one target virtual central processing unit vCPU, wherein the storage space of the current IPI interrupt manager includes at least one IPI request information area, the IPI request information area corresponds to a virtual machine, and the IPI request information area is mapped to the corresponding virtual machine through a memory mapped input and output MMIO;

[0051] In step S120, the predetermined interrupt request is sent to an interrupt controller, so that the interrupt controller sends the predetermined interrupt request to each of the target vCPUs.

[0052] like Figure 3 As shown, an embodiment of the present disclosure provides an IPI interrupt manager, wherein the storage space of the IPI interrupt manager is divided into multiple IPI request information areas, each IPI request information area corresponds to a virtual machine, and is used to store IPI interrupt request information sent by the vCPU of the virtual machine. The IPI interrupt manager triggers an IPI processing action by monitoring the write operation of the virtual machine to the corresponding IPI request information area.

[0053] In the disclosed embodiment, the IPI request information area is mapped to the corresponding virtual machine through memory-mapped I / O (MMIO). It should be noted that MMIO is part of the peripheral component interconnect standard (PCI) specification, and the I / O device is placed in the memory space instead of the I / O space. After completing the MMIO mapping, the CPU can use the instruction to access the memory to access the I / O device. In the disclosed embodiment, the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO, and the MMIO mapping of the IPI request information area and the corresponding virtual machine is completed. The vCPU of the virtual machine can use the instruction of the CPU to access the memory to write the IPI interrupt request information to the corresponding IPI request information area. Therefore, during the notification process of the IPI interrupt, the virtual machine does not need to exit the Guest state.

[0054] It should be noted that, in the embodiment of the present disclosure, the IPI interrupt manager may be implemented based on hardware or software, which is not specifically limited in the embodiment of the present disclosure.

[0055] In step S110, the predetermined interrupt request generated according to the IPI request information written into the IPI request information area satisfies the requirement of being directly injected into the target vCPU without causing the target vCPU to exit the Guest state. As an optional implementation, the predetermined interrupt is an external interrupt, such as a message signaled interrupt (MSI).

[0056] In the embodiment of the present disclosure, based on the hardware interrupt virtualization function provided by the CPU, the IPI interrupt can be directly injected into the target vCPU without the target vCPU exiting the Guest state. For example, on the X86 architecture, the external interrupt is directly processed by the virtual machine based on the VT-D (Virtualization Technology for Direct I / O) mechanism; on the ARM architecture, the external interrupt is directly processed by the virtual machine based on the vGSI mechanism. Therefore, in the embodiment of the present disclosure, by converting the IPI interrupt request into a predetermined interrupt request that can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state, the virtual machine does not need to exit the Guest state when the IPI interrupt is injected into the target vCPU.

[0057] In the interrupt processing method provided by the embodiment of the present disclosure, an IPI interrupt manager is provided, and the IPI request information area in the storage space of the IPI interrupt manager is mapped to the corresponding virtual machine through the memory mapping input and output MMIO. When the vCPU sends an IPI interrupt, the vCPU can directly write the IPI interrupt request information into the corresponding IPI request information area without exiting the Guest state; the IPI interrupt manager converts the IPI interrupt into a predetermined interrupt that can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state. Based on the hardware interrupt virtualization function provided by the CPU, the IPI interrupt can be directly injected into the target vCPU without the target vCPU exiting the Guest state. Therefore, in the embodiment of the present disclosure, in the process of the vCPU sending the IPI interrupt request information and injecting the IPI interrupt into the target vCPU, the virtual machine does not need to exit the Guest state, which reduces the performance loss caused by the virtualization exit and improves the virtualization operation efficiency.

[0058] As an optional implementation, on the X86 architecture, the MSI interrupt is injected into the target vCPU based on the VT-D mechanism, so that the virtual machine can respond to the interrupt without exiting the Guest state.

[0059] In the X86 architecture, the interrupt controller is an Advanced Programmable Interrupt Controller (APIC), which includes two parts: IO-APIC and Local-APIC. Among them, IO-APIC is unique in the system and is used to manage the forwarding of external MSI interrupts to Local-APIC; each CPU has a Local-APIC, which is used to manage the sending of MSI interrupts routed from IO-APIC to the corresponding CPU, and also manages the sending of IPI interrupts. In the interrupt virtualization scenario, IO-APIC supports remapping mode (reMapping), and manages the interrupt remapping table in IO-APIC, which includes interrupt remapping table entries of multiple physical central processing units pCPU. If it is identified that the MSI interrupt sent by the device is a remapping mode and a posted type interrupt (Posted-Interrupt), the corresponding interrupt remapping table entry in the interrupt remapping table is searched according to the information carried in the MSI interrupt, the notification vector (Notify Vector) corresponding to the MSI interrupt is determined, and then the interrupt is sent to Local-APIC. If the corresponding target vCPU has been scheduled, Local-APIC will directly send an interrupt to the target vCPU. If the corresponding target vCPU has not been scheduled, VMM will be notified for processing.

[0060] As an optional implementation, in step S110, the IPI interrupt is converted into an MSI interrupt, and the type of the MSI interrupt is a posted interrupt in a remapping manner, so that the virtual machine does not need to exit the Guest state when the IPI interrupt is injected into the target vCPU.

[0061] Accordingly, refer to Figure 4 In some embodiments, step S110 includes:

[0062] In step S111, a message signal interrupt MSI request is generated as the predetermined interrupt request according to the IPI request information, and the type of the MSI request is a post-interrupt of a remapping mode.

[0063] It should be noted that in the disclosed embodiment, there is an MSI configuration register in the configuration space of the IPI interrupt manager. By setting the content of the MSI setting register, the type of the MSI generated in the IPI interrupt manager can be configured as a release type interrupt in a remapping manner.

[0064] As an optional implementation, in the disclosed embodiment, the VMM configures the Posted-Interrupt attribute for the IPI interrupt manager. That is, by writing configuration content into the MSI configuration register of the IPI interrupt manager, the Posted-Interrupt attribute is configured for the IPI interrupt manager, so that the type of the MSI generated in the IPI interrupt manager is a posting type interrupt in a remapped manner.

[0065] In the disclosed embodiment, the VMM allocates an interrupt remapping table entry (IRTE, InterruptRemap Table Entry) to each pCPU, that is, the interrupt remapping table entry of the pCPU in the interrupt remapping table managed by the IO-APIC. In the disclosed embodiment, the storage space of the IPI interrupt manager also includes a pCPU information area, in which the pCPUID and the IRTE index corresponding to the pCPU are stored. When the MSI request information is generated through step S111, the MSI request is generated according to the IRTE index corresponding to the target vCPU and the IPI vector to be sent, and the MSI request is sent to the IO-APIC, so that the IO-APIC sends the interrupt to the corresponding Local-APIC by searching the interrupt remapping table, and further injects it into the scheduled target vCPU.

[0066] In the disclosed embodiment, the storage space of the IPI interrupt manager includes a plurality of vCPU scheduling information areas, the plurality of vCPU scheduling information areas correspond to a plurality of vCPUs one by one, and the vCPU scheduling information area stores the identifier of the pCPU that schedules the corresponding vCPU. After the IPI interrupt request information is written into the IPI interrupt request information area, the identifier of the pCPU that schedules the target vCPU is read from the vCPU scheduling information area corresponding to the target vCPU according to the identifier of the target vCPU.

[0067] Accordingly, refer to Figure 5 In some embodiments, the IPI request information carries an interrupt number vector, and step S111 includes:

[0068] In step S111a, the identifier of the target pCPU stored in the vCPU scheduling information area corresponding to the target vCPU is read, the target pCPU is the pCPU that schedules the target vCPU, wherein the storage space of the current IPI interrupt manager includes multiple vCPU scheduling information areas, the multiple vCPU scheduling information areas correspond one-to-one to multiple vCPUs, and the vCPU scheduling information area stores the identifier of the pCPU that schedules the corresponding vCPU;

[0069] In step S111b, the interrupt remapping table entry index corresponding to the target pCPU is read from the pCPU information area according to the identifier of the target pCPU, wherein the pCPU information area in the storage space of the current IPI interrupt manager stores a correspondence between multiple pCPU identifiers and interrupt remapping table entry indexes;

[0070] In step S111c, the MSI request is generated according to the interrupt remapping table entry index corresponding to each target pCPU and the vector carried by the IPI request information.

[0071] In the disclosed embodiment, when the target vCPU is scheduled, the IPI interrupt manager generates a scheduled interrupt request and directly sends the scheduled interrupt to the target vCPU through the interrupt controller; when the target vCPU is not scheduled, the IPI interrupt manager notifies the VMM to process the IPI request.

[0072] Accordingly, refer to Figure 6 In some embodiments, when the IPI request information area writes the inter-processor interrupt IPI request information, before step S110, the interrupt processing method further includes:

[0073] In step S130, the scheduling state of the target vCPU is determined according to the identifier of the target vCPU;

[0074] When the target vCPU is scheduled, step S110 is executed.

[0075] The storage space of the IPI interrupt manager of the embodiment of the present disclosure also includes a to-be-sent IPI request vCPU set data area for storing the to-be-sent IPI request vCPU set, and a to-be-sent IPI request VM set data area for storing the to-be-sent IPI request vCPU to which the to-be-sent IPI request vCPU belongs. The to-be-sent IPI request vCPU set refers to the set of vCPUs that initiate the IPI request, and the to-be-sent IPI request vCPU to which the VM set refers to the set of VMs to which the to-be-sent IPI request vCPU belongs.

[0076] When it is necessary to notify the VMM to process an IPI request, the IPI interrupt manager writes the identification information of the vCPU to which the IPI request is to be sent into the vCPU set data area of ​​the IPI request to be sent, writes the identification information of the virtual machine to which the vCPU to which the IPI request is to be sent belongs into the VM set data area of ​​the IPI request to be sent, and sends a VMM notification interrupt, which can wake up the VMM to process the IPI request.

[0077] Accordingly, refer to Figure 6 , when the target vCPU is not scheduled, the interrupt processing method includes:

[0078] In step S141, the identification information of the vCPU that initiates the IPI request is written into the data area of ​​the vCPU set of IPI requests to be sent in the storage space of the current IPI interrupt manager;

[0079] In step S142, the identification information of the virtual machine to which the vCPU that initiates the IPI request belongs is written into the IPI request VM set data area to be sent in the storage space of the current IPI interrupt manager;

[0080] In step S143, a VMM notification interrupt is sent according to a preset vector of the virtual machine manager VMM notification interrupt.

[0081] It should be noted that the vCPU that initiates the IPI request is the vCPU that writes the IPI request information into the IPI request information area.

[0082] It should be noted that in the embodiments of the present disclosure, by binding the vCPU and the pCPU, the vCPU can be scheduled in most cases, thereby ensuring that the virtual machine does not need to exit the Guest state during the notification process of the IPI request in most cases.

[0083] In the disclosed embodiment, the bits of the vCPU set data area of ​​the IPI request to be sent correspond one-to-one to the vCPU, and the bit position of the vCPU set data area of ​​the IPI request to be sent indicates that the corresponding vCPU has an IPI request to be sent; the bits of the VM set data area of ​​the IPI request to be sent correspond one-to-one to the virtual machine, and the bit position of the VM set data area of ​​the IPI request to be sent indicates that the vCPU in the corresponding virtual machine has an IPI request to be sent.

[0084] Accordingly, refer to Figure 7 In some embodiments, step S141 includes:

[0085] In step S141a, the corresponding bit of the vCPU data area of ​​the to-be-sent IPI request is set with the identifier of the vCPU that initiates the IPI request as an offset;

[0086] Step S142 includes:

[0087] In step S142a, the corresponding bit of the VM set data area of ​​the to-be-sent IPI request is set according to the identifier of the virtual machine to which the vCPU that initiates the IPI request belongs.

[0088] In the disclosed embodiment, the VMM obtains the physical first address of the storage space of the IPI interrupt manager during initialization, and applies to the IPI interrupt manager for the IPI request information area when creating a virtual machine. The IPI interrupt manager allocates the IPI request information area to the virtual machine and returns the index number of the allocated IPI request information area. The address of the IPI request information area corresponding to the virtual machine can be determined by the index number and the physical first address of the storage space of the IPI interrupt manager obtained by the VMM during initialization.

[0089] Accordingly, refer to Figure 8 In some embodiments, the interrupt processing method further includes:

[0090] In step S151, in response to a message requesting an IPI request information area, an IPI request information area is allocated to a target virtual machine;

[0091] In step S152, the index number of the IPI request information area allocated to the target virtual machine is returned.

[0092] Second, refer to Fig. 9 , the present disclosure provides an interrupt processing method, including:

[0093] In step S210, when the vCPU initiates an IPI request, the IPI request information is written into an IPI request information area in the storage space of the IPI interrupt manager corresponding to the virtual machine to which the vCPU belongs, wherein the IPI request information carries an identifier of at least one target vCPU, wherein the storage space of the IPI interrupt manager includes at least one IPI request information area, and the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO;

[0094] In step S220, when the target vCPU receives a predetermined interrupt request, an IPI processing operation is called to process the predetermined interrupt request.

[0095] It should be noted that step S210 is executed by the host Host when any virtual machine initiates an IPI request, and step S220 is executed by the host Host when any virtual machine receives a predetermined interrupt request.

[0096] The embodiment of the present disclosure provides an IPI interrupt manager, wherein the storage space of the IPI interrupt manager is divided into multiple IPI request information areas, each IPI request information area corresponds to a virtual machine, and is used to store IPI interrupt request information sent by the vCPU of the virtual machine. The IPI interrupt manager triggers an IPI processing action by monitoring the write operation of the virtual machine to the corresponding IPI request information area.

[0097] In the disclosed embodiment, the IPI request information area is mapped to the corresponding virtual machine through memory-mapped I / O (MMIO). After the MMIO mapping is completed, the CPU can use the instruction to access the memory to access the I / O device. In the disclosed embodiment, the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO, and the MMIO mapping of the IPI request information area and the corresponding virtual machine is completed. The vCPU of the virtual machine can use the instruction of the CPU to access the memory to write the IPI interrupt request information to the corresponding IPI request information area. Therefore, during the notification process of the IPI interrupt, the virtual machine does not need to exit the Guest state.

[0098] It should be noted that the predetermined interrupt request in step S220 satisfies the requirement of being directly injected into the target vCPU without causing the target vCPU to exit the Guest state. As an optional implementation, the predetermined interrupt request is an MSI request, and the type of the MSI request is a Posted-Interrupt interrupt in a remapped manner.

[0099] In the embodiment of the present disclosure, the predetermined interrupt request received by the vCPU is processed as an IPI interrupt, that is, in step S220, when the predetermined interrupt request is received, the IPI processing operation is called to process the predetermined interrupt request.

[0100] It should be noted that the predetermined interrupt request received by the target vCPU is directly injected into the target vCPU based on the hardware interrupt virtualization function provided by the CPU, and the target vCPU does not need to exit the Guest state. Therefore, in the embodiment of the present disclosure, the current vCPU does not need to exit the Guest state when receiving the IPI interrupt.

[0101] In the interrupt processing method provided by the embodiment of the present disclosure, an IPI interrupt manager is provided, and the IPI request information area in the storage space of the IPI interrupt manager is mapped to the corresponding virtual machine through the memory mapping input and output MMIO. When the vCPU sends an IPI interrupt, the vCPU can directly write the IPI interrupt request information into the corresponding IPI request information area without exiting the Guest state; the IPI interrupt manager converts the IPI interrupt into a predetermined interrupt that can be directly injected into the target vCPU without causing the target vCPU to exit the Guest state. Based on the hardware interrupt virtualization function provided by the CPU, the IPI interrupt can be directly injected into the target vCPU, and the target vCPU does not need to exit the Guest state when receiving the IPI interrupt. Therefore, in the embodiment of the present disclosure, in the process of the vCPU sending the IPI interrupt request information and injecting the IPI interrupt into the target vCPU, the virtual machine does not need to exit the Guest state, which reduces the performance loss caused by the virtualization exit and improves the virtualization operation efficiency.

[0102] In the disclosed embodiment, corresponding to the multiple vCPUs of the virtual machine, the IPI request information area in the storage space of the IPI interrupt manager is further divided to obtain multiple IPI request information memory blocks corresponding to the vCPUs. When the vCPU sends an IPI request, the IPI request information is written into the corresponding IPI request information memory block.

[0103] Accordingly, refer to Fig.10 In some embodiments, step S210 includes:

[0104] In step S211, the IPI request information is written into the IPI request information memory block corresponding to the vCPU that initiates the IPI request, wherein the IPI request information area corresponding to each virtual machine includes multiple IPI request information memory blocks, and the IPI request information memory blocks correspond one-to-one to the vCPUs in the virtual machines.

[0105] In the disclosed embodiment, a virtual machine is created by a VMM. When creating a virtual machine, the VMM will apply to the IPI interrupt manager for the IPI request information area corresponding to the virtual machine to be created, and after the virtual machine is created, the MMIO mapping between the virtual machine and the corresponding IPI request information area is completed. Among them, the IPI interrupt manager allocates an IPI request information area to the virtual machine and returns the index number of the allocated IPI request information area. The physical address of the IPI request information area corresponding to the virtual machine can be determined by the index number and the physical first address of the storage space of the IPI interrupt manager obtained by the VMM during initialization. As an optional implementation method, the index number is used as the identifier of the virtual machine to be created.

[0106] Accordingly, refer to Fig.11In some embodiments, before step S210, the interrupt processing method further includes:

[0107] In step S230, a message for applying for an IPI request information area is sent to the IPI interrupt manager;

[0108] In step S240, a target virtual machine is created, where the identifier of the target virtual machine is the index number of the IPI request information area returned by the IPI interrupt manager and allocated to the target virtual machine;

[0109] In step S250, the IPI request information area allocated to the target virtual machine is mapped to the target virtual machine through MMIO.

[0110] As an optional implementation, the IPI interrupt manager in the embodiment of the present disclosure exists as a PCI device. In the embodiment of the present disclosure, corresponding to the IPI interrupt manager existing as an IPI device, a virtual PCI device is created, and the base address register of the virtual PCI device stores the physical first address of the IPI request information area assigned to the virtual machine as the base address. The virtual machine writes the IPI request information into the IPI request information area in the IPI interrupt manager by communicating with the virtual PCI device.

[0111] Accordingly, refer to Fig.12 In some embodiments, step S250 includes:

[0112] In step S251, the physical address of the IPI request information area allocated to the target virtual machine is determined according to the received index number of the IPI request information area allocated to the target virtual machine and the physical first address of the storage space of the IPI interrupt manager;

[0113] In step S252, a virtual PCI device is created, wherein a base address register BAR of the virtual PCI device stores a physical first address of an IPI request information area allocated to the target virtual machine;

[0114] In step S253, a virtual PCI device driver is created.

[0115] In the disclosed embodiment, the IPI interrupt manager converts the IPI interrupt into an MSI interrupt, and the type of the MSI interrupt is a release type interrupt in a remapping manner, so that the virtual machine does not need to exit the Guest state when the IPI interrupt is injected into the target vCPU. It should be noted that in the disclosed embodiment, there is an MSI configuration register in the configuration space of the IPI interrupt manager, and by setting the content of the MSI configuration register, the type of the MSI generated in the IPI interrupt manager can be configured as a release type interrupt in a remapping manner.

[0116] As an optional implementation, in the disclosed embodiment, the VMM configures the Posted-Interrupt attribute for the IPI interrupt manager. That is, by writing configuration content into the MSI configuration register of the IPI interrupt manager, the Posted-Interrupt attribute is configured for the IPI interrupt manager, so that the type of the MSI generated in the IPI interrupt manager is a posting type interrupt in a remapped manner.

[0117] In the disclosed embodiment, the VMM allocates an interrupt remapping table entry (IRTE) to each pCPU, that is, the interrupt remapping table entry of the pCPU in the interrupt remapping table managed by the IO-APIC. In the disclosed embodiment, the storage space of the IPI interrupt manager also includes a pCPU information area, in which the pCPUID and the IRTE index corresponding to the pCPU are stored.

[0118] Accordingly, refer to Fig.13 In some embodiments, before step S210, the interrupt processing method further includes:

[0119] In step S260, an interrupt remapping table entry IRTE is allocated to each physical central processing unit pCPU;

[0120] In step S270, a Posted Interrupt attribute is configured for the IPI interrupt manager;

[0121] In step S280, the pCPU identifier and the IRTE index corresponding to the pCPU are written into the pCPU information area in the storage space of the IPI interrupt manager.

[0122] In the disclosed embodiment, the storage space of the IPI interrupt manager includes multiple vCPU scheduling information areas, the multiple vCPU scheduling information areas correspond to multiple vCPUs one by one, and the vCPU scheduling information area stores the identifier of the pCPU that schedules the corresponding vCPU. In the disclosed embodiment, the VMM writes the scheduling information of the vCPU into the corresponding vCPU scheduling information area.

[0123] Accordingly, refer to Fig.14 In some embodiments, the interrupt processing method further includes:

[0124] In step S290, when scheduling a vCPU, the identifier of the pCPU that schedules the vCPU is written into the vCPU scheduling information area corresponding to the scheduled vCPU, wherein the storage space of the IPI interrupt manager includes multiple vCPU scheduling information areas, and the multiple vCPU scheduling information areas correspond one-to-one to multiple vCPUs.

[0125] It should be noted that, in the embodiment of the present disclosure, the vCPU scheduling information area is mapped into the host host memory, so that it can be directly accessed by the VMM.

[0126] In the disclosed embodiment, when the target vCPU is scheduled, the IPI interrupt manager generates a scheduled interrupt request and directly sends the scheduled interrupt to the target vCPU through the interrupt controller; when the target vCPU is not scheduled, the IPI interrupt manager notifies the VMM to process the IPI request.

[0127] The storage space of the IPI interrupt manager of the embodiment of the present disclosure also includes a to-be-sent IPI request vCPU set data area for storing the to-be-sent IPI request vCPU set, and a to-be-sent IPI request VM set data area for storing the to-be-sent IPI request vCPU to which the to-be-sent IPI request vCPU belongs. The to-be-sent IPI request vCPU set refers to the set of vCPUs that initiate the IPI request, and the to-be-sent IPI request vCPU to which the to-be-sent VM set belongs refers to the set of virtual machines to which the to-be-sent IPI request vCPU belongs.

[0128] When it is necessary to notify the VMM to process an IPI request, the IPI interrupt manager writes the identification information of the vCPU to which the IPI request is to be sent into the vCPU set data area of ​​the IPI request to be sent, writes the identification information of the virtual machine to which the vCPU to which the IPI request is to be sent belongs into the VM set data area of ​​the IPI request to be sent, and sends a VMM notification interrupt, which can wake up the VMM to process the IPI request. The VMM determines the virtual machine to which the vCPU to which the IPI request is to be sent belongs by reading the VM set data area of ​​the IPI request to be sent, and determines the vCPU to which the IPI request is to be sent by reading the vCPU set data area of ​​the IPI request to be sent. Then, the corresponding IPI request information is read from the IPI request information area corresponding to the vCPU to which the IPI request is to be sent, and the IPI interrupt is sent.

[0129] Accordingly, refer to Fig.15 In some embodiments, the interrupt processing method further includes:

[0130] In step S310, in response to the VMM notification interrupt sent by the IPI interrupt manager, the VM set data area of ​​the to-be-sent IPI request in the storage space of the IPI interrupt manager is read to determine the identifier of the virtual machine to which the vCPU to which the to-be-sent IPI request belongs belongs;

[0131] In step S320, the vCPU set data area of ​​the IPI request to be sent in the storage space of the IPI interrupt manager is read to determine the identifier of the vCPU to which the IPI request is to be sent;

[0132] In step S330, according to the identifier of the virtual machine to which the vCPU to which the IPI request is to be sent belongs and the identifier of the vCPU to which the IPI request is to be sent, the IPI request information memory block corresponding to the vCPU to which the IPI request is to be sent is read to obtain the IPI request information;

[0133] In step S340, an IPI request is sent according to the acquired IPI request information.

[0134] In the disclosed embodiment, the bits of the vCPU set data area of ​​the IPI request to be sent correspond to the vCPUs one by one, and the bit positions of the vCPU set data area of ​​the IPI request to be sent indicate that the corresponding vCPU has an IPI request to be sent; the bits of the VM set data area of ​​the IPI request to be sent correspond to the VMs one by one, and the bit positions of the VM set data area of ​​the IPI request to be sent indicate that the vCPU in the corresponding VM has an IPI request to be sent. Accordingly, the VMM determines the virtual machine to which the vCPU with the IPI request to be sent belongs by reading the bits of the VM set data area of ​​the IPI request to be sent, and determines the vCPU with the IPI request to be sent by reading the bits of the vCPU set data area of ​​the IPI request to be sent.

[0135] Accordingly, in the embodiment of the present disclosure, after the VMM completes sending the IPI interrupt, the process further includes:

[0136] Restoring the bits in the VM set data area of ​​the IPI request to be sent to an initial state;

[0137] The bits in the vCPU set data area of ​​the IPI request to be sent are restored to their initial state.

[0138] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific embodiments:

[0139] Embodiment 1

[0140] Fig.16 It is a schematic diagram of the storage space of the IPI interrupt manager described in the embodiment of the present disclosure.

[0141] like Fig.16 As shown, in the storage space of the IPI interrupt manager, different virtual machines have independent IPI interrupt information storage spaces, and each IPI interrupt information storage space includes:

[0142] The IPI interrupt request information area is 4K page aligned. Each IPI interrupt request information area is divided into multiple IPI request information memory blocks, and multiple IPI request information memory blocks correspond one-to-one to each vCPU in the VM. In the first embodiment, each IPI request information memory block is 32 bits, including 16 bits of IPI target vCPU information and 16 bits of IPI interrupt vector number. The IPI interrupt request information area is mapped to the corresponding VM through MMIO and can be written directly by the vCPU;

[0143] The vCPU status information area includes the vCPU scheduling information area and the vCPU set data area for IPI requests to be sent. The vCPU scheduling information area stores the corresponding relationship between vCPU and pCPU; the vCPU set data area for IPI requests to be sent stores the vCPU ID waiting to send IPI. The vCPU status information area is mapped into the Host memory and can be directly accessed by the VMM;

[0144] pCPU information data area, including pCPU ID and the index idx of the IRTE assigned to the Posted Interrupt;

[0145] VMM notification interrupt vector data area, used to store the interrupt number of VMM notification interrupt;

[0146] The VM set data area for the IPI request to be sent indicates in bit form the VM to which the vCPU to which the IPI information is to be sent belongs.

[0147] In the first embodiment, the pCPU information data area, the VMM notification interrupt vector data area, and the to-be-sent IPI request VM set data area can only be accessed by the host VMM.

[0148] Embodiment 2

[0149] This second embodiment provides a process for initializing the host VMM.

[0150] When VMM is initialized, it reads PCI control information, obtains the physical first address of the storage space of the IPI interrupt manager, and completes MMIO mapping;

[0151] The VMM allocates and sets the VMM notification interrupt. The IPI interrupt manager can wake up the VMM by sending the VMM notification interrupt.

[0152] VMM sets the Posted Interrupt interrupt, and the setting method is as follows:

[0153] Traverse all pCPUs;

[0154] Assign an IRTE to each pCPU and set it as the attribute of Posted Interrupt, and set its delivery target pCPU;

[0155] The pCPU ID and the corresponding IRTE index are written into the pCPU information area of ​​the IPI interrupt manager.

[0156] Embodiment 3

[0157] This third embodiment provides a VM creation process.

[0158] After receiving the virtual machine creation command, the VMM applies for a new virtual machine IPI request information area from the IPI interrupt manager;

[0159] The VMM creates a VM and an IPI virtual PCI device, and the BAR address space of the virtual PCI device is set to the newly allocated IPI request information area address.

[0160] When the virtual machine starts, it creates an IPI driver, obtains the address of the IPI request information area corresponding to the virtual machine from the virtual PCI device, and completes the MMIO mapping, which is actually mapped to the corresponding IPI request information area. Subsequently, the IPI driver can write directly through the virtual address space GVA to complete the IPI interrupt request. Since each VM can only map its own corresponding IPI request information area, the IPI requests of different VMs will not affect other VMs, supporting the security isolation feature.

[0161] Embodiment 4

[0162] Reference Fig.17 When the VMM schedules the vCPU of a VM to run, it performs the following operations:

[0163] According to the VM ID and vCPU ID, locate the corresponding vCPU scheduling information area;

[0164] Write the pCPU ID that the vCPU will schedule to run into the corresponding vCPU scheduling information area;

[0165] When a vCPU is called out, a value of -1 is written to the corresponding vCPU scheduling information area.

[0166] Embodiment 5

[0167] Reference Fig.17 , this embodiment 5 provides an IPI interrupt sending and processing process.

[0168] The vCPU calls the IPI driver to send an IPI interrupt. The IPI driver obtains the vCPU ID, determines the IPI request information area corresponding to the vCPU, and writes the destination vCPU and IPI vector of the IPI into the IPI request information area.

[0169] The write operation of the IPI request information area triggers the IPI interrupt manager, which analyzes the IPI request information written into the IPI request information area, determines the target vCPU set of the IPI interrupt, and checks the vCPU status information area to determine the scheduling status of the target vCPU;

[0170] If all target vCPUs are in the scheduling state, the IRTE idx of posted int. and the IPI vector to be sent will be obtained according to the pCPU information corresponding to the target vCPU, assembled into interrupt request information, and the scheduled interrupt request will be sent to the interrupt controller. The interrupt request has been set as the Posted Interrupt of Remapping and will be directly sent to the corresponding target pCPU to complete the interrupt sending;

[0171] If there is an unscheduled vCPU, the IPI interrupt manager sets the corresponding bit of the vCPU set data area of ​​the IPI request to be sent with the corresponding vCPU ID as the offset, and uses the VM ID to set the corresponding bit of the VM set data area of ​​the IPI request to be sent, and sends the VMM notification interrupt according to the set VMM notification interrupt vector; the VMM will read the VM set data area of ​​the IPI request to be sent, obtain the corresponding VM ID, and then read the vCPU set data area of ​​the IPI request to be sent of the corresponding VM, and for the bit therein, read the IPI request information area corresponding to the vCPU, obtain the IPI request information, and then complete the IPI interrupt sending one by one.

[0172] Thirdly, refer to Fig.18 The present disclosure provides an IPI interrupt manager, which includes:

[0173] One or more processors 101;

[0174] A memory 102, on which one or more programs are stored. When the one or more programs are executed by one or more processors, the one or more processors implement the interrupt processing method provided by the first aspect of the embodiment of the present disclosure;

[0175] One or more I / O interfaces 103 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0176] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU) and the like; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus) and the like.

[0177] In some embodiments, the processor 101 , the memory 102 , and the I / O interface 103 are connected to each other via a bus 104 , and further connected to other components of the computing device.

[0178] The interrupt handling method provided by the first aspect of the embodiment of the present disclosure has been described in detail above and will not be repeated here.

[0179] Fourthly, refer to Fig.19 , an embodiment of the present disclosure provides an electronic device, comprising:

[0180] One or more processors 201;

[0181] A memory 202 on which one or more programs are stored. When the one or more programs are executed by one or more processors, the one or more processors implement the interrupt processing method provided in the first aspect of the embodiment of the present disclosure and / or the interrupt processing method provided in the second aspect;

[0182] One or more I / O interfaces 203 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0183] Among them, the processor 201 is a device with data processing capabilities, including but not limited to a central processing unit (CPU) and the like; the memory 202 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 203 is connected between the processor 201 and the memory 202, and can realize information interaction between the processor 201 and the memory 202, including but not limited to a data bus (Bus) and the like.

[0184] In some embodiments, the processor 201 , the memory 202 , and the I / O interface 203 are connected to each other via a bus 204 , and further connected to other components of the computing device.

[0185] The interrupt handling method provided in the first aspect and the interrupt handling method provided in the second aspect of the embodiment of the present disclosure have been described in detail above and will not be repeated here.

[0186] Fifth, refer to Fig. 20 An embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the interrupt processing method provided in the first aspect of the embodiment of the present disclosure and / or the interrupt processing method provided in the second aspect are implemented.

[0187] The interrupt handling method provided in the first aspect and the interrupt handling method provided in the second aspect of the embodiment of the present disclosure have been described in detail above and will not be repeated here.

[0188] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0189] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. An interrupt processing method, comprising: When IPI request information is written into the inter-processor interrupt IPI request information area, a predetermined interrupt request is generated according to the IPI request information, the IPI request information carries an identifier of at least one target virtual central processing unit vCPU, wherein the storage space of the current IPI interrupt manager includes at least one IPI request information area, the IPI request information area corresponds to a virtual machine, and the IPI request information area is mapped to the corresponding virtual machine through a memory mapped input and output MMIO; The predetermined interrupt request is sent to an interrupt controller so that the interrupt controller sends the predetermined interrupt request to each target vCPU; the predetermined interrupt request is used to instruct the interrupt controller to inject the predetermined interrupt request into each target vCPU based on a hardware interrupt virtualization function.

2. The interrupt processing method according to claim 1, wherein: The step of generating a predetermined interrupt request according to the IPI request information comprises: A message signal interrupt MSI request is generated as the predetermined interrupt request according to the IPI request information, and the type of the MSI request is a Posted-Interrupt of a remapping mode.

3. The interrupt processing method according to claim 2, wherein: The IPI request information carries an interrupt number vector, and the step of generating a message signal interrupt MSI request according to the IPI request information includes: Reading the identifier of the target physical central processing unit pCPU stored in the vCPU scheduling information area corresponding to the target vCPU, the target pCPU is the pCPU that schedules the target vCPU, wherein the storage space of the current IPI interrupt manager includes multiple vCPU scheduling information areas, the multiple vCPU scheduling information areas correspond one-to-one to the multiple vCPUs, and the vCPU scheduling information area stores the identifier of the pCPU that schedules the corresponding vCPU; Reading an interrupt remapping table entry index corresponding to the target pCPU from a pCPU information area according to the target pCPU identifier, wherein the pCPU information area in the storage space of the current IPI interrupt manager stores a correspondence between multiple pCPU identifiers and interrupt remapping table entry indexes; The MSI request is generated according to the interrupt remapping table entry index corresponding to each target pCPU and the vector carried by the IPI request information.

4. The interrupt processing method according to any one of claims 1 to 3, wherein: When the IPI request information area is written with the IPI request information, before the step of generating a predetermined interrupt request according to the IPI request information, the interrupt processing method further includes: Determine the scheduling state of the target vCPU according to the identifier of the target vCPU; When the target vCPU is scheduled, a step of generating a predetermined interrupt request according to the IPI request information is executed.

5. The interrupt processing method according to claim 4, wherein: When the target vCPU is not scheduled, the interrupt processing method includes: Write the identification information of the vCPU that initiates the IPI request into the vCPU set data area of ​​the IPI request to be sent in the storage space of the current IPI interrupt manager; Write the identification information of the virtual machine to which the vCPU initiating the IPI request belongs into the IPI request VM set data area to be sent in the storage space of the current IPI interrupt manager; Send a VMM notification interrupt according to the preset virtual machine manager VMM notification interrupt vector.

6. The interrupt processing method according to claim 5, wherein: The step of writing the identification information of the vCPU that initiates the IPI request into the data area of ​​the vCPU set of IPI requests to be sent in the storage space of the current IPI interrupt manager includes: Using the identifier of the vCPU that initiates the IPI request as an offset, setting the corresponding bit of the vCPU set data area of ​​the IPI request to be sent, wherein the bit of the vCPU set data area of ​​the IPI request to be sent corresponds to the vCPU one-to-one, and the bit position of the vCPU set data area of ​​the IPI request to be sent indicates that the corresponding vCPU has an IPI request to be sent; The step of writing the identification information of the virtual machine to which the vCPU initiating the IPI request belongs into the IPI request VM set data area to be sent in the storage space of the current IPI interrupt manager includes: The corresponding bit of the VM set data area of ​​the IPI request to be sent is set according to the identifier of the virtual machine to which the vCPU that initiates the IPI request belongs, wherein the bit of the VM set data area of ​​the IPI request to be sent corresponds one-to-one to the virtual machine, and the bit position of the VM set data area of ​​the IPI request to be sent indicates that the vCPU in the corresponding virtual machine has an IPI request to be sent.

7. The interrupt processing method according to any one of claims 1 to 3, wherein: The interrupt processing method further includes: In response to the message for applying for the IPI request information area, allocating the IPI request information area for the target virtual machine; Returns the index number of the IPI request information area allocated to the target virtual machine.

8. An interrupt processing method, comprising: When a vCPU initiates an IPI request, the IPI request information is written into an IPI request information area in the storage space of the IPI interrupt manager corresponding to the virtual machine to which the vCPU initiating the IPI request belongs, wherein the IPI request information carries an identifier of at least one target vCPU, wherein the storage space of the IPI interrupt manager includes at least one IPI request information area, and the physical address of the IPI request information area is mapped to the corresponding virtual machine through MMIO; When the target vCPU receives a predetermined interrupt request sent by the interrupt controller, an IPI processing operation is called to process the predetermined interrupt request; the predetermined interrupt request is used to instruct the interrupt controller to inject the predetermined interrupt request into the target vCPU based on the hardware interrupt virtualization function.

9. The interrupt processing method according to claim 8, wherein: The step of writing the IPI request information into the IPI request information area in the storage space of the IPI interrupt manager corresponding to the virtual machine to which the vCPU that initiates the IPI request belongs comprises: The IPI request information is written into the IPI request information memory block corresponding to the vCPU initiating the IPI request, wherein the IPI request information area corresponding to each virtual machine includes multiple IPI request information memory blocks, and the IPI request information memory blocks correspond one-to-one to the vCPUs in the virtual machines.

10. The interrupt processing method according to claim 8 or 9, wherein: Before the step of writing the IPI request information into the IPI request information area in the storage space of the IPI interrupt manager corresponding to the virtual machine to which the vCPU that initiates the IPI request belongs, the interrupt processing method further includes: Sending a message for applying for an IPI request information area to the IPI interrupt manager; Creating a target virtual machine, where the identifier of the target virtual machine is the index number of the IPI request information area returned by the IPI interrupt manager and allocated to the target virtual machine; The IPI request information area allocated to the target virtual machine is mapped to the target virtual machine through MMIO.

11. The interrupt processing method according to claim 10, wherein: The step of mapping the IPI request information area allocated to the target virtual machine to the target virtual machine through MMIO comprises: Determine the physical first address of the IPI request information area assigned to the target virtual machine according to the received index number of the IPI request information area assigned to the target virtual machine and the physical first address of the storage space of the IPI interrupt manager; Creating a virtual peripheral component interconnect standard PCI device, wherein a base address register BAR of the virtual PCI device stores a physical first address of an IPI request information area allocated to the target virtual machine; Create a virtual PCI device driver.

12. The interrupt processing method according to claim 8 or 9, wherein: The interrupt processing method further includes: Allocate interrupt remapping table entry IRTE to each physical central processor pCPU; Configuring a Posted-Interrupt attribute for the IPI interrupt manager; The identification of the pCPU and the IRTE index corresponding to the pCPU are written into the pCPU information area in the storage space of the IPI interrupt manager.

13. The interrupt processing method according to claim 8 or 9, wherein: The interrupt processing method further includes: When scheduling a vCPU, the identifier of the pCPU that schedules the vCPU is written into the vCPU scheduling information area corresponding to the scheduled vCPU, wherein the storage space of the IPI interrupt manager includes multiple vCPU scheduling information areas, and the multiple vCPU scheduling information areas correspond one-to-one to multiple vCPUs.

14. The interrupt processing method according to claim 8, wherein: The interrupt processing method further includes: In response to the VMM notification interrupt sent by the IPI interrupt manager, read the IPI request VM set data area to be sent in the storage space of the IPI interrupt manager to determine the identifier of the virtual machine to which the vCPU that initiates the IPI request belongs; Reading the vCPU set data area of ​​the IPI request to be sent in the storage space of the IPI interrupt manager to determine the identifier of the vCPU that initiates the IPI request; According to the identifier of the virtual machine to which the vCPU that initiates the IPI request belongs and the identifier of the vCPU that initiates the IPI request, read the IPI request information memory block corresponding to the vCPU that initiates the IPI request to obtain the IPI request information; Send an IPI request according to the obtained IPI request information.

15. An IPI interrupt manager, comprising: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the interrupt processing method according to any one of claims 1 to 7.

16. An electronic device, comprising: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the interrupt processing method according to any one of claims 1 to 7 and / or the interrupt processing method according to any one of claims 8 to 14; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

17. A computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the interrupt processing method according to any one of claims 1 to 7 and / or the interrupt processing method according to any one of claims 8 to 14 is implemented.

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