Display device

Abstract

The display device includes: a substrate including a plurality of pixel areas and non-pixel areas around each of the pixel areas; an element layer arranged on the substrate; a pixel defining film arranged on the element layer and defining a first opening portion overlapping with the pixel area and a second opening portion overlapping with the non-pixel area and extending between the pixel areas; a plurality of light-emitting elements arranged in the first opening portion; an encapsulation layer arranged on the element layer to cover the light-emitting elements and the pixel defining film; and an input sensing portion overlapping with the second opening portion and arranged on the encapsulation layer.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] Electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs that provide images to users include a display device for displaying images. The display device generates images and provides the images to users through a display screen.

[0003] The display device includes a display panel for generating an image and an input device such as a keyboard, a mouse or an input sensing unit. The input sensing unit is arranged on the display panel and senses the touch of the user. The signal sensed by the input sensing unit is converted into an input signal. The display panel provides the user with an image corresponding to the input signal of the input sensing unit.

[0004] The display panel includes a plurality of pixels for generating an image. The input sensing unit includes a plurality of sensing units for sensing a user's touch. A parasitic capacitor is formed between the sensing unit as a conductor and the conductor of the pixel. The parasitic capacitor causes an image to a signal applied to the sensing unit and generates noise to the signal applied to the sensing unit. In this case, the touch sensitivity of the input sensing unit will be reduced. Summary of the invention

[0005] An object of the present invention is to provide a display device capable of improving touch sensitivity.

[0006] A display device according to an embodiment of the present invention may include: a substrate including a plurality of pixel areas and non-pixel areas around each of the pixel areas; an element layer arranged on the substrate; a pixel defining film arranged on the element layer and defining a first opening portion overlapping with the pixel area and a second opening portion overlapping with the non-pixel area and extending between the pixel areas; a plurality of light-emitting elements arranged in the first opening portion; an encapsulation layer arranged on the element layer to cover the light-emitting elements and the pixel defining film; and an input sensing portion overlapping with the second opening portion and arranged on the encapsulation layer.

[0007] The display device according to the embodiment of the present invention can reduce the capacity of the parasitic capacitor between the sensing part and the pixel, thereby improving the touch sensitivity of the input sensing part. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0009] Figure 2 is schematically shown in Figure 1 A cross-sectional view of a display device is shown.

[0010] Figure 3 is Figure 2 A plan view of the display panel shown in FIG.

[0011] Figure 4 It is shown in Figure 3 A diagram of a portion of a display panel shown in FIG.

[0012] Figure 5 is Figure 2 A plan view of the input sensing portion shown in FIG.

[0013] Figure 6 is Figure 5 An enlarged view of the first area A1 is shown in FIG.

[0014] Figure 7 It is only a picture Figure 6 Figure 2 shows a diagram of the first sensing part, the second sensing part and the second connecting part.

[0015] Figure 8 It is only a picture Figure 6 Figure 1 shows a diagram of the first connection in FIG.

[0016] Fig. 9 is Figure 5 An enlarged view of the second area A2 is shown in FIG.

[0017] Fig.10 is Figure 4 The cross-sectional view along the line II' is shown in FIG.

[0018] Fig.11 is Figure 4 The cross-sectional view along the line II-II' is shown in FIG.

[0019] Fig.12 is Figure 6 The cross-sectional view along line III-III' is shown in FIG.

[0020] Fig.13 It is shown in Fig.10 FIG. 4 is a diagram of a cross section of a portion of the pixels shown in FIG.

[0021] Fig.14 is a diagram illustrating a portion of a display panel of a display device according to another embodiment of the present invention.

[0022] Explanation of symbols:

[0023] DD: Display device DP: Display panel

[0024] SUB: Substrate PA1, PA2, PA3: Pixel area

[0025] NPA: Non-Pixel Area PDL: Pixel Definition Layer

[0026] PDL1: first pixel definition layer PDL2: second pixel definition layer

[0027] OP1: first opening OP2: second opening

[0028] SPC: separator PRT: protrusion

[0029] ELL: Component layer TFE: Encapsulation layer

[0030] ISP: Input sensing part SP1: First sensing part

[0031] SP2: Second sensor DETAILED DESCRIPTION

[0032] In this specification, when a certain component (or region, layer, part, etc.) is mentioned as being "on" another component, "connected to" another component, or "combined with" another component, it means that it can be directly arranged / connected / combined on the other component, or a third component can be arranged between them.

[0033] The same reference numerals refer to the same components. In addition, in order to effectively explain the technical content, the thickness, ratio and size of the components are exaggerated in the drawings.

[0034] “And / or” means that all of the combinations of more than one that can be defined for the related components are included.

[0035] The terms first, second, etc. may be used to describe a variety of constituent elements, but the constituent elements should not be limited by the terms. The terms are only used to distinguish one constituent element from another constituent element. For example, without departing from the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Singular expressions include plural expressions as long as they do not clearly indicate different meanings in the context.

[0036] Furthermore, terms such as “below”, “lower side”, “above”, and “upper side” are used to describe the correlation between the components shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

[0037] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. Also, terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with those in the context of the relevant technology, and are explicitly defined in this specification unless interpreted in an ideal or excessively formal meaning.

[0038] The terms such as “including” or “having” should be understood as intending to specify the existence of the features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, and are not intended to preclude the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof.

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0041] Reference Figure 1 The display device DD according to the embodiment of the present invention may have a rectangular shape having a long side extending along the first direction DR1 and a short side extending along the second direction DR2 crossing the first direction DR1. However, it is not limited thereto, and the display device DD may have various shapes such as a circle or a polygon.

[0042] Hereinafter, a direction substantially perpendicularly intersecting a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. Hereinafter, the expression "when viewed from a plane" may mean a state viewed from the third direction DR3.

[0043] The upper surface of the display device DD may be defined as a display surface DS, and may have a plane defined by the first direction DR1 and the second direction DR2. The image IM generated in the display device DD may be provided to the user through the display surface DS.

[0044] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and may define a frame of the display device DD printed with a predetermined color.

[0045] The display device DD can be used in large electronic devices such as televisions, monitors, or external advertising boards. In addition, the display device DD can also be used in small and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation systems, game consoles, smart phones, tablet computers, or cameras. However, these are only examples proposed as exemplary embodiments, and can also be used in other electronic devices as long as they do not exceed the concept of the present invention.

[0046] Figure 2 is schematically shown in Figure 1 A cross-sectional view of a display device is shown.

[0047] Reference Figure 2 , the display device DD according to the embodiment of the present invention may further include: a display panel DP; an input sensing portion ISP arranged on the display panel DP; a window WIN arranged on the input sensing portion ISP; and an adhesive OCA arranged between the input sensing portion ISP and the window WIN.

[0048] The display panel DP according to an embodiment of the present invention may be a light-emitting display panel, and is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. In the following, the display panel DP is described as an organic light-emitting display panel.

[0049] The display panel DP may include: a substrate SUB; a pixel layer PXL arranged on the substrate SUB; and a thin film encapsulation layer TFE arranged on the substrate SUB in a manner of covering the pixel layer PXL. The substrate SUB, as a transparent substrate, may include a flexible plastic substrate. For example, the substrate SUB may include polyimide (PI).

[0050] Like the display surface DS of the display device DD, the substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The pixel layer PXL may be arranged on the display area DA. The pixel layer PXL may include a plurality of pixels, each of which may include a light emitting element.

[0051] The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer arranged between the inorganic layers. The inorganic layer may include an inorganic substance, which may protect the pixel layer PXL from the influence of moisture / oxygen. The organic layer may include an organic substance, which may protect the pixel layer PXL from the image of foreign matter such as dust particles. The thickness of the organic layer may be greater than the thickness of each inorganic layer. The input sensing unit ISP may sense an external input (a user's hand or a touch pen, etc.) and change it into a predetermined input signal, and provide the input signal to the display panel DP. The input sensing unit ISP may include a plurality of sensing units (not shown) for sensing external input. The sensing unit may sense the external input in a capacitive manner. The display panel DP may receive an input signal from the input sensing unit ISP, and may generate an image corresponding to the input signal.

[0052] The window WIN can protect the display panel DP and the input sensing part ISP from external scratches and impacts. The window WIN can be attached to the input sensing part ISP by means of an adhesive OCA. The adhesive OCA can include an optical clear adhesive. The image generated on the display panel DP can be provided to the user through the window WIN.

[0053] Figure 3 is Figure 2 A plan view of the display panel shown in FIG.

[0054] Reference Figure 3 The display device DD according to the embodiment of the present invention may include a display panel DP, a scan driver SDV, a data driver DDV, and an emission driver EDV.

[0055] The display panel DP may be a flexible display panel. The display panel DP may have a rectangular shape having long sides extending in the first direction DR1 and short sides extending in the second direction DR2. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0056] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1-SLm, a plurality of data lines DL1-DLn, and a plurality of emission lines EL1-ELm. m and n are positive integers. The pixels PX may be arranged in the display area DA and may be connected to the scan lines SL1-SLm, the data lines DL1-DLn, and the emission lines EL1-ELm.

[0057] The scan driving part SDV, the data driving part DDV, and the light emitting driving part EDV may be disposed in the non-display area NDA. The scan driving part SDV and the light emitting driving part EDV may be disposed adjacent to long sides of the display panel DP, respectively.

[0058] The data driver DDV may be manufactured in the form of an integrated circuit chip and arranged adjacent to any one of the short sides of the display panel DP. However, the present invention is not limited thereto, and the data driver DDV may be mounted on a flexible circuit substrate (not shown) and connected to the display panel DP via the flexible circuit substrate.

[0059] The scan lines SL1-SLm may extend along the second direction DR2 and be connected to the scan driving part SDV. The data lines DL1-DLn may extend along the first direction DR1 and be connected to the data driving part DDV. The light emitting lines EL1-ELm may extend along the second direction DR2 and be connected to the light emitting driving part EDV.

[0060] The scan driving unit SDV may generate a plurality of scan signals, which may be applied to the pixels PX through the scan lines SL1 to SLm. The scan signals may be applied to the pixels PX in sequence. The data driving unit DDV may generate a plurality of data voltages, which may be applied to the pixels PX through the data lines DL1 to DLn. The light emitting driving unit EDV may generate a plurality of light emitting signals, which may be applied to the pixels PX through the light emitting lines EL1 to ELm.

[0061] Although not shown, the display device DD may further include a timing controller (not shown) for controlling operations of the scan driving part SDV, the data driving part DDV, and the light emitting driving part EDV.

[0062] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may emit light having a brightness corresponding to the data voltage in response to a light emission signal, thereby displaying an image. The light emission time of the pixel PX may be controlled by the light emission signal.

[0063] Figure 4 It is shown in Figure 3 A diagram of a portion of a display panel shown in FIG.

[0064] Reference Figure 4 When viewed from a plane, the display panel DP may include a plurality of pixel areas PA1, PA2, PA3 and a non-pixel area NPA around each pixel area PA1, PA2, PA3. The pixel areas PA1, PA2, PA3 may be defined as light-emitting areas, and the non-pixel area NPA may be defined as a non-light-emitting area.

[0065] Figure 3Each pixel PX shown may include a transistor arranged in the non-pixel area NPA and a light emitting element arranged in each pixel area PA1, PA2, PA3. Figure 8 A detailed description is given below.

[0066] The pixel areas PA1, PA2, and PA3 can display predetermined colors. For example, the pixel areas PA1, PA2, and PA3 can display red, green, and blue. However, this is not limited to this. The pixel areas PA1, PA2, and PA3 can also generate white light by combining organic substances that generate red, green, and blue.

[0067] The pixel areas PA1, PA2, PA3 may have a rhombus shape, but are not limited thereto, and may have various shapes such as a circle and a polygon. The pixel areas PA1, PA2, PA3 may be arranged along a first diagonal direction DDR1 and a second diagonal direction DDR2.

[0068] The first diagonal direction DDR1 may be defined as a direction crossing the first direction DR1 and the second direction DR2 on a plane defined by the first direction DR1 and the second direction DR2. The second diagonal direction DDR2 may be defined as a direction crossing the first diagonal direction DDR1 on a plane defined by the first direction DR1 and the second direction DR2. Exemplarily, the first direction DR1 and the second direction DR2 may cross each other perpendicularly, and the first diagonal direction DDR1 and the second diagonal direction DDR2 may cross each other perpendicularly.

[0069] The pixel areas PA1, PA2, and PA3 may include a plurality of first pixel areas PA1, a plurality of second pixel areas PA2, and a plurality of third pixel areas PA3. The first pixel area PA1 may display red. The second pixel area PA2 may display green. The third pixel area PA3 may display blue.

[0070] The pixel areas PA1, PA2, and PA3 may have different sizes according to the displayed colors. The third pixel area PA3 displaying blue may be larger than the first pixel area PA1 displaying red, and the first pixel area PA1 may be larger than the second pixel area PA2 displaying green.

[0071] The display panel DP may include a pixel defining film PDL and a plurality of spacers SPC. Exemplarily, the pixel defining film PDL may have a black color. A first opening OP1 overlapping the pixel areas PA1, PA2, and PA3 may be defined in the pixel defining film PDL. In fact, the pixel areas PA1, PA2, and PA3 may be defined by the first opening OP1.

[0072] The pixel definition layer PDL may define a second opening OP2 overlapping the non-pixel area NPA and extending between the pixel areas PA1, PA2, and PA3. The second opening OP2 may extend along the first diagonal direction DDR1 and the second diagonal direction DDR2.

[0073] The pixel defining film PDL may include: a plurality of first pixel defining films PDL1 separated from each other by the second opening OP2 and surrounding the pixel areas PA1, PA2, and PA3; and a plurality of protrusions PRT protruding from the first pixel defining films PDL1. Each protrusion PRT may protrude from any vertex of each of the first pixel defining films PDL1.

[0074] The protrusions PRT may protrude from lower ends of pixel regions arranged in the k-th row k_ROW and upper ends of pixel regions arranged in the k+1-th row k+1_ROW. k may be an odd number among positive integers. The protrusions PRT may be arranged along the second direction DR2.

[0075] The spacer SPC may be disposed at a predetermined portion of the second opening portion OP2. Exemplarily, the spacer SPC may have a circular shape, however the shape of the spacer SPC may not be limited thereto.

[0076] Figure 5 is Figure 2 A plan view of the input sensing portion shown in FIG.

[0077] Reference Figure 5 The input sensing part ISP may include a plurality of sensing electrodes SE1, SE2, a plurality of wirings SNL1, SNL2, and a plurality of pads PD. The sensing electrodes SE1, SE2, the wirings SNL1, SNL2, and the pads PD may be arranged on the thin film encapsulation layer TFE.

[0078] The plane area of ​​the input sensing part ISP may include an active area AA and an inactive area NAA surrounding the active area AA. The sensing electrodes SE1 and SE2 may be arranged in the active area AA, and the pad PD may be arranged in the inactive area NAA. The wirings SNL1 and SNL2 may be connected to the sensing electrodes SE1 and SE2, and may extend to the inactive area NAA and be connected to the pad PD.

[0079] Although not shown, the pad PD may be connected to a driving unit for driving the input sensing unit ISP through a flexible printed circuit board (FPCB).

[0080] The sensing electrodes SE1 and SE2 may include: a plurality of first sensing electrodes SE1 extending along the first direction DR1 and arranged along the second direction DR2; and a plurality of second sensing electrodes SE2 extending along the second direction DR2 and arranged along the first direction DR1. The wirings SNL1 and SNL2 may include: a plurality of first signal wirings SNL1 connected to the first sensing electrodes SE1; and a plurality of second signal wirings SNL2 connected to the second sensing electrodes SE2.

[0081] The second sensing electrodes SE2 may extend in a manner of being insulated from and crossing the first sensing electrodes SE1. The first sensing electrodes SE1 may be defined as output sensing electrodes, and the second sensing electrodes SE2 may be defined as input sensing electrodes.

[0082] Each first sensing electrode SE1 may include a plurality of first sensing parts SP1 arranged along the first direction DR1 and a plurality of first connection parts CP1 connecting the first sensing parts SP1. Each first connection part CP1 may be disposed between two first sensing parts SP1 adjacent to each other along the first direction DR1 to electrically connect the two first sensing parts SP1.

[0083] Each second sensing electrode SE2 may include a plurality of second sensing parts SP2 arranged along the second direction DR2 and a plurality of second connection parts CP2 connecting the second sensing parts SP2. Each second connection part CP2 may be disposed between two second sensing parts SP2 adjacent to each other along the second direction DR2 to electrically connect the two second sensing parts SP2.

[0084] The first sensing portion SP1 and the second sensing portion SP2 may have a grid shape. The first sensing portion SP1 and the second sensing portion SP2 may not overlap each other and may be spaced apart from each other, so as to be arranged alternately with each other. A capacitor may be formed by the first sensing portion SP1 and the second sensing portion SP2. The second connection portion CP2 may not overlap with the first connection portion CP1.

[0085] The first sensing part SP1, the second sensing part SP2 and the second connecting part CP2 may be arranged on the same layer. The first connecting part CP1 may be arranged on a different layer from the first sensing part SP1, the second sensing part SP2 and the second connecting part CP2.

[0086] Each first signal wire SNL1 is connected to one end of the first sensing electrode SE1 and may extend to the inactive area NAA to be connected to the pad PD. Each second signal wire SNL2 is connected to one end of the second sensing electrode SE2 and may extend to the inactive area NAA to be connected to the pad PD.

[0087] The driving unit can make each second sensing electrode SE2 work as a driving electrode and make each first sensing electrode SE1 work as a sensing electrode. For example, the driving unit can apply a driving signal to each second sensing electrode SE2 through the second signal wiring SNL2 and receive a sensing signal from each first sensing electrode SE1 through the first signal wiring SNL1.

[0088] Figure 6 is Figure 5 An enlarged view of the first area A1 is shown in FIG. Figure 7 It is only a picture Figure 6 Figure 2 shows a diagram of the first sensing part, the second sensing part and the second connecting part. Figure 8 It is only a picture Figure 6 . Exemplarily, Figure 6 , two first sensing portions SP1 adjacent to each other and two second sensing portions SP2 adjacent to each other are shown.

[0089] Reference Figure 6 , Figure 7 as well as Figure 8 The first sensing portion SP1 and the second sensing portion SP2 may have a grid shape. For example, the first sensing portion SP1 and the second sensing portion SP2 may each include a plurality of first branches BP1 extending along a first diagonal direction DDR1 and a plurality of second branches BP2 extending along a second diagonal direction DDR2.

[0090] The first branch BP1 of each of the first sensing part SP1 and the second sensing part SP2 may intersect with the second branch BP2 and form a whole with each other. The grid shape may be defined by the first branch BP1 and the second branch BP2 intersecting each other. In addition, the diamond-shaped touch opening TOP may be defined by the first branch BP1 and the second branch BP2. The first branch BP1 and the second branch BP2 may be defined by grid lines, and the line width of each grid line may be several microns.

[0091] The first connection part CP1 may extend in a manner that does not overlap with the second connection part CP2 and electrically connect the two first sensing parts SP1 adjacent to each other. The first connection part CP1 may not be formed as one body with the first sensing part SP1. The first connection part CP1 may be connected to the first sensing part SP1 through a plurality of contact holes TS-CH. The first connection part CP1 may extend toward the first sensing part SP1 through a predetermined area of ​​each second sensing part SP2 adjacent to the second connection part CP2. The second connection part CP2 may electrically connect the two second sensing parts SP2 adjacent to each other. In fact, the second sensing part SP2 and the second connection part CP2 may be formed as one body. The second connection part CP2 may have a grid shape and may extend from the second sensing part SP2. The second connection part CP2, the first sensing part SP1 and the second sensing part SP2 may be formed by patterning at the same time using the same material.

[0092] The first connection portion CP1 may include a first extension portion EX1 and a second extension portion EX2 having a shape symmetrical to the first extension portion EX1. The first extension portion EX1 and the second extension portion EX2 may not overlap with the second connection portion CP2. The second connection portion CP2 may be disposed between the first extension portion EX1 and the second extension portion EX2.

[0093] The first extension portion EX1 may extend through one second sensing portion SP2 of the plurality of second sensing portions SP2 and may be connected to the first sensing portion SP1. The second extension portion EX2 may extend through another second sensing portion SP2 of the plurality of second sensing portions SP2 and may be connected to the first sensing portion SP1.

[0094] Below, in Figure 6 as well as Figure 7 In the embodiment, the first sensing portion SP1 can be defined as an upper first sensing portion SP1 and a lower first sensing portion SP1 according to relative arrangement positions, and the second sensing portion SP2 can be defined as a left second sensing portion SP2 and a right second sensing portion SP2 according to relative arrangement positions.

[0095] A predetermined region of the first extension portion EX1 adjacent to one side of the first extension portion EX1 may be connected to the lower first sensing portion SP1 through a plurality of contact holes TS-CH. A predetermined region of the first extension portion EX1 adjacent to the other side of the first extension portion EX1 may be connected to the upper first sensing portion SP1 through a plurality of contact holes TS-CH. The contact holes TS-CH may be defined in the insulating layer disposed on the first connection portion CP1, and the structure of the contact holes TS-CH will be described below. Fig.12 Medium picture.

[0096] A predetermined region of the second extension portion EX2 adjacent to one side of the second extension portion EX2 may be connected to the lower first sensing portion SP1 through a plurality of contact holes TS-CH. A predetermined region of the second extension portion EX2 adjacent to the other side of the second extension portion EX2 may be connected to the upper first sensing portion SP1 through a plurality of contact holes TS-CH. The first extension portion EX1 may extend through the right second sensing portion SP2. The second extension portion EX2 may extend through the left second sensing portion SP2.

[0097] The first extension portion EX1 may include: a first sub-extension portion EX1_1 and a second sub-extension portion EX1_2 extending along a first diagonal direction DDR1; a third sub-extension portion EX1_3 and a fourth sub-extension portion EX1_4 extending along a second diagonal direction DDR2; a first sub-connection portion SCP1 extending along the second diagonal direction DDR2; and a second sub-connection portion SCP2 extending along the first diagonal direction DDR1. The second sub-extension portion EX1_2 may have a smaller length than the first sub-extension portion EX1_1, and the fourth sub-extension portion EX1_4 may have a smaller length than the third sub-extension portion EX1_3.

[0098] A predetermined region of the first sub-extension portion EX1_1 adjacent to one side of the first sub-extension portion EX1_1 may be connected to the lower first sensing portion SP1 through a plurality of contact holes TS-CH. A predetermined region of the second sub-extension portion EX1_2 adjacent to one side of the second sub-extension portion EX1_2 may be connected to the lower first sensing portion SP1 through a plurality of contact holes TS-CH. Exemplarily, the first sub-extension portion EX1_1 and the second sub-extension portion EX1_2 are connected to the lower first sensing portion SP1 through two contact holes TS-CH, respectively, but the number of the contact holes TS-CH is not limited thereto.

[0099] A predetermined region of the third sub-extension EX1_3 adjacent to one side of the third sub-extension EX1_3 may be connected to the upper first sensing portion SP1 through a plurality of contact holes TS-CH. A predetermined region of the fourth sub-extension EX1_4 adjacent to one side of the fourth sub-extension EX1_4 may be connected to the upper first sensing portion SP1 through a plurality of contact holes TS-CH. Exemplarily, the third sub-extension EX1_3 and the fourth sub-extension EX1_4 are connected to the upper first sensing portion SP1 through two contact holes TS-CH, respectively, but the number of the contact holes TS-CH is not limited thereto.

[0100] The other side of the first sub-extension portion EX1_1 may be connected to the other side of the third sub-extension portion EX1_3, and the other side of the second sub-extension portion EX1_2 may be connected to the other side of the fourth sub-extension portion EX1_4. The first sub-connection portion SCP1 may extend from the other side of the fourth sub-extension portion EX1_4 along the second diagonal direction DDR2 and be connected to the first sub-extension portion EX1_1. The second sub-connection portion SCP2 may extend from the other side of the second sub-extension portion EX1_2 along the first diagonal direction DDR1 and be connected to the third sub-extension portion EX1_3.

[0101] The first sub-extension portion EX1_1 , the second sub-extension portion EX1_2 , the third sub-extension portion EX1_3 , the fourth sub-extension portion EX1_4 , the first sub-connection portion SCP1 , and the second sub-connection portion SCP2 may be formed as one body.

[0102] The first sub-extension portion EX1_1 and the second sub-extension portion EX1_2 may extend in a manner of crossing a predetermined number of second branches BP2 of the second branches BP2 of the right second sensing portion SP2 adjacent to the lower first sensing portion SP1. Figure 6 The two second branches BP2 in the right side cross the first extension part EX1_1 and the second extension part EX1_2, but the number of the crossed second branches BP2 is not limited thereto. The first branch BP1 of the right second sensing part SP2 may not be arranged in the area overlapping the first extension part EX1_1, the second extension part EX1_2 and the second connection part SCP2.

[0103] The third sub-extension portion EX1_3 and the fourth sub-extension portion EX1_4 may extend in a manner of crossing a predetermined number of first branches BP1 of the first branches BP1 of the right second sensing portion SP2 that are adjacent to the upper first sensing portion SP1. Figure 6 The two first branches BP1 in the third extension part EX1_3 and the fourth extension part EX1_4 intersect each other, but the number of intersecting first branches BP1 is not limited thereto. The second branch BP2 of the right second sensing part SP2 may not be arranged in the area overlapping the third extension part EX1_3, the fourth extension part EX1_4 and the first connection part SCP1.

[0104] The second extension portion EX2 may include: a fifth sub-extension portion EX2_1 and a sixth sub-extension portion EX2_2 extending along the second diagonal direction DDR2; a seventh sub-extension portion EX2_3 and an eighth sub-extension portion EX2_4 extending along the first diagonal direction DDR1; a third sub-connection portion SCP3 extending along the first diagonal direction DDR1; and a fourth sub-connection portion SCP4 extending along the second diagonal direction DDR2.

[0105] The second extension portion EX2 has a symmetrical structure with the first extension portion EX1, so that the fifth sub-extension portion EX2_1 to the eighth sub-extension portion EX2_4, the third sub-connection portion SCP3 and the fourth sub-connection portion SCP4 may have symmetrical structures with the first sub-extension portion EX1_1 to the fourth sub-extension portion EX1_4, the first sub-connection portion SCP1 and the second sub-connection portion SCP2, respectively. Therefore, a predetermined region of each of the fifth sub-extension portion EX2_1 to the eighth sub-extension portion EX2_4 adjacent to one side of each of the fifth sub-extension portion EX2_1 to the eighth sub-extension portion EX2_4 may be connected to the first sensing portion SP1 through a plurality of contact holes TS-CH.

[0106] In the same manner as the first to fourth sub-extensions EX1_1 to EX1_4 are connected to the first sensing portion SP1 via the right second sensing portion SP2, the fifth to eighth sub-extensions EX2_1 to EX2_4 may be connected to the first sensing portion SP1 via the left second sensing portion SP2. The first branch BP1 and the second branch BP2 of the left second sensing portion SP2 may not be arranged in the region overlapping with the fifth to eighth sub-extensions EX2_1 to EX2_4, the third sub-connection portion SCP3, and the fourth sub-connection portion SCP4. The second extension portion EX2 has a symmetrical structure with the first extension portion EX1, and thus a more detailed description of the second extension portion EX2 is omitted.

[0107] Fig. 9 is Figure 5 An enlarged view of the second area A2 is shown in FIG.

[0108] For ease of explanation, Fig. 9 , the pixel areas PA1, PA2, and PA3 are illustrated together with the first sensor portion SP1 and the second sensor portion SP2.

[0109] Reference Fig. 9 The first sensing portion SP1 and the second sensing portion SP2 may overlap with the non-pixel area NPA. For example, the first branch portion BP1 and the second branch portion BP2 may overlap with the non-pixel area NPA.

[0110] The touch opening portion TOP may overlap with the pixel areas PA1, PA2, and PA3. The touch opening portion TOP may have a rhombus shape corresponding to the shape of the pixel areas PA1, PA2, and PA3, and may have a size corresponding to the pixel areas PA1, PA2, and PA3.

[0111] The first sensing portion SP1 and the second sensing portion SP2 are arranged in the non-pixel region NPA, so that the light generated in the pixel areas PA1, PA2, and PA3 can be normally emitted without being affected by the first sensing portion SP1 and the second sensing portion SP2.

[0112] Fig.10 is Figure 4 The cross-sectional view along the line II' is shown in FIG. Fig.11 is Figure 4 The cross-sectional view along the line II-II' is shown in FIG.

[0113] exist Fig.10 as well as Fig.11 The input sensing unit ISP and the window WIN are shown in the figure at the same time. Figure 4 will with Fig.10 as well as Fig.11 Explain together.

[0114] Reference Figure 4 as well as Fig.10 The pixel PX may include a transistor TR and a light emitting element OLED connected to the transistor TR. The light emitting element OLED may be defined as an organic light emitting element. The transistor TR and the light emitting element OLED may be arranged on a substrate SUB.

[0115] The substrate SUB may include: a plurality of first pixel areas PA1, a second pixel area PA2, and a third pixel area PA3; and a non-pixel area NPA around each of the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3. The transistor TR may be arranged on the non-pixel area NPA, and the light emitting element OLED may be arranged on the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3, respectively. The light emitting element OLED may be arranged in the first opening OP1.

[0116] The configurations of the pixels PX are substantially the same as each other. Hereinafter, the configuration of the pixel PX including the light emitting element OLED disposed in the first pixel area PA1 will be exemplarily described.

[0117] The light emitting element OLED may include: a first electrode E1; a second electrode E2; and a light emitting layer OEL arranged between the first electrode E1 and the second electrode E2. The light emitting layer OEL may be defined as an organic light emitting layer. The first electrode E1 may be an anode electrode, and the second electrode E2 may be a cathode electrode. The first electrode E1 may be defined as a pixel electrode, and the second electrode E2 may be defined as a common electrode.

[0118] The transistor TR and the light emitting element OLED may be disposed on the substrate SUB. A buffer layer BFL may be disposed on the substrate SUB, and the buffer layer BFL may include an inorganic substance.

[0119] A semiconductor layer SM of the transistor TR may be disposed on the buffer layer BFL. The semiconductor layer SM may include a semiconductor of an inorganic material such as amorphous silicon or polycrystalline silicon or an organic semiconductor. Also, the semiconductor layer SM may include an oxide semiconductor. Fig.10 As shown in , however, the semiconductor layer SM may include a source region, a drain region, and a channel region between the source region and the drain region.

[0120] A first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layer SM. The first insulating layer INS1 may include an inorganic substance. A gate electrode GE of the transistor TR may be disposed on the first insulating layer INS1 to overlap the semiconductor layer SM. The gate electrode GE may be disposed to overlap the channel region of the semiconductor layer SM.

[0121] The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the gate electrode GE. The second insulating layer INS2 may include an organic substance and / or an inorganic substance.

[0122] The source electrode SE and the drain electrode DE of the transistor TR may be arranged on the second insulating layer INS2 to be separated from each other. The source electrode SE may be connected to the source region of the semiconductor layer SM through a first contact hole CH1 defined in the first insulating layer INS1 and the second insulating layer INS2. The drain electrode DE may be connected to the drain region of the semiconductor layer SM through a second contact hole CH2 defined in the first insulating layer INS1 and the second insulating layer INS2.

[0123] A third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the source electrode SE and the drain electrode DE of the transistor TR. The third insulating layer INS3 may be defined as a planarization film providing a flat upper surface and may include an organic substance. The layer from the buffer layer BFL to the third insulating layer INS3 may be defined as an element layer ELL for arranging the transistor TR.

[0124] A pixel definition layer PDL and a light emitting element OLED may be disposed on the element layer ELL. Specifically, a first electrode E1 may be disposed on the third insulating layer INS3. The first electrode E1 may be connected to the drain electrode DE of the transistor TR through a third contact hole CH3 defined by penetrating the third insulating layer INS3.

[0125] A pixel defining film PDL exposing a predetermined portion of the first electrode E1 may be disposed on the first electrode E1 and the third insulating layer INS3. The pixel defining film PDL may overlap the non-pixel area NPA. A first opening OP1 overlapping the first pixel area PA1 and exposing a predetermined portion of the first electrode E1 may be defined in the pixel defining film PDL. Furthermore, as described above, a second opening OP2 overlapping the non-pixel area NPA may be defined in the pixel defining film PDL.

[0126] The first electrode E1 may include: a first portion PT1 disposed in the first opening OP1; and a second portion PT2 extending from the first portion PT1 to overlap with the protrusion PRT. The second portion PT2 may be connected to the transistor TR through the third contact hole CH3. The protrusion PRT may be disposed on the element layer ELL to cover the second portion PT2. And, the protrusion PRT may protrude toward the transistor TR.

[0127] In the first opening OP1, the light emitting layer OEL may be disposed on the first electrode E1. The light emitting layer OEL may generate any one of red, green and blue light. However, this is not limited thereto, and the light emitting layer OEL may also generate white light by combining organic substances that generate red, green and blue.

[0128] A second electrode E2 may be arranged on the pixel defining film PDL and the light emitting layer OEL. The second electrode E2 may be arranged on the element layer ELL at the second opening OP2 so as to be able to contact the element layer ELL. A thin film encapsulation layer TFE may be arranged on the element layer ELL to cover the light emitting element OLED and the pixel defining film PEL. The dielectric constant of the thin film encapsulation layer TFE may be lower than the dielectric constant of the pixel defining film PDL. Specifically, the dielectric constant of the organic layer of the thin film encapsulation layer TFE may be lower than the dielectric constant of the pixel defining film PDL. The layer between the substrate SUB and the thin film encapsulation layer TFE may be defined as a pixel layer PXL.

[0129] A first voltage may be applied to the first electrode E1, and a second voltage having a level lower than the first voltage may be applied to the second electrode E2. The holes and electrons injected into the light-emitting layer OEL combine to form excitons, and the excitons may transition to a ground state to make the light-emitting element OLED emit light. The light-emitting element OLED emits red, green, and blue light as current flows, thereby displaying an image.

[0130] The input sensing part ISP may be arranged on the thin film encapsulation layer TFE. The first sensing part SP1 and the second sensing part SP2 of the input sensing part ISP may overlap with the second opening part OP2 defined in the non-pixel area NPA. Specifically, the first branch BP1 and the second branch BP2 of the first sensing part SP1 and the second sensing part SP2 may overlap with the second opening part OP2.

[0131] An adhesive OCA may be disposed on the input sensing part ISP, and a window WIN may be disposed on the adhesive OCA.

[0132] Reference Figure 4 as well as Fig.11 , a spacer SPC may be disposed at a portion of the second opening OP2. The pixel definition film PDL may include a second pixel definition film PDL2 disposed between the spacer SPC and the element layer ELL. The second pixel definition film PDL2 may be formed substantially simultaneously with the first pixel definition film PDL1. The second pixel definition film PDL2 may be separated from the first pixel definition film PDL1.

[0133] The spacer SPC may include an organic substance. The spacer SPC may be a single layer or a multilayer. Exemplarily, the spacer SPC may be arranged separately on the second pixel defining film PDL2, but is not limited thereto, and the spacer SPC may be formed as a whole with the second pixel defining film PDL2. That is, the spacer SPC may be formed by protruding upward from the upper surface of the second pixel defining film PDL2. The spacer SPC may make the bonding between the substrate SUB and the thin film encapsulation layer TFE firm.

[0134] Fig.12 is Figure 6 The cross-sectional view along line III-III' is shown in FIG.

[0135] Reference Fig.12 , a first connection part CP1 may be arranged on the thin film encapsulation layer TFE. A first insulating layer TS-IL1 may be arranged on the thin film encapsulation layer TFE to cover the first connection part CP1. A first sensing part SP1 and a second sensing part SP2 may be arranged on the first insulating layer TS-IL1. The second connection part CP2 formed as a whole with the second sensing part SP2 may of course also be arranged on the first insulating layer TS-IL1. A second insulating layer TS-IL2 may be arranged on the first insulating layer TS-IL1 to cover the first sensing part SP1 and the second sensing part SP2.

[0136] The first connection part CP1 may be connected to the first sensing part SP1 through a plurality of contact holes TS-CH defined in the first insulating layer TS-IL1.

[0137] Fig.13 It is shown in Fig.10 FIG. 4 is a diagram of a cross section of a portion of the pixels shown in FIG.

[0138] Reference Fig.13 In the non-pixel area NPA, a parasitic capacitor C-P1_1 may be formed by the first sensing portion SP1, the second sensing portion SP2, and the second electrode E2. In addition, a parasitic capacitor C-P1_2 may be formed between the second electrode E2 and the transistor TR.

[0139] The capacity of a capacitor may be inversely proportional to the distance between two electrical conductors forming the capacitor, and may be directly proportional to the dielectric constant of an insulating layer disposed between the electrical conductors.

[0140] In the embodiment of the present invention, the pixel defining film PDL is not disposed at the second opening portion OP2. A thin film encapsulation layer TFE including an organic layer having a dielectric constant smaller than that of the pixel defining film PDL may be disposed at the second opening portion OP2.

[0141] like Fig.13 As shown by the dotted line in , the pixel defining film PDL can be arranged in the entire non-pixel area NPA without forming the second opening portion OP2. In this case, the distance between the first sensing portion SP1 and the second sensing portion SP2 and the second electrode E2 can become closer. Therefore, a parasitic capacitor C-P2_1 having a larger capacity than the parasitic capacitor C-P1_1 may be formed by the first sensing portion SP1 and the second sensing portion SP2 and the second electrode E2. In addition, the pixel defining film PDL has a dielectric constant greater than the dielectric constant of the organic layer of the thin film encapsulation layer TFE, so that a parasitic capacitor C-P2_2 having a larger capacity than the parasitic capacitor C-P1_2 may be formed by the second electrode E2 and the transistor TR.

[0142] The inorganic layer of the thin film encapsulation layer TFE has a very thin thickness relative to the organic layer, so the dielectric constant of the inorganic layer may have little effect on the capacitance of the parasitic capacitor. However, in an embodiment of the present invention, the pixel defining film PDL is not arranged in the second opening portion OP2, so the distance between the first sensing portion SP1 and the second sensing portion SP2 and the second electrode E2 can be separated to be larger. Therefore, a parasitic capacitor C-P1_1 having a smaller capacity relative to the parasitic capacitor C-P2_1 can be formed. In addition, the thin film encapsulation layer TFE including an organic layer having a dielectric constant smaller than the dielectric constant of the pixel defining film PDL is arranged in the second opening portion OP2, so that a parasitic capacitor C-P1_2 having a smaller capacity relative to the parasitic capacitor C-P2_2 can be formed.

[0143] The larger the capacity of the parasitic capacitor, the lower the touch sensitivity of the first sensing portion SP1 and the second sensing portion SP2 may be due to the influence of the parasitic capacitor. In the embodiment of the present invention, since the parasitic capacitors C-P1_1 and C-P1_2 with smaller capacity are formed, the touch sensitivity of the first sensing portion SP1 and the second sensing portion SP2 can be improved.

[0144] Finally, in the display device according to the embodiment of the present invention, the capacitances of the parasitic capacitors C-P1_1 and C-P1_2 between the first sensing part SP1 and the second sensing part SP2 and the pixel PX are reduced, thereby improving the touch sensitivity of the input sensing part ISP.

[0145] Fig.14 is a diagram illustrating a portion of a display panel of a display device according to another embodiment of the present invention.

[0146] If the shapes and arrangements of the pixel regions PA1', PA2', and PA3' are excluded, the configuration of the display device according to another embodiment of the present invention is substantially the same as the configuration of the display device DD described above. Fig.14 The shapes and arrangements of the pixel areas PA1 ′, PA2 ′, and PA3 ′ will be mainly described.

[0147] Reference Fig.14 When viewed from a plane, the display panel DP' may include a plurality of pixel areas PA1', PA2', PA3' and non-pixel areas NPA' around the respective pixel areas PA1', PA2', PA3'. The pixel areas PA1', PA2', PA3' may have a rectangular shape.

[0148] The pixel regions PA1', PA2', and PA3' may include: a plurality of first pixel regions PA1' displaying red; a plurality of second pixel regions PA2' displaying green; and a plurality of third pixel regions PA3' displaying blue. The first pixel regions PA1' and the second pixel regions PA2' may be alternately arranged along the first direction DR1.

[0149] The third pixel region PA3' may be disposed adjacent to one of both sides of the first and second pixel regions PA1' and PA2' opposite to each other in the second direction DR2 and arranged in the first direction DR1. The third pixel region PA3' may have a rectangular shape extending longer in the first direction DR1.

[0150] The display panel DP' may include a pixel defining film PDL' and a plurality of spacers SPC'. The pixel defining film PDL' may define a first opening OP1' overlapping with the pixel areas PA1', PA2', and PA3'. The pixel areas PA1', PA2', and PA3' may be defined by the first opening OP1'.

[0151] The pixel defining film PDL' may be defined with a second opening OP2' that overlaps the non-pixel area NPA' and extends between the pixel areas PA1', PA2', and PA3'. The pixel defining film PDL' may include: a plurality of first pixel defining films PDL1', which are separated from each other by the second opening OP2' and surround the pixel areas PA1', PA2', and PA3'; and a plurality of protrusions PRT' that protrude from the first pixel defining film PDL1'. Each protrusion PRT' may protrude from a portion of each first pixel defining film PDL1'.

[0152] The spacer SPC' may be disposed at a predetermined portion of the second opening portion OP2'. The spacer SPC' may be spaced apart from the pixel areas PA1', PA2', and PA3', and may have a rectangular shape.

[0153] Although the above description is made with reference to the embodiments, it is understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the scope of the concept and field of the present invention recorded in the claims. In addition, the embodiments disclosed in the present invention are not intended to limit the technical concept of the present invention, and should be interpreted as the scope of the present invention includes all technical concepts within the scope of the claims and equivalents thereof.

Claims

1. A display device, comprising: A substrate comprising a plurality of pixel regions and a non-pixel region around each of the pixel regions; A component layer is arranged on the substrate; A pixel definition film is arranged on the element layer and defines a plurality of first openings overlapping the pixel region and a plurality of second openings overlapping the non-pixel region and extending between the pixel regions; A plurality of light emitting elements are arranged in the first opening; An encapsulation layer is arranged on the element layer to cover the light-emitting element and the pixel definition film; a plurality of partitions arranged at predetermined portions of the second opening; as well as an input sensing portion, overlapping with the second opening portion and arranged on the packaging layer, The pixel definition film comprises: a plurality of first pixel definition films separated from each other by each of the plurality of second openings and surrounding the pixel region; a plurality of second pixel defining films arranged between the partition and the element layer and spaced apart from the first pixel defining films; and A plurality of protrusions protrude from the first pixel defining film.

2. The display device according to claim 1, wherein: The pixel regions are arranged along a first diagonal direction and a second diagonal direction intersecting the first diagonal direction, The second opening portion extends along the first diagonal direction and the second diagonal direction.

3. The display device according to claim 1, wherein: The dielectric constant of the organic layer of the encapsulation layer is lower than the dielectric constant of the pixel defining film.

4. The display device according to claim 1, wherein: The pixel defining film has a black color.

5. The display device according to claim 1, wherein: The input sensing unit comprises: A plurality of first sensing portions having a grid shape and arranged along a first direction; A plurality of first connecting parts, connected to the first sensing parts; a plurality of second sensing portions having the grid shape and arranged along a second direction intersecting the first direction; and A plurality of second connecting parts connected to the second sensing parts, When viewed from a plane defined by the first direction and the second direction, the first sensing portions and the second sensing portions are spaced from each other and arranged alternately, and the second connecting portion does not overlap with the first connecting portion.

6. The display device according to claim 5, wherein: The first sensing unit and the second sensing unit each include: A plurality of first branches extending on the plane along a first diagonal direction intersecting the first direction and the second direction; A plurality of second branches extending along a second diagonal direction intersecting the first diagonal direction, The grid shape is defined by the first branch and the second branch.

7. The display device according to claim 6, wherein: A touch opening defined by the first branch and the second branch overlaps with the pixel region, and the first branch and the second branch overlap with the second opening.

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