Display device

Abstract

A display device includes a substrate, a data line provided on the substrate to which a data voltage is applied, a scan line provided on the substrate to which a scan signal is applied, and a pixel connected to at least one of the data line and the scan line. The pixel includes a light emitting element, a drive transistor that supplies a drive current flowing between a first electrode and a second electrode to the light emitting element in accordance with the data voltage of the data line applied to a gate electrode, a first transistor between the gate electrode and the second electrode of the drive transistor, and a shield electrode overlapping at least a portion of the first transistor in a thickness direction of the substrate. The shield electrode does not overlap the data line in the thickness direction of the substrate.

Description

[0001] This application claims priority to and all the benefits of Korean Patent Application No. 10-2019-0143721, filed on November 11, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Exemplary embodiments of the present application relate to a display apparatus. BACKGROUND

[0003] As the information society develops, the demand for display apparatuses for displaying images has increased in various forms. Display apparatuses are applied to various electronic appliances such as smart phones, digital cameras, notebook computers, navigators, and smart TVs. Display apparatuses include flat panel display apparatuses such as liquid crystal display apparatuses, field emission display apparatuses, or light emitting display apparatuses.

[0004] Since a light emitting display apparatus includes pixels each including a light emitting element that emits light by itself, it can display an image without a backlight unit for providing light to a display panel. Each of the pixels in the light emitting display apparatus can include a light emitting element, a driving transistor for adjusting an amount of driving current supplied to the light emitting element from a driving voltage line according to a data voltage applied to a gate electrode through a data line, and a plurality of switching transistors turned on in response to a scan signal of a scan line. SUMMARY

[0005] Among the plurality of switching transistors, a switching transistor arranged adjacent to the data line can be affected by a voltage change of the data line.

[0006] Exemplary embodiments of the present application provide a display apparatus capable of preventing or reducing an effect of a voltage change of a data line on a switching transistor adjacent to the data line.

[0007] Exemplary embodiments of the present application provide a display apparatus including a substrate, a data line disposed on the substrate to which a data voltage is applied, a scan line disposed on the substrate to which a scan signal is applied, and a pixel connected to at least one of the data line and the scan line. The pixel includes a light emitting element, a driving transistor including a gate electrode, a first electrode, and a second electrode, and supplying a driving current flowing between the first electrode and the second electrode to the light emitting element according to a data voltage of the data line applied to the gate electrode, a first transistor between the gate electrode and the second electrode of the driving transistor, and a shield electrode overlapping at least a portion of the first transistor in a thickness direction of the substrate. The shield electrode does not overlap the data line in the thickness direction of the substrate.

[0008] An exemplary embodiment of the present invention provides a display device, comprising: a substrate; a light-emitting element; a driving transistor including a gate electrode, a first electrode, and a second electrode, wherein a driving current flowing between the first electrode and the second electrode is supplied to the light-emitting element according to a data voltage applied to a data line of the gate electrode; a first transistor arranged adjacent to another data line of the adjacent data line; and a shielding electrode overlapping at least a portion of the first transistor in the thickness direction of the substrate. The shielding electrode does not overlap with the data line. Attached Figure Description

[0009] These and / or other features of the invention will become apparent and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a perspective view of an exemplary embodiment of the display device;

[0011] Figure 2 It is a floor plan of the display device;

[0012] Figure 3 This is a block diagram of an exemplary embodiment of the display device;

[0013] Figure 4 This is a detailed circuit diagram of an exemplary embodiment of a sub-pixel;

[0014] Figure 5 This is a detailed plan view of an exemplary embodiment of a sub-pixel;

[0015] Figure 6 yes Figure 5 Detailed plan of area A;

[0016] Figure 7 It is along Figure 5 A cross-sectional view taken from line I-I';

[0017] Figure 8 It is along Figure 5 A cross-sectional view taken from line II-II';

[0018] Figure 9 This is an exemplary diagram illustrating horizontal crosstalk that occurs when the shielding electrode overlaps with the data line;

[0019] Figure 10 This is a detailed plan view of another exemplary embodiment of the sub-pixel;

[0020] Figure 11 yes Figure 10 Detailed plan of area B;

[0021] Figure 12 It is along Figure 10 A cross-sectional view taken from line III-III';

[0022] Figure 13 is a detailed plan view of another exemplary embodiment of a sub-pixel;

[0023] Figure 14 is a detailed plan view of region C of Figure 13

[0024] Figure 15 is a cross-sectional view taken along line IV-IV' of Figure 13

[0025] Figure 16 is another cross-sectional view taken along line IV-IV' of Figure 13

[0026] Figure 17 is a detailed plan view of another exemplary embodiment of a sub-pixel;

[0027] Figure 18 is a detailed plan view of region D of Figure 17

[0028] Figure 19 is a cross-sectional view taken along line V-V' of Figure 17

[0029] Figure 20 is a detailed plan view of another exemplary embodiment of a sub-pixel;

[0030] Figure 21 is a detailed plan view of region E of Figure 20

[0031] Figure 22 is a cross-sectional view taken along line VI-VI' of Figure 20

[0032] Figure 23 is a detailed plan view of another exemplary embodiment of a sub-pixel;

[0033] Figure 24 is a detailed plan view of region F of Figure 23

[0034] Figure 25 is a cross-sectional view taken along line VII-VII' of Figure 23

[0035] Figure 26 is a detailed plan view of another exemplary embodiment of a sub-pixel;

[0036] Figure 27 is a detailed plan view of region G of Figure 26

[0037] Figure 28 ​​​​​​​​​​It is along Figure 26 The cross-sectional view taken from line VIII-VIII'. Detailed Implementation

[0038] Exemplary embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the specification, the same reference numerals denote the same parts. In the drawings, the thickness of layers and regions is exaggerated for clarity.

[0039] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part without departing from the teachings of this document.

[0040] It should also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there may be an intermediate layer. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The singular forms “a” and “the (described)” as used herein are intended to include the plural forms, including “at least one”, unless the context clearly indicates otherwise. “Or” means “and / or”. “At least one of A and B” means “A and / or B”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0042] "about" or "approximately," as used in this patent document, is intended to include the value and mean the value plus or minus the limitations of the measuring system, as well as the error associated with the particular value in question, as determined by one of ordinary skill in the art.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0044] Herein, exemplary embodiments are described with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, a region illustrated or described as linear can typically have rough and / or nonlinear features. Likewise, illustrated sharp corners can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims to a precise region shape.

[0045] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a perspective view of an exemplary embodiment of a display device, Figure 2 is a plan view of an exemplary embodiment of a display device, and Figure 3 is a block diagram of an exemplary embodiment of a display device.

[0047] In this specification, a first direction (X-axis direction) can be a direction parallel to a short side of the display device 10 in a plan view, for example, a horizontal direction of the display device 10. A second direction (Y-axis direction) can be a direction parallel to a long side of the display device 10 in a plan view, for example, a vertical direction of the display device 10. A third direction (Z-axis direction) can be a thickness direction of the display panel 100.

[0048] Reference is made to Figures 1 to 3As a device for displaying a moving image or a still image, the display device 10 can be used as a display screen of various products such as a television, a notebook, a monitor, a billboard, an Internet of Things ("IOT"), and portable electronic appliances such as a mobile phone, a smart phone, a tablet personal computer (tablet "PC"), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player ("PMP"), a navigator, and an Ultra Mobile PC ("UMPC").

[0049] The display device 10 can be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode ("OLED"), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro light-emitting display device using a micro light-emitting diode (micro "LED"). Hereinafter, the display device 10 will be mainly described as an organic light-emitting display device, but the present application is not limited thereto.

[0050] The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0051] The display panel 100 can have a rectangular planar shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). An angle at which the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) can have a circular shape having a predetermined curvature or a right-angled shape. The planar shape of the display panel 100 is not limited to a rectangular shape, and can be provided as another polygonal shape, a circular shape, or an elliptical shape. The display panel 100 can be flat, but the present application is not limited thereto. For example, in an exemplary embodiment, the display panel 100 can include curved portions provided at left and right ends thereof and having a constant curvature or a variable curvature. In addition, the display panel 100 can be flexible to be bent, wound, folded, or curled.

[0052] The display panel 100 can include a main area MA and a sub area SA. The main area MA can include a display area DA in which a sub-pixel SP displays an image and a non-display area NDA which is a surrounding area of the display area DA. The display area DA can be provided with a scan line SL, an emission line EL, a data line DL, and a first driving voltage line VDDL connected to the sub-pixel SP, in addition to the sub-pixel SP.

[0053] The scan line SL and the emission line EL can be disposed in parallel in the first direction (X-axis direction). The data line DL can be disposed in parallel in the second direction (Y-axis direction) which intersects the first direction (X-axis direction).

[0054] The first driving voltage lines VDDL can extend in parallel in the second direction (Y-axis direction) in the display area DA. The first driving voltage lines VDDL extending in parallel in the second direction (Y-axis direction) in the display area DA can be connected to each other in the non-display area NDA. In an alternative exemplary embodiment, the first driving voltage lines VDDL can include first sub-driving voltage lines provided in parallel in the second direction (Y-axis direction) in the display area DA and second sub-driving voltage lines provided in parallel in the first direction (X-axis direction) in the display area DA.

[0055] Each of the subpixels SP can be connected to at least one of the scan lines SL, one of the data lines DL, at least one of the emission lines EL, and the first driving voltage line VDDL. Although it is shown in Figure 2 that each of the subpixels SP is connected to two scan lines SL, one data line DL, one emission line EL, and the first driving voltage line VDDL, the present application is not limited thereto, and each of the subpixels SP can be connected to, for example, three scan lines SL instead of two scan lines SL.

[0056] Each of the subpixels SP can include a driving transistor, at least one transistor, an emission element, and a capacitor. When a scan signal is applied from the scan line SL, the transistor is turned on, and thus a data voltage of the data line DL can be applied to a gate electrode of the driving transistor DT (refer to FIG. 1). The driving transistor DT can supply a driving current to the emission element according to the data voltage applied to the gate electrode, so that the emission element emits light. The driving transistor DT and the at least one transistor ST1-ST6 (refer to FIG. 1) can be thin film transistors ("TFTs"). The emission element can emit light according to the driving current of the driving transistor DT. The emission element can be an OLED including a first electrode, an organic emission layer, and a second electrode. The capacitor can function to maintain the data voltage applied to the gate electrode of the driving transistor DT constant. Figure 4 Figure 4 Each of the subpixels SP can include a driving transistor, at least one transistor, an emission element, and a capacitor. When a scan signal is applied from the scan line SL, the transistor is turned on, and thus a data voltage of the data line DL can be applied to a gate electrode of the driving transistor DT (refer to FIG. 1). The driving transistor DT can supply a driving current to the emission element according to the data voltage applied to the gate electrode, so that the emission element emits light. The driving transistor DT and the at least one transistor ST1-ST6 (refer to FIG. 1) can be thin film transistors ("TFTs"). The emission element can emit light according to the driving current of the driving transistor DT. The emission element can be an OLED including a first electrode, an organic emission layer, and a second electrode. The capacitor can function to maintain the data voltage applied to the gate electrode of the driving transistor DT constant.

[0057] The non-display area NDA can be defined as an area from an outside of the display area DA to an edge of the display panel 100. The non-display area NDA can be provided with a scan driver 400 for applying a scan signal to the scan lines SL, fan-out lines FL located between the data lines DL and the display driving circuit 200, and a pad DP connected to the display driving circuit 200. The display driving circuit 200 and the pad DP can be disposed at one side edge of the display panel 100. The pad DP can be disposed adjacent to the display driving circuit 200 at one side edge of the display panel 100.

[0058] The sub-area SA can protrude in the second direction (Y-axis direction) from one side of the main area MA. As shown in FIG. 2, the sub-area SA can be provided with a plurality of subpixels SP.​Figure 2 As shown, the length of sub-region SA in the first direction (X-axis direction) can be less than the length of main region MA in the first direction (X-axis direction), and the length of sub-region SA in the second direction (Y-axis direction) can be less than the length of main region MA in the second direction (Y-axis direction), but the present invention is not limited thereto.

[0059] The sub-region SA can be bent and can be arranged on the lower surface of the display panel 100. The sub-region SA can overlap with the main region MA in the thickness direction (Z-axis direction) of the substrate. The pad DP and the display driving circuit 200 can be disposed in the sub-region SA.

[0060] The scan driver 400 can be connected to the display driver circuit 200 via multiple scan control lines SCL. The scan driver 400 can receive scan control signals SCS and light emission control signals ECS from the display driver circuit 200 via multiple scan control lines SCL.

[0061] like Figure 3 As shown, the scan driver 400 may include a scan signal output unit 410 and a light emission signal output unit 420. The scan signal output unit 410 can generate a scan signal according to the scan control signal SCS, and can output the scan signal sequentially to the scan line SL. The light emission signal output unit 420 can generate a light emission control signal according to the light emission control signal ECS, and can output the light emission control signal sequentially to the light emission line EL.

[0062] The scan driver 400 may include a plurality of TFTs. The scan driver 400 may be arranged in the same layer as the TFTs of the sub-pixel SP. In an alternative exemplary embodiment, the scan driver 400 may be arranged in a different layer from the TFTs of the sub-pixel SP.

[0063] Despite Figure 2 The diagram shows a scan driver 400 arranged in a non-display area NDA located on one side (e.g., the left side) of the display area DA, but the invention is not limited thereto. For example, in an exemplary embodiment, the scan driver 400 may be arranged in non-display areas NDA located on both sides (e.g., the left and right sides) of the display area DA.

[0064] In an exemplary embodiment, the display driving circuit 200 may be provided as an integrated circuit (“IC”) and may be attached to the display panel 100 via a chip-on-glass (“COG”) method, a chip-on-plastic (“COP”) method, or an ultrasonic bonding method. However, the invention is not limited thereto. For example, in an exemplary embodiment, the display driving circuit 200 may be attached to a circuit board 300 via a COG method. Figure 3As shown in the middle, the display driving circuit 200 can include a timing controller 210, a data driver 220, and a power supply unit 230.

[0065] The timing controller 210 receives digital video data and a timing signal from the circuit board 300. The timing controller 210 can generate a scan control signal SCS for controlling the operation timing of the scan signal output unit 410 according to the timing signal, can generate an emission control signal ECS for controlling the operation timing of the emission signal output unit 420, and can generate a data control signal DCS for controlling the operation timing of the data driver 220. The timing controller 210 can output the scan control signal SCS to the scan signal output unit 410 through a plurality of scan control lines SCL, and can output the emission control signal ECS to the emission signal output unit 420. The timing controller 210 can output the digital video data DATA and the data control signal DCS to the data driver 220.

[0066] The data driver 220 converts the digital video data DATA into data voltages of an analog positive polarity or a negative polarity, and outputs the data voltages to the data lines DL through fan-out lines FL. The sub-pixels SP are selected by the scan signals of the scan driver 400, and the data voltages are supplied to the selected sub-pixels SP.

[0067] The power supply unit 230 can generate a first driving voltage, and supply the first driving voltage to a first driving voltage line VDDL. In addition, the power supply unit 230 can generate a second driving voltage, and supply the second driving voltage to the cathode electrode of the OLED of each of the sub-pixels SP. The first driving voltage can be a high potential voltage for driving the OLED, and the second driving voltage can be a low potential voltage for driving the OLED. That is, the first driving voltage can have a higher potential than the second driving voltage.

[0068] The circuit board 300 can be attached to the pad DP using an anisotropic conductive film. Accordingly, the lead of the circuit board 300 can be electrically connected to the pad DP. In an exemplary embodiment, the circuit board 300 can be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip on film.

[0069] Figure 4 is a detailed circuit diagram of an exemplary embodiment of a sub-pixel.

[0070] Reference Figure 4The sub-pixel SP can be connected to a (k-1)-th (k is an integer equal to or greater than 2) scan line Sk-1, a k-th scan line Sk, and a j-th (j is a positive integer) data line Dj. Further, the sub-pixel SP can be connected to a first drive voltage line VDDL for supplying a first drive voltage, an initialization voltage line VIL for supplying an initialization voltage, and a second drive voltage line VSSL for supplying a second drive voltage.

[0071] The sub-pixel SP includes a drive transistor DT, a light emitting element LEL, a switching element, and a capacitor C1. The switching element includes first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0072] The drive transistor DT can include a gate electrode, a first electrode, and a second electrode.

[0073] The drive transistor DT controls a drain-source current Ids (hereinafter referred to as a "drive current") flowing between the first electrode and the second electrode in accordance with a data voltage applied to the gate electrode. The drive current Ids flowing through a channel of the drive transistor DT is proportional to the square of the difference between a gate-source voltage Vgs of the drive transistor DT and a threshold voltage Vth, as shown in the following Equation 1.

[0074] [Equation 1] Ids = k' × (Vgs - Vth) 2

[0075] In Equation 1, k' is a proportional coefficient determined by the structure and physical characteristics of the drive transistor DT, Vgs is the gate-source voltage of the drive transistor DT, and Vth is the threshold voltage of the drive transistor DT.

[0076] The light emitting element LEL emits light in accordance with the drive current Ids. The amount of light emission of the light emitting element LEL can be proportional to the drive current Ids.

[0077] The light emitting element LEL can be an OLED including an anode electrode, a cathode electrode, and an organic light emitting layer arranged between the anode electrode and the cathode electrode. In an alternative exemplary embodiment, the light emitting element LEL can be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor arranged between the anode electrode and the cathode electrode. In an alternative exemplary embodiment, the light emitting element LEL can be a quantum dot light emitting element including an anode electrode, a cathode electrode, and a quantum dot light emitting layer arranged between the anode electrode and the cathode electrode. In an alternative exemplary embodiment, the light emitting element LEL can be a micro LED.

[0078] The anode electrode of the light emitting element LEL can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode of the light emitting element LEL can be connected to the second drive voltage line VSSL. A parasitic capacitance Cel can be provided between the anode electrode and the cathode electrode of the light emitting element LEL.

[0079] The first transistor ST1 can be a dual transistor including a 1-1 transistor ST1-1 and a 1-2 transistor ST1-2. The 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 are turned on by a scan signal of the k-th scan line Sk to connect the gate electrode and the second electrode of the driving transistor DT. That is, when the 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 are turned on, the gate electrode and the second electrode of the driving transistor DT are connected to each other so that the driving transistor DT is driven as a diode. The gate electrode of the 1-1 transistor ST1-1 can be connected to the k-th scan line Sk, the first electrode of the 1-1 transistor ST1-1 can be connected to the second electrode of the 1-2 transistor ST1-2, and the second electrode of the 1-1 transistor ST1-1 can be connected to the gate electrode of the driving transistor DT. The gate electrode of the 1-2 transistor ST1-2 can be connected to the k-th scan line Sk, the first electrode of the 1-2 transistor ST1-2 can be connected to the second electrode of the driving transistor DT, and the second electrode of the 1-2 transistor ST1-2 can be connected to the first electrode of the 1-1 transistor ST1-1.

[0080] The second transistor ST2 is turned on by a scan signal of the k-th scan line Sk to connect the first electrode of the driving transistor DT to the j-th data line Dj. The gate electrode of the second transistor ST2 can be connected to the k-th scan line Sk, the first electrode of the second transistor ST2 can be connected to the first electrode of the driving transistor DT, and the second electrode of the second transistor ST2 can be connected to the j-th data line Dj.

[0081] The third transistor ST3 can be a dual transistor including a 3-1 transistor ST3-1 and a 3-2 transistor ST3-2. The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 are turned on by a scan signal of the k-1th scan line Sk-1 to connect the gate electrode of the driving transistor DT to the initialization voltage line VIL. The gate electrode of the driving transistor DT can be discharged to the initialization voltage of the initialization voltage line VIL. The gate electrode of the 3-1 transistor ST3-1 can be connected to the k-1th scan line Sk-1, the first electrode of the 3-1 transistor ST3-1 can be connected to the gate electrode of the driving transistor DT, and the second electrode of the 3-1 transistor ST3-1 can be connected to the first electrode of the 3-2 transistor ST3-2. The gate electrode of the 3-2 transistor ST3-2 can be connected to the k-1th scan line Sk-1, the first electrode of the 3-2 transistor ST3-2 can be connected to the second electrode of the 3-1 transistor ST3-1, and the second electrode of the 3-2 transistor ST3-2 can be connected to the initialization voltage line VIL.

[0082] The fourth transistor ST4 is turned on by a scan signal of the kth scan line Sk to connect the anode electrode of the light emitting element LEL to the initialization voltage line VIL. The anode electrode of the light emitting element LEL can be discharged to the initialization voltage of the initialization voltage line VIL. The gate electrode of the fourth transistor ST4 can be connected to the kth scan line Sk, the first electrode of the fourth transistor ST4 can be connected to the anode electrode of the light emitting element LEL, and the second electrode of the fourth transistor ST4 can be connected to the initialization voltage line VIL.

[0083] The fifth transistor ST5 is turned on by a light emitting control signal of the kth light emitting control line Ek to connect the first electrode of the driving transistor DT to the first driving voltage line VDDL. The gate electrode of the fifth transistor ST5 is connected to the kth light emitting control line Ek, the first electrode of the fifth transistor ST5 is connected to the first driving voltage line VDDL, and the second electrode of the fifth transistor ST5 is connected to the first electrode of the driving transistor DT.

[0084] The sixth transistor ST6 is connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LEL. The sixth transistor ST6 is turned on by a light emitting control signal of the kth light emitting control line Ek to connect the second electrode of the driving transistor DT to the anode electrode of the light emitting element LEL. The gate electrode of the sixth transistor ST6 is connected to the kth light emitting control line Ek, the first electrode of the sixth transistor ST6 is connected to the second electrode of the driving transistor DT, and the second electrode of the sixth transistor ST6 is connected to the anode electrode of the light emitting element LEL. When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving current Ids can be supplied to the light emitting element LEL.

[0085] The capacitor C1 is provided between the gate electrode of the drive transistor DT and the first drive voltage line VDDL. One electrode of the capacitor C1 can be connected to the gate electrode of the drive transistor DT, and the other electrode of the capacitor C1 can be connected to the first drive voltage line VDDL.

[0086] When the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the drive transistor DT is a source electrode, the second electrode thereof can be a drain electrode. In an alternative exemplary embodiment, when the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the drive transistor DT is a drain electrode, the second electrode thereof can be a source electrode.

[0087] The active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the drive transistor DT can include any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the drive transistor DT can include polysilicon, a process of forming the active layer can be, for example, a low temperature polysilicon ("LTPS") process.

[0088] Although it is mainly described in Figure 4 that the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 and the drive transistor DT include P-type metal oxide semiconductor field effect transistors ("MOSFETs"), the present application is not limited thereto, and they can include N-type MOSFETs.

[0089] The first drive voltage of the first drive voltage line VDDL, the second drive voltage of the second drive voltage line VSSL, and the initialization voltage of the initialization voltage line VIL can be set in consideration of the characteristics of the drive transistor DT and the characteristics of the light emitting element LEL. For example, in an exemplary embodiment, a voltage difference between the initialization voltage and the data voltage supplied to the first electrode of the drive transistor DT can be set to be less than the threshold voltage of the drive transistor DT.

[0090] Figure 5 is a detailed plan view of the exemplary embodiment of the sub-pixel, and Figure 6 is Figure 5 a detailed plan view of the region A of

[0091] Reference is made to Figure 5 and Figure 6The sub-pixel SP can include a driving transistor DT, first to sixth transistors ST1 to ST6, a capacitor C1, a first connection electrode BE1, a second connection electrode VIE, a data connection electrode DCE, and a shield electrode SHE.

[0092] The sub-pixel SP can overlap the (k-1)th scan line Sk-1, the kth scan line Sk, the kth light emission control line Ek, the jth data line Dj, the first driving voltage line VDDL1, and the initialization voltage line VIL in the third direction (Z-axis direction). The sub-pixel SP can be connected to the (k-1)th scan line Sk-1, the kth scan line Sk, the jth data line Dj, and the first driving voltage line VDDL1 through the first to sixth transistors ST1 to ST6. The (k-1)th scan line Sk-1, the kth scan line Sk, the kth light emission control line Ek, and the initialization voltage line VIL can extend in the first direction (X-axis direction). The jth data line Dj can extend in the second direction (Y-axis direction).

[0093] The first driving voltage line VDDL1 can include a first sub-driving voltage line SVDDL1 and a second sub-driving voltage line SVDDL2. The first sub-driving voltage line SVDDL1 can extend in the second direction (Y-axis direction), and the second sub-driving voltage line SVDDL2 can extend in the first direction (X-axis direction). The first sub-driving voltage line SVDDL1 can be disposed between the jth data line Dj and the first connection electrode BE1 in the first direction (X-axis direction). The second sub-driving voltage line SVDDL2 can be disposed between the kth scan line Sk and the kth light emission control line Ek in the second direction (Y-axis direction). The first sub-driving voltage line SVDDL1 can be connected to the second sub-driving voltage line SVDDL2 through an eighth contact hole CNT8.

[0094] The driving transistor DT can include an active layer DT_ACT, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The active layer DT_ACT of the driving transistor DT can overlap the gate electrode DT_G of the driving transistor DT in the third direction (Z-axis direction). The gate electrode DT_G can be disposed on the active layer DT_ACT of the driving transistor DT.

[0095] The gate electrode DT_G can be connected to the first connection electrode BE1 through a first connection contact hole BCNT1. The first connection electrode BE1 can be connected to the second electrode D1-1 of the 1-1th transistor ST1-1 through a second connection contact hole BCNT2. Since the first connection electrode BE1 extends in the second direction (Y-axis direction), the first connection electrode BE1 can cross the kth scan line Sk.

[0096] The first electrode DT_S of the drive transistor DT can be connected to the first electrode S2 of the second transistor ST2. The second electrode DT_D of the drive transistor DT can be connected to the first electrode S1-2 of the first-2 transistor ST1-2 and the first electrode S6 of the sixth transistor ST6.

[0097] The first transistor ST1 can be provided as a dual transistor. The first transistor ST1 can include a first-1 transistor ST1-1 and a first-2 transistor ST1-2.

[0098] The first-1 transistor ST1-1 can include an active layer ACT1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. The gate electrode G1-1 of the first-1 transistor ST1-1 is a part of the k-th scan line Sk, and can be an overlapping area of the active layer ACT1-1 of the first-1 transistor ST1-1 and the k-th scan line Sk in the third direction (Z-axis direction). The first electrode S1-1 of the first-1 transistor ST1-1 can be connected to the second electrode D1-2 of the first-2 transistor ST1-2. The second electrode D1-1 of the first-1 transistor ST1-1 can be connected to the first connection electrode BE1 through the second connection contact hole BCNT2.

[0099] The first-2 transistor ST1-2 can include an active layer ACT1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. The gate electrode G1-2 of the first-2 transistor ST1-2 is a part of the k-th scan line Sk, and can be an overlapping area of the active layer ACT1-2 of the first-2 transistor ST1-2 and the k-th scan line Sk in the third direction (Z-axis direction). The first electrode S1-2 of the first-2 transistor ST1-2 can be connected to the second electrode DT_D of the drive transistor DT. The second electrode D1-2 of the first-2 transistor ST1-2 can be connected to the first electrode S1-1 of the first-1 transistor ST1-1.

[0100] The second transistor ST2 can include an active layer ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 is a part of the k-th scan line Sk, and can be an overlapping area of the active layer ACT2 of the second transistor ST2 and the k-th scan line Sk in the third direction (Z-axis direction). The first electrode S2 of the second transistor ST2 can be connected to the first electrode DT_S of the drive transistor DT. The second electrode D2 of the second transistor ST2 can be connected to the data connection electrode DCE through the third contact hole CNT3. The data connection electrode DCE can be connected to the j-th data line Dj through the data contact hole DCNT.

[0101] The third transistor ST3 can be provided as a dual transistor. The third transistor ST3 can include a 3-1 transistor ST3-1 and a 3-2 transistor ST3-2.

[0102] The 3-1 transistor ST3-1 can include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of the 3-1 transistor ST3-1 is a part of the k-1th scan line Sk-1, and can be an overlapping area of the active layer ACT3-1 of the 3-1 transistor ST3-1 and the k-1th scan line Sk-1. The first electrode S3-1 of the 3-1 transistor ST3-1 can be connected to the first connection electrode BE1 through a second connection contact hole BCNT2. The second electrode D3-1 of the 3-1 transistor ST3-1 can be connected to the first electrode S3-2 of the 3-2 transistor ST3-2.

[0103] The 3-2 transistor ST3-2 can include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of the 3-2 transistor ST3-2 is a part of the k-1th scan line Sk-1, and can be an overlapping area of the active layer ACT3-2 of the 3-2 transistor ST3-2 and the k-1th scan line Sk-1. The first electrode S3-2 of the 3-2 transistor ST3-2 can be connected to the second electrode D3-1 of the 3-1 transistor ST3-1. The second electrode D3-2 of the 3-2 transistor ST3-2 can be connected to the second connection electrode VIE through a fourth contact hole CNT4.

[0104] The fourth transistor ST4 can include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 is a part of the kth scan line Sk, and can be an overlapping area of the active layer ACT4 of the fourth transistor ST4 and the kth scan line Sk. The first electrode S4 of the fourth transistor ST4 can be connected to the first anode connection electrode ANDE1 through a sixth contact hole CNT6. An anode electrode of the light emitting element can be connected to the first anode connection electrode ANDE1 through a second anode connection electrode ANDE2 (see Figure 7 ). The second electrode D4 of the fourth transistor ST4 can be connected to the second connection electrode VIE through a fourth contact hole CNT4. An initialization voltage line VIL can be connected to the second connection electrode VIE through a fifth contact hole CNT5, and the second connection electrode VIE can be connected to the second electrode D3-2 of the 3-2 transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 through the fourth contact hole CNT4. The second connection electrode VIE can extend in a second direction (Y-axis direction), and can intersect the k-1th scan line Sk-1.

[0105] The fifth transistor ST5 can include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 is part of the kth light emission control line Ek, and can be an overlapping region of the active layer ACT5 of the fifth transistor ST5 and the kth light emission control line Ek. The first electrode S5 of the fifth transistor ST5 can be connected to the first sub driving voltage line SVDDL1 through the seventh contact hole CNT7. The second electrode D5 of the fifth transistor ST5 can be connected to the first electrode DT_S of the driving transistor DT.

[0106] The sixth transistor ST6 can include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6 is part of the kth light emission control line Ek, and can be an overlapping region of the active layer ACT6 of the sixth transistor ST6 and the kth light emission control line Ek. The first electrode S6 of the sixth transistor ST6 can be connected to the second electrode DT_D of the driving transistor DT. The second electrode D6 of the sixth transistor ST6 can be connected to the first anode connection electrode ANDE1 through the sixth contact hole CNT6.

[0107] The first electrode of the capacitor C1 is part of the gate electrode DT_G of the driving transistor DT, and the second electrode of the capacitor C1 can be the second sub driving voltage line SVDDL2 overlapping the gate electrode DT_G of the driving transistor DT.

[0108] The shield electrode SHE can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). Among the first transistor ST1 to the sixth transistor ST6, the first transistor ST1 can be disposed closest to the j+1th data line Dj+1.

[0109] Specifically, as shown in Figure 5 and Figure 6 , the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 can be disposed adjacent to the j+1th data line Dj+1. In this case, a parasitic capacitance can be provided between the first electrode S1-1 of the 1-1 transistor ST1-1 and the j+1th data line Dj+1 and between the second electrode D1-2 of the 1-2 transistor ST1-2 and the j+1th data line Dj+1. The parasitic capacitance can be an edge capacitance. Due to the parasitic capacitance, the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 can be affected by a data voltage jump of the j+1th data line Dj+1.

[0110] The shield electrode SHE can overlap the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 in the third direction (Z-axis direction). Due to the shield electrode SHE, a parasitic capacitance can be reduced. Thus, an influence of a data voltage jump of the (j+1)th data line Dj+1 on the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 can be reduced.

[0111] The shield electrode SHE can include a connection portion CNP and a shield portion SHP. The connection portion CNP can be connected to a first sub drive voltage line SVDDL1 adjacent to the (j+1)th data line Dj+1 in the first direction (X-axis direction). The connection portion CNP can be connected to the first sub drive voltage line SVDDL1 through a first contact hole CNT1.

[0112] The connection portion CNP can overlap the first sub drive voltage line SVDDL1 in the third direction (Z-axis direction). In an overlapping region of the first sub drive voltage line SVDDL1 and the connection portion CNP, a length of the connection portion CNP in the first direction (X-axis direction) can be longer than a length of the first sub drive voltage line SVDDL1 in the first direction (X-axis direction).

[0113] The connection portion CNP can extend in the second direction (Y-axis direction). One end of the connection portion CNP in the second direction (Y-axis direction) can be adjacent to the (k-1)th scan line Sk-1, and the other end of the connection portion CNP in the second direction (Y-axis direction) can be adjacent to the kth scan line Sk.

[0114] The shield portion SHP can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). The shield portion SHP can overlap the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 in the third direction (Z-axis direction).

[0115] The shield portion SHP can protrude from the connection portion CNP and extend in the first direction (X-axis direction). The shield portion SHP can intersect the (j+1)th data line Dj+1.

[0116] Figure 7 is a cross-sectional view taken along the line I-I’ of Figure 5 and Figure 8 is a cross-sectional view taken along the line II-II’ of Figure 5 .

[0117] Referring to Figure 7 and Figure 8The TFT layer TFTL, the light emitting element layer EML, and the encapsulation layer TFE can be sequentially arranged on the substrate SUB1.

[0118] The TFT layer TFTL includes the light blocking layer BML, the buffer film BF, the active layer, the first gate layer GTL1, the second gate layer GTL2, the data metal layer including the first data metal layer DTL1 and the second data metal layer DTL2, the gate insulating film 130, the first interlayer insulating film 141, the second interlayer insulating film 142, the protective film 150, the first organic film 160, and the second organic film 161.

[0119] The light blocking layer BML can be arranged on one surface of the substrate SUB1. The light blocking layer BML can overlap the active layer DT_ACT of the drive transistor DT in the third direction (Z-axis direction) to block light incident on the active layer DT_ACT of the drive transistor DT, but the present application is not limited thereto. In alternative exemplary embodiments, the light blocking layer BML can overlap the active layer DT_ACT of the drive transistor DT and the active layers ACT1 to ACT6 of the first to sixth transistors ST1 to ST6 in the third direction (Z-axis direction) so as to block light incident on the active layers DT_ACT of the drive transistor DT and the active layers ACT1 to ACT6 of the first to sixth transistors ST1 to ST6. The third direction (Z-axis direction) can be a thickness direction of the substrate SUB1. For example, in exemplary embodiments, the light blocking layer BML can have a single-layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0120] The buffer film BF can be arranged on the light blocking layer BML. The buffer film BF can be arranged on one surface of the substrate SUB1 to protect the TFT and the organic light emitting layer 172 of the light emitting element layer EML from moisture permeating through the substrate SUB1 susceptible to moisture permeation. The buffer film BF can include a plurality of inorganic films alternately laminated. For example, in exemplary embodiments, the buffer film BF can be a multi-layer film in which two or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated. In another exemplary embodiment, the buffer film BF can be omitted.

[0121] The active layer can be disposed on the substrate SUB1 or the buffer film BF. In an exemplary embodiment, the active layer can include polysilicon, single crystal silicon, low-temperature polysilicon, amorphous silicon, or an oxide semiconductor. When the active layer includes polysilicon or an oxide semiconductor, the active layer doped with ions can have conductivity. Accordingly, the active layer can include not only the active layers DT_ACT, ACT1-1, ACT1-2, ACT2, ACT3-1, ACT3-2, ACT4, ACT5, and ACT6 of the driving transistor DT and the first to sixth transistors ST1 to ST6 but also the first electrodes DT_S, S1-1, S1-2, S2, S3-1, S3-2, S4, S5, and S6 and the second electrodes DT_D, D1-1, D1-2, D2, D3-1, D3-2, D4, D5, and D6.

[0122] The gate insulating film 130 can be disposed on the active layer. In an exemplary embodiment, the gate insulating film 130 can include an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0123] The first gate layer GTL1 can be disposed on the gate insulating film 130. The first gate layer GTL1 can include not only the gate electrode DT_G of the driving transistor DT and the gate electrodes G1-1, G1-2, G2, G3-1, G3-2, G4, G5, and G6 of the first to sixth transistors ST1 to ST6 but also the scan lines Sk-1 and Sk and the emission control lines Ek. For example, in an exemplary embodiment, the first gate layer GTL1 can have a single-layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0124] The first interlayer insulating film 141 can be disposed on the first gate layer GTL1. In an exemplary embodiment, the first interlayer insulating film 141 can include an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 can include a plurality of inorganic films.

[0125] The second gate layer GTL2 can be disposed on the first interlayer insulating film 141. The second gate layer GTL2 can include the initialization voltage line VIL, the second sub driving voltage line SVDDL2, and the shield electrode SHE. For example, in an exemplary embodiment, the second gate layer GTL2 can have a single-layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0126] A second interlayer insulating film 142 can be disposed on the second gate layer GTL2. In an exemplary embodiment, the second interlayer insulating film 142 can include an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 can include a plurality of inorganic films.

[0127] A first data metal layer DTL1 can be disposed on the second interlayer insulating film 142. The first data metal layer DTL1 can include a first sub driving voltage line SVDDL1, a first connection electrode BE1, a second connection electrode VIE, a data connection electrode DCE, and a first anode connection electrode ANDE1. For example, in an exemplary embodiment,

[0128] The first data metal layer DTL1 can have a single layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0129] A first organic film 160 for planarizing a step due to the active layer, the first gate layer GTL1, the second gate layer GTL2, and the first data metal layer DTL1 can be disposed on the first data metal layer DTL1. For example, in an exemplary embodiment, the first organic film 160 can be an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0130] A protective film 150 can be additionally disposed between the first data metal layer DTL1 and the first organic film 160. The protective film 150 can include an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0131] A second data metal layer DTL2 can be disposed on the first organic film 160. The second data metal layer DTL2 can include data lines Dj and Dj+1 and a second anode connection electrode ANDE2. For example, in an exemplary embodiment, the second data metal layer DTL2 can have a single layer structure or a multi-layer structure including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof.

[0132] A second organic film 161 for planarizing a step can be disposed on the second data metal layer DTL2. The second organic film 161 can be an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0133] Although it is exemplified that the drive transistor DT and the first to sixth transistors ST1 to ST6 are provided by a top gate method in which the gate electrode is arranged above the active layer, the present application is not limited thereto. That is, the drive transistor DT and the first to sixth transistors ST1 to ST6 can be provided by a bottom gate method in which the gate electrode is arranged below the active layer or a dual gate method in which the gate electrode is arranged above and below the active layer.

[0134] The first connection contact hole BCNT1 can be a hole that penetrates the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the gate electrode DT_G of the drive transistor DT. The first connection electrode BE1 can be connected to the gate electrode DT_G of the drive transistor DT through the first connection contact hole BCNT1.

[0135] The second connection contact hole BCNT2 can be a hole that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D1-1 of the 1-1 transistor ST1-1. The first connection electrode BE1 can be connected to the second electrode D1-1 of the 1-1 transistor ST1-1 through the second connection contact hole BCNT2.

[0136] The data contact hole DCNT can be a hole that penetrates the protective film 150 and the first organic film 160 to expose the data connection electrode DCE. Each of the data lines Dj and Dj+1 can be connected to the data connection electrode DCE through the data contact hole DCNT.

[0137] The first contact hole CNT1 can be a hole that penetrates the second interlayer insulating film 142 to expose the shield electrode SHE. The first sub drive voltage line SVDDL1 can be connected to the shield electrode SHE through the first contact hole CNT1.

[0138] The third contact hole CNT3 can be a hole that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D2 of the second transistor ST2. The data connection electrode DCE can be connected to the second electrode D2 of the second transistor ST2 through the third contact hole CNT3.

[0139] The fourth contact hole CNT4 can be a hole that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D3-2 of the 3-2 transistor ST3-2 and the second electrode D4 of the fourth transistor ST4. The second connection electrode VIE can be connected to the second electrode D3-2 of the 3-2 transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 through the fourth contact hole CNT4.

[0140] The fifth contact hole CNT5 can be a hole that penetrates through the second interlayer insulating film 142 to expose the initialization voltage line VIL. The second connection electrode VIE can be connected to the initialization voltage line VIL through the fifth contact hole CNT5.

[0141] The sixth contact hole CNT6 can be a hole that penetrates through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D6 of the sixth transistor ST6. The first anode connection electrode ANDE1 can be connected to the second electrode D6 of the sixth transistor ST6 through the sixth contact hole CNT6.

[0142] The seventh contact hole CNT7 can be a hole that penetrates through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the first electrode S5 of the fifth transistor ST5. The first sub drive voltage line SVDDL1 can be connected to the first electrode S5 of the fifth transistor ST5 through the seventh contact hole CNT7.

[0143] The eighth contact hole CNT8 can be a hole that penetrates through the second interlayer insulating film 142 to expose the second sub drive voltage line SVDDL2. The first sub drive voltage line SVDDL1 can be connected to the second sub drive voltage line SVDDL2 through the eighth contact hole CNT8.

[0144] The first anode contact hole AND_CNT1 can be a hole that penetrates through the protective film 150 and the first organic film 160 to expose the first anode connection electrode ANDE1. The second anode connection electrode ANDE2 can be connected to the first anode connection electrode ANDE1 through the first anode contact hole AND_CNT1.

[0145] The second anode contact hole AND_CNT2 can be a hole that penetrates through the second organic film 161 to expose the second anode connection electrode ANDE2.

[0146] The light emitting element layer EML can be arranged on the TFT layer TFTL. The light emitting element layer EML can include the light emitting element 170 and the pixel defining film 180.

[0147] The light emitting element 170 and the pixel defining film 180 are arranged on the second organic film 161. Each of the light emitting elements 170 can include a first electrode 171, an organic light emitting layer 172, and a second electrode 173.

[0148] The first electrode 171 can be arranged on the second organic film 161. The first electrode 171 can be connected to the second anode connection electrode ANDE2 through the second anode contact hole AND_CNT2.

[0149] In a top emission structure in which light is emitted from the organic light emitting layer 172 toward the second electrode 173, the first electrode 171 can include a metal material having high reflectivity, such as a laminate structure of aluminum and titanium (Ti / Al / Ti), a laminate structure of aluminum and indium tin oxide ("ITO") ("ITO / Al / ITO"), an APC alloy, or a laminate structure of an APC alloy and ITO ("ITO / APC / ITO"). The APC alloy refers to an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0150] The pixel defining film 180 can divide the first electrode 171 on the second organic film 161 to define the light emitting area EA of each of the sub-pixels SP in the sub-pixel SP. For example, the pixel defining film 180 can cover edges of the first electrode 171, and can include an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0151] The light emitting area EA of each of the sub-pixels SP is defined as an area in which the first electrode 171, the organic light emitting layer 172, and the second electrode 173 are sequentially laminated and thus holes from the first electrode 171 and electrons from the second electrode 173 are combined to emit light.

[0152] The organic light emitting layer 172 can be disposed on the first electrode 171 and the pixel defining film 180. The organic light emitting layer 172 can include an organic material that emits light of a predetermined color. For example, in an exemplary embodiment, the organic light emitting layer 172 can include a hole transport layer, an organic material layer, and an electron transport layer. Among the sub-pixels SP, the organic light emitting layer 172 of the first sub-pixel can emit light of a first color, the organic light emitting layer 172 of the second sub-pixel can emit light of a second color, and the organic light emitting layer 172 of the third sub-pixel can emit light of a third color. In an alternative exemplary embodiment, the organic light emitting layer 172 of the sub-pixel SP can emit white light. In this case, the first sub-pixel can overlap with a color filter layer of the first color, the second sub-pixel can overlap with a color filter layer of the second color, and the third sub-pixel can overlap with a color filter layer of the third color. For example, in an exemplary embodiment, the first color can be red, the second color can be green, and the third color can be blue, but the present application is not limited thereto.

[0153] The second electrode 173 is disposed on the organic light emitting layer 172. The second electrode 173 can cover the organic light emitting layer 172, and can be a common layer commonly provided in the sub-pixels SP. A capping layer can be disposed on the second electrode 173.

[0154] In the top emission structure, the second electrode 173 can include a transparent conductive material ("TCO") such as ITO or indium zinc oxide ("IZO") that can transmit light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 173 includes the semi-transmissive conductive material, light emission efficiency can be improved by a microcavity.

[0155] An encapsulation layer TFE can be disposed on the light emitting element layer EML. The encapsulation layer TFE can include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE can include at least one organic film to protect the light emitting element layer EML from foreign substances such as dust.

[0156] In alternative exemplary embodiments, instead of the encapsulation layer TFE, a substrate can be disposed on the light emitting element layer EML, and a space between the light emitting element layer EML and the substrate can be empty in a vacuum state or can be provided with a filling film. The filling film can be an epoxy filling film or a silicon filling film.

[0157] Referring to Figure 5 , Figure 7 and Figure 8 , the shield electrode SHE can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). For example, in an exemplary embodiment, the shield electrode SHE can overlap the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 in the third direction (Z-axis direction). The shield electrode SHE can serve as a barrier between the first electrode S1-1 of the 1-1 transistor ST1-1 and the j+1 data line Dj+1 and between the second electrode D1-2 of the 1-2 transistor ST1-2 and the j+1 data line Dj+1. Accordingly, the influence of a data voltage jump of the j+1 data line Dj+1 on the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 can be reduced.

[0158] As shown in Figure 6 , the shield portion SHP of the shield electrode SHE can cross the j+1 data line Dj+1. Accordingly, a parasitic capacitance can be provided between the shield portion SHP of the shield electrode SHE and the j+1 data line Dj+1. Due to the parasitic capacitance, the first driving voltage of the first driving voltage line VDDL1 can be influenced by a data voltage jump of the j+1 data line Dj+1.

[0159] For example, in an exemplary embodiment, as shown in Figure 9As shown in the middle, when the center region of the display panel 100 displays a black image B and the remaining regions thereof display a gray image G, the data voltage applied to the sub-pixel SP displaying the black image B can be higher than the data voltage applied to the sub-pixel SP displaying the gray image G.

[0160] The first driving voltage of the first driving voltage line VDDL1 can increase at a boundary between the black image B and the gray image G located at the upper end of the black image B. Accordingly, the sub-pixel SP displaying the gray image G is expected to display a white image, and thus horizontal crosstalk in which a white line WL is visible to a user can occur. In addition, the first driving voltage of the first driving voltage line VDDL1 can decrease at a boundary between the black image B and the gray image G located at the lower end of the black image B. Accordingly, the sub-pixel SP displaying the gray image G is expected to display a black image, and thus horizontal crosstalk in which a black line BL is visible to a user can occur.

[0161] Hereinafter, the display apparatus 10 capable of reducing the influence of a data voltage jump of a data line on a first transistor ST1 adjacent to the data line and preventing horizontal crosstalk from occurring will be described in detail.

[0162] Figure 10 is a detailed plan view of another exemplary embodiment of a sub-pixel, Figure 11 is a detailed plan view of a region B of Figure 10 , and Figure 12 is a cross-sectional view taken along line III-III' of Figure 10 .

[0163] Figures 10 to 12 The exemplary embodiment of Figures 5 to 8 differs from the exemplary embodiment of in that the overlapping region of the shield electrode SHE and the (j+1)th data line Dj+1 in the third direction (Z-axis direction) is reduced, and the shield electrode SHE is connected to the first sub-driving voltage line SVDDL1 adjacent to the jth data line Dj in the first direction (X-axis direction).

[0164] Referring to Figures 10 to 12 , the shield electrode SHE can include a connection portion CNP, a protrusion portion PRP, and a shield portion SHP.

[0165] The connection portion CNP can be connected to the first sub-driving voltage line SVDDL1 adjacent to the jth data line Dj in the first direction (X-axis direction). The connection portion CNP can be connected to the first sub-driving voltage line SVDDL1 through a first contact hole CNT1.

[0166] The connection portion CNP can overlap the first sub drive voltage line SVDDL1 in the third direction (Z-axis direction). In the overlapping region of the first sub drive voltage line SVDDL1 and the connection portion CNP, the length of the connection portion CNP in the first direction (X-axis direction) can be longer than the length of the first sub drive voltage line SVDDL1 in the first direction (X-axis direction).

[0167] The connection portion CNP can extend in the second direction (Y-axis direction). One end of the connection portion CNP in the second direction (Y-axis direction) can be adjacent to the (k-1)th scan line Sk-1, and the other end of the connection portion CNP in the second direction (Y-axis direction) can be adjacent to the kth scan line Sk. The connection portion CNP can be arranged between the (k-1)th scan line Sk-1 and the kth scan line Sk in the second direction (Y-axis direction). The connection portion CNP can not overlap the (k-1)th scan line Sk-1 and the kth scan line Sk in the third direction (Z-axis direction).

[0168] The protruding portion PRP can protrude from the connection portion CNP and extend in the first direction (X-axis direction). One end of the protruding portion PRP can overlap the (j+1)th data line Dj+1 in the third direction (Z-axis direction). One end of the protruding portion PRP can overlap the data connection electrode DCE in the third direction (Z-axis direction). The protruding portion PRP can be arranged between the second connection electrode VIE and the gate electrode G1-1 of the 1-1st transistor ST1-1 in the second direction (Y-axis direction). The protruding portion PRP can not overlap the second connection electrode VIE and the gate electrode G1-1 of the 1-1st transistor ST1-1 in the third direction (Z-axis direction).

[0169] The shielding portion SHP can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). The shielding portion SHP can overlap the first electrode S1-1 of the 1-1st transistor ST1-1 and the second electrode D1-2 of the 1-2nd transistor ST1-2 in the third direction (Z-axis direction).

[0170] The shielding portion SHP can protrude from the protruding portion PRP and extend in the second direction (Y-axis direction). The shielding portion SHP can protrude from one end of the protruding portion PRP. One end of the shielding portion SHP in the second direction (Y-axis direction) can be adjacent to the kth scan line Sk. The shielding portion SHP can not overlap the kth scan line Sk in the third direction (Z-axis direction).

[0171] The first electrode S1-1 of the first 1-1 transistor ST1-1 and the second electrode D1-2 of the first 1-2 transistor ST1-2 can be arranged on the buffer film BF, and the shield electrode SHE can be arranged on the first interlayer insulating film 141. The first sub drive voltage line SVDDL1 and the data connection electrode DCE can be arranged on the second interlayer insulating film 142, and the (j+1)th data line Dj+1 can be arranged on the first organic film 160.

[0172] The first connection electrode BE1 can be adjacent to the connection portion CNP in the first direction (X-axis direction), and can be adjacent to the protruding portion PRP in the second direction (Y-axis direction).

[0173] According to Figures 10 to 12 an exemplary embodiment, the shield electrode SHE can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). For example, in an exemplary embodiment, the shield electrode SHE can overlap the first electrode S1-1 of the first 1-1 transistor ST1-1 and the second electrode D1-2 of the first 1-2 transistor ST1-2 in the third direction (Z-axis direction). The shield electrode SHE can be arranged between the first electrode S1-1 of the first 1-1 transistor ST1-1 and the (j+1)th data line Dj+1 and between the second electrode D1-2 of the first 1-2 transistor ST1-2 and the (j+1)th data line Dj+1 to function as a barrier. Accordingly, the influence of the data voltage jump of the (j+1)th data line Dj+1 on the first electrode S1-1 of the first 1-1 transistor ST1-1 and the second electrode D1-2 of the first 1-2 transistor ST1-2 can be reduced.

[0174] The parasitic capacitance provided between the shield electrode SHE and the (j+1)th data line Dj+1 in an exemplary embodiment of Figures 5 to 8 the parasitic capacitance provided between the shield electrode SHE and the (j+1)th data line Dj+1 in an exemplary embodiment of Figures 10 to 12 the parasitic capacitance provided between the shield electrode SHE and the (j+1)th data line Dj+1 in an exemplary embodiment of

[0175] [Table 1]

[0176] Figures 5 to 8 Implementation examples Figures 10 to 12 Implementation examples Capacitance 3.13 x 10 -14 F]] 1.23 x 10 -14 F]]>

[0177] Figure 13 is a detailed plan view of another exemplary embodiment of a sub-pixel, Figure 14 is a detailed plan view of the region C of Figure 13 andFigure 15 is a cross-sectional view taken along Figure 13 line IV-IV' of FIG. 8.

[0178] Figures 13 to 15 The exemplary embodiment of Figures 10 to 12 differs from the exemplary embodiment of

[0179] With reference to Figures 13 to 15 , the protruding portion PRP of the shield electrode SHE can protrude from the connection portion CNP and extend in the first direction (X-axis direction). One end of the protruding portion PRP in the first direction (X-axis direction) can be adjacent to the j+1th data line Dj+1. One end of the protruding portion PRP in the first direction (X-axis direction) can be adjacent to the data connection electrode DCE. The protruding portion PRP can not overlap the j+1th data line Dj+1 in the third direction (Z-axis direction). The protruding portion PRP can not overlap the data connection electrode DCE in the third direction (Z-axis direction).

[0180] The protruding portion PRP can be disposed between the second connection electrode VIE and the gate electrode G1-1 of the 1-1st transistor ST1-1 in the second direction (Y-axis direction). The protruding portion PRP can not overlap the second connection electrode VIE and the gate electrode G1-1 of the 1-1st transistor ST1-1 in the third direction (Z-axis direction).

[0181] The first electrode S1-1 of the 1-1st transistor ST1-1 and the second electrode D1-2 of the 1-2nd transistor ST1-2 can be disposed on the buffer film BF, and the shield electrode SHE can be disposed on the first interlayer insulating film 141. The first sub drive voltage line SVDDL1 and the data connection electrode DCE can be disposed on the second interlayer insulating film 142, and the j+1th data line Dj+1 can be disposed on the first organic film 160.

[0182] The parasitic capacitance provided between the shield electrode SHE and the j+1th data line Dj+1 in the exemplary embodiment of Figures 10 to 12 and the parasitic capacitance provided between the shield electrode SHE and the j+1th data line Dj+1 in the exemplary embodiment of Figures 13 to 15 As given in Table 2, the parasitic capacitance provided between the shield electrode SHE and the j+1th data line Dj+1 can be reduced by reducing the overlapping area of the shield electrode SHE and the j+1th data line Dj+1. Thus, the influence of the data voltage jump of the data lines Dj and Dj+1 on the first drive voltage line VDDL can be reduced.

[0183] [Table 2]

[0184] Figures 10 to 12 Implementation examples Figures 13 to 15 Implementation examples Capacitance 1.23 x 10 -14 F]]> 0.88 x 10 -14 F]]>

[0185] like Figure 14 and Figure 15 As shown, in order to minimize the parasitic capacitance provided between the shielding electrode SHE and the (j+1)th data line Dj+1, the distance DIS between the protruding portion PRP and the (j+1)th data line Dj+1 in the first direction (X-axis direction) can be equal to or greater than approximately 1 micrometer (μm).

[0186] Figure 16 It is along Figure 13 Another cross-sectional view taken from line IV-IV'.

[0187] Figure 16 Exemplary embodiments and Figure 15 The difference in the exemplary embodiment is that the shielding electrode SHE is disposed on the substrate SUB1, and the buffer film BF is disposed on the shielding electrode SHE.

[0188] refer to Figure 16 The first sub-driving voltage line SVDDL1 can be connected to the shielding electrode SHE through the first contact hole CNT1 that passes through the buffer film BF, the gate insulating film 130, the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0189] like Figure 16 As shown, due to the shielding electrode SHE, the coupling caused by the parasitic capacitance provided between the first electrode S1-1 of transistor ST1-1 and the (j+1)th data line Dj+1, and between the second electrode D1-2 of transistor ST1-2 and the (j+1)th data line Dj+1, can be reduced. Therefore, the effect of the data voltage jump of the (j+1)th data line Dj+1 on the first electrode S1-1 of transistor ST1-1 and the second electrode D1-2 of transistor ST1-2 can be reduced.

[0190] Figure 17 This is a detailed plan view of another exemplary embodiment of the sub-pixel. Figure 18 yes Figure 17 A detailed plan of area D, and Figure 19 It is along Figure 17 A cross-sectional view taken from line V-V'.

[0191] Figures 17 to 19 Exemplary embodiments and Figures 13 to 15The exemplary embodiment of FIG. 1 is different from the exemplary embodiment of FIG. 2 only in that the data lines Dj, Dj+1, and Dj+2 are arranged in the first data metal layer DTL1, the data connection electrode DCE and the data contact hole DCNT are omitted, and each of the data lines Dj, Dj+1, and Dj+2 is connected to the second electrode D2 of the second transistor ST2. Thus, the following will be omitted Figures 17 to 19 Detailed description of the exemplary embodiment of FIG. 1.

[0192] Figure 20 is a detailed plan view of the region E of the exemplary embodiment of FIG. 1, Figure 21 is a detailed plan view of the region E of the exemplary embodiment of FIG. 1, and Figure 20 is a cross-sectional view taken along the line VI-VI’ of the exemplary embodiment of FIG. 1. Figure 22 Figure 20 The exemplary embodiment of FIG. 1 is different from the exemplary embodiment of FIG. 2 only in that the data lines Dj, Dj+1, and Dj+2 are arranged in the first data metal layer DTL1, the data connection electrode DCE and the data contact hole DCNT are omitted, and each of the data lines Dj, Dj+1, and Dj+2 is connected to the second electrode D2 of the second transistor ST2. Thus, the following will be omitted

[0193] Figures 20 to 22 The exemplary embodiment of FIG. 1 is different from the exemplary embodiment of FIG. 2 only in that the data lines Dj, Dj+1, and Dj+2 are arranged in the first data metal layer DTL1, the data connection electrode DCE and the data contact hole DCNT are omitted, and each of the data lines Dj, Dj+1, and Dj+2 is connected to the second electrode D2 of the second transistor ST2. Thus, the following will be omitted Figures 13 to 15

[0194] With reference to FIG. 1, Figures 20 to 22 The shield electrode SHE can include a protruding portion PRP and a shield portion SHP.

[0195] The protruding portion PRP can protrude from the first sub drive voltage line SVDDL1 and extend in the first direction (X-axis direction). One end of the protruding portion PRP in the first direction (X-axis direction) can be adjacent to the j+1th data line Dj+1. One end of the protruding portion PRP in the first direction (X-axis direction) can be adjacent to the data connection electrode DCE. The protruding portion PRP can not overlap the j+1th data line Dj+1 in the third direction (Z-axis direction). The protruding portion PRP can not overlap the data connection electrode DCE in the third direction (Z-axis direction).

[0196] The protruding portion PRP can be arranged between the second connection electrode VIE and the gate electrode G1-1 of the 1-1th transistor ST1-1 in the second direction (Y-axis direction). The protruding portion PRP can not overlap the second connection electrode VIE and the gate electrode G1-1 of the 1-1th transistor ST1-1 in the third direction (Z-axis direction).

[0197] The shield portion SHP can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). The shield portion SHP can overlap the first electrode S1-1 of the 1-1th transistor ST1-1 and the second electrode D1-2 of the 1-2th transistor ST1-2 in the third direction (Z-axis direction).

[0198] ​​The shield portion SHP can protrude from the protruding portion PRP and extend in the second direction (Y-axis direction). The shield portion SHP can protrude from one end of the protruding portion PRP. One end of the shield portion SHP in the second direction (Y-axis direction) can be adjacent to the k-th scan line Sk. The shield portion SHP can not overlap the k-th scan line Sk in the third direction (Z-axis direction).

[0199] The first electrode S1-1 of the 1st-1 transistor ST1-1 and the second electrode D1-2 of the 1st-2 transistor ST1-2 can be arranged on the buffer film BF, the shield electrode SHE, the first sub drive voltage line SVDDL1, and the data connection electrode DCE can be arranged on the second interlayer insulating film 142, and the (j+1)th data line Dj+1 can be arranged on the first organic film 160.

[0200] According to Figures 20 to 22 According to an exemplary embodiment of the present technology, the shield electrode SHE can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). For example, in the exemplary embodiment, the shield electrode SHE can overlap the first electrode S1-1 of the 1st-1 transistor ST1-1 and the second electrode D1-2 of the 1st-2 transistor ST1-2 in the third direction (Z-axis direction). The shield electrode SHE can be arranged between the first electrode S1-1 of the 1st-1 transistor ST1-1 and the (j+1)th data line Dj+1 and between the second electrode D1-2 of the 1st-2 transistor ST1-2 and the (j+1)th data line Dj+1 to function as a barrier. Therefore, it is possible to reduce the influence of the data voltage jump of the (j+1)th data line Dj+1 on the first electrode S1-1 of the 1st-1 transistor ST1-1 and the second electrode D1-2 of the 1st-2 transistor ST1-2.

[0201] Further, since the shield electrode SHE does not overlap the (j+1)th data line Dj+1 in the third direction (Z-axis direction), it is possible to reduce the parasitic capacitance provided between the shield electrode SHE and the (j+1)th data line Dj+1. Therefore, it is possible to reduce the influence of the data voltage jump of the data lines Dj and Dj+1 on the first drive voltage line VDDL.

[0202] Figure 23 is a detailed plan view of another exemplary embodiment of a sub-pixel, Figure 24 is a detailed plan view of the region F of Figure 23 and is a detailed plan view of the region F of Figure 25 is a cross-sectional view taken along the line VII-VII’ of Figure 23

[0203] Figures 23 to 25 The exemplary embodiment of the present technology is different from Figures 13 to 15 ​The difference in the exemplary embodiment is that the shielding electrode SHE is not connected to the first sub-drive voltage line SVDDL1 and is electrically floated.

[0204] refer to Figures 23 to 25 Since the shielding electrode SHE is not connected to a wire or electrode, it can be electrically floated. The shielding electrode SHE may overlap with at least a portion of the first transistor ST1 in the third direction (Z-axis direction). The shielding electrode SHE may also overlap with the first electrode S1-1 of the first-1 transistor ST1-1 and the second electrode D1-2 of the first-2 transistor ST1-2 in the third direction (Z-axis direction).

[0205] The shielding electrode SHE can extend in the second direction (Y-axis direction). The shielding electrode SHE can be arranged in the second direction (Y-axis direction) between the second connecting electrode VIE and the k-th scan line Sk. The shielding electrode SHE can be in the third direction (Z-axis direction) without overlapping with the second connecting electrode VIE and the k-th scan line Sk.

[0206] The first electrode S1-1 of transistor ST1-1 and the second electrode D1-2 of transistor ST1-2 can be arranged on the buffer film BF, and the shielding electrode SHE can be arranged on the first interlayer insulating film 141. The first sub-drive voltage line SVDDL1 and the data connection electrode DCE can be arranged on the second interlayer insulating film 142, and the (j+1)th data line Dj+1 can be arranged on the first organic film 160.

[0207] according to Figures 23 to 25 In an exemplary embodiment, the shielding electrode SHE may overlap with at least a portion of the first transistor ST1 in the third direction (Z-axis direction). For example, in an exemplary embodiment, the shielding electrode SHE may overlap with the first electrode S1-1 of the first-1 transistor ST1-1 and the second electrode D1-2 of the first-2 transistor ST1-2 in the third direction (Z-axis direction). The shielding electrode SHE may be arranged between the first electrode S1-1 of the first-1 transistor ST1-1 and the (j+1)th data line Dj+1, and between the second electrode D1-2 of the first-2 transistor ST1-2 and the (j+1)th data line Dj+1, to act as a barrier. Therefore, the impact of the data voltage jump of the (j+1)th data line Dj+1 on the first electrode S1-1 of the first-1 transistor ST1-1 and the second electrode D1-2 of the first-2 transistor ST1-2 can be reduced.

[0208] Figure 26 This is a detailed plan view of another exemplary embodiment of the sub-pixel. Figure 27 yes Figure 26 A detailed plan of region G, and Figure 28 It is alongFigure 26 a cross-sectional view taken along the line VIII-VIII' of Fig. 8.

[0209] Figures 26 to 28 The exemplary embodiment of Figures 13 to 15 The exemplary embodiment of differs from the exemplary embodiment of in that the shield electrode SHE is connected to the second sub-drive voltage line SVDDL2, instead of the first sub-drive voltage line SVDDL1.

[0210] With reference to Figures 26 to 28 The shield electrode SHE can overlap at least a portion of the first transistor ST1 in the third direction (Z-axis direction). The shield electrode SHE can overlap the first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 in the third direction (Z-axis direction).

[0211] The shield electrode SHE can be connected to the second sub-drive voltage line SVDDL2 through the first contact hole CNT1'. The shield electrode SHE can be disposed on the second interlayer insulating film 142, and in this case, the first contact hole CNT1' can be a hole that penetrates the second interlayer insulating film 142.

[0212] The shield electrode SHE can extend in the second direction (Y-axis direction). The shield electrode SHE can intersect the k-th scan line Sk.

[0213] The first electrode S1-1 of the 1-1 transistor ST1-1 and the second electrode D1-2 of the 1-2 transistor ST1-2 can be disposed on the buffer film BF, and the second sub-drive voltage line SVDDL2 can be disposed on the first interlayer insulating film 141. The shield electrode SHE, the first sub-drive voltage line SVDDL1, and the data connection electrode DCE can be disposed on the second interlayer insulating film 142, and the (j+1)-th data line Dj+1 can be disposed on the first organic film 160.

[0214] According to Figures 26 to 28In the exemplary embodiment of the display device, the shield electrode SHE can overlap at least a portion of the transistor adjacent to the data line in the thickness direction of the substrate. In this case, the shield electrode is arranged between the data line and the transistor adjacent to the data line to function as a barrier. Accordingly, it is possible to reduce the influence of the data voltage jump of the data line on the first electrode or the second electrode of the transistor adjacent to the data line.

[0215] In the exemplary embodiment of the display device, the shield electrode can overlap at least a portion of the transistor adjacent to the data line in the thickness direction of the substrate. In this case, the shield electrode is arranged between the data line and the transistor adjacent to the data line to function as a barrier. Accordingly, it is possible to reduce the influence of the data voltage jump of the data line on the first electrode or the second electrode of the transistor adjacent to the data line.

[0216] Further, in the exemplary embodiment of the display device, the overlapping area of the shield electrode and the data line in the thickness direction of the substrate is reduced, or the shield electrode and the data line are arranged not to overlap each other, thereby reducing the parasitic capacitance provided between the shield electrode and the data line. Accordingly, it is possible to reduce the influence of the data voltage jump of the data line on the first driving voltage line.

[0217] The present application should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the present application will be thorough and complete, and will fully convey the concept of the present application to those skilled in the art.

[0218] While the present application has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit or scope of the application.

Claims

1. A display device, comprising: substrate; Multiple data lines are disposed on the substrate, and data voltage is applied to the multiple data lines; Multiple scan lines are disposed on the substrate, and scan signals are applied to the multiple scan lines; A first pixel connected to a first data line among the plurality of data lines and at least one scan line among the plurality of scan lines; as well as A second pixel is connected to a second data line among the plurality of data lines and the at least one scan line, wherein the first data line and the second data line are adjacent to each other, and The first pixel includes: Light-emitting elements; A driving transistor includes a gate electrode, a first electrode, and a second electrode, and a driving current flowing between the first electrode and the second electrode is supplied to the light-emitting element according to the data voltage applied to the first data line of the gate electrode; The first transistor between the gate electrode and the second electrode of the driving transistor; and A shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate. The shielding electrode does not overlap with the first data line in the thickness direction of the substrate.

2. The display device according to claim 1, further comprising: Multiple first driving voltage lines are disposed on the substrate, and a first driving voltage is applied to the multiple first driving voltage lines. The first pixel is connected to the first driving voltage line among the plurality of first driving voltage lines, and The shielding electrode is connected to the first driving voltage line.

3. The display device according to claim 2, The first transistor includes: The first transistor includes a first electrode, a second electrode, and a gate electrode connected to a scan line in the plurality of scan lines; as well as The first-second transistor includes a gate electrode connected to the scan line, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the first electrode of the first-first transistor. The second electrode of the first-1 transistor is connected to the gate electrode of the driving transistor.

4. The display device according to claim 3, The shielding electrode overlaps with the first electrode of the first-1 transistor and the second electrode of the first-2 transistor in the thickness direction of the substrate.

5. The display device according to claim 3, Wherein the first pixel further includes: The data voltage of the first data line is supplied to the second transistor of the gate electrode of the driving transistor; as well as The third-first transistor includes a gate electrode connected to another scan line of the plurality of scan lines and a first electrode connected to the gate electrode of the driving transistor.

6. The display device according to claim 5, The shielding electrode includes: A connection portion extending in the first direction and connected to the first drive voltage line; A protruding portion that protrudes and extends from the connecting portion in a second direction intersecting the first direction; as well as A shielding portion that protrudes from the protruding portion and overlaps with the first electrode of the first-1 transistor and the second electrode of the first-2 transistor in the thickness direction of the substrate.

7. The display device according to claim 6, The connection portion is located between the scan line and the other scan line adjacent to the scan line in the first direction, and does not overlap with the scan line and the other scan line in the thickness direction of the substrate.

8. The display device according to claim 6, The protruding portion is adjacent to the second data line and overlaps with the second data line in the thickness direction of the substrate.

9. The display device according to claim 6, The shielding portion extends in the first direction.

10. The display device according to claim 6, The protruding portion is adjacent to the second data line and does not overlap with the second data line in the thickness direction of the substrate.

11. The display device according to claim 6, The first pixel further includes a first connection electrode, which connects the gate electrode of the driving transistor and the second electrode of the first-1 transistor. The first connecting electrode is adjacent to the connecting portion in the second direction and to the protruding portion in the first direction.

12. The display device according to claim 2, The first driving voltage line includes: The first sub-driving voltage line extending in the first direction; as well as The second sub-driving voltage line extends in a second direction that intersects the first direction. The shielding electrode is connected to the first sub-driving voltage line.

13. The display device according to claim 12, The at least one scan line and the gate electrode of the driving transistor are disposed on a gate insulating film, which is disposed on the substrate. The shielding electrode and the second sub-driving voltage line are disposed on a first interlayer insulating film, which is disposed on the at least one scan line and the gate electrode of the driving transistor. The first sub-driving voltage line is disposed on the second interlayer insulating film, and the second interlayer insulating film is disposed on the shielding electrode and the second sub-driving voltage line. The first data line is arranged on the first organic film, and the first organic film is arranged on the first sub-driving voltage line.

14. The display device according to claim 13, The first sub-driving voltage line is connected to the shielding electrode through a first contact hole that penetrates the second interlayer insulating film.

15. The display device according to claim 12, The shielding electrode is disposed on the substrate. The at least one scan line and the gate electrode of the driving transistor are arranged on a buffer film, and the buffer film is arranged on the shielding electrode. The second sub-driving voltage line is disposed on the first interlayer insulating film, which is disposed on the at least one scan line and the gate electrode of the driving transistor. The first sub-driving voltage line is disposed on the second interlayer insulating film, and the second interlayer insulating film is disposed on the second sub-driving voltage line. The first data line is arranged on the first organic film, and the first organic film is arranged on the first sub-driving voltage line.

16. The display device according to claim 15, The first sub-driving voltage line is connected to the shielding electrode through a first contact hole that passes through the buffer film, the first interlayer insulating film, and the second interlayer insulating film.

17. The display device according to claim 1, Wherein the first pixel further includes: The data voltage is supplied to the second transistor at the gate electrode of the driving transistor; as well as The data connection electrode that connects the first data line and the first electrode of the second transistor. The shielding electrode overlaps with the data connection electrode in the thickness direction of the substrate.

18. The display device according to claim 12, The shielding electrode includes: A protruding portion that protrudes and extends from the first sub-driving voltage line in a second direction that intersects the first direction; as well as A shielding portion extending from the protruding portion and overlapping at least a portion of the first transistor in the thickness direction of the substrate.

19. The display device according to claim 1, The shielding electrode is electrically floating.

20. The display device according to claim 2, The shielding electrode is spaced apart from the first driving voltage line.

21. The display device according to claim 2, The first driving voltage line includes: The first sub-driving voltage line extending in the first direction; as well as The second sub-driving voltage line extends in a second direction that intersects the first direction. The shielding electrode is connected to the second sub-driving voltage line.

22. The display device according to claim 21, The shielding electrode extends in the first direction.

23. The display device according to claim 21, The shielding electrode intersects with the at least one scan line.

24. The display device according to claim 21, The at least one scan line and the gate electrode of the driving transistor are disposed on a gate insulating film, which is disposed on the substrate. The second sub-driving voltage line is disposed on the first interlayer insulating film, which is disposed on the at least one scan line and the gate electrode of the driving transistor. The first sub-driving voltage line and the shielding electrode are disposed on the second interlayer insulating film, and the second interlayer insulating film is disposed on the second sub-driving voltage line. The first data line is disposed on the first organic film, which is disposed on the first sub-driving voltage line and the shielding electrode.

25. The display device according to claim 24, The shielding electrode is connected to the second sub-driving voltage line through a first contact hole penetrating the second interlayer insulating film.

26. A display device, comprising: substrate; Light-emitting elements; A driving transistor includes a gate electrode, a first electrode, and a second electrode, and a driving current flowing between the first electrode and the second electrode is supplied to the light-emitting element according to the data voltage of a first data line applied to the gate electrode; The first transistor is arranged adjacent to the second data line immediately following the first data line; as well as A shielding electrode that overlaps with at least a portion of the first transistor in the thickness direction of the substrate. The driving transistor and the first transistor are arranged between the first data line and the second data line, and The shielding electrode does not overlap with at least the central portion of the second data line along the direction in which the first and second data lines are arranged.

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