Semiconductor element and semiconductor component comprising the same

Abstract

A semiconductor element and a semiconductor component including the same are disclosed. The semiconductor element includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is on the first semiconductor structure and includes a second dopant different from the first dopant. The active region is between the first semiconductor structure and the second semiconductor structure and includes the first dopant. The semiconductor element has a maximum external quantum efficiency E max % at a current density of J_E 2 A / cm max , and has an external quantum efficiency of E max % that is 15% or more at a current density of 0.001 x (J_E 2 ) A / cm max .

Description

Technical Field

[0001] This invention relates to semiconductor elements, and more particularly to semiconductor light-emitting elements, such as light-emitting diodes (LEDs). Background Technology

[0002] Semiconductor components have a wide range of applications, and the development and research of related materials are ongoing. For example, III-V semiconductor materials containing group III and group V elements can be used in various optoelectronic semiconductor components such as light-emitting diodes (LEDs), laser diodes (LDs), photodetectors, or solar cells, or as power components such as switches or rectifiers, and can be used in lighting, medical, display, communication, sensing, and power systems. As one of the semiconductor light-emitting components, the LED has advantages such as low power consumption and long lifespan, and is therefore widely used. Summary of the Invention

[0003] This invention provides a semiconductor device comprising a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region is located between the first and second semiconductor structures and includes the first dopant. This semiconductor device is available in J_E. max A / cm 2 It has a maximum external quantum efficiency E at current density max %, of which 0.001A / cm 2 ≤J_E max A / cm 2 ≤100A / cm 2 And at 0.001×(J_E) max A / cm 2 At current densities of , semiconductor devices have E max External quantum efficiency of over 15%.

[0004] This invention provides a semiconductor device comprising a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region is located between the first and second semiconductor structures and includes multiple pairs of semiconductor stacks, each semiconductor stack including a barrier layer and a well layer, and the active region includes the first dopant. The active region does not contain nitrogen (N), and the doping concentration of the first dopant in the first semiconductor structure is higher than the doping concentration of the first dopant in the active region.

[0005] In one embodiment of the present invention, the semiconductor element is rectangular in the top view, and the rectangle has a length and a width, the length and the width being less than or equal to 500 μm and greater than 1 μm, respectively.

[0006] In one embodiment of the present invention, the barrier layer has a first thickness and the well layer has a second thickness, wherein the first thickness is greater than the second thickness.

[0007] In one embodiment of the present invention, the ratio of the first thickness to the second thickness is in the range of 2:1 to 40:1.

[0008] In one embodiment of the present invention, the first semiconductor structure further includes a first confinement layer that directly contacts the active region.

[0009] In one embodiment of the present invention, the barrier layer has an aluminum content percentage of 25% or higher.

[0010] In one embodiment of the present invention, the second semiconductor structure further includes a second confinement layer that directly contacts the active region, and the second confinement layer includes a first dopant and a second dopant.

[0011] In one embodiment of the present invention, the first dopant is present in each barrier layer and each well layer of the active region.

[0012] In one embodiment of the present invention, the first dopant comprises C, Zn, Si, Ge, Sn, Se, Mg, or Te.

[0013] In one embodiment of the present invention, the first dopant in the active region has a doping concentration greater than or equal to 1 × 10⁻⁶. 16 / cm 3 .

[0014] This invention provides a semiconductor device comprising a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first confinement layer and a first dopant. The second semiconductor structure is located on the first semiconductor structure, includes a second confinement layer, and includes a second dopant different from the first dopant. The active region is located between the first and second semiconductor structures and includes multiple pairs of semiconductor stacks, each semiconductor stack including a barrier layer and a well layer, and the active region includes the first dopant. The barrier layer has a first thickness and a first aluminum content percentage, and the well layer has a second thickness and a second aluminum content percentage. The first aluminum content percentage is greater than the second aluminum content percentage. The first and second confinement layers are adjacent to and in direct contact with the active region. The first confinement layer has a third thickness and a third aluminum content percentage. The second confinement layer has a fourth thickness and a fourth aluminum content percentage. The first dopant is continuously and uninterruptedly distributed in the first confinement layer and the active region. The third and fourth aluminum content percentages are greater than the second aluminum content percentage. The third thickness is greater than or equal to the second thickness, and the fourth thickness is greater than or equal to the second thickness.

[0015] In one embodiment of the present invention, the first thickness is greater than the second thickness.

[0016] In one embodiment of the present invention, the ratio of the first thickness to the second thickness is in the range of 2:1 to 40:1.

[0017] In one embodiment of the present invention, the first aluminum content percentage is in the range of 15% to 50%, and the second aluminum content percentage is in the range of 0% to 15%.

[0018] In one embodiment of the present invention, the doping concentration of the first dopant in the active region is greater than or equal to 1 × 10⁻⁶. 16 / cm 3 .

[0019] In one embodiment of the present invention, the number of semiconductor stacks in the active region is less than 10 pairs.

[0020] In one embodiment of the present invention, the length of the semiconductor element is less than 200 μm and the width is less than 200 μm.

[0021] In one embodiment of the present invention, viewed from above, the area of ​​the upper surface of the semiconductor element is 10000 μm. 2 The following describes semiconductor components in J_E max A / cm 2 It has the highest external quantum efficiency E at current density max %, and at 0.1×(J_E) max A / cm 2 At current densities of , semiconductor devices have E max External quantum efficiency of over 80%.

[0022] In one embodiment of the present invention, viewed from above, the area of ​​the upper surface of the semiconductor element is 10000 μm. 2 The semiconductor element has a first light output value at a first temperature and a second light output value at a second temperature lower than the first temperature, wherein the difference between the first temperature and the second temperature is 30°C or more, and the ratio of the first light output value to the second light output value is greater than or equal to 30%.

[0023] The present invention provides a semiconductor component comprising the aforementioned semiconductor element. Attached Figure Description

[0024] Figure 1A This is a top view of a semiconductor element according to an embodiment of the present invention;

[0025] Figure 1B and Figure 1CThis is a cross-sectional structural diagram and a partially enlarged diagram of a semiconductor device according to an embodiment of the present invention;

[0026] Figure 1D This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 1E This is a top view of a semiconductor element according to an embodiment of the present invention;

[0028] Figure 1F This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0029] Figure 2A This is a schematic diagram illustrating the relationship between current density and internal quantum efficiency (IQE) of a semiconductor element in an embodiment of the present invention.

[0030] Figure 2B This is a schematic diagram illustrating the relationship between current density and external quantum efficiency (EQE) of a semiconductor element in an embodiment of the present invention.

[0031] Figure 2C This is a schematic diagram showing the relationship between the R value of a semiconductor element and its relative EQE ratio in an embodiment of the present invention;

[0032] Figure 2D This is a schematic diagram illustrating the relationship between current density and external quantum efficiency (EQE) of a semiconductor element in an embodiment of the present invention.

[0033] Figure 3 This is a graph showing the relationship between the concentration and depth of elements in a portion of a semiconductor device according to an embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram illustrating the relationship between current density and internal quantum efficiency (IQE) of a semiconductor element in an embodiment of the present invention.

[0035] Figure 5A This is a cross-sectional structural diagram of a semiconductor component according to an embodiment of the present invention;

[0036] Figure 5B This is a cross-sectional structural diagram of a semiconductor component according to an embodiment of the present invention;

[0037] Figure 6 This is a cross-sectional structural diagram of a semiconductor component according to an embodiment of the present invention;

[0038] Figure 7 This is a top view schematic diagram of a semiconductor component according to an embodiment of the present invention.

[0039] Symbol Explanation

[0040] 10, 10', 20, 40, 40': Semiconductor components

[0041] 22, 42: Supporting substrate

[0042] 24, 44: Adhesive layer

[0043] 200, 400, 600, 800: Semiconductor components

[0044] 61: Packaging substrate

[0045] 62: Through hole

[0046] 63: Carrier

[0047] 63a: Part 1

[0048] 63b: Part Two

[0049] 65: Joint line

[0050] 66: Contact Structure

[0051] 66a: First contact pad

[0052] 66b: Second contact pad

[0053] 68: Encapsulation layer

[0054] 80: Carrier board

[0055] 82: Pixel unit

[0056] 84: First semiconductor element

[0057] 86: Second semiconductor element

[0058] 88: Third semiconductor element

[0059] 100: Base

[0060] 102: Extensional Structure

[0061] 104: First Semiconductor Structure

[0062] 106: Second Semiconductor Structure

[0063] 108: Active region

[0064] 108a: Barrier layer

[0065] 108b: Trap layer

[0066] 108c: Semiconductor stack

[0067] 110: First electrode

[0068] 110a: Electrode pad

[0069] 110b: Extended electrode

[0070] 110b1: First extension

[0071] 110b2: Second extension

[0072] 112: Second electrode

[0073] 114: First Limitation Layer

[0074] 116: Second confinement layer

[0075] 118: First Covering Layer

[0076] 119: Second Covering Layer

[0077] 130: First window layer

[0078] 140a: First contact structure

[0079] 140b: Second contact structure

[0080] 160: Dielectric material layer

[0081] 120: Insulation layer

[0082] 122: Conductive layer

[0083] 124: Reflective layer

[0084] 126: Porosity

[0085] 128: Joint structure

[0086] R: Region

[0087] L0: Length

[0088] W0: Width

[0089] C1, C2, D1, D2, E0, E1, E2, E3, E4, E5, F1, F2, G1, G2, Q1, Q2, Q3: Curves

[0090] X-X', Y-Y': lines Detailed Implementation

[0091] The following embodiments will illustrate the concept of the present invention with the accompanying drawings. In the drawings or description, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the elements in the drawings are merely illustrative and are not actually limited thereto. It should be noted that elements not shown or described in the drawings may be in forms known to those skilled in the art.

[0092] Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, where 0 < x0 < 1; the general formula AlInP represents Al x1 In 1-x1 P, where 0 < x1 < 1; the general formula AlGaInP represents Al x2 Ga x3 In 1-x2-x3 P, where 0 < x2 < 1 and 0 < x3 < 1; the general formula InGaAsP represents In x4 Ga 1-x4 As x5 P 1-x5 , where 0 < x4 < 1, 0 < x5 < 1; the general formula AlGaInAs represents Al x6 Ga x7 In 1-x6-x7 As, where 0 < x6 < 1, 0 < x7 < 1; the general formula InGaNAs represents In x8 Ga 1-x8 N x9 As 1-x9 , where 0 < x8 < 1, 0 < x9 < 1; the general formula InGaAs represents In x10 Ga 1-x10 As, where 0 < x10 < 1; the general formula AlGaAs represents Al x11 Ga 1-x11 As, where 0 < x1 < 1; the general formula InGaN represents In x12 Ga 1-x12 N, where 0 < x12 < 1; the general formula AlGaN represents Al x13 [[ID=5O]]Ga 1-x13 N, where 0 < x13 < 1; the general formula AlGaAsP represents Al x14 Ga 1-x14 As x15 P 1-x15 , where 0 < x14 < 1, and 0 < x15 < 1; the general formula InGaAsN represents In x16 Ga 1-x16 As x17 N 1-x17 , where 0 < x16 < 1, and 0 < x17 < 1; the general formula AlInGaN represents Al x18 In x19 Ga 1-x18-x19 N, where 0 < x18 < 1 and 0 < x19 < 1. The content of each element can be adjusted according to different purposes, for example, but not limited to, adjusting the energy level, or when the semiconductor device is a light-emitting device, the main wavelength (domain wavelength) or peak wavelength (peak wavelength) of the light-emitting device can be adjusted accordingly.

[0093] The semiconductor element described in this invention is, for example, a light-emitting element (e.g., a light-emitting diode, a laser diode), a light-absorbing element (e.g., a photodetector), or a non-light-emitting element. The composition of each layer and the dopant in the semiconductor element described in this invention can be analyzed using any suitable method, such as secondary ion mass spectrometry (SIMS), and the thickness of each layer can also be analyzed using any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM).

[0094] Those skilled in the art will understand that other components can be added to the embodiments described below. For example, unless otherwise specified, a description such as "the first layer (or structure) is located on the second layer (or structure)" can include embodiments where the first layer (or structure) and the second layer (or structure) are in direct contact, or embodiments where the first layer (or structure) and the second layer (or structure) have other structures between them and are not in direct contact. Furthermore, it should be understood that the vertical positional relationship of the layers (or structures) may change depending on the viewing angle.

[0095] Furthermore, in the context of this invention, the statement that a layer or structure is "substantially composed of M" indicates that the main component of the layer or structure is M, but does not preclude the inclusion of dopants or unavoidable impurities in the layer or structure.

[0096] Figure 1A This is a top view of a semiconductor element 10 according to an embodiment of the present invention. Figure 1B for Figure 1A A schematic diagram of the cross-sectional structure of semiconductor element 10 along line X-X'. Figure 1C for Figure 1B A magnified schematic diagram of a portion of region R in semiconductor device 10. (See attached diagram.) Figure 1AAs shown, viewed from above, the semiconductor element 10 may have a length L0 and a width W0. The length L0 and width W0 may be less than or equal to 500 μm, for example, less than or equal to 450 μm, 400 μm, 350 μm, 300 μm, 250 μm, 200 μm, 150 μm, 100 μm, 50 μm, 30 μm, or 10 μm, and may be greater than or equal to 1 μm. Viewed from above, the semiconductor element 10 may be rectangular or circular. In one embodiment, the length L0 and width W0 of the semiconductor element 10 may be approximately equal, forming a square. In one embodiment, viewed from above, the area (L0 × W0) of the upper surface of the semiconductor element 10 is 10000 μm². 2 Below, for example at 1μm 2 Up to 5000μm 2 Within the range (e.g., 100μm) 2 625μm 2 1250μm 2 2000μm 2 Or 2500μm 2 ).like Figure 1A and Figure 1B As shown, the semiconductor device 10 includes a substrate 100, an epitaxial structure 102, a first electrode 110, and a second electrode 112. The epitaxial structure 102 is located on the substrate 100. The first electrode 110 is located on the epitaxial structure 102, while the second electrode 112 is located below the substrate 100.

[0097] The substrate 100 comprises a conductive or insulating material, such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si); the insulating material is such as sapphire. In one embodiment, the substrate 100 is a growth substrate, i.e., an epitaxial structure 102 is formed on the substrate 100 by, for example, metal-organic chemical vapor deposition (MOCVD). In one embodiment, the substrate 100 is a bonding substrate rather than a growth substrate, which is bonded to the epitaxial structure 102 by an adhesive material.

[0098] like Figure 1BAs shown, the epitaxial structure 102 includes a first semiconductor structure 104, a second semiconductor structure 106, and an active region 108 between the first semiconductor structure 104 and the second semiconductor structure 106. The first semiconductor structure 104 and the second semiconductor structure 106 may have opposite conductivity types. For example, the first semiconductor structure 104 may be n-type and the second semiconductor structure 106 may be p-type; or, the first semiconductor structure 104 may be p-type and the second semiconductor structure 106 may be n-type. Thus, the first semiconductor structure 104 and the second semiconductor structure 106 may provide electrons and holes, respectively. The first semiconductor structure 104, the second semiconductor structure 106, and the active region 108 may each contain a group III-V semiconductor material. The aforementioned group III-V semiconductor material may contain Al, Ga, As, P, N, or In. In one embodiment, the first semiconductor structure 104, the second semiconductor structure 106, and the active region 108 may not contain N. Specifically, the aforementioned group III-V semiconductor materials can be binary compound semiconductors (such as GaAs, GaP, or GaN), ternary compound semiconductors (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the active region 108 is substantially composed of a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP).

[0099] Semiconductor element 10 may comprise a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum well (MQW) structure. According to one embodiment, when semiconductor element 10 is a light-emitting element and during operation of semiconductor element 10, active region 108 may emit light. The light may be visible or invisible. The light emitted by semiconductor element 10 depends on the material composition of active region 108. For example, when the material of the active region 108 contains the InGaN series, it can emit blue light or deep blue light with a peak wavelength of 400nm to 490nm, or green light with a peak wavelength of 490nm to 550nm; when the material of the active region 108 contains the AlGaN series, it can emit ultraviolet light with a peak wavelength of 250nm to 400nm; when the material of the active region 108 contains the InGaAs series, InGaAsP series, AlGaAs series, or AlGaInAs series, it can emit infrared light with a peak wavelength of 700nm to 1700nm; when the material of the active region 108 contains the InGaP series or AlGaInP series, it can emit red light with a peak wavelength of 610nm to 700nm, or yellow light with a peak wavelength of 530nm to 600nm.

[0100] In one embodiment, the active region 108 may include a semiconductor stack 108c consisting of a barrier layer 108a and a well layer 108b adjacent thereto; that is, a pair of semiconductor stacks 108c includes one barrier layer 108a and one well layer 108b. Specifically, the active region 108 may include one or more pairs of semiconductor stacks 108c. In one embodiment, the number of pairs of semiconductor stacks 108c may be greater than or equal to 2. In another embodiment, the number of pairs of semiconductor stacks 108c may be less than or equal to 20, and less than or equal to 10. The number of pairs of semiconductor stacks 108c is, for example, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, or 19. In one embodiment, when the active region 108 comprises five or fewer pairs of semiconductor stacks 108c (i.e., five or fewer barrier layers 108a and five or fewer well layers 108b), the semiconductor device 10 can have relatively high quantum efficiency, especially at low current densities (e.g., 1 A / cm²). 2 The device exhibits better efficiency when operating under the following conditions (e.g., below 10 mA) or low current conditions. Specifically, the current density can be calculated by dividing the magnitude of the current applied to the semiconductor element 10 (in amperes (A)) by the top-view area of ​​the epitaxial structure 102 (in cm²). 2This is achieved by [the method described]. In one embodiment, the top-view area of ​​the epitaxial structure 102 can be 1 μm. 2 Up to 2500μm 2 Within a range, for example, 50μm 2 Up to 100μm 2 600μm 2 1200μm 2 1500μm 2 or 2000μm 2 When viewed from above, the extensional structure 102 has multiple areas of different sizes; the aforementioned upward-viewed area refers to the largest of these areas.

[0101] The barrier layer 108a and / or the well layer 108b may contain aluminum. In one embodiment, the active region 108 includes n pairs of semiconductor stacks 108c having n barrier layers 108a and n well layers 108b, where n is a positive integer. Each barrier layer 108a may have a first aluminum content percentage (ai%, i = 1, 2...n), and each well layer 108b may have a second aluminum content percentage (bi%, i = 1, 2...n). a1% is the first aluminum content percentage of the first barrier layer 108a, a2% is the first aluminum content percentage of the second barrier layer 108a, and an% is the first aluminum content percentage of the nth barrier layer 108a; b1% is the second aluminum content percentage of the first well layer 108b, b2% is the second aluminum content percentage of the second well layer 108b, and bn% is the second aluminum content percentage of the nth well layer 108b. In one embodiment, the first aluminum content percentage of each barrier layer 108a can be the same or different. The difference in aluminum content percentage (Al%) between barrier layers 108a can be between 0 and 1 atom%. In one embodiment, the second aluminum content percentage of each well layer 108b can be the same or different. The difference in aluminum content percentage (Al%) between well layers 108b can be between 0 and 1 atom%.

[0102] Specifically, the first and second aluminum content percentages refer to the atomic percentages (atom%) of Al in the barrier layer 108a and the well layer 108b, respectively, and can be obtained, for example, by measuring the barrier layer 108a and the well layer 108b using an energy dispersive spectroscopy (EDX) instrument. For instance, when the barrier layer 108a contains Al... z1 Ga 0.5-z1 In 0.5 P (where 0 ≤ z1 ≤ 0.5), well layer 108b contains Al z2 Ga 0.5-z2 In 0.5When P (where 0 ≤ z2 ≤ 0.5), z1 and z2 can be obtained from the EDX measurement results. Here, the first aluminum content percentage (ai%) of the barrier layer 108a can be defined as z1 × 100%, and the second aluminum content percentage (bi%) of the well layer 108b can be defined as z2 × 100%. That is, the aluminum content percentage represents the proportion of Al to the total atomic percentage of all Group 3 elements. For example, when z1 = 0.3, it means the first aluminum content percentage is 30%. In one embodiment, the aluminum content percentages of the barrier layer 108a and the well layer 108b can also be obtained using SIMS analysis. In one embodiment, the first aluminum content percentage is greater than the second aluminum content percentage. In one embodiment, the first aluminum content percentage can be in the range of 15% to 50%, for example, 20%, 25%, 30%, 35%, 40%, 45%, or 50%. In one embodiment, the second aluminum content percentage can be in the range of 0% to 15%, for example, 5% or 10%. In one embodiment, when the first aluminum content percentage is greater than or equal to 25%, the confined electron capability of the barrier layer 108a can be further improved, resulting in better quantum efficiency (such as EQE or IQE). In another embodiment, when the first aluminum content percentage is greater than or equal to 35%, even better quantum efficiency can be achieved.

[0103] In one embodiment, the active region 108 comprises n pairs of semiconductor stacks 108c having n barrier layers 108a and n well layers 108b, where n is a positive integer. Each barrier layer 108a may have a first thickness (t1i, i = 1, 2...n), and each well layer 108b may have a second thickness (t2i, i = 1, 2...n). The first thickness may be greater than or equal to the second thickness. t11 is the first thickness of the first barrier layer 108a, t12 is the first thickness of the second barrier layer 108a, and t1n is the first thickness of the nth barrier layer 108a; t21 is the second thickness of the first well layer 108b, t22 is the second thickness of the second well layer 108b, and t2n is the second thickness of the nth well layer 108b. In one embodiment, the first thickness of each barrier layer 108a may be the same or different, and the difference in thickness between the barrier layers 108a may be between 0 and 1 nm. In one embodiment, the second thickness of each well layer 108b can be the same or different, and the thickness difference between well layers 108b can be between 0 and 1 nm. The first thickness and the second thickness can be less than or equal to [missing information]. For example, approximately respectively or In one embodiment, when the thicknesses of both the barrier layer 108a and the well layer 108b are less than or equal to... The semiconductor device 10 exhibits superior quantum efficiency. In one embodiment, the ratio of the first thickness (t1i) to the second thickness (t2i) is in the range of 2:1 to 40:1. For example, the ratio of the first thickness to the second thickness (t1i / t2i) can be in the range of 10:1 to 35:1. By having a larger first thickness, the ability of the barrier layer 108a to confine electrons can be improved. In one embodiment, the first thickness can be... to Within a range, for example, greater than or equal to and less than or equal to The second thickness can be to Within the range, for example or

[0104] like Figure 1BAs shown, the first semiconductor structure 104 includes a first confinement layer 114, and the second semiconductor structure 106 includes a second confinement layer 116. In this embodiment, the first confinement layer 114 and the second confinement layer 116 are adjacent to and in direct contact with the active region 108. The first confinement layer 114 and the second confinement layer 116 may respectively comprise a group III-V semiconductor material such as a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first confinement layer 114 and the second confinement layer 116 have the same material as the barrier layer 108a. The first confinement layer 114 and / or the second confinement layer 116 may comprise aluminum. The first confinement layer 114 may have a third aluminum content percentage, and the second confinement layer 116 may have a fourth aluminum content percentage. As previously stated, the aluminum content percentage here represents the proportion of Al to the total atomic percentage of all Group 3 elements. In one embodiment, both the third and fourth aluminum content percentages are greater than the second aluminum content percentage. In one embodiment, the third and fourth aluminum content percentages are greater than or equal to the first aluminum content percentage. In one embodiment, the first confinement layer 114 may have a third thickness (t3), and the second confinement layer 116 may have a fourth thickness (t4). The third and fourth thicknesses may be the same or different. In one embodiment, the third thickness is greater than or equal to the second thickness, and the fourth thickness is greater than or equal to the second thickness, thereby enhancing the ability of the first confinement layer 114 and the second confinement layer 116 to confine electrons. In one embodiment, the ratio of the third thickness to the first or second thickness (t3 / t1i or t3 / t2i) is in the range of 1.5:1 to 10:1, for example, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1. In one embodiment, the ratio of the fourth thickness to the first or second thickness (t4 / t1i or t4 / t2i) is in the range of 1.5:1 to 10:1, for example, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, or 9:1. In one embodiment, when t3 / t1i, t3 / t2i, t4 / t1i, or t4 / t2i fall within the above range, the confinement electron capability of the first confinement layer 114 / second confinement layer 116 can be further enhanced.

[0105] In one embodiment, the active region 108 includes a first dopant. The first dopant has a doping concentration in the active region 108. The first dopant may be an n-type or p-type dopant for the active region 108. In one embodiment, the first dopant may include a Group II, Group IV, or Group VI element from the periodic table. In one embodiment, the first dopant includes C, Zn, Si, Ge, Sn, Se, Mg, or Te. In one embodiment, the doping concentration of the first dopant in the active region 108 is greater than or equal to 1 × 10⁻⁶. 16 / cm 3 In one embodiment, the doping concentration of the first dopant in the active region 108 is less than 1 × 10⁻⁶. 18 / cm 3 Specifically, the doping concentration of the first dopant in the active region 108 can be 5 × 10⁸. 15 / cm 3 Up to 1×10 16 / cm 3 5×10 16 / cm 3 8×10 16 / cm 3 1×10 17 / cm 3 Or 5×10 17 / cm 3 Within the range. The first dopant may also be distributed in the first semiconductor structure 104 and / or the second semiconductor structure 106. In one embodiment, the doping concentration of the first dopant in the first semiconductor structure 104 is higher than the doping concentration of the first dopant in the active region 108. In one embodiment, the first dopant is distributed at least in the first confinement layer 114 and the active region 108. In one embodiment, the first dopant is continuously and uninterruptedly distributed in the first confinement layer 114 and the active region 108 and may have a doping concentration of not less than 1×10⁻⁶. 16 / cm 3 The doping concentration. "Continuously and uninterruptedly distributed in the first confinement layer 114 and the active region 108" means that when the first confinement layer 114 and the active region 108 are analyzed using SIMS, a signal of the first dopant can be obtained at each depth location in the first confinement layer 114 and the active region 108. Specifically, in one embodiment, when the first dopant is analyzed using SIMS, the first dopant is present at least between the surface of the first confinement layer 114 away from the active region 108 and the interface between the active region 108 and the second confinement layer 116, and is present in each barrier layer 108a and each well layer 108b of the active region 108.

[0106] In one embodiment, in the semiconductor stack 108c of the active region 108 closest to the first confinement layer 114, the doping concentration of the first dopant may be not less than 1 × 10⁻⁶. 16 / cm 3and not greater than 1×10 18 / cm 3 In one embodiment, in the semiconductor stack 108c closest to the active region 108 of the second confinement layer 116, the doping concentration of the first dopant may be not less than 1 × 10⁻⁶. 16 / cm 3 and not greater than 1×10 17 / cm 3 In one embodiment, the doping concentration of the first dopant in the semiconductor stack 108c closest to the active region 108 of the first confining layer 114 is greater than or equal to the doping concentration of the first dopant in the semiconductor stack 108c closest to the active region 108 of the second confining layer 116. In one embodiment, the first dopant is distributed at least in the first confining layer 114, the second confining layer 116, and the active region 108. In one embodiment, the doping concentration of the first dopant in the first confining layer 114 is greater than or equal to the doping concentration of the first dopant in the active region 108. In one embodiment, the doping concentration of the first dopant in the active region 108 is greater than or equal to the doping concentration of the first dopant in the second confining layer 116. In one embodiment, the doping concentration of the first dopant gradually decreases from the first confining layer 114 to the second confining layer 116. Specifically, in one embodiment, the first dopant may have a minimum doping concentration c1 in the first confinement layer 114, a minimum doping concentration c2 in the second confinement layer 116, and a minimum doping concentration c3 in the active region 108, wherein c1 ≥ c3 ≥ c2. The minimum doping concentrations c1, c2, and c3 can be the minimum doping concentrations of the first dopant in the first confinement layer 114, the second confinement layer 116, and the active region 108, respectively. When the first dopant is analyzed using SIMS, these minimum values ​​can correspond to the lowest trough positions (in the absence of obvious troughs) of the first dopant concentration curve in the SIMS analysis results for the lowest possible concentration in the first confinement layer 114, the second confinement layer 116, and the active region 108.

[0107] The first semiconductor structure 104 may further include a first capping layer 118 located below the first confinement layer 114. The first capping layer 118 may comprise a group III-V semiconductor material such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the first capping layer 118 also comprises a first dopant. In one embodiment, the doping concentration of the first dopant in the first capping layer 118 is greater than or equal to the doping concentration of the first dopant in the first confinement layer 114.

[0108] In one embodiment, the first semiconductor structure 104 may optionally further include a first window layer (not shown) located below the first capping layer 118. The first window layer may comprise a group III-V semiconductor material such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). The materials of the first window layer and the first capping layer 118 may be different. In one embodiment, the thickness of the first window layer is greater than the thickness of the first capping layer 118. In one embodiment, the first window layer also comprises a first dopant. In one embodiment, the doping concentration of the first dopant in the first window layer is greater than or equal to the doping concentration of the first dopant in the first capping layer 118 or the first confinement layer 114. In one embodiment, the doping concentration of the first dopant in the first capping layer 118 and / or the first window layer is less than or equal to 1 × 10⁻⁶. 19 / cm 3 For example, in 5×10 17 / cm 3 Up to 1×10 18 / cm 3 2×10 18 / cm 3 Or 3×10 18 / cm 3 Within the range.

[0109] In one embodiment, the second semiconductor structure 106 further includes a second capping layer 119 located above the second confinement layer 116. The second capping layer 119 may comprise a group III-V semiconductor material such as a ternary compound semiconductor (e.g., InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN) or a quaternary compound semiconductor (e.g., AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In one embodiment, the second capping layer 119 comprises a second dopant different from the first dopant. In one embodiment, the second dopant may comprise a group II, IV, or VI element from the periodic table. In one embodiment, the second dopant comprises C, Zn, Si, Ge, Sn, Se, Mg, or Te. The second dopant may also be distributed in the active region 108 and / or the second confinement layer 116. In one embodiment, the first and second dopant may coexist in the second confinement layer 116 and / or the second capping layer 119. In one embodiment, the second dopant in the second confining layer 116 and / or the second capping layer 119 may have a content of not less than 1 × 10⁻⁶. 16 / cm 3 The doping concentration.

[0110] In one embodiment, the first semiconductor structure 104 may include a third dopant different from the first and second dopants. In one embodiment, the third dopant is distributed in the first capping layer 118 and / or the first window layer. In one embodiment, the first dopant is distributed in the first capping layer 118, the first confinement layer 114, and the active region 108, while the third dopant is mainly distributed in the first window layer. In one embodiment, the first and third dopants do not coexist in the first confinement layer 114, the active region 108, the first capping layer 118, or the first window layer simultaneously; for example, in the first confinement layer 114, the active region 108, the first capping layer 118, or the first window layer, the minimum doping concentration of one of the first and third dopants is less than 1 × 10⁻⁶. 16 / cm 3 In one embodiment, the third dopant may comprise an element from Group II, Group IV, or Group VI of the periodic table. In one embodiment, the third dopant comprises C, Zn, Si, Ge, Sn, Se, Mg, or Te. In one embodiment, the atomic radius of the third dopant is smaller than the atomic radius of the first or second dopant. In one embodiment, for the first semiconductor structure 104, the first and third dopants are dopants of the same conductivity type, and the second dopant is a dopant of the opposite conductivity type. For example, for the first semiconductor structure 104, the first and third dopants are p-type dopants, and the second dopant is an n-type dopant, or the first and third dopants are n-type dopants, and the second dopant is a p-type dopant. In one embodiment, a first dopant is continuously and uninterruptedly distributed in the first capping layer 118 to the second confining layer 116. For example, when analyzing the first capping layer 118 to the second confining layer 116 with SIMS, a signal of the first dopant can be obtained at each depth position in the first capping layer 118 to the second confining layer 116. In one embodiment, a second dopant is continuously and uninterruptedly distributed in the second capping layer 119. For example, when analyzing the second capping layer 119 with SIMS, a signal of the second dopant can be obtained at each depth position in the second capping layer 119. In one embodiment, a third dopant is continuously and uninterruptedly distributed in the first window layer. For example, when analyzing the first window layer with SIMS, a signal of the third dopant can be obtained at each depth position in the first window layer. In one embodiment, the doping concentration of the second dopant in the second confining layer 116 may be slightly less than the doping concentration of the second dopant in the second capping layer 119. In one embodiment, the doping concentration of the third dopant in the first window layer may be greater than the doping concentration of the third dopant in the first capping layer 118. In one embodiment, the first dopant and the third dopant may coexist at the interface between the first window layer and the first cover layer 118.

[0111] The first electrode 110 and the second electrode 112 are used for electrical connection to an external power source. The materials of the first electrode 110 and the second electrode 112 may be the same or different, for example, comprising metal oxides, metals, or alloys respectively. Metal oxides include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO), etc. Metals may include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), nickel (Ni), or copper (Cu), etc. Alloys may contain at least two selected from the group consisting of the aforementioned metals, such as germanium-gold-nickel (GeAuNi), beryllium-gold (BeAu), germanium-gold (GeAu), or zinc-gold (ZnAu), etc. Figure 1A As shown, the first electrode 110 may include an electrode pad 110a and an extension electrode 110b connected to the electrode pad 110a. In this embodiment, the extension electrode 110b includes a first extension 110b1 and a second extension 110b2. The first extension 110b1 is in direct contact with the electrode pad 110a, and the second extension 110b2 is in direct contact with the first extension 110b1 and can extend in a direction perpendicular to the first extension 110b1. In one embodiment, the semiconductor element 10 may have only one electrode pad 110a, but is not limited thereto.

[0112] Figure 1D This is a cross-sectional view of a semiconductor element 20 according to an embodiment of the present invention. The main difference between the semiconductor element 20 and the semiconductor element 10 in this embodiment is that the semiconductor element 20 further includes an insulating layer 120, a conductive layer 122, a reflective layer 124, and a bonding structure 128. The insulating layer 120, conductive layer 122, reflective layer 124, and bonding structure 128 are located between the epitaxial structure 102 and the substrate 100. In this embodiment, the insulating layer 120 is connected to the second semiconductor structure 106, and the first electrode 110 is located on and connected to the first semiconductor structure 104. The conductive layer 122 covers the insulating layer 120, the reflective layer 124 covers the conductive layer 122, and the bonding structure 128 is located between the substrate 100 and the reflective layer 124.

[0113] The insulating layer 120 may be a patterned dielectric material layer, such as an insulating material with a refractive index less than 2, such as silicon nitride (SiN). x ), aluminum oxide (AlO) x ), silicon dioxide (SiO) x ), magnesium fluoride (MgF) x(or combinations thereof). In one embodiment, x = 1.5 or 2. For example... Figure 1D As shown, the insulating layer 120 has a plurality of pores 126, and the conductive layer 122 can cover the insulating layer 120 and fill the pores 126. The conductive layer 122 and the epitaxial structure 102 can form contact regions at the pores 126. Thus, the conductive layer 122 can be electrically connected to the epitaxial structure 102. The conductive layer 122 may contain a metal or a metal oxide. The metal may contain silver (Ag), germanium (Ge), gold (Au), nickel (Ni), or combinations thereof. The metal oxide may contain indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), indium zinc oxide (IZO), or combinations thereof.

[0114] The reflective layer 124 reflects light emitted from the active region 108 so that it exits the semiconductor element 20 in the direction of the first electrode 110. The reflective layer 124 may comprise a semiconductor material, a metal, or an alloy. The semiconductor material may comprise a group III-V semiconductor material, such as a binary, ternary, or quaternary group III-V semiconductor material. The metal includes, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The alloy may comprise at least two selected from the group consisting of the aforementioned metals. In one embodiment, the reflective layer 124 may comprise a distributed Bragg reflector structure (DBR). The Bragg reflector structure may be formed by alternating stacks of two or more semiconductor materials with different refractive indices, such as AlAs / GaAs, AlGaAs / GaAs, or InGaP / GaAs.

[0115] A bonding structure 128 connects the substrate 100 and the reflective layer 124. In one embodiment, the bonding structure 128 may be a single layer or multiple layers (not shown). The material of the bonding structure 128 may include a transparent conductive material, a metal, or an alloy. Transparent conductive materials include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO), graphene, or combinations thereof. Metals include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The alloy may contain at least two of the metals selected from the group consisting of the metals described above.

[0116] Although Figure 1D The diagram shows a first semiconductor structure 104 located above the active region 108 and a second semiconductor structure 106 located below the active region 108. However, in another embodiment, it may also have the following configuration: the first semiconductor structure 104 is located below the active region 108 and is in contact with the insulating layer 120 and the conductive layer 122, and the second semiconductor structure 106 is located above the active region 108 and is in contact with the first electrode 110. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0117] Figure 1E This is a top view of a semiconductor element 40 according to an embodiment of the present invention. Figure 1F for Figure 1E A schematic cross-sectional view of the semiconductor element 40 along the Y-Y' line is shown. The main difference between the semiconductor element 40 and semiconductor element 10 in this embodiment is that the first electrode 110 and the second electrode 112 in semiconductor element 40 are located on the same side of the substrate 100, while the first electrode 110 and the second electrode 112 in semiconductor element 10 are located on opposite sides of the substrate 100. In this embodiment, the epitaxial structure 102 is located on the substrate 100, and the first electrode 110 and the second electrode 112 are located on the epitaxial structure 102. The first electrode 110 can be connected to the second semiconductor structure 106, and the second electrode 112 can be connected to the first semiconductor structure 104. In this embodiment, the first semiconductor structure 104 and the active region 108 have a width smaller than the width of the second semiconductor structure 106. Although... Figure 1FThe illustration shows a first semiconductor structure 104 located above the active region 108 and a second semiconductor structure 106 located below the active region 108. However, in another embodiment, the first semiconductor structure 104 may be located below the active region 108 and in contact with the substrate 100, while the second semiconductor structure 106 may be located above the active region 108 and in contact with the second electrode 112. Similarly, the insulating layer 120, conductive layer 122, reflective layer 124, or bonding structure 128 described in the previous embodiments may be located between the second semiconductor structure 106 and the substrate 100. The bonding structure 128 may contain conductive or non-conductive materials. The positions, relative relationships, material compositions, and structural variations of the other layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0118] Figure 2A This diagram illustrates the relationship between current density and internal quantum efficiency (IQE) of a semiconductor element in an embodiment of the present invention. Specifically, Figure 2A The figure shows the IQE performance obtained from simulations using the semiconductor device simulation software APSYS (Crosslight Software Inc.). The semiconductor device corresponding to curve C1 has an undoped structure in the active region 108, while the semiconductor device corresponding to curve C2 contains approximately 1 × 10⁻⁶ doped structures in the active region 108. 16 / cm 3 The structure of the first dopant with the highest doping concentration. For example... Figure 2A As shown, both are at a current density of approximately 30 A / cm². 2 It has the highest IQE value at 1 A / cm. Furthermore, at 1 A / cm... 2 In the following low current density range, the semiconductor device with the first dopant in the active region 108 exhibits a higher IQE value compared to the semiconductor device without doping in the active region 108. Therefore, the presence of the first dopant in the active region contributes to an improved IQE value, particularly in low current density environments (e.g., 1 A / cm²). 2 (The following) IQE values ​​can be significantly improved.

[0119] Figure 2B This diagram illustrates the relationship between current density and external quantum efficiency (EQE) of a semiconductor element in an embodiment of the present invention. The semiconductor element corresponding to curve F1 has an undoped structure in the active region 108, while the semiconductor element corresponding to curve F2 contains a structure with a first dopant in the active region 108. Figure 2B As shown, at 1A / cm 2 The following low current density range (e.g., 0.001–1 A / cm) 2 Semiconductor devices with a first dopant in the active region 108 have high external quantum efficiency.

[0120] Figure 2C This diagram illustrates the relationship between the R value and the relative EQE ratio of semiconductor elements in embodiments of the present invention. The semiconductor element corresponding to curve G1 has an undoped structure in the active region 108, while the semiconductor element corresponding to curve G2 contains a structure with a first dopant in the active region 108. The semiconductor elements corresponding to curves G1 and G2 are at 0.001 A / cm². 2 ~100A / cm 2 When measured within the current density range, the semiconductor device will have a maximum external quantum efficiency E within the aforementioned current density range. max The current density corresponding to this maximum external quantum efficiency is defined as J_E. max A / cm 2 . Figure 2C A value of R = 1 corresponds to a current density of 1 × (J_E) max A / cm 2 The result, and Figure 2C To display in 0.001×(J_E max A / cm 2 Up to 1×(J_E) max A / cm 2 The relative EQE ratio within the current density range. In other words, the above relative EQE ratio is the ratio of E... max The percentage is set to 100%, and the EQE value obtained under different current densities is calculated as a percentage of E. max It is obtained as a percentage. For example, Figure 2C As shown, a semiconductor device with a first dopant in the active region 108 operates below J_E. max It exhibits relatively good EQE performance across the entire current density range, for example, at 0.001×(J_E) max A / cm 2 At a given current density, a semiconductor device with a first dopant in the active region 108 is significantly superior to a semiconductor device without dopant in the active region 108.

[0121] Figure 2D This diagram illustrates the relationship between current density and external quantum efficiency (EQE) of a semiconductor element in an embodiment of the present invention. The difference between the semiconductor elements represented by curves Q1 to Q3 lies in the percentage of aluminum content in the barrier layer. Curve Q1 corresponds to a semiconductor element with an aluminum content of approximately 17.5% per 108a barrier layer, curve Q2 corresponds to approximately 35% per 108a barrier layer, and curve Q3 corresponds to approximately 50% per 108a barrier layer. Figure 2D It can be seen that when the current density is 1 A / cm 2Increasing the percentage of aluminum content in the barrier layer 108a contributes to the EQE performance of semiconductor devices.

[0122] Figure 3 This is a graph showing the relationship between element concentration and depth in a portion of a semiconductor device according to an embodiment of the present invention. Specifically, Figure 3 The results of SIMS analysis of a portion of the structure of a semiconductor device 10 containing a first dopant and a second dopant. For example... Figure 3 As shown, the semiconductor element 10 in this embodiment sequentially includes a second capping layer 119, a second confinement layer 116, an active region 108, a first confinement layer 114, a first capping layer 118, and a first window layer 130. In this embodiment, the second capping layer 119 contains AlInP; the second confinement layer 116 contains AlGaInP; the active region 108 contains 16 pairs of semiconductor stacks 108c (16 barrier layers 108a and 16 well layers 108b), and both barrier layers 108a and well layers 108b contain AlGaInP; the first confinement layer 114 contains AlGaInP; the first capping layer 118 contains AlInP and the first window layer 130 contains AlGaInP. Figure 3 Curve D1 in the figure represents the dopant concentration of the first dopant, while curve D2 represents the dopant concentration of the second dopant. In this embodiment, the first dopant is distributed at least in the range from the first window layer 130 to the second confinement layer 116, and the second dopant is mainly distributed in the second capping layer 119 and the second confinement layer 116. Figure 3 As shown, the doping concentration of the second dopant in the second confining layer 116 is significantly lower than that of the second dopant in the second capping layer 119.

[0123] Figure 4 This is a schematic diagram illustrating the relationship between current density and internal quantum efficiency (IQE) of a semiconductor element in an embodiment of the present invention. Specifically, Figure 4 The IQE performance is shown in the simulation results obtained using the semiconductor device simulation software APSYS (Crosslight Software Inc.). The differences between the semiconductor devices lie in the different doping concentrations of the first dopant in the active region 108. Specifically, the semiconductor device corresponding to curve E0 has an undoped structure in the active region 108, while curves E1 to E5 correspond to doping concentrations of approximately 1 × 10⁻⁶ for the first dopant in the active region 108. 16 / cm 3 5×10 16 / cm 3 1×10 17 / cm 3 5×10 17 / cm 3 1×10 18 / cm 3The structure. For example... Figure 4 As shown, in this embodiment, at 1A / cm 2 At the following low current densities, the doping concentration of the first dopant is approximately 1 × 10⁻⁶. 16 / cm 3 Up to 1×10 17 / cm 3 The IQE performance of the structures within the range (curves E1 to E3) is significantly better than that of the undoped structures in active region 108 (curve E0). In this embodiment, when the doping concentration of the first dopant increases to 1×10⁻⁶, the IQE performance is significantly better than that of the structures in active region 108 (curve E0). 17 / cm 3 At 1A / cm 2 The following values ​​have the highest IQE. When the doping concentration of the first dopant increases to 5 × 10⁻⁶,... 17 / cm 3 Or 1×10 18 / cm 3 At times (curves E4-E5), the IQE performance is still better than the undoped structure in the active region 108 (curve E0) within certain current density ranges. Figure 4 It can be seen that, in this embodiment, by having a first dopant with a specific doping concentration range in the active region 108, the low current density (e.g., 1 A / cm²) can be improved while maintaining maximum quantum efficiency. 2 Quantum efficiency performance under the following conditions.

[0124] Figure 5A This is a cross-sectional structural diagram of a semiconductor component 200 according to an embodiment of the present invention. Figure 5AAs shown, the semiconductor component 200 includes a carrier substrate 22, an adhesive layer 24 on the carrier substrate 22, and a plurality of semiconductor elements 10' on the adhesive layer 24. In this embodiment, the semiconductor elements 10' do not include a substrate and include an epitaxial structure 102 as described in various embodiments and a first electrode 110 and a second electrode 112 located on both sides of the epitaxial structure 102, respectively. The carrier substrate 22 is connected to the semiconductor elements 10' through the adhesive layer 24. The carrier substrate 22 may contain conductive or insulating materials, such as sapphire, glass, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), germanium (Ge), or silicon (Si). The adhesive layer 24 may be made of polymeric materials such as benzocyclobutene (BCB), epoxy resin, polyimide, silicone resin, or SOG (Spin On Glass). The positions, relative relationships, material compositions, and structural variations of the other layers or structures in this embodiment have been described in detail in previous embodiments and will not be repeated here.

[0125] Figure 5B This is a cross-sectional structural diagram of a semiconductor component 400 according to an embodiment of the present invention. Figure 5B As shown, the semiconductor component 400 includes a carrier substrate 42, an adhesive layer 44 on the carrier substrate 42, and a plurality of semiconductor elements 40' on the adhesive layer 44. In this embodiment, the semiconductor elements 40' do not include a substrate and may include an epitaxial structure 102 as described in previous embodiments, and a first electrode 110 and a second electrode 112 located on one side of the epitaxial structure 102. The semiconductor element 40' also includes a first contact structure 140a located between the first electrode 110 and the epitaxial structure 102, and a second contact structure 140b located between the second electrode 112 and the epitaxial structure 102. The first contact structure 140a and the second contact structure 140b may respectively comprise a group III-V semiconductor material, a metal, or an alloy. The semiconductor element 40' also includes a dielectric material layer 160 covering the epitaxial structure 102 and having an opening. Figure 5B As shown, the first electrode 110 and the second electrode 112 can be filled into the openings of the dielectric material layer 160 and electrically connected to the first contact structure 140a and the second contact structure 140b, respectively. Regarding the carrier substrate 42 and the adhesive layer 44, please refer to the descriptions of the carrier substrate 22 and the adhesive layer 24, respectively. The positions, relative relationships, material compositions, and structural variations of other layers or structures in this embodiment have been described in detail in previous embodiments and will not be repeated here.

[0126] Figure 6 This is a cross-sectional structural diagram of a semiconductor component 600 according to an embodiment of the present invention. Please refer to... Figure 6 The semiconductor component 600 includes a semiconductor element 60, a packaging substrate 61, a carrier 63, bonding wires 65, a contact structure 66, and a packaging layer 68. The packaging substrate 61 may contain ceramic or glass material. The packaging substrate 61 has a plurality of through-holes 62. The through-holes 62 may be filled with a conductive material such as metal to facilitate conductivity and / or heat dissipation. The carrier 63 is located on one side of the surface of the packaging substrate 61 and also contains a conductive material such as metal. The contact structure 66 is located on the other side of the surface of the packaging substrate 61. In this embodiment, the contact structure 66 includes a first contact pad 66a and a second contact pad 66b, and the first contact pad 66a and the second contact pad 66b can be electrically connected to the carrier 63 through the through-holes 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the first contact pad 66a and the second contact pad 66b.

[0127] Semiconductor element 60 is located on carrier 63. Semiconductor element 60 can be any of the semiconductor elements described in any embodiment of the present invention (such as semiconductor elements 10, 10', 20, 40, 40'). In this embodiment, carrier 63 includes a first portion 63a and a second portion 63b, and semiconductor element 60 is electrically connected to the second portion 63b of carrier 63 via bonding wire 65. The bonding wire 65 may be made of a metal, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. Encapsulation layer 68 covers semiconductor element 60 and has the effect of protecting semiconductor element 60. Specifically, encapsulation layer 68 may contain resin materials such as epoxy resin, silicone resin, etc. Encapsulation layer 68 may also contain a plurality of wavelength conversion particles (not shown) to convert the first light emitted by semiconductor element 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

[0128] Figure 7 This is a top view schematic diagram of a semiconductor component 800 according to an embodiment of the present invention. The semiconductor component 800 in this embodiment is, for example, a display unit. Figure 7As shown, the semiconductor component 800 includes a carrier plate 80 and a plurality of pixel units 82 located on the carrier plate 80. The plurality of pixel units 82 are arranged in an array along directions parallel to the x-axis and y-axis, and are arranged at a spacing d in the direction parallel to the x-axis. The number of pixel units 82 can be adjusted as needed; for example, in one embodiment, the plurality of pixel units 82 included in the semiconductor component 800 can provide a resolution of 1920 × 1080 pixels. In one embodiment, the spacing d is less than 1.4 mm; for example, the spacing d is between 0.2 mm and 1.3 mm, specifically 0.75 mm, 0.8 mm, 1 mm, and 1.25 mm. Figure 7 As shown, each pixel unit 82 includes a first semiconductor element 84, a second semiconductor element 86, and a third semiconductor element 88 arranged along a direction parallel to the y-axis. One or more of the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 can be semiconductor elements described in any embodiment of the present invention (such as semiconductor elements 10, 10', 20, 40, 40'). In one embodiment, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 are all light-emitting elements and can emit red, green, and blue light, respectively. In one embodiment, the arrangement order of these light-emitting elements can also be adjusted as needed; for example, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 can emit red, blue, and green light, respectively. Each pixel unit 82 can be electrically connected to a circuit (not shown) on the surface of the carrier plate 80, enabling the light-emitting elements therein to receive external signals and emit light according to the external signals. The carrier plate 80 can be a single-layer or multi-layer structure. The carrier plate 80 may be made of polyester, polyimide (PI), BT resin (Bismaleimide Triazine), PTFE resin (Polytetrafluoroethylene), phenolic resins (PF), or glass fiber epoxy resin (FR4). In one embodiment, the carrier plate 80 is bendable and, for example, can withstand a radius of curvature less than 50 mm, such as 25 mm or 32 mm.

[0129] As described above, when the length L0 and width W0 of the semiconductor element are within the aforementioned range (less than or equal to 500 μm) and the operating current of the semiconductor element is between 0.001 mA and 100 mA and / or the current density is between 0.001 A / cm², 2 and 100A / cm 2Between these factors, the logarithm of the semiconductor stack 108c in the active region 108 and / or the percentage of the first aluminum content and / or the thickness of the barrier layer 108a and the well layer 108b and / or the thickness of the first or second confinement layer and / or the aluminum content of the first or second confinement layer and / or the concentration of the first dopant in the active region 108 will affect the quantum efficiency of the semiconductor device.

[0130] Specifically, in one embodiment, when the operating current is between 0.01mA and 5mA and / or the current density is between 0.01A / cm², 2 and 5A / cm 2 Between these conditions, an epitaxial structure or semiconductor element that satisfies any one or a combination of two or more of the following conditions (i) to (vi) can have a relatively high quantum efficiency: (i) the first aluminum content percentage is 25% or more; (ii) the ratio of the first thickness to the second thickness is in the range of 2:1 to 40:1; (iii) the number of pairs of semiconductor stacks 108c in the active region 108 is less than 10 pairs; (iv) the third / fourth aluminum content percentage is greater than the second aluminum content percentage; (v) the third thickness is greater than or equal to the second thickness and the fourth thickness is greater than or equal to the second thickness; (vi) the active region 108 contains a first dopant. Furthermore, the length L0 of the semiconductor element 10 is less than 200 μm and the width W0 is less than 200 μm and / or the top-view area of ​​the epitaxial structure 102 is 50 μm. 2 Up to 2000μm 2 When the range is within the range, epitaxial structures or semiconductor devices that satisfy any one or more of the above conditions (i) to (vi) show a more significant improvement in quantum efficiency.

[0131] According to one embodiment, when at different current densities (e.g., 0.001 to 100 A / cm²), 2 Within the range, such as 0.001 to 0.01, 0.1, 1, 5, 10 or 50 A / cm 2 When measuring the external quantum efficiency (e.g., in %) of an epitaxial structure or semiconductor element, the epitaxial structure or semiconductor element that satisfies any one or a combination of two or more of the above conditions (i) to (vi) has a maximum external quantum efficiency E within the above current density range. 1max %, and the maximum external quantum efficiency E 1max The current density corresponding to % is defined as J_E 1max A / cm 2 External quantum efficiency is obtained, for example, through an integrating sphere system. At 0.1 × (J_E) 1max A / cm 2 At a current density of [value missing], the aforementioned epitaxial structure or semiconductor device can have E [value missing]. 1maxWith an external quantum efficiency of over 80%, and preferably with E 1max External quantum efficiency of 85% or 90% or higher. At 0.01 × (J_E) 1max A / cm 2 At a current density of [value missing], the aforementioned epitaxial structure or semiconductor device can have E [value missing]. 1max With an external quantum efficiency of over 50%, and preferably with E 1max External quantum efficiency of 60% or 70% or higher. At 0.001 × (J_E) 1max A / cm 2 At a current density of [value missing], the aforementioned epitaxial structure or semiconductor device can have E [value missing]. 1max External quantum efficiency of over 15%, and preferably E 1max External quantum efficiency of 20%, 25%, 30% or 40% or more.

[0132] According to one embodiment, when the external quantum efficiency (e.g., in %) of an epitaxial structure or semiconductor element is measured at different current intensities (e.g., in the range of 0.001 to 100 mA, such as 0.001 to 0.01, 0.1, 1, 5, 10, 20, 30, 40, or 50 mA), the epitaxial structure or semiconductor element that satisfies any one or a combination of two or more of the above conditions (i) to (vi) has a maximum external quantum efficiency E within the above current range. 2max %, and the maximum external quantum efficiency E 2max The current density corresponding to % is defined as C_E 2max mA. External quantum efficiency, for example, is measured using an integrating sphere system. E 2max The percentage can be over 80%, and the best is E. 2max The percentage is 85% or 90% or higher. Within 0.01×(C_E) 2max At a current of ) mA, the aforementioned epitaxial structure or semiconductor device may have E 2max With an external quantum efficiency of over 50%, and preferably with E 2max External quantum efficiency of 60% or 70% or higher. At 0.001 × (C_E) 2max At a current of ) mA, the aforementioned epitaxial structure or semiconductor device may have E 2max External quantum efficiency of over 15%, and preferably E 2max External quantum efficiency of 20%, 25%, 30% or 40% or more.

[0133] According to one embodiment, an epitaxial structure or semiconductor element satisfying any one or more of the conditions (i) to (vi) above has a first light output value O1 (e.g., in lumens (lm)) at a first temperature and a second light output value O2 at a second temperature, wherein the second temperature is lower than the first temperature. The first and second temperatures are, for example, different ambient temperatures used to test or operate the epitaxial structure / semiconductor component. The ratio of the first light output value O1 to the second light output value O2 may be greater than or equal to 30%, for example, 40%, 50%, 60%, 70%, 80%, or 90%. The ratio of the first light output value O1 to the second light output value O2 may be less than or equal to 100%. The difference between the first and second temperatures may be greater than or equal to 30°C, for example, about 40°C, 50°C, 60°C, 70°C, or 80°C. In one embodiment, the second temperature is room temperature (e.g., about 25°C), and the first temperature is about 85°C. That is, the light output value of an epitaxial structure or semiconductor element that satisfies any one or more of the above conditions (i) to (vi) is less affected by temperature changes and can have a low temperature dependence.

[0134] Based on the above, embodiments of the present invention can provide an epitaxial structure, semiconductor element, or semiconductor assembly, which can further improve characteristics such as internal or external quantum efficiency, and is particularly suitable for low current (e.g., below 10 mA) or low current density (e.g., 1 A / cm²). 2 The following applies to applications requiring operation and / or miniaturization. Specifically, the epitaxial structures, semiconductor elements, or semiconductor assemblies described in this invention offer improvements in surface recombination velocity (SRV), temperature dependence, current distribution, and droop. More specifically, the epitaxial structures, semiconductor elements, and semiconductor assemblies described in this invention can be applied to products in the fields of lighting, medical, display, communication, sensing, and power systems, such as lamps, monitors, mobile phones, tablet computers, automotive dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, and medical devices.

[0135] While the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the invention. Those skilled in the art will understand that modifications or alterations can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims. Furthermore, the above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure, comprising a first dopant; A second semiconductor structure is located on the first semiconductor structure and includes the first dopant and a second dopant different from the first dopant; as well as An active region is located between the first semiconductor structure and the second semiconductor structure and includes multiple pairs of semiconductor stacks, each of which includes a barrier layer and a well layer, and the active region includes the first dopant. The first semiconductor structure further includes a third dopant that is different from the first dopant and the second dopant. The active region does not contain N, and the doping concentration of the first dopant in the first semiconductor structure is higher than the doping concentration of the first dopant in the active region.

2. The semiconductor device of claim 1, wherein the atomic radius of the third dopant is smaller than the atomic radius of the first dopant or the second dopant.

3. The semiconductor device of claim 1, wherein the barrier layer has a first thickness, the well layer has a second thickness, and the first thickness is greater than the second thickness.

4. The semiconductor element of claim 3, wherein the ratio of the first thickness to the second thickness is in the range of 2:1 to 40:

1.

5. The semiconductor device of claim 1, wherein the first semiconductor structure further includes a first confining layer in direct contact with the active region, and a first capping layer located below the first confining layer.

6. The semiconductor device as claimed in claim 1, wherein, The first dopant and the third dopant are dopants with the same conductivity type.

7. The semiconductor device of claim 5, wherein the second semiconductor structure further includes a second confining layer directly contacting the active region and a second capping layer located above the second confining layer, the second capping layer comprising the first dopant and the second dopant.

8. The semiconductor device as claimed in claim 5, wherein, The first capping layer contains the third dopant.

9. The semiconductor device of claim 1, wherein the first dopant comprises C, Zn, Si, Ge, Sn, Se, Mg or Te.

10. The semiconductor device of claim 1, wherein the first dopant in the active region has a doping concentration greater than or equal to 1 × 10⁻⁶. 16 / cm 3 .

11. A semiconductor element, characterized in that, include: A first semiconductor structure includes a first confinement layer and a first dopant; A second semiconductor structure is located on the first semiconductor structure, includes a second confinement layer and includes a second dopant that is different from the first dopant; as well as An active region is located between the first semiconductor structure and the second semiconductor structure and includes multiple pairs of semiconductor stacks, each of which includes a barrier layer and a well layer, and the active region includes the first dopant. The barrier layer has a first thickness and a first aluminum content percentage, the well layer has a second thickness and a second aluminum content percentage, and the first aluminum content percentage is greater than the second aluminum content percentage; the first confinement layer and the second confinement layer are adjacent to the active region and in direct contact with the active region; the first confinement layer has a third thickness and a third aluminum content percentage, the second confinement layer has a fourth thickness and a fourth aluminum content percentage; the first dopant is continuously and uninterruptedly distributed in the first confinement layer and the active region; the third aluminum content percentage and the fourth aluminum content percentage are greater than the second aluminum content percentage; the third thickness is greater than or equal to the second thickness; and the fourth thickness is greater than or equal to the second thickness.

12. The semiconductor device of claim 11, wherein the first thickness is greater than the second thickness.

13. The semiconductor element of claim 12, wherein the ratio of the first thickness to the second thickness is in the range of 2:1 to 40:

1.

14. The semiconductor device of claim 11, wherein the first aluminum content percentage is in the range of 15% to 50%, and the second aluminum content percentage is in the range of 0% to 15%.

15. The semiconductor device of claim 11, wherein the doping concentration of the first dopant in the active region is greater than or equal to 1 × 10⁻⁶. 16 / cm 3 .

16. The semiconductor device of claim 11, wherein the number of pairs of the semiconductor stack in the active region is 10 or less.

17. The semiconductor element of claim 11, wherein the length of the semiconductor element is less than 200 μm and the width is less than 200 μm.

18. The semiconductor device of claim 11, wherein, viewed from above, the area of ​​the upper surface of the semiconductor device is 10000 μm. 2 The following describes the semiconductor device in J_E max A / cm 2 It has the highest external quantum efficiency E at current density max %, and at 0.1×(J_E) max A / cm 2 At a current density of , the semiconductor device has E max External quantum efficiency of over 80%.

19. The semiconductor device of claim 11, wherein, viewed from above, the area of ​​the upper surface of the semiconductor device is 10000 μm. 2 The semiconductor element has a first light output value at a first temperature and a second light output value at a second temperature lower than the first temperature, wherein the difference between the first temperature and the second temperature is 30°C or more, and the ratio of the first light output value to the second light output value is greater than or equal to 30%.

20. A semiconductor component, characterized in that, Includes the semiconductor element as described in any one of claims 1 to 19.

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