Active Burst ZVS Boost PFC Converter

Abstract

The present invention discloses a power converter, which can be configured to convert an AC input voltage into a regulated DC output voltage while keeping the input current in phase with the rectified AC input voltage. The control circuit of the power converter can be configured to enable the switch of at least one switching device of the power converter in response to determining that the input voltage is greater than a threshold voltage, and selectively disable the switch of the at least one switching device in response to determining that the rectified AC input voltage is less than the threshold voltage. The control circuit can be configured to selectively enable and disable the switch using an active burst mode signal having a frequency lower than the switching frequency of the converter. The control circuit can be further configured to operate at least one switching device of the converter under zero voltage switching conditions.

Description

Background Art

[0001] There has been an increasing demand for high efficiency, high power density AC-DC converters recently. For output power ratings of 70 watts or more, a power factor correction stage may be required. In many applications, a high output voltage boost converter with a critical conduction mode (CrM) switch is used to achieve unity power factor. The switching frequency of such a boost / PFC stage is typically designed to have a widely varying switching frequency, which may result in undesirable low frequency operation within at least a portion of the operating range. For example, the maximum switching frequency may occur at a high Vac line input with a low peak current, but the switching frequency becomes very low at a low Vac line input with a high peak current. Therefore, the boost inductor value may be selected so that it has a sufficiently high current rating at a low line input voltage. However, the minimum inductance value may be limited by the maximum switching frequency at a high line input voltage. Because the switching frequency at the low line may be quite low, a large inductance value may be required for a high peak current rating. This may result in a large physical size for a boost inductor with a somewhat limited switching frequency. In addition, under high line input voltage conditions, switching losses may be undesirably high.

[0002] Therefore, there is a need for an improved boost / PFC converter design that alleviates these and other design issues to achieve higher operating efficiency and power density. Summary of the invention

[0003] The AC / DC power converter may include: an input terminal configured to receive an AC input voltage; a rectifier configured to convert the AC input voltage into a rectified AC input voltage; a boost converter configured to receive the rectified AC input voltage and deliver a regulated output voltage; and a control circuit coupled to the boost converter. The control circuit may be configured to monitor the regulated output voltage, an input current of the boost converter, and the rectified AC input voltage. The control circuit may be further configured to switch at least one switching device of the boost converter to deliver the regulated output voltage while keeping the input current in phase with the rectified AC input voltage. The control circuit may be further configured to selectively enable a switch of the boost converter in response to determining that the rectified AC input voltage is greater than a threshold voltage, and selectively disable a switch of the boost converter in response to determining that the rectified AC input voltage is less than the threshold voltage.

[0004] The boost converter of the AC / DC power converter may include: a boost inductor having a first terminal coupled to the rectified AC input voltage; a boost switching device coupled between a second terminal of the boost inductor and ground; and a boost rectifier having a first terminal coupled to the second terminal of the boost inductor and a second terminal coupled to an output of the converter. The boost rectifier may be a rectifier switching device that switches complementarily with the boost switching device. The rectifier switching device may further switch complementarily with the boost switching device via a dead time.

[0005] The control circuit of the AC / DC power converter may be further configured to selectively enable and disable the switch of the boost converter using an active burst mode signal having a frequency lower than the switching frequency of the boost converter. If the input voltage is lower than the threshold voltage, which may be zero or non-zero, the active burst mode signal may be zero. The control circuit may be further configured to operate at least one switching device of the boost converter under zero voltage switching conditions. To this end, the power converter may include a zero voltage switching capacitor coupled to the boost converter. Therefore, the control circuit may be configured to control the timing of at least one switching device of the boost converter to allow reverse current to pass through the at least one switching device before the at least one switching device is turned on, thereby allowing zero voltage switching of the at least one switching device.

[0006] The AC / DC converter circuit may include a first phase, the first phase including a first high-side switch and a first low-side switch, the first high-side switch having a first terminal coupled to the DC output terminal of the converter and a second terminal coupled to the first AC input terminal of the converter, the first low-side switch having a first terminal coupled to the second terminal of the first high-side switch and a second terminal coupled to ground. The AC / DC converter circuit may also include a second phase, the second phase including a second high-side switch and a second low-side switch, the second high-side switch having a first terminal coupled to the DC output terminal of the converter and a second terminal coupled to the second AC input terminal of the converter, the second low-side switch having a first terminal coupled to the second terminal of the first high-side switch and a second terminal coupled to ground. The AC / DC converter circuit may also include at least one inductor, the at least one inductor coupled between at least one of the first AC input terminal and the second AC input terminal and an AC input source. The at least one inductor may include a first inductor coupled between the first AC input terminal and the AC input source, and a second inductor coupled between the second AC input terminal and the AC input source.

[0007] The AC / DC converter circuit may further include a controller configured to operate the first switch phase and the second switch phase according to a switching sequence during a positive half cycle of the AC input voltage, and to operate the first switch phase and the second switch phase according to a second switching sequence during a negative half cycle of the AC input voltage. The controller may be further configured to selectively enable switching of the first switch phase and the second switch phase in response to determining that the instantaneous value of the AC input voltage is greater than a threshold voltage, and selectively disable switching of the boost converter in response to determining that the instantaneous value of the AC input voltage is less than the threshold voltage. The switching sequence during the positive half cycle of the AC input voltage may include: turning off the first high-side switch of the first phase; turning on the first low-side switch of the first phase; and switching the second high-side switch and the second low-side switch of the second phase in a critical conduction mode through a negative current limit, thereby achieving zero voltage switching of the second high-side switch and the second low-side switch. The switching sequence during the negative half cycle of the AC input voltage may include: turning off the second high-side switch of the second phase; turning on the second low-side switch of the second phase; and switching the first high-side switch and the first low-side switch of the second phase in a critical conduction mode through a negative current limit, thereby achieving zero voltage switching of the first high-side switch and the first low-side switch.

[0008] Alternatively, the switching sequence during the positive half cycle of the AC input voltage may include: turning on the first high-side switch of the first phase; turning off the first low-side switch of the first phase; and switching the second high-side switch and the second low-side switch of the second phase in a critical conduction mode by a negative current limit, thereby achieving zero voltage switching of the second high-side switch and the second low-side switch. In this alternative switching sequence, the switching sequence during the negative half cycle of the AC input voltage may include: turning on the first high-side switch of the first phase; turning off the first low-side switch of the first phase; and switching the second high-side switch and the second low-side switch of the second phase in a critical conduction mode by a negative current limit, thereby achieving zero voltage switching of the second high-side switch and the second low-side switch.

[0009] A method of operating an AC / DC converter may include monitoring a regulated output voltage, an input current, and an input voltage of the converter. The method may also include selectively switching at least one switching device to deliver the regulated output voltage while keeping the input current in phase with the input voltage. The method may also include selectively enabling switching of the at least one switching device in response to determining that the input voltage is greater than a threshold voltage, and selectively disabling switching of the at least one switching device in response to determining that the input voltage is less than the threshold voltage. The threshold voltage may be zero or non-zero. Selectively enabling and selectively disabling switching of the at least one switching device may include using an active burst mode signal having a frequency lower than a switching frequency of the boost converter. Selectively switching at least one switching device may include switching the at least one switching device under a zero voltage switching condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A schematic diagram of a boost / power factor correction converter that may be operated in critical conduction mode is shown.

[0011] Figure 1B The conceptual switching duty cycle, reference current, and inductor current of a boost / power factor correction converter are shown.

[0012] Figure 1C The simulated switch duty cycle, reference current, and inductor current of a boost / power factor correction converter operating at a relatively low input voltage are shown.

[0013] Figure 1D The simulated switch duty cycle, reference current, and inductor current of a boost / power factor correction converter operating at a relatively high input voltage are shown.

[0014] Figure 1E is a graph of switching frequency versus phase angle within a half-cycle of an AC input waveform for a boost / power factor correction converter at relatively low input voltage and relatively high input voltage.

[0015] Figure 2A Graphs of switching frequency versus phase angle within a half-cycle of an AC input waveform for a boost / power factor correction converter at relatively low input voltages and relatively high input voltages for active burst mode control operation are shown.

[0016] Figure 2B A schematic diagram of an active burst mode (ABM) boost / power factor correction converter and its control circuit.

[0017] Figure 2CConceptual switching duty cycle, reference current, and inductor current of an active burst mode boost / power factor correction converter with active burst mode selectively enabled with reference to a zero threshold voltage are shown.

[0018] Figure 2D An idealized switch duty cycle, reference current, and inductor current are shown for an active burst mode boost / power factor correction converter with active burst mode selectively enabled with reference to a threshold voltage greater than zero.

[0019] Figure 3A A half-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter is shown.

[0020] Figure 3B The conceptual switching duty cycle, reference current, and inductor current of a zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter are shown.

[0021] Figure 4 The switching sequence of a zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter is shown.

[0022] Figure 5 A schematic diagram of a half-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter and its control system is shown.

[0023] Figure 6 A flow chart outlining the control scheme of an active burst mode boost / power factor correction converter is shown.

[0024] Fig. 7A A schematic diagram of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter is shown.

[0025] Figure 7B An alternative schematic diagram of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter is shown.

[0026] Fig. 8A A first switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a positive half cycle of the input current is shown.

[0027] Figure 8B Various voltages and currents and associated waveforms are shown for a first switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a positive half-cycle of an input current.

[0028] Figure 8CA first switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a negative half cycle of the input current is shown.

[0029] Fig.8D Various voltages and currents and associated waveforms are shown for a first switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a negative half-cycle of the input current.

[0030] Fig.9A Shows FIG. 8A to FIG. 8D A generalized flow chart of the first switching sequence is depicted in FIG.

[0031] Fig. 9B Shows FIG. 8A to FIG. 8D A generalized flow chart of the first switching sequence is depicted in FIG.

[0032] Fig. 10A A second switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a positive half cycle of the input current is shown.

[0033] Fig. 10B Various voltages and currents and associated waveforms corresponding to a second switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a positive half-cycle of an input current are shown.

[0034] Fig. 10C A second switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a negative half cycle of the input current is shown.

[0035] Fig. 10D Various voltages and currents and associated waveforms corresponding to a second switching sequence of a full-bridge zero voltage switching (ZVS) active burst mode (ABM) boost / power factor correction converter during a negative half-cycle of the input current are shown.

[0036] Fig.11A Shows FIG. 10A to FIG. 10D A generalized flow chart of the second switching sequence is depicted in FIG.

[0037] Fig. 11B Shows FIG. 10A to FIG. 10D A generalized flow chart of the second switching sequence is depicted in FIG. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the disclosed concepts. As part of this description, some of the drawings in the drawings of the present disclosure represent structures and devices in block diagram form for simplicity. For the sake of clarity, not all features of actual implementations are described in the present disclosure. In addition, the language used in the present disclosure is selected for readability and instructional purposes and has not been selected to describe or limit the disclosed subject matter. Instead, the attached claims are intended for this purpose.

[0039] Various embodiments of the disclosed concepts are described by way of example, and are not limited to individual drawings, in which similar reference numerals indicate similar elements. For simplicity and clarity of description, reference numerals are repeated in different drawings to indicate corresponding or similar elements, where appropriate. In addition, many specific details are shown in order to provide a full understanding of the specific implementation described herein. In other cases, methods, procedures, and components are not described in detail to avoid blurring the related functions described. Mentioning "one", "a kind of" or "another" embodiment in this disclosure is not necessarily the same or different embodiments, and this means at least one. A given drawing may be used to illustrate more than one embodiment or more than one type of features of the present disclosure, and all elements in the drawings may not be required for a given embodiment or type. When provided in a given drawing, the reference numeral refers to the same element throughout several drawings, but it may not be repeated in each drawing. Unless otherwise specified, the drawings are not drawn to scale, and the proportions of certain components may be enlarged to better illustrate the details and features of the present disclosure.

[0040] Figures 1A to 1E Various aspects of an exemplary critical conduction mode boost / power factor correction (boost PFC converter) 100 are shown. Figure 1A A schematic diagram of the converter is shown. The AC input voltage passes through an (optional) electromagnetic interference (EMI) filter to a rectifier, which in the illustrated embodiment is a full-bridge rectifier consisting of diodes D1-D4. It should be understood that other rectifier topologies may alternatively be used. Rectifiers D1-D4 produce a full-wave rectified voltage that appears at the input of a boost converter consisting of a boost inductor Lb, a boost switching device Qm, and a boost diode Do. The switching device Qm may be operated to cause the boost / PFC converter 100 to draw a substantially sinusoidal current that is substantially in phase with the AC input voltage and to produce a DC voltage that is delivered to the load (represented here by an output capacitor Co and an output resistor Ro).

[0041] Figure 1B1 shows some aspects of the switch Qm used to implement the above operation. More specifically, waveform 102 shows the switching cycle of the main switch Qm. When the Qm signal is high, the switch Qm can be closed, which causes the current IL ( Figure 1A ) flows through the boost inductor Lb, thereby storing energy therein. When the Qm signal is low, the switch Qm can be turned on, causing the boost inductor current IL to flow to the load through the boost diode Do. The switch control signal Qm can be generated by a controller (not shown), which compares the boost inductor current I with a reference current iref (104), which can be a sinusoidal current in phase with the AC input voltage. The current window controller can be configured to turn on the boost switching device Qm when the boost inductor current IL reaches zero (i.e., critical conduction mode). As described above, turning on the boost switch Qm generates a linearly increasing current IL, which stores energy in the boost inductor Lb. The boost current IL is generated by Figure 1B The controller may also be configured to turn off the boost switch Qm when the current IL reaches the reference current iref 104. Turning off the switch results in a linear decrease in the current IL as the energy stored in the boost inductor Lb is released into the load, which is depicted by the falling slope 106b.

[0042] Boost / PFC converter 100 may be designed so that it can operate over a range of input voltages. For example, a switching power converter designed to operate from normal AC mains power in different regions of the world may experience input voltages ranging from about 100 Vac to about 240 Vac. Figure 1C Depicted are the boost switch control switch signal Qm (102a), the rectified AC input voltage 108a, and the boost inductor current IL (110a) when operating at a low line voltage (eg, an input voltage of 90 Vac). Figure 1D Depicted is the corresponding switch signal 102b, the corresponding rectified AC input voltage 108b, and the corresponding boost inductor current IL (110b) when operating at a high line voltage (e.g., an input voltage of 264Vac). In each case, the boost / PFC converter 100 is delivering the same power. Comparison of the two figures shows that the boost inductor current 110a (low voltage) is slightly greater than the boost inductor current 110b (high voltage), delivering the same amount of energy as expected.

[0043] It should be understood that the switching frequency is determined by the inductance value of the boost inductor Lb together with the input AC voltage level and the output DC voltage level. In at least some embodiments, the boost / PFC output voltage is a design target value selected based on the requirements of downstream components. Therefore, the switching frequency becomes a function of the input voltage and the boost inductor value. Figure 1EHigh-line switching frequency values ​​and low-line switching frequency values ​​for an exemplary embodiment using exemplary load conditions and inductor values ​​are shown. Figure 1E In the graph of FIG. 1 , the phase angle (in degrees) of the rectified AC input waveform is depicted on the horizontal axis, where the AC input voltage and / or switching frequency (in kilohertz) is depicted on the vertical axis. Curve 108a depicts a low AC input voltage waveform with a peak value of about 130V (corresponding to an RMS value of about 90V). Curve 112a depicts a corresponding range of required switching frequencies for a given boost inductor value and load condition. The required switching frequency is therefore in the range of about 70kHz to about 105kHz. Curve 108b depicts a high AC input voltage waveform with a peak value of about 375V (corresponding to an RMS value of about 265V). Curve 112b depicts a corresponding range of required switching frequencies for the same boost inductor value and load condition. The required switching frequency is in the range of about 20kHz to up to about 340kHz. Those skilled in the art will appreciate that in many cases, limitations on the range of switching frequencies that can be practically implemented result in the selection of relatively large inductance values, resulting in large physical sizes of the boost inductor, which may be undesirable in some implementations. Therefore, alternative control techniques that avoid this problem are desired.

[0044] FIG. 2A to FIG. 2D Various aspects of a wide range of active burst mode (ABM) controlled boost / PFC converters 200 that can be used to reduce the required switching frequency discussed above are shown. Figure 2A , the active burst mode control of the critical conduction boost / PFC converter introduces an ABM burst frequency fB signal 203 that can be much lower than the switching frequency of the boost switch Qm. The duty cycle of the ABM burst frequency fB 203 can be controlled or varied to intermittently enable and disable the switching of the switch Qm, particularly when the instantaneous rectified AC input voltage is low (i.e., close to the zero crossing point of the AC input waveform). If the ABM burst frequency signal fB is high, the main switch Qm can be enabled / allowed to switch at the desired switching frequency. Alternatively, if the ABM burst frequency signal fB is low, the switching of the main switch Qm can be disabled. If the AC input voltage drops below a predetermined design value, the ABM burst frequency signal fB can be configured so that fB becomes zero. Further reference Figure 2A , the hatched area 205 indicates the position where the switching frequency is zero when fB=0, i.e., the region where the operation of the main switch Qm can be disabled. This arrangement can allow the switching frequency fsw to be limited to a relatively narrow range of relatively high frequencies, thereby allowing a relatively small inductance value to be selected for the boost inductor.

[0045] Figure 2BAn exemplary active burst mode (ABM) boost / PFC converter 200 with an exemplary control system is shown. The power conversion stage of the circuit is substantially similar to the boost / PFC converter 100 discussed above. That is, an AC input voltage Vac is received from an input source, which passes through an (optional) EMI filter to a rectifier. The rectified AC input voltage is based on a boost converter consisting of a boost inductor LB, a boost switch Qm, and a boost diode Do. The boost switch Qm can be operated as described below to operate in an active burst mode, thereby drawing an AC input current in phase with the AC input voltage and generating a desired output voltage V across an output capacitor Cout at the output of the converter.

[0046] Regarding the control system, the ABM boost / PFC converter 200 may include an output voltage control and an input current control. The output voltage control may include an output voltage sensor 236. The output voltage Vout may be scaled by the voltage loop gain Kv (block 235) and subtracted from the output voltage reference V*o by the adder 226. The resulting output voltage error signal may be provided to any suitable controller (e.g., a proportional integral derivative controller 227). The resulting control signal may be multiplied by the instantaneous input current iC (part of the input current control) at the multiplier 228 and passed to the comparator 230 coupled to the reset input of the flip-flop 232. The input current control may also include a current sensor 224 that senses the input current, which may be scaled by the current gain Ki (block 225). The scaled input current signal may be applied to a comparator 229, which may ground its other input, thereby becoming an input current zero detector. The output of the zero current detector 229 may be provided to the set input of the flip-flop 232. Therefore, the output signal of the flip-flop 232 will be a control voltage that can be provided to the switch driver 234 to generate a control signal for the main switch Qm, which operates the switch to regulate the output voltage and input current, as described above with reference to Figures 1A to 1E described.

[0047] ABM control may also be part of the control system. More specifically, the rectified AC input voltage ("VDC") may be sensed by a voltage sensor 222. Similarly, the inductor current IL may be sensed by a current sensor 224. (Many suitable types of voltage sensors and current sensors are known to those skilled in the art and are therefore not listed or described in detail herein.) The rectified AC input voltage and inductor current may be used in the control block as follows. A sensing gain Ks (box 223) may be applied to the rectified AC input voltage signal. A sensing gain Ki (box 225) may be applied to the inductor current signal. A comparator 231 may compare the scaled / sensed rectified input voltage Vdc sense voltage with a reference / threshold voltage Vk. (See below for details.) Figure 2C and Figure 2D 230. The reference voltage / threshold voltage Vk is discussed in more detail. If VDC is less than Vk, the ABM burst frequency signal fb may be set to zero. In this case, the output of comparator 231 is low, thereby providing a low input to AND gate 233, which also receives the fsw signal generated by flip-flop 232 as discussed above. Due to the zero input into AND gate 233, a low input is provided to switch driver 234, and the main switch Qm is effectively disabled. Otherwise, the ABM switching frequency fB (having a selected frequency and duty cycle) may be set with a selected duty cycle DB. More specifically, if VDC is greater than Vk, a high output is delivered to AND gate 233, allowing the switch driver to be triggered whenever fB and fsw are both high.

[0048] Figure 2C 2 shows the operation of the converter 200 when the reference voltage / threshold voltage Vk is zero. As described above, if the ABM signal fB (203a, Figure 2B ) is high, the fsw signal 202a is allowed to turn on or off the boost switch Qm at the switching frequency determined by the control loop as described above. This generates the current pulse 206 as described above. Alternatively, if the burst frequency fB is low, the boost switch Qm is not switched.

[0049] In some embodiments, if the input voltage is less than a certain design reference / threshold Vk, it may be desirable for the ABM burst frequency signal fB to go to zero. Figure 2D 2 shows the operation of the converter 200 when the reference / threshold voltage Vk (207) is non-zero. As described above, if the ABM signal fB (203b, Figure 2C ) is high, the fsw signal 202b is allowed to turn on or off the boost switch Qm at the switching frequency determined by the control loop as described above. This generates the current pulse 206 as described above. Alternatively, if the burst frequency fB is low, the boost switch Qm is not switched.

[0050] Figure 3A An exemplary zero voltage switching (ZVS) active burst mode (ABM) half-bridge boost / PFC converter 300 is shown. The converter 300 receives an AC input voltage, which is passed to a bridge rectifier (composed of diodes D1-D4) via an (optional) EMI filter. The rectified AC input voltage (VDC) appears on a small ZVS capacitor Cz, which can provide the energy required for the ZVS switch, as described below. The rectified AC input voltage (VDC) also appears at the input of a half-bridge boost / PFC converter composed of a boost inductor Lb, a main switch Qm, and an auxiliary switch Qa. The boost / PFC converter can present an output voltage across the output capacitor Co and the load Ro.

[0051] For reference Figure 3B and Figure 4 Understand the operating principle of the ZVS ABM boost / PFC converter 300 . Figure 3B A control signal 302a for the main switch Qm, a control signal 302b for the auxiliary switch 302b, a reference current (iref) waveform 304, and a boost inductor current (IL) waveform 306a / 306b are shown. Figure 4 The current through the converter is shown and the ZVS transition is emphasized. When the control signal 302a is high, the main switch Qm ( Figure 4 This results in a linearly increasing boost inductor current 306a. When the boost inductor current IL reaches the reference current (iref) value, the main switch Qm may be turned off. Because the current through the boost inductor Lb cannot change instantaneously, the boost inductor current begins to flow to the output through the intrinsic body diode of the auxiliary switch Qa, as shown in FIG. Figure 4 Then, after a short suitable delay time (Tdead), the auxiliary switch Qa can be turned on under zero voltage switching (ZVS) conditions, as shown in box (c) of FIG. Figure 4 As shown in the box (d) of . Turning on Qa reduces the voltage drop across the auxiliary switch Qa, thereby improving efficiency, and switching Qa under ZVS conditions also reduces the switching losses associated with this operation. During this interval, the boost inductor current I can be linearly reduced (306b). The auxiliary switch Qa thus replaces the boost diode Do and can improve the efficiency of the circuit because it can have a lower on-resistance than a conventional diode or even a low forward voltage drop diode (such as a Schottky diode).

[0052] Once the energy stored in the boost inductor Lb has been released to the load, the boost inductor current IL becomes zero and can be reversed / driven negative by the capacitor Cz, as Figure 3B The lower part and Figure 4 As shown in the box (e) of FIG. 1 , the auxiliary switch Qa can be turned off, which can cause the current to flow through the intrinsic body diode of the main switch Qm ( Figure 4 This allows the main switch Qm to be turned on again under zero voltage conditions ( Figure 4 ), which can reduce the switching losses associated with the operation of the main switch Qm.

[0053] Figure 5 A ZVS ABM half-bridge boost / PFC converter 500 is shown. Figure 2A The controller is merged into Figure 3A in the switching topology. Figure 5 include Figure 2A In addition, the converter 500 is as described above with reference to Figures 2A to 4The MOSFET operates as described above, except that a negative ZVS reference current (-iZVS) is provided to comparator 529. Thus, comparator 529 operates as a negative current limit detector rather than a current zero detector. This allows the negative boost inductor current discussed above to flow, thereby allowing ZVS switching of the main switch Qm.

[0054] Figure 6 A flow chart 600 outlining the active burst mode (ABM) control technique for the PFC / boost converter discussed above is depicted. In block 602, the controller may sense the output voltage and the input current. In block 604, the controller may operate the main switch and the auxiliary switch to regulate the output voltage and the input current. In block 606, the input voltage may be sensed. In block 608, the input voltage may be compared to a threshold. As described above, the threshold may be a zero or non-zero value. In block 610, the switching operation (i.e., block 604) may be selectively enabled / disabled in response to the comparison of the input voltage to the threshold.

[0055] Figure 6 The flowchart of can be implemented by any suitable controller, including analog control circuits, digital control circuits (including control circuits using logic gates and similar elements or programmable processors, controllers, microcontrollers, etc.). In some embodiments, the controller can be implemented as a hybrid analog / digital circuit, and in at least some embodiments, can be implemented in an application specific integrated circuit.

[0056] Fig. 7A and Figure 7B An alternative embodiment of a ZVS ABM boost / PFC converter employing a full-bridge switching arrangement to eliminate the need for a separate rectifier stage is shown. Fig. 7A A first embodiment of a bridgeless ZVS ABM boost / PFC converter 700a is shown. In the converter 700a, the AC input voltage can pass through an (optional) EMI filter to the boost inductor LB2. The optionally filtered AC input voltage can be delivered to a full-bridge switch arrangement consisting of switches Q11-Q14 through the boost inductor LB2. Switches Q11-Q14 form two corresponding phases, each phase including a high-side switch and a low-side switch. In subsequent figures and descriptions, switch Q14 is a phase A high-side switch and is represented as QAH. Similarly, switch Q12 is a phase A low-side switch and is represented as QAL. Switch Q11 is a phase B high-side switch and is represented as QBH. Finally, switch Q13 is a phase B low-side switch and is represented as QBL.

[0057] Switching bridge Q11-Q14 is operable as described below to produce a DC output voltage (Vout) that appears across capacitor CB2, which serves as both a filter capacitor and an energy storage source to achieve zero voltage switching (ZVS) of the switching components, as described in more detail below. Figure 7BA second embodiment of a bridgeless ZVS ABM boost / PFC converter 700b is shown. In converter 700b, boost inductance is provided by separate boost inductors LB3 and LB4 located in each leg of the (optionally filtered) AC input waveform.

[0058] FIG. 8A to FIG. 8D A first control scheme for a bridgeless ZVS ABM boost / PFC converter is shown. FIG. 10A to FIG. 10D A second control scheme for a bridgeless ZVS ABM boost / PFC converter is shown. Referring to the first control scheme, Fig. 8A and Figure 8B shows the switching operation during the positive half cycle of the AC input waveform, and Figure 8C and Fig.8D The switching operation during the negative half cycle of the AC input waveform is shown. Referring to the second control scheme, Fig. 10A and Fig. 10B shows the switching operation during the positive half cycle of the AC input waveform, and Fig. 10C and Fig. 10D The switching operation during the negative half cycle of the AC input waveform is shown.

[0059] Now go to Fig. 8A and Figure 8B , shows the positive half-cycle switching sequence of the first control scheme. During the positive half-cycle of the first switching scheme, switch QBH will remain off, switch QBL will remain on, and switches QAH and QAL will switch alternately to provide the desired output voltage Vout and power factor correction to the input. With the two lower switches QAL and QBL closed, it is possible to Fig. 8A The positive half-cycle switching sequence is started in box (a). Box (a) shows Figure 8B The time period depicted in FIG. 8 starts from zero and extends until time t1. Because both low-side switches QAL and QBL are turned on, current 840a can flow from the AC input through the boost inductor LB, through the on switch QAL, through the on switch QBL, and back to the AC input source. This results in Figure 8B The linear increase (806) of the boost inductor current iLB is depicted in FIG. Figure 8B It can be further seen that the drive signals 802b and 802d of switches QAL and QBL are high during time period (a). In addition, the current (862) through the low-side switch QAL increases linearly, and the output voltage Vout appears on the high-side switch QAH (as shown by voltage waveform 866).

[0060] When the boost inductor current iLB reaches the peak current reference value 807 ( Figure 8B), at time t1, switch QAL may be turned off, thereby starting a time period (b) extending from time t1 until time t2. During period (b), current 840b continues to flow through the boost inductor (iLB), through the intrinsic body diode of switch QAH, through the load (iL), and back to the AC input via switch QBL. Figure 8B As shown, the drive signal 802d of switch QBL remains high during period (b), while all other switch drive signals (802a, 802b and 802c) remain low. The inductor current iLB (806) begins to decrease, which corresponds to a decrease in current through the low-side switch QAL (862) and an increase in current through the high-side switch QAH (waveform 864). The output voltage Vout appears across switch QBH (waveform 867), and the voltage across switch QAH ramps down to zero (waveform 866), while the voltage across switch QAL ramps up to Vout (waveform 868).

[0061] As described above, by time t2, current is established through the intrinsic body diode of switch QAH. This allows switch QAH to achieve zero voltage turn-on at time t3, i.e., the beginning of time period (c). During time period (c), current 840c continues to flow through switch QAH, through the load, and back to the AC input via switch QBL. Therefore, boost inductor LB is released during period (c), as shown by the falling current waveform 806. This ramp-down current also flows through switch QBL (waveform 864). Therefore, during time period (c), there is zero voltage across switches QAH and QBL, where the output voltage appears across switches QAL (waveform 868) and QBH (waveform 867).

[0062] As in the embodiments discussed above, the boost inductor current iLB and the load current iload may be allowed to achieve a slightly negative value 863 driven by the capacitor output Co, thereby indicating the beginning of time period (d), which is a short period of time around time t3. Fig. 8A As shown in box (d) of FIG. 8 , the negative boost inductor current 840c flows from the AC input through the switch QBL (which remains on), through the load, and back to the AC input through the inductor Lb. Figure 8B , during time period (d), drive signal 802d (for switch QBL) remains high, with drive signals 802a (for switch QAH), 802b (for switch QAL), and 802c (for switch QBH) remaining low. (Switch QAH may be turned off at time t3, i.e., the beginning of time period (d).) Boost inductor current iLB remains at its slightly negative value (waveform 806), and the output voltage transitions to appear across switch QAH (waveform 866) and switch QBH (waveform 867), while the voltage across switch QAL transitions from Vout to zero (waveform 868).

[0063] With switch QAH off, the negative boost current 840e flows as shown in time period (e), which extends from time t3 until time t4 when switch QAL is turned on under ZVS conditions. During period (e), the negative boost inductor current 840e flows from the AC source through the turned-on switch QBL, through the intrinsic body diode of switch QAL, through the boost inductor LB, and back to the AC input. The reverse current through the body diode of switch QAL allows QAL to turn on under ZVS conditions at time t4, thereby marking the beginning of time period (f) running from time t4 until time t5 (which corresponds to the start of the switching cycle, i.e., time t0). Once switch QAL is turned on, a positive current 840f flows from the AC input through the boost inductor LB, through switch QAL, and back to the AC input through QBL. Figure 8B The corresponding waveform is shown in .

[0064] Now go to Figure 8C and Fig.8D , shows the negative half-cycle switching sequence of the first control scheme. During the negative half-cycle of the first switching scheme, switch QAH will remain off, switch QAL will remain on, and switches QBH and QBL will alternately switch to provide the desired output voltage Vout and power factor correction to the input. Starting from time t0, time period (a) begins. During time period (a), both high-side switches QAH and QBH are off, with both low-side switches QAL and QBL being on. Fig.8D 802a, 802b, 802c, and 802d are shown in FIG. Thus, negative inductor current 842a flows from the AC source through the on switches QBL and QAL, through inductor LB, and back to the AC input source. This results in an increasingly negative inductor current 806, with a corresponding positive current 862 through switch QBL. The output voltage Vout appears across switches QAH (waveform 866) and QBH (waveform 867).

[0065] At time t1, when the inductor current reaches its peak value 807, switch QBL may turn off, thereby starting a time period (b) extending from time t1 to time t2. During this interval, switch QAL remains on, and switches QAH, QBH, and QBL are all off. Therefore, negative inductor current 842b flows from the AC input through the intrinsic body diode of switch QBH, through the load, through switch QAL, and back to the AC input through boost inductor LB. Fig.8D802a, 802b, 802c, and 802d are shown in FIG. During time period (b), inductor current 806 remains at its negative peak value, but the current transitions from flowing through switch QBL (waveform 862) to flowing through switch QBH (waveform 864). The output voltage continues to appear across switch QAH (waveform 866), but transitions from appearing across switch QBH (waveform 862) to appearing across switch QBL (waveform 869).

[0066] At time t2, since current 842c flows through the intrinsic body diode of switch QBH, switch QBH can be turned on under ZVS conditions. Current 842c will be Figure 8C Current continues to flow as indicated, starting from the AC source, through the now-on switch QBH, through the load, through switch QAL, and back to the AC input via boost inductor LB. During time period (c), switches QBH and QAL are on, with switches QAH and QBL off. Fig.8D The corresponding driving waveforms 802a, 802b, 802c and 802d are shown in FIG. Fig.8D As shown, the inductor current 806 decreases to zero and then decreases to a slightly positive value 863. The output voltage continues to appear across switch QAH (waveform 866) and switch QBL (waveform 869).

[0067] The time period (d) corresponding to a short interval near time t3 shows that the current 842f ( Figure 8C ). The reversed inductor current 842f flows from the AC source through switch QAL, backward through the output load, through switch QBH, and back to the AC input. During time period (d), switches QBH and QAL remain on, and switches QAH and QBL remain off. Fig.8D 802a, 802b, 802c, and 802d are shown in FIG. After time t3, positive current 842e continues to flow through boost inductor Lb and switch QAL, thereby switching from flowing through the output / load to flowing through the intrinsic body diode of switch QBL, thereby returning to the AC input. This allows switch QBL to turn on under ZVS conditions at time t4, thereby then allowing inductor current 842f to reverse again, returning the cycle to time t5, which corresponds to time t0, the beginning of the negative half cycle.

[0068] Fig.9A and Fig. 9B The above reference FIG. 8A to FIG. 8D More specifically, Fig.9A Flowchart 900 is depicted starting with determining whether the AC input waveform is in a positive half cycle or a negative half cycle (block 902). It should be understood that flowchart 900 may include the following steps according to the above description with respect to FIG. Figures 2A to 5The discussion of FIG. 10 is followed by a preliminary step (not shown) to determine whether the switch is enabled or disabled. If the AC input waveform is in a positive half cycle, control passes to block 904 where the phase B high side switch QBH is turned off and the phase B low side switch QBL is turned on. These switches will remain in these positions for the duration of the positive half cycle.

[0069] Then, in box 906, the phase A low side switch QAL phase can be turned on, and the phase A high side switch QAH phase can be turned off. As will be explained in more detail below, the QAL turn-on transition can be a zero voltage switching (ZVS) transition. In any case, the switch configuration causes current to flow through the boost inductor, thereby storing energy therein. Box 908 can monitor the inductor current to determine whether the inductor current has reached its predetermined peak current limit. If not, the switch can be maintained in the appropriate position, causing the inductor current to continue to increase linearly as more energy is stored in the inductor. Otherwise, when it is determined by box 908 that the inductor current has reached its peak value, the phase A low side switch can be turned off, thereby diverting the inductor current to the load.

[0070] In addition to diverting energy to the load, this switch configuration will cause current to flow through the intrinsic body diode of the phase A high side switch QAH, thereby allowing the switch QAH to turn on under ZVS conditions, thereby improving the operating efficiency of the circuit. As energy from the inductor is delivered to the load, the inductor current will continue to decrease linearly, which can be monitored in box 914. As long as the current remains above the predetermined negative current limit, the switch can be maintained in this position. When the inductor current reaches the predetermined negative current limit, as determined in box 914, the phase A high side switch QAH can be turned off (box 916). The phase A high side switch QAL can then be turned on under zero voltage switching conditions, and the cycle can be repeated for the duration of the positive half cycle of the AC input waveform (and as long as the switch remains enabled).

[0071] During the negative cycle of the AC input waveform, control from box 902 is passed to box 905, where the phase A high side switch QAH is turned off and the phase A low side switch QAL is turned on. Then, in box 907, the phase B low side switch QBL is turned on and the phase B high side switch QBH is turned off. As will be explained in more detail below, the QBL turn-on transition may be a zero voltage switch (ZVS) transition. The switch configuration establishes a negative current through the inductor, which stores energy in the inductor. Box 909 may monitor the inductor current to determine whether the inductor current has reached a predetermined inductor current limit. If not, the switch may remain in place, thereby continuing to store energy in the inductor. If yes, control is passed to box 911, where the phase B low side switch QBL is turned off. This begins to transfer energy from the boost inductor to the load, and also establishes a current condition that allows the phase B high side switch QBH to be turned on under zero voltage conditions, thereby improving the operating efficiency of the circuit.

[0072] As the energy stored in the boost inductor is transferred to the load, the (negative) inductor current will continue to decrease. Block 915 may monitor the inductor current, waiting for a current reversal to a slightly positive value. The switch may remain in its configuration until this slightly positive current limit is reached. Once the positive current limit is reached, the phase B high side switch QBH may be turned off (block 917), which establishes the conditions under which the phase B low side switch may be turned on under ZVS conditions. The cycle may repeat for the duration of the negative half cycle of the AC input waveform (and as long as the switch remains enabled).

[0073] Fig. 9B A further simplified flowchart 920 depicting and outlining the same control operation is shown. First, in block 922, a determination may be made as to whether a switch is enabled (e.g., based on the above with respect to Figures 2A to 5 924). If not, then box 922 may continue to test the enabled switch, and when the switch is enabled, box 924 may determine whether the AC input waveform is currently in its negative half cycle or positive half cycle. If in the positive half cycle, control may proceed to box 926, wherein the first phase high side switch may be turned off and the first phase low side switch may be turned on. Control may then be passed to box 928, wherein the second phase high side switch and the second phase low side switch may be alternately switched in critical conduction mode by a negative current limit to achieve zero voltage switching. Alternatively, if it is determined in box 924 that the AC input source is in its negative half cycle, control may be passed to box 927, wherein the second phase high side switch may be turned off and the second phase low side switch may be turned on. Control may then be passed to box 929, wherein the first phase high side switch and the first phase low side switch may be alternately switched in critical conduction mode by a negative current limit to allow zero voltage switching to turn on transition.

[0074] Fig.9A and Fig. 9B The foregoing flow charts may be implemented by any suitable controller, including analog control circuits, digital control circuits (including control circuits using logic gates and similar elements or programmable processors, controllers, microcontrollers, etc.). In some embodiments, the controller may be implemented as a hybrid analog / digital circuit, and in at least some embodiments, may be implemented in an application specific integrated circuit.

[0075] Now go to Fig. 10A and Fig. 10B , shows the positive half-cycle switching sequence of the second control scheme. Fig. 10A In frame (a), starting from time t0, the high-side switches QAH and QBH are turned on, while the low-side switches QAL and QBL are turned off. Fig. 10BThe corresponding drive signals 1002a (QAH), 1002b (QAL), 1002c (QBH), and 1002d (QBL) are shown in FIG. As a result of this switch configuration, a positive inductor current 1040a flows from the AC source through switch QAH, through switch QBH, and back to the AC source. This current is a linearly increasing current, such as Fig. 10B 1006 in FIG. 1007. Waveform 1062 shows the corresponding increase in current through switch QBH. As shown in waveforms 1066-1069, the converter output voltage Vout appears across switches QBH and QAL.

[0076] At time t1, when the inductor current iLB reaches the peak current limit 1007, the switch QBH may turn off. The current 1040b continues to flow through the boost inductor LB. Because QBH is turned off, the current flows through the load and returns to the AC source through the intrinsic body diode of the low-side switch QBL. Fig. 10B , showing all switches except QAH turned off. As shown by waveforms 1062 (switch QBH current) and 1064 (switch QBL current), the inductor current (and now also the load current) transitions from switch QBH to QBL. Similarly, the output voltage transitions from appearing on switch QAL (voltage waveform 1068) and switch QBH (waveform 1067) to appearing on switch QAL (voltage waveform 1068) and switch QBL (waveform 1069).

[0077] The current 1040b flowing through the intrinsic body diode of switch QBL allows switch QBL to turn on under ZVS conditions at time t2. This begins time period (c), where the inductor current 1040c continues to flow through boost inductor LB, through the high-side switch QAH that remains on, through the load, and back to the AC source through the now-on low-side switch QBL. Fig. 10B As shown, during the time period from t2 to t3 (i.e., time period (c)), drive signals 1002a and 1002d are high, corresponding to the turning on of switches QAH and QBL, and drive signals 1002b and 1002c are low, corresponding to the turning off of switches QAL and QBH. During this time period, the energy stored in boost inductor LB is released to the load, as shown by the linearly decreasing inductor current 1006. This includes a corresponding decrease in the current through switch QBL, as shown by waveform 1064. As in time period (b), the output voltage appears across switches QAL and QBL.

[0078] At time t3, the inductor current decreases to the negative current limit 1063, as discussed above. At this point, the current 1040d flows in the reverse direction through the inductor. Thus, the current path is from the AC source through switch QBL (which remains on), through the load (in the opposite direction), through switch QAH, through the boost inductor LB, back to the AC input source. Fig. 10B The corresponding switch drive waveforms 1002a-1002d are shown in FIG. At time t3, the low-side switch QBL may be turned off, causing the negative current 1040e to flow along Fig. 10A Specifically, the current continues to flow from the AC source through the intrinsic body diode of the high-side switch QBH, through the high-side switch QAH (which remains continuously turned on), and back to the AC source through the boost inductor LB. The reverse current flowing through the body diode of the high-side switch QBH allows the switch to turn on under ZVS switching conditions at time t4, thereby starting a time period (f) corresponding to the time period (a) discussed above.

[0079] Now go to Fig. 10C and Fig. 10D , shows the negative half-cycle switching sequence of the second control scheme. During the negative half-cycle of the second switching scheme, starting from time t0, the high-side switches QAH and QBH are turned off, while the low-side switches QAL and QBL are turned on. Fig. 10D 1002a-1002d. As a result of the switch configuration, the inductor current 1042a flows through the low-side switches QBL and QAL from the AC source, thereby returning to the AC source via the boost inductor LB. This results in a linearly increased inductor current iLB (waveform 1006), which stores energy in the inductor. Waveform 1062 shows the corresponding increased current through the low-side switch QBL. As shown in voltage waveforms 1066-1069, during the first time period (a), between time t0 and t1, the output voltage appears on high-side switches QAH and QBH.

[0080] At time t1, when the inductor current iLB reaches the programmed peak limit 1007, the low-side switch QBL may be turned off, thereby starting time period (b). Therefore, current 1042b flows from the AC source through the intrinsic body diode of the high-side switch QBH, through the load, through the low-side switch QAL (which remains on throughout the negative half-cycle), and back to the AC source via the boost inductor LB. In addition, the current changes from flowing through the low-side switch QBL to flowing through the high-side switch QBH, as shown in waveforms 1062 and 1064. Correspondingly, the output voltage changes from appearing on the high-side switches QAH and QBH to appearing on the high-side switch QAH and the low-side switch QBL, as shown in voltage waveforms 1066-1069.

[0081] At time t2, with current 1042b flowing through the intrinsic body diode of the high-side switch QBH, the switch QBH may be turned on under zero voltage conditions, marking the beginning of time period (c). During this time period, current continues to flow from the AC input through the high-side switch QBH, through the load, through the low-side switch QAL, and back to the AC source via the boost inductor LB. Fig. 10D The corresponding drive voltage waveforms 1002a-1002d are shown in FIG. As shown in current waveform 1006, the inductor current iLB decreases, thereby delivering the energy stored in the boost inductor LB to the load. In addition, during this period, the output voltage is maintained on the high-side switch QAH and the low-side switch QBL, as shown in voltage waveforms 1066-1069.

[0082] The boost inductor current iLB continues to decrease until time t3, at which time it reaches the negative (actually positive in this case) current limit 1063. At time t3, current 1042d flows from the AC source through inductor LB, through the low-side switch QAL, which remains on at all times, through the load (in the opposite direction), and back to the AC source via the high-side switch QBH. The high-side switch QBH can now be turned off. Fig. 10D 1002a-1002d are shown in FIG. 1002. At time t3, current begins to transition from high-side switch QBH back to low-side switch QBL, as shown by current waveforms 1062 and 1064. Likewise, the output voltage transitions from appearing on high-side switch QAH and low-side switch QBL to appearing on high-side switches QAH and QBH, as shown by voltage waveforms 1066-1069.

[0083] Turning off switch QBH causes Fig. 10C The current path 1042e is shown. The current 1042e continues to flow through the boost inductor LB, through the low-side switch QAL which remains on at all times, through the intrinsic body diode of the low-side switch QBL, and back to the AC input source. The current through the body diode of switch QBL allows the low-side switch QBL to turn on under ZVS switching conditions at time t4, thereby starting time period (f) corresponding to time period (a) discussed above. Fig. 10D The corresponding waveform is shown in .

[0084] Fig.11A and Fig. 11B The above reference FIG. 10A to FIG. 10D More specifically, Fig.11A A flowchart 1100 is depicted that begins with determining whether the AC input waveform is in a positive half cycle or a negative half cycle (block 1102). It should be understood that the flowchart 1100 may include the following steps according to the above description with respect to FIG. Figures 2A to 51004, where the phase A high side switch QAH is turned on and the phase A low side switch QAL is turned off. These switches will remain in these positions for the duration of the positive half cycle.

[0085] Then, in box 1106, the phase B low side switch QBL can be turned off, and the phase B high side switch QBH can be turned on. As will be explained in more detail below, the QBH turn-on transition can be a zero voltage switching (ZVS) transition. In any case, the switch configuration causes current to flow through the boost inductor, thereby storing energy therein. Box 1108 can monitor the inductor current to determine whether the inductor current has reached its predetermined peak current limit. If not, the switch can be maintained in the appropriate position, causing the inductor current to continue to increase linearly as more energy is stored in the inductor. Otherwise, when it is determined by box 1108 that the inductor current has reached its peak value, the phase B high side switch can be turned off, thereby diverting the inductor current to the load.

[0086] In addition to diverting energy to the load, this switch configuration will cause current to flow through the intrinsic body diode of the phase B low side switch QBL, thereby allowing the switch QBL to be turned on under ZVS conditions, thereby improving the operating efficiency of the circuit. As energy from the inductor is delivered to the load, the inductor current will continue to decrease linearly, which can be monitored in box 1114. As long as the current remains above the predetermined negative current limit, the switch can be kept in this position. When the inductor current reaches the predetermined negative current limit, as determined in box 1114, the phase B low side switch QBH can be turned off (box 1116). Then, the phase B high side switch QBH can be turned on under zero voltage switching conditions, and the cycle can be repeated for the duration of the positive half cycle of the AC input waveform (and as long as the switch remains enabled).

[0087] During the negative cycle of the AC input waveform, control from box 1102 is passed to box 1105, where the phase A high side switch QAH is turned off and the phase A low side switch QAL is turned on. Then, in box 1107, the phase B low side switch QBL is turned on and the phase B high side switch QBH is turned off. As will be explained in more detail below, the QBL turn-on transition may be a zero voltage switch (ZVS) transition. The switch configuration establishes a negative current through the inductor, which stores energy in the inductor. Box 1109 may monitor the inductor current to determine whether the inductor current has reached a predetermined inductor current limit. If not, the switch may remain in place, thereby continuing to store energy in the inductor. If yes, control is passed to box 1111, where the phase B low side switch QBL is turned off. This begins to transfer energy from the boost inductor to the load, and also establishes a current condition that allows the phase B high side switch QBH to be turned on under zero voltage conditions, thereby improving the operating efficiency of the circuit.

[0088] As the energy stored in the boost inductor is transferred to the load, the (negative) inductor current will continue to decrease. Block 1115 may monitor the inductor current, waiting for a current reversal to a slightly positive value. The switch may remain in its configuration until this slightly positive current limit is reached. Once the positive current limit is reached, the phase B high side switch QBH may be turned off (block 1117), which establishes the conditions under which the phase B low side switch QBL may be turned on under ZVS conditions (block 1119). The cycle may be repeated for the duration of the negative half cycle of the AC input waveform (and as long as the switch remains enabled).

[0089] Fig. 11B A further simplified flowchart 1120 depicting and outlining the same control operation is shown. First, in block 1122, a determination may be made as to whether a switch is enabled (e.g., based on the above with respect to Figures 2A to 5 1124). If not, then box 1122 may continue to test the enabled switch, and when the switch is enabled, box 1124 may determine whether the AC input waveform is currently in its negative half cycle or positive half cycle. If in the positive half cycle, control may proceed to box 1126, where the first phase high side switch may be turned on and the first phase low side switch may be turned off. Control may then be passed to box 1128, where the second phase high side switch and the second phase low side switch may be alternately switched in critical conduction mode by a negative current limit to achieve zero voltage switching. Alternatively, if it is determined in box 1124 that the AC input source is in its negative half cycle, control may be passed to box 1127, where the first phase high side switch may be turned off and the first phase low side switch may be turned on. Control may then be passed to box 1129, where the second phase high side switch and the second phase low side switch may be alternately switched in critical conduction mode by a negative current limit to allow zero voltage switching to turn on transition.

[0090] Fig.11A and Fig. 11B The foregoing flow charts may be implemented by any suitable controller, including analog control circuits, digital control circuits (including control circuits using logic gates and similar elements or programmable processors, controllers, microcontrollers, etc.). In some embodiments, the controller may be implemented as a hybrid analog / digital circuit, and in at least some embodiments, may be implemented in an application specific integrated circuit.

[0091] Various features and embodiments related to boost / PFC converters are described above. Such circuits can be used in a variety of applications, but can be particularly advantageous when used in conjunction with computer power supplies, AC-DC converters / adapters (colloquially referred to as chargers or external power blocks) for portable electronic devices, small form factor computers, and the like. In addition, although many specific features and various embodiments have been described, it should be understood that the various features and embodiments may be combined into various arrangements in a particular embodiment unless otherwise specified as mutually exclusive. Therefore, the various embodiments described above are provided by way of example only and should not be construed as limiting the scope of the present disclosure. Various modifications and changes may be made to the principles and embodiments herein without departing from the scope of the present disclosure and without departing from the scope of the claims.

Claims

1. A power converter, comprising: an input terminal configured to receive an AC input voltage; a rectifier configured to convert the AC input voltage into a rectified AC input voltage; a boost converter configured to receive the rectified AC input voltage and deliver a regulated output voltage; and a control circuit coupled to the boost converter and configured to: monitoring the regulated output voltage, an input current of the boost converter, and the rectified AC input voltage; switching at least one switching device of the boost converter to deliver the regulated output voltage while maintaining the input current in phase with the rectified AC input voltage; as well as A switch of the boost converter is selectively enabled in response to determining that the rectified AC input voltage is greater than a threshold voltage, and a switch of the boost converter is selectively disabled in response to determining that the rectified AC input voltage is less than the threshold voltage, wherein the threshold voltage is zero or non-zero.

2. The power converter of claim 1 , wherein the boost converter comprises: a boost inductor having a first terminal coupled to the rectified AC input voltage; a boost switching device coupled between a second terminal of the boost inductor and ground; and A boost rectifier has a first terminal coupled to the second terminal of the boost inductor and a second terminal coupled to an output of the boost converter. 3 . The power converter of claim 2 , wherein the boost rectifier is a rectifier switching device that switches complementarily to the boost switching device. 4 . The power converter of claim 3 , wherein the rectifier switching device is switched complementarily to the boost switching device with a dead time. The power converter of claim 1 , wherein the threshold voltage is zero. 6 . The power converter of claim 1 , wherein the control circuit is configured to selectively enable and disable switching of the boost converter using an active burst mode signal having a frequency lower than a switching frequency of the boost converter. 7 . The power converter of claim 6 , wherein the active burst mode signal is zero if the rectified AC input voltage is below the threshold voltage. 8 . The power converter of claim 1 , wherein the control circuit is configured to operate at least one switching device of the boost converter under a zero voltage switching condition.

9. The power converter according to claim 8 further includes a zero voltage switching capacitor coupled to the boost converter, wherein the control circuit is configured to control the timing of at least one switching device of the boost converter to allow reverse current to pass through the at least one switching device before the at least one switching device is turned on, thereby allowing zero voltage switching of the at least one switching device.

10. An AC / DC converter circuit comprising: a first phase, the first phase comprising a first high-side switch having a first terminal coupled to a DC output terminal of a converter and a second terminal coupled to a first AC input terminal of the converter, and a first low-side switch having a first terminal coupled to the second terminal of the first high-side switch and a second terminal coupled to ground; a second phase, the second phase comprising a second high-side switch having a first terminal coupled to the DC output terminal of the converter and a second terminal coupled to a second AC input terminal of the converter, and a second low-side switch having a first terminal coupled to the second terminal of the second high-side switch and a second terminal coupled to ground; and at least one inductor coupled between at least one of the first AC input terminal and the second AC input terminal and an AC input source; and a controller configured to operate a first switching phase and a second switching phase according to a first switching sequence during a positive half cycle of an AC input voltage, and to operate the first switching phase and the second switching phase according to a second switching sequence during a negative half cycle of the AC input voltage; The controller is further configured to selectively enable switches of the first switch phase and the second switch phase in response to determining that the instantaneous value of the AC input voltage is greater than a threshold voltage, and selectively disable switches of the first switch phase and the second switch phase in response to determining that the instantaneous value of the AC input voltage is less than the threshold voltage, wherein the threshold voltage is zero or non-zero.

11. The AC / DC converter circuit of claim 10, wherein the at least one inductor comprises a first inductor coupled between the first AC input terminal and the AC input source, and a second inductor coupled between the second AC input terminal and the AC input source.

12. The AC / DC converter circuit of claim 10 , wherein the first switching sequence during the negative half cycle of the AC input voltage comprises: turning off the first high-side switch of the first phase; turning on the first low-side switch of the first phase; as well as The second high-side switch and the second low-side switch of the second phase are switched in a critical conduction mode by a negative current limit, thereby achieving zero voltage switching of the second high-side switch and the second low-side switch of the second phase.

13. The AC / DC converter circuit of claim 10, wherein the second switching sequence during a positive half cycle of the AC input voltage comprises: turning off the second high-side switch of the second phase; turning on the second low-side switch of the second phase; as well as The first high-side switch and the first low-side switch of the first phase are switched in a critical conduction mode by a negative current limit, thereby achieving zero voltage switching of the first high-side switch and the first low-side switch of the first phase.

14. The AC / DC converter circuit of claim 10, wherein the first switching sequence during the positive half cycle of the AC input voltage comprises: turning on the first high-side switch of the first phase; turning off the first low-side switch of the first phase; as well as The second high-side switch and the second low-side switch of the second phase are switched in a critical conduction mode by a negative current limit, thereby achieving zero voltage switching of the second high-side switch and the second low-side switch of the second phase.

15. The AC / DC converter circuit of claim 10, wherein the second switching sequence during the negative half cycle of the AC input voltage comprises: turning off the first high-side switch of the first phase; turning on the first low-side switch of the first phase; as well as The second high-side switch and the second low-side switch of the second phase are switched in a critical conduction mode by a negative current limit, thereby achieving zero voltage switching of the second high-side switch and the second low-side switch of the second phase.

16. A method of operating an AC / DC converter, the method comprising: monitoring a regulated output voltage, an input current, and an input voltage of the converter; selectively switching at least one switching device to deliver the regulated output voltage while maintaining the input current in phase with the input voltage; as well as Switching of the at least one switching device is selectively enabled in response to determining that the input voltage is greater than a threshold voltage, and switching of the at least one switching device is selectively disabled in response to determining that the input voltage is less than the threshold voltage, wherein the threshold voltage is zero or non-zero. The method of claim 16 , wherein the threshold voltage is zero. 18 . The method of claim 16 , wherein selectively enabling and selectively disabling switching of the at least one switching device comprises using an active burst mode signal having a frequency lower than a switching frequency of the converter.

19. The method of claim 16, wherein selectively switching at least one switching device comprises switching the at least one switching device under a zero voltage switching condition.

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