Dual-channel synchronous reload pulse generation method

Abstract

The present invention discloses a dual-channel synchronous reload pulse generation method, comprising three parts: a clock generation module, a synchronous reload counting module and a signal edge trigger module. The steps of the generation method are as follows: 1) the clock generation module generates two counting clock signals and a synchronous loading signal with similar frequencies; 2) the counting clock and the synchronous loading signal are output to the synchronous reload counting module; 3) when the count value of the synchronous reload counting module meets the conditions, an indication signal is output to the signal edge trigger module to generate a pulse signal of the required width, thereby realizing the FPGA direct output of the nanosecond pulse signal. In the above manner, the present invention directly generates nanosecond transient pulses by logically operating the indication signal through the cursor effect generated between the two channels. On this basis, the pulse width modulation with nanosecond precision can also be realized by changing the count value.

Description

Technical Field

[0001] The invention relates to the fields of industrial control and optoelectronic communication, and in particular to a dual-channel synchronous reload pulse generation method. Background Art

[0002] As the foundation of modern electronic technology, high-speed pulse signals are widely used in electronic communications, industrial control, acquisition and measurement. With the continuous development of information science, in order to make electronic devices more versatile and flexible, narrower pulse widths and high-precision pulse width modulation are important development directions for the generation of high-speed pulse signals.

[0003] In the early 20th century, humans had already begun to use string vibration to generate pulse signals of a certain frequency. Subsequently, people used gas and spark discharge methods to reduce the pulse width from milliseconds to microseconds. However, the development cost is high and the design process is complicated, so it is rarely used anymore.

[0004] Since the 1970s, the original analog signal processing has been replaced by digital signal processing, and the method of using integrated logic gate circuits to control the generation of pulse signals has been applied [6]. With the continuous development of computer technology, programmable real-time pulse generation circuits have become mainstream. Devices such as single-chip microcomputers and microcontrollers have the advantages of low cost and small size. Using clock signals to control their input and output ports to generate pulses has become a common method. However, since the clock frequency of such devices is generally low, the accuracy is relatively low. In addition, they are limited by peripheral analog circuits, have poor control flexibility and weak anti-interference ability. Programmable logic devices such as FPGAs have incomparable advantages in the field of pulse signal generation due to their high flexibility, good real-time performance, and efficient data processing. They have achieved nanosecond-level precision pulse generation and pulse width modulation, meeting most measurement and control needs. However, further reducing the pulse width requires a very high operating frequency, which is generally difficult for general-purpose FPGAs to meet. Although the method of building semiconductor transistor circuits can achieve extremely narrow pulse signals, it is difficult to achieve pulse width modulation due to circuit design and is difficult to use. The edge compression technology based on nonlinear transmission lines can greatly compress the transition time of the pulse signal edge to generate a picosecond pulse signal through the setting of transmission materials, technical processes and parameters. However, the nonlinear transmission line technology has not been made public and has a technical monopoly. In addition, the technology of using polarization gating technology to generate pulses with higher resolution has just started, the design is very complex, and the generated pulse width is difficult to control and use. It is currently a cutting-edge topic. Summary of the invention

[0005] The purpose of the present invention is to provide a dual-channel synchronous reload pulse generation method, which directly generates nanosecond transient pulses by logical operation of indication signals through the cursor effect generated between the two channels. On this basis, pulse width modulation with nanosecond accuracy can also be achieved by changing the count value.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a dual-channel synchronous reload pulse generation method, including a clock generation module, a synchronous reload counting module and a signal edge trigger module. The steps of the generation method are as follows:

[0007] 1) The clock generation module generates two counting clock signals and a synchronous loading signal with similar frequencies;

[0008] 2) Outputting the above counting clock and synchronous loading signal to the synchronous reloading counting module;

[0009] 3) When the count value of the synchronous reload counting module meets the conditions, the output indication signal is given to the signal edge trigger module to generate a pulse signal of the required width, thus realizing the FPGA direct output of nanosecond pulse signals.

[0010] Furthermore, in step 1), the clock generation module generates two clock signals CLK A and CLKB with similar frequencies and a load signal LOAD of 1 MHz.

[0011] Furthermore, the synchronous reloading counting module in step 2) includes a first channel Reloader_A and a second channel Reloader_B, and the first channel Reloader_A and the second channel Reloader_B count their respective input clock pulses, and the count values ​​are the input A_Value and B_Value respectively.

[0012] Furthermore, the clock signal CLK A is used as a counting clock of the first channel Reloader_A of the synchronous reloader counting part; and the clock signal CLK B is used as a counting clock of the second channel Reloader_B.

[0013] Furthermore, when the rising edge of the load signal LOAD clock signal arrives, A_Value and B_Value will be synchronously loaded into the two counting channels again, and the next round of counting will start again.

[0014] Furthermore, each time the count value reaches the loaded count value A_Value or B_Value, the corresponding counting channel will generate an indication signal Signal. The indication signal generated by the first channel Reloader_A is a SET signal, and the indication signal generated by the second channel Reloader_B is a RESET signal. Due to the different counting clock frequencies, there will be a phase difference in the generation time of the rising edges of the generated SET and RESET signals. The rising edges of the SET signal and the RESET signal trigger the output signal level to flip, generating a transient pulse signal with adjustable pulse width.

[0015] Furthermore, the LOAD signal continuously reloads the count values ​​of the two channels synchronously, and this pulse signal continuously appears at a certain frequency to achieve pulse generation.

[0016] Furthermore, the clock generation module uses a single phase-locked loop, and the optimal clock signal combination generated is 48 MHz and 50 MHz.

[0017] Furthermore, the reload counting module is designed as a state machine using a register state, and the state of the state machine is controlled by the input RELOAD signal and the count value cnt.

[0018] Furthermore, the signal edge trigger module is composed of a basic logic gate and a latch, and the latch latches the signal state and the output signal q.state as a state quantity, representing the current state of the RESET signal.

[0019] The beneficial effects of the present invention are as follows: a dual-channel synchronous reload pulse generation method of the present invention can use a dual-channel synchronous reload counting module to count clock signals with similar frequencies and generate indication signals under a limited FPGA operating frequency, and can ultimately achieve a nanosecond pulse resolution of 0.833ns. Compared with other design methods with adjustable pulse width, the minimum pulse width is narrower and the pulse width adjustment resolution is higher. Compared with the dual-NOT gate structure design that utilizes the component competition hazard phenomenon, the design is more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a flow chart of a dual-channel synchronous reload pulse generation method of the present invention;

[0022] Figure 2 It is a timing diagram of a dual-channel synchronous reload pulse generation of the present invention;

[0023] Figure 3 It is an RTL view of a dual-channel synchronous reload pulse generation method of the present invention;

[0024] Figure 4 It is a structure diagram of an FPGA chip PLL of a dual-channel synchronous reload pulse generation method of the present invention;

[0025] Figure 5 It is an RTL view of a synchronous reloading module of a dual-channel synchronous reloading pulse generation method of the present invention;

[0026] Figure 6 It is a working timing diagram of a synchronous reloading module of a dual-channel synchronous reloading pulse generation method of the present invention;

[0027] Figure 7 It is a signal edge trigger module RTL view of a dual-channel synchronous reload pulse generation method of the present invention;

[0028] Figure 8 It is the Modelsim minimum resolution simulation waveform of a dual-channel synchronous reload pulse generation method of the present invention;

[0029] Fig. 9 It is a ModelSim functional simulation waveform of a dual-channel synchronous reload pulse generation method of the present invention;

[0030] Fig.10 It is a 0.833ns pulse signal waveform of a dual-channel synchronous reload pulse generation method of the present invention;

[0031] Fig.11 The invention discloses a 4.998ns pulse signal waveform of a dual-channel synchronous reload pulse generation method. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the present invention clearer, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in the accompanying drawings and described according to the accompanying drawings are merely exemplary, and the present invention is not limited to these embodiments.

[0033] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0034] Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0035] See also Figures 1 to 10 The embodiment of the present invention includes: a dual-channel synchronous reload pulse generation method, including a clock generation module, a synchronous reload counting module and a signal edge trigger module. The steps of the generation method are as follows:

[0036] 1) The clock generation module generates two counting clock signals and a synchronous loading signal with similar frequencies;

[0037] 2) Outputting the above counting clock and synchronous loading signal to the synchronous reloading counting module;

[0038] 3) When the count value of the synchronous reload counting module meets the conditions, the output indication signal is given to the signal edge trigger module to generate a pulse signal of the required width, thus realizing the FPGA direct output of nanosecond pulse signals.

[0039] Furthermore, in step 1), the clock generation module generates two clock signals CLK A and CLKB with similar frequencies and a load signal LOAD of 1 MHz.

[0040] Furthermore, the synchronous reloading counting module in step 2) includes a first channel Reloader_A and a second channel Reloader_B, and the first channel Reloader_A and the second channel Reloader_B count their respective input clock pulses, and the count values ​​are the input A_Value and B_Value respectively.

[0041] Furthermore, the clock signal CLK A is used as a counting clock of the first channel Reloader_A of the synchronous reloader counting part; and the clock signal CLK B is used as a counting clock of the second channel Reloader_B.

[0042] Furthermore, when the rising edge of the load signal LOAD clock signal arrives, A_Value and B_Value will be synchronously loaded into the two counting channels again, and the next round of counting will start again.

[0043] Furthermore, each time the count value reaches the loaded count value A_Value or B_Value, the corresponding counting channel will generate an indication signal Signal. The indication signal generated by the first channel Reloader_A is a SET signal, and the indication signal generated by the second channel Reloader_B is a RESET signal. Due to the different counting clock frequencies, there will be a phase difference in the generation time of the rising edges of the generated SET and RESET signals. The rising edges of the SET signal and the RESET signal trigger the output signal level to flip, generating a transient pulse signal with adjustable pulse width.

[0044] Furthermore, the LOAD signal continuously reloads the count values ​​of the two channels synchronously, and this pulse signal continuously appears at a certain frequency to achieve pulse generation.

[0045] Furthermore, the clock generation module uses a single phase-locked loop, and the optimal clock signal combination generated is 48 MHz and 50 MHz.

[0046] Furthermore, the reload counting module is designed as a state machine using a register state, and the state of the state machine is controlled by the input RELOAD signal and the count value cnt.

[0047] Furthermore, the signal edge trigger module is composed of a basic logic gate and a latch, and the latch latches the signal state and the output signal q.state as a state quantity, representing the current state of the RESET signal.

[0048] In view of the problems existing in the pulse signal generation method of current FPGA design, this paper proposes a dual-channel synchronous reload pulse generation method, and designs a nanosecond transient pulse generation system based on this method. The system uses a dual-channel structure to generate an indication signal output for the rising edge of a clock signal with a similar frequency, and uses the cursor effect generated between the two channels to directly generate nanosecond transient pulses for the indication signal logic operation. On this basis, it can also achieve nanosecond-level precision pulse width modulation by changing the count value.

[0049] The dual-channel synchronous reload pulse generation method of the present invention, the current general FPGA maximum operating frequency is usually below 500MHz, which cannot meet the requirements of directly generating nanosecond transient pulses. This paper designs a dual-channel synchronous reload pulse generation method, which includes three parts: clock generation (Clock Generator), synchronous reload counting (Reloader_A, Reloader_B) and signal edge trigger (Signal edge Trigger). The clock generation part mainly generates two clock signals with similar frequencies and a loading signal. The synchronous reload counting part is a control module composed of two counting channels that can be loaded with count values ​​synchronously by the loading signal. Each channel counts its own clock signal and generates an indication signal. The two generated indication signals are triggered by the signal edge to achieve output level flipping to generate narrow pulses with nanosecond accuracy.

[0050] like Figure 1 As shown, the dual-channel synchronous reload pulse generation method first generates two clock signals CLK A and CLK B with similar frequencies and a 1MHz loading signal LOAD. CLK A has a higher frequency and serves as the counting clock of the first channel Reloader_A of the synchronous reload counting part. CLK B has a slightly lower frequency and serves as the counting clock of the second channel Reloader_B. The two channels count their respective input clock pulses, and the count values ​​are the input A_Value and B_Value respectively. Whenever the rising edge of the LOAD clock signal arrives, A_Value and B_Value will be synchronously loaded into the two counting channels again, and the next round of counting will start again. Every time the count value reaches the loaded count value A_Value or B_Value, the corresponding counting channel will generate an indication signal Signal. The indication signal generated by channel Reloader_A is the SET signal, and the indication signal generated by channel Reloader_B is the RESET signal. Due to the different counting clock frequencies, there will be a phase difference in the generation time of the rising edges of the generated SET and RESET signals. The rising edges of the SET signal and the RESET signal trigger the output signal level to flip, and a transient pulse signal with adjustable pulse width can be generated. The LOAD signal continuously reloads the count values ​​of the two channels synchronously, and this pulse signal will appear continuously at a certain frequency to achieve pulse generation. Figure 2 shown.

[0051] When the rising edge of the generated load signal LOAD arrives, the count values ​​A_Value and B_Value will be synchronously loaded into the two channels. The two channels use CLK_A and CLK_B for counting respectively. The count value decreases by 1 at the rising edge of each clock signal. When the count value becomes 0, the two channels output SET and RESET signals respectively. The rising edge of the SET signal sets the output OUT to 1, and the rising edge of the RESET signal sets the output OUT to 0, generating a transient pulse signal. When the next rising edge of the LOAD signal arrives, the synchronous reloading of the dual-channel count values ​​is realized, and the pulse signal generation process is repeated.

[0052] The width of the generated pulse signal is related to the input count value (A_Value, B_Value) and the frequency of the input clock (CLK A, CLKB). The frequency of the input clock determines the minimum resolution of the pulse signal width. Taking 48MHz and 50MHz as examples, the time required for a 48MHz clock count is 1 / 48MHz, and the time required for a 50MHz clock count is 1 / 50MHz. Through the above analysis, the time difference between the two channels is the minimum resolution of the output. The minimum resolution can be calculated as:

[0053]

[0054] That is, the minimum pulse width generated is 0.833ns.

[0055] The pulse width W generated by changing the count value is calculated as follows:

[0056]

[0057] According to the pulse width calculation formula, the pulse width corresponding to each value of A_Value and B_Value is shown in Table 1.

[0058] Table 1 Relationship between pulse width and A_Value, B_Value (unit: ns)

[0059]

[0060] When A_Value and B_Value are both 0, the pulse width is 0 and no pulse signal is generated; when A_Value=B_Value, the generated pulse width is A_Value (or B_Value) × 0.833ns; in other value cases, if the clock frequency is 50MHz and 48MHz, and the initial value loading signal is 1MHz, in order for the module to generate an indication signal before the next initial value reloading, the maximum count values ​​of B_Value and A_Value are 49 and 47 respectively. When A_Value takes the maximum value of 49 and B_Value takes the maximum value of 47, the maximum pulse width can be generated, which is 999.151ns.

[0061] The transient pulse generation method based on dual-channel synchronous reloading of the present invention is a nanosecond transient pulse generation system, and the RTL view of the system is as follows: Figure 3 As shown in the figure, the system can be divided into a clock generation module, a synchronous reload module and a signal edge trigger module. The following article will describe the design of these three important modules in detail.

[0062] As the basis of sequential circuits, clock is very important in the entire FPGA program development process. Direct digital frequency synthesis (DDS) technology can generate clock signals of any frequency, and multiple phase-locked loops (PLLs) can also generate any clock signal combination within the FPGA operating frequency. However, the dual-channel synchronous reload pulse generation method proposed in this paper has extremely high requirements for the phase synchronization of the generated clock, and the above methods cannot guarantee that the initial phase of the signal is exactly the same. In order to make the phase of the clock signal equal and the frequency stable, the clock generation module of the dual-channel synchronous reload pulse generation method is designed using a single phase-locked loop. Since the multi-channel clock generated by a single phase-locked loop will be restricted by the internal structure of the FPGA, the generated clock frequency needs to be carefully designed. After many tests, the best clock signal combination generated is 48MHz and 50MHz.

[0063] like Figure 4 As shown in the figure, the phase-locked loop is a closed-loop frequency control system. The nanosecond pulse generator designed in this paper uses Altera's FPGA chip, and the parameters of the PLL can be set through the IP core. First, the 50MHz clock generated by the external crystal oscillator is sent to the phase detector through the pre-dividing counter (N=25) to generate a 2MHz clock. The phase detector compares the feedback signal with the input clock and sends a control signal to drive the voltage-controlled oscillator through the loop filter to adjust the output clock frequency until the two signals are synchronized. When the feedback counter M in the feedback loop is 24, the system reaches stability when the output clock is 48MHz, which is equivalent to dividing 50MHz by 25 and multiplying it by 24 to output a 48MH clock signal.

[0064] The 50MHz and 48MHz clocks generated by the clock generation module will be used as the working clocks of the dual-channel synchronous reload counting module.

[0065] The dual-channel synchronous reload counting module consists of two reload counting modules, which plays a core control role in the design of this transient pulse generation circuit. In order to generate a pulse signal with a stable frequency, the indication signals output by the two channel modules must be able to appear synchronously and stably at a certain period, and the indication signal output is directly controlled by the pulse count value. Therefore, whether the two channel count values ​​can be synchronously reloaded will have a significant impact on the generated pulse signal.

[0066] In order to realize the periodic synchronous reloading of the count value, this paper gives a design method for a reload counting module. Its RTL view is shown in Figure 5. The reload counting module is designed with register state as the state machine. The state of the state machine is controlled by the input RELOAD signal and the count value cnt. The initial state machine working state is 0, and the output Signal signal selected by Selector12 is 0. Each bit of the value of the eight-bit counting register cnt is controlled by the selector to be a fixed value and remains unchanged, waiting for the load signal to load the count value. When the rising edge of the RELOAD signal arrives, the state machine working state becomes 1. After the register cnt is assigned the initial value, it counts down on the rising edge of the CLK signal. When the comparator counts to 0, the output of the comparator changes, so that the selector Selector12 outputs 1 to change the indication signal Signal to a high level, and the state machine working state changes to 2. Working state 2 maintains a CLK clock cycle, and enters state 3 after the indication signal is pulled low. When the falling edge of the LOAD signal is detected, state 3 returns to state 0 and waits for the next load signal, avoiding the cnt register from being reloaded multiple times in a load signal.

[0067] The working sequence diagram of the reloading module in this design is as follows Figure 6 As shown in the figure, the rising edge of the LOAD signal triggers the loading of the count value Value to start counting. When each rising edge of the CLK clock signal arrives, the value of the register decreases by 1. When the value in the register decreases by 1 and becomes 0, the counting is completed, and the indication signal is output. After one clock cycle, it waits for the next loading. When the next rising edge of the LOAD signal arrives, the Value value is reloaded and counting starts again, generating a stable indication signal at a certain period.

[0068] When the counting clock signals of the two reload counting modules have the same initial phase and use the same LOAD signal to reload the count value, a dual-channel synchronous reload counting module is formed. The two indication signals Signal generated by the dual-channel synchronous reload module are generated through the signal edge trigger module to generate corresponding transient pulse signals.

[0069] The function of the signal edge trigger module is to output a transient pulse signal. Depending on the pre-designed values ​​of the synchronous reload counting module, the phase difference of the generated indication signal is also different. To realize the pulse signal of any width in Table 1, the signal edge trigger module must be strictly required to realize that the output signal becomes a high level at the rising edge of the input signal SET, and the output signal becomes a low level at the rising edge of RESET. When the output indication signals of the two-channel synchronous reload counter, that is, the rising edges of the SET and RESET signals, are very close, the high and low levels of the output signal can be flipped in a very short time to generate an extremely narrow transient pulse signal. This article provides a feasible design method. The RTL view is as follows: Figure 7 shown.

[0070] The circuit is actually composed of basic logic gates and latches. The latch latches the signal state and the output signal q respectively. state is a state quantity, which represents the current state of the RESET signal. When state is 1, it means that the rising edge of the RESET signal has arrived and RESET still maintains a high level; when state is 0, it means that the RESET signal is a low level. state only changes when the RESET signal state changes, otherwise it is latched by the latch. The initial states of the SET and RESET signals are both low levels. At this time, the state and output q states are both 0. As long as the rising edge of the RESET signal arrives, the latch reset pin ACLR of the output q will be enabled, the q value will be cleared, and then state will be set to 1. When the rising edge of the SET signal arrives, as long as the rising edge of the RESET signal does not appear at the same time, after logical operation, the PRESET of the q latch can always become a high level output 1.

[0071] The truth table of the signal edge trigger module designed by the present invention is shown in Table 2.

[0072] Table 2 Signal edge trigger module truth table

[0073] SET 0 0 0 0 ↑ ↑ ↑ ↑ 1 1 1 1 ↓ ↓ ↓ ↓ RESET 0 ↑ 1 ↓ 0 ↑ 1 ↓ 0 ↑ 1 ↓ 0 ↑ 1 ↓ q Keep 0 Keep Keep 1 0 1 1 Keep 0 Keep Keep Keep 0 Keep Keep

[0074] As shown in the signal edge trigger module truth table, the SET signal is low level. Only when the RESET signal reaches the rising edge, the output signal is 0. In other states, the output remains unchanged. At the rising edge of SET, only the RESET signal also outputs 0 for the rising edge module, and the rest of the states are all 1. When the SET signal is at a high level or falling edge state, only the rising edge of the RESET signal triggers 0 output, and the output remains unchanged in other states. It can be seen from the truth table that only the rising edge of the input signals SET and RESET can trigger the output state to change. The rising edge of SET makes the output signal 1, and the rising edge of RESET makes the output signal 0. When the rising edges of SET and RESET arrive together, the output signal state becomes 0.

[0075] Through the design of the above functional modules, nanosecond pulse generation is achieved. The pulse generator first generates two clock signals with similar frequencies of 50MHz and 48MHz from the clock generation module, which are used as the working clocks of the synchronous reloading modules Reloader_A and Reloader_B respectively. Reloader_A and Reloader_B generate indication signals Signal_A and Signal_B respectively. If the count value A_Value=B_Value=1, Reloader_A and Reloader_B will both output indication signals after one working cycle. Due to the different working frequencies, the frequency of CLK_A is higher, so the rising edge of Signal_A will arrive before Signal_B, and the time difference between the two is 0.833ns.

[0076] Input Signal_A and Signal_B into the signal edge trigger module, Signal_A as SET, Signal_B as RESET. The signal edge trigger module will trigger the output change only on the rising edge of the signal. When the rising edge of Signal_A arrives, the output signal becomes 1. After 0.833ns, the rising edge of the Signal_B signal sets the output signal to 0, thus generating a narrow pulse signal with a width of 0.833ns.

[0077] The present invention uses Modelsim software to perform functional simulation. In order to test the minimum accuracy of the pulse width, the count value of the synchronous reload module is set to 1, and a 50MHz square wave is used as the input clock. The experimental results are shown in Figure 2. Figure 8 As shown. When the initial count values ​​of the dual-channel synchronous reload counting module are all 1, the generated pulse width should be the minimum pulse width that can be generated by the dual-channel synchronous reload pulse generation method, which is also the minimum resolution of pulse width adjustment. According to the pulse width calculation formula, the generated pulse width should be 0.833ns, which is the same as the Modelsim simulation result, and the minimum resolution simulation is correct.

[0078] When the count values ​​are all set to 6, the simulation waveform is as follows Fig. 9 As shown, the pulse width value calculated using the Modelsim ruler is 4.998ns. According to the pulse width calculation formula, when the initial count value is 6, the output pulse width should be 4.998ns. The results are completely consistent, and the experimental pulse width modulation functional verification results are correct.

[0079] Next, we use an oscilloscope to test the pulse signal actually generated by the FPGA. The FPGA uses Altera's EP4CE15F23C8 chip. The oscilloscope model is Yokogawa DL9240, with an analog bandwidth of 1.5GHz and a maximum real-time sampling rate of 10GSa / s. Fig.10 and Fig.11 The signal waveforms are set to 0.833ns and 4.998ns respectively, and each grid represents 5ns. By measuring the effective width of the pulse signal, the actual pulse signal shown in the figure is consistent with the set value. The results of the oscilloscope show that the pulse generator achieves nanosecond pulse signal generation and pulse width modulation.

[0080] Through the analysis of the above experimental data, the performance of the dual-channel synchronous reloaded pulse generation method and other narrow pulse generation methods are shown in Table 3.

[0081] Table 3 Pulse parameters generated by dual-channel synchronous reload pulse generation method and other methods

[0082]

[0083] The direct counting method uses the internal phase-locked loop of the FPGA to multiply the frequency of the external crystal oscillator and use it as the counting clock for counting. Generating a pulse signal with a resolution of 1ns requires a stable operating frequency of at least 1GHz, which is obviously difficult for a general-purpose FPGA to meet. The pulse encoding and decoding method uses the fact that the pulse signal has only two states, 1 and 0, to cut the pulse signal into time slices, and the pulse state of each time slice is represented by a binary number. The corresponding pulse signal can be generated by sending the binary sequence data to the FPGA through the host computer. However, the minimum time slice accuracy of the encoding and decoding is restricted by the operating frequency of the FPGA itself, making it difficult to achieve higher resolution.

[0084] In addition, the dual triode parallel circuit uses the LC circuit damping principle and the avalanche effect produced by the dual RF triodes in parallel to generate a pulse signal with a large amplitude, but the pulse width is also large. The dual NOT gate structure design that uses the competitive risk of digital logic devices to achieve narrow pulse generation generates an extremely narrow pulse signal, but its pulse width is restricted by the circuit design and cannot be adjusted.

[0085] The direct counting method and pulse encoding and decoding generation method improve the minimum resolution by increasing the operating frequency of the FPGA itself. The operating frequency of a common FPGA is generally within 500MHz, and the minimum resolution of pulse width modulation will not be less than 2ns. Different from its principle, the dual-channel synchronous reload pulse generation method designed in this paper uses a dual-channel synchronous reload counting module to count the 48MHz and 50MHz clock signals with similar frequencies and generate indication signals under the limited FPGA operating frequency. There will be a phase difference between the indication signals of the two channels due to the vernier effect. The equivalent operating frequency of the narrow pulse generated by the phase difference can reach more than 1GHz, regardless of the maximum operating frequency of the FPGA itself, so it can eventually achieve a nanosecond pulse resolution of 0.833ns. In addition, the 0.833ns minimum pulse width of the dual-channel synchronous reload pulse generation method still has a significant advantage over the dual triode parallel circuit design with an unadjustable pulse width. The dual NOT gate structure design can generate a narrow pulse signal with a minimum pulse width of 0.15ns, but after the circuit design is completed, the pulse width cannot be adjusted, making it difficult to apply. The method in this paper not only realizes the generation of narrow pulse signal of 0.833ns, but also realizes the pulse width regulation accuracy of 0.833ns.

[0086] In addition, it should be noted that in this specification, "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0087] It should be understood that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A dual-channel synchronous reload pulse generation method, characterized in that: It includes three parts: clock generation module, synchronous reload counting module and signal edge trigger module. The steps of the generation method are as follows: 1) The clock generation module generates two counting clock signals and a synchronous loading signal with similar frequencies; 2) outputting the above counting clock and synchronous loading signal to the synchronous reloading counting module; 3) When the count value of the synchronous reload counting module meets the conditions, the output indication signal is given to the signal edge trigger module to generate a pulse signal of the required width, thus realizing the FPGA direct output of nanosecond pulse signals; The clock generation module generates two clock signals CLK A and CLK B with similar frequencies and a 1MHz load signal LOAD. The synchronous reload counting module includes a first channel Reloader_A and a second channel Reloader_B. The first channel Reloader_A and the second channel Reloader_B count their respective input clock pulses, and the count values ​​are the input A_Value and B_Value respectively.

2. The dual-channel synchronous reload pulse generation method according to claim 1, characterized in that: The clock signal CLK A is used as a counting clock of the first channel Reloader_A of the synchronous reloader counting part; and the clock signal CLK B is used as a counting clock of the second channel Reloader_B.

3. The dual-channel synchronous reload pulse generation method according to claim 1, characterized in that: When the rising edge of the load signal LOAD clock signal arrives, A_Value and B_Value will be synchronously loaded into the two counting channels again, and the next round of counting will start again.

4. The dual-channel synchronous reload pulse generation method according to claim 3, characterized in that: Each time the count value reaches the loaded count value A_Value or B_Value, the corresponding counting channel will generate an indication signal Signal. The indication signal generated by the first channel Reloader_A is the SET signal, and the indication signal generated by the second channel Reloader_B is the RESET signal. Due to the different counting clock frequencies, there will be a phase difference between the rising edges of the generated SET and RESET signals. The rising edges of the SET signal and the RESET signal trigger the output signal level to flip, generating a transient pulse signal with adjustable pulse width.

5. The dual-channel synchronous reload pulse generation method according to claim 1, characterized in that: The loading signal LOAD signal continuously and synchronously reloads the count values ​​of the two channels. This pulse signal continuously appears at a certain frequency to realize pulse generation.

6. The dual-channel synchronous reload pulse generation method according to claim 1, characterized in that: The clock generation module uses a single phase-locked loop, and the optimal clock signal combination generated is 48 MHz and 50 MHz.

7. The dual-channel synchronous reload pulse generation method according to claim 1, characterized in that: The reload counting module is designed as a state machine using a register state, and the state of the state machine is controlled by the input RELOAD signal and the count value cnt.

8. The dual-channel synchronous reload pulse generation method according to claim 1, characterized in that: The signal edge trigger module is composed of basic logic gates and latches, and the latches latch the signal state and the output signal q.state respectively. The state is a state quantity, which represents the current state of the RESET signal.

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