Efficient Energy Recovery in Nanosecond Pulse Generator Circuits

Abstract

Some embodiments include a nanosecond pulse generator circuit. In some embodiments, the nanosecond pulse generator circuit may include: a high-voltage power supply; a nanosecond pulse generator electrically coupled to the high-voltage power supply and switching a voltage from the high-voltage power supply at a high frequency; a transformer having a primary side and a secondary side, the nanosecond pulse generator electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the secondary side of the transformer. In some embodiments, the energy recovery circuit includes: an inductor electrically coupled to the high-voltage power supply; a crowbar diode arranged in parallel with the secondary side of the transformer; and a second diode disposed in series with the inductor and arranged to conduct current from a load to the high-voltage power supply.

Description

Background Art

[0001] Generating high voltage pulses with fast rise and / or fast fall times is challenging. For example, to achieve fast rise and / or fast fall times (e.g., less than about 50 ns) for high voltage pulses (e.g., greater than about 5 kV), the slope of the pulse rise and / or fall must be incredibly steep (e.g., greater than 10 -11 V / s). Such steep rise and / or fall times can be very difficult to generate, especially in circuits driving capacitive loads. Such pulses can be particularly difficult to generate using standard electronic components in a compact manner; with pulses having variable pulse width, voltage, and repetition rate; and / or in applications with capacitive loads (such as plasma, for example). Summary of the Invention

[0002] Some embodiments include a nanosecond pulse generator circuit. In some embodiments, the nanosecond pulse generator circuit may include: a high-voltage power supply; a nanosecond pulse generator electrically coupled to the high-voltage power supply and switching a voltage from the high-voltage power supply at a high frequency; a transformer having a primary side and a secondary side, the nanosecond pulse generator electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the secondary side of the transformer. In some embodiments, the energy recovery circuit includes: an inductor electrically coupled to the high-voltage power supply; a crowbar diode arranged in parallel with the secondary side of the transformer; and a second diode disposed in series with the inductor and arranged to conduct current from a load to the high-voltage power supply.

[0003] In some embodiments, the energy recovery inductor comprises an inductance greater than approximately 50 μH.

[0004] In some embodiments, the nanosecond pulse generator switches the voltage from the high-voltage power supply at a frequency greater than about 100 kHz. In some embodiments, the nanosecond pulse generator switches the voltage from the high-voltage power supply at a frequency from about 0 kHz to about 500 kHz. In some embodiments, the nanosecond pulse generator circuit provides a voltage greater than about 5 kV to a load.

[0005] In some embodiments, the energy recovery circuit includes a switch. In some embodiments, the energy recovery circuit further includes a high voltage switch connected in series with the second diode and the inductor. In some embodiments, the high voltage switch switches a voltage greater than approximately 5 kV.

[0006] In some embodiments, the load comprises a capacitive load. In some embodiments, the load comprises a plasma deposition chamber.

[0007] In some embodiments, the high voltage power supply provides DC power having a voltage greater than 500V, 750V, 1 kV, 1.5 kV, etc.

[0008] Some embodiments include a circuit comprising: a storage capacitor; a switching circuit coupled to the storage capacitor, the switching circuit outputting a waveform having a voltage greater than 1 kV and a frequency greater than 1 kHz; a transformer having a primary side and a secondary side, the switching circuit electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the secondary side of the transformer (e.g., via an energy recovery diode) and the storage capacitor. In some embodiments, the energy recovery circuit comprises: an inductor electrically coupled to the high-voltage power supply; and a second diode disposed in series with the inductor and arranged to conduct current from a load to the high-voltage power supply.

[0009] In some embodiments, the energy recovery circuit includes a crowbar diode arranged in parallel with the secondary transformer.

[0010] In some embodiments, the inductor comprises an inductance greater than approximately 50 μH.

[0011] In some embodiments, the switching circuit comprises a nanosecond pulse generator. In some embodiments, the switching circuit comprises an RF driver. In some embodiments, the RF driver comprises a half-bridge driver, a full-bridge driver, a high-frequency solid-state switch, an RF generator, an amplifier tube-based RF generator, or a tube-based RF generator.

[0012] In some embodiments, the circuit further comprises: the bias compensation circuit comprising: a bias compensation diode connected in parallel with the bias compensation switch; and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

[0013] Some embodiments include a method for creating a high voltage pulse. The method may include: opening a bias compensation switch within a bias compensation circuit while closing a pulse generator switch, the bias compensation circuit being coupled to a secondary of a transformer; closing a pulse generator switch of a nanosecond pulse generator coupled to a primary side of the transformer and a DC power source to create a pulse, the pulse having a voltage greater than 1 kV at the secondary side of the transformer; opening an energy recovery switch within an energy recovery circuit while closing the pulse generator switch, the energy recovery circuit being coupled to the secondary side of the transformer and the DC power source; pausing for a period of less than approximately 100 nanoseconds; closing the pulse generator switch of the nanosecond pulse generator; and opening the energy recovery switch within the energy recovery circuit while closing the pulse generator switch.

[0014] In some embodiments, the energy recovery circuit includes an inductor and a diode connected in series with the energy recovery switch.

[0015] In some embodiments, the energy recovery switch includes a plurality of switches arranged in series and having a plurality of voltage distribution resistors such that each of the plurality of voltage distribution resistors is arranged across a corresponding switch of the plurality of switches.

[0016] In some embodiments, the bias compensation circuit includes: a bias compensation diode connected in parallel with the bias compensation switch; and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

[0017] Some embodiments include a method for creating a high voltage pulse. The method may include: before a pulse burst, opening a bias compensation switch within a bias compensation circuit coupled to a nanosecond pulse generator through a transformer, the bias compensation circuit coupled to a secondary of the transformer; during the pulse burst, repeatedly opening and closing a pulse generator switch of the nanosecond pulse generator to create a plurality of pulses within the pulse burst, the nanosecond pulse generator coupled to a primary side of the transformer and a DC power source, the opening and closing of the pulse generator switch occurring at a pulse repetition frequency greater than about 1 kHz, and the closing of the pulse generator switch generating pulses having a voltage greater than 1 kV on the secondary side of the transformer; during the pulse burst, repeatedly closing and opening an energy recovery switch within an energy recovery circuit such that the energy recovery switch is closed when the pulse generator switch is open and the energy recovery switch is closed when the pulse generator switch is closed, the energy recovery circuit coupled to the secondary side of the transformer and the DC power source; and after the pulse burst, closing the bias compensation switch within the bias compensation circuit.

[0018] In some embodiments, the method further includes: pausing for a time period of less than approximately 100 microseconds; opening the bias compensation switch before a second pulse burst; opening and closing the pulse generator switch during the second pulse burst; and closing the open energy recovery switch during the second pulse burst; and closing the bias compensation switch after the second burst.

[0019] In some embodiments, the energy recovery circuit includes an inductor and a diode connected in series with the energy recovery switch.

[0020] In some embodiments, the energy recovery switch includes a plurality of switches arranged in series and having a plurality of voltage distribution resistors such that each of the plurality of voltage distribution resistors is arranged across a corresponding switch of the plurality of switches.

[0021] In some embodiments, the bias compensation circuit includes: a bias compensation diode connected in parallel with the bias compensation switch; and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

[0022] Some embodiments include a nanosecond pulse generator circuit comprising: a high-voltage power supply; a nanosecond pulse generator electrically coupled to the high-voltage power supply and switching a voltage from the high-voltage power supply at a high frequency; a transformer having a primary side and a secondary side; and an energy recovery circuit arranged in parallel with the secondary side of the transformer. In some embodiments, the energy recovery circuit comprises: a switch; an inductor; a first diode arranged in series with the switch and the inductor such that when the switch is closed, the first diode conducts current from the switch to the inductor; and a second diode arranged to: when the switch is closed, conduct current from a point in the nanosecond pulse generator circuit between the switch and the first diode to a point in the nanosecond pulse generator circuit between the high-voltage power supply and the nanosecond pulse generator.

[0023] Some embodiments include a nanosecond pulse generator circuit comprising: a high-voltage power supply; a nanosecond pulse generator electrically coupled to the high-voltage power supply and switching a voltage from the high-voltage power supply at a high frequency; a transformer having a primary side and a secondary side, the nanosecond pulse generator electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the second side of the transformer in parallel with the primary side of the transformer. In some embodiments, the energy recovery circuit comprises: an inductor electrically coupled to the high-voltage power supply; a crowbar diode arranged in parallel with the secondary side of the transformer; and a second diode disposed in series with the inductor and arranged to conduct current from a load to the high-voltage power supply.

[0024] In some embodiments, the inductor comprises an inductance of less than about 1,000 nH. In some embodiments, the nanosecond pulse generator switches the voltage from the high-voltage power supply at a frequency greater than about 100 kHz. In some embodiments, the nanosecond pulse generator switches the voltage from the high-voltage power supply at a frequency from about 0 kHz to about 500 kHz. In some embodiments, the nanosecond pulse generator circuit provides a voltage greater than about 5 kV to a load. In some embodiments, the secondary side of the transformer is coupled to a capacitive load. In some embodiments, the secondary side of the transformer is coupled to one or more electrodes for generating or manipulating a plasma. In some embodiments, the energy recovery circuit comprises a switch.

[0025] These illustrative embodiments are not intended to limit or qualify the present disclosure, but rather to provide examples to aid understanding thereof. Additional embodiments are discussed in the detailed description, and further description is provided herein. Advantages provided by one or more of the various embodiments may be further understood by examining this specification or by practicing one or more of the embodiments presented.

[0026] Some embodiments include a high-voltage, high-frequency switching circuit. In some embodiments, the high-voltage, high-frequency switching circuit includes: a high-voltage switching power supply that generates pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz (or any frequency); a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; and a primary snubber electrically coupled to the primary side of the transformer and connected in parallel with the high-voltage switching power supply, the primary snubber including at least one resistor that discharges a load coupled to the output.

[0027] In some

[0028] The resistor in the primary absorber has a value of less than about 400 ohms.

[0029] In some embodiments, the high voltage, high frequency switching circuit, wherein the primary absorber is configured to dissipate power in excess of approximately 1 kilowatt. In some embodiments, the primary absorber is configured to dissipate an average power of 30W-30kW.

[0030] In some embodiments, the primary absorber includes at least one inductor connected in series with the at least one resistor.

[0031] In some embodiments, the primary absorber includes a switch connected in series with the at least one resistor.

[0032] In some embodiments, the output is coupled to a plasma load that is primarily capacitive.

[0033] In some embodiments, the output is coupled to a plasma load comprising a dielectric barrier discharge.

[0034] In some embodiments, the resistance is greater than 100 kW.

[0035] In some embodiments, the resistor in the primary absorber comprises a resistor R, and the output is coupled to a load having a capacitance C such that where tf is the pulse fall time, and

[0036] In some embodiments, the load is capacitive in nature, having a capacitance less than 50 nF, wherein the load capacitance does not hold a charge for more than 1 μs.

[0037] In some embodiments, wherein the load is capacitive in nature, and the high voltage, high frequency switching circuit rapidly charges and discharges the load capacitance.

[0038] In some embodiments, when the high voltage switching power supply does not provide a high voltage pulse, the output generates a negative bias voltage greater than -2 kV relative to the electrode, substrate or wafer relative to ground. In some embodiments, the bias voltage may be positive.

[0039] In some embodiments, the output can generate a high voltage pulse having a voltage greater than 1 kV and a frequency greater than 10 kHz, wherein the pulse fall time is less than approximately 400 ns, 40 ns, 4 ns, etc.

[0040] Some embodiments include a high-voltage, high-frequency switching circuit. In some embodiments, the high-voltage, high-frequency switching circuit includes: a high-voltage switching power supply that generates pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz; a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; and a primary absorber electrically coupled to the primary side of the transformer and connected in parallel with the output of the high-voltage switching power supply, the primary absorber including: at least one resistor that discharges a load coupled to the output coupled to the secondary side of the transformer; and at least one inductor connected in series with the at least one resistor.

[0041] In some embodiments, the primary absorber includes a switch connected in series with the at least one resistor and / or the at least one inductor.

[0042] In some embodiments, the output can generate a high voltage pulse having a voltage greater than 1 kV and having a frequency greater than 10 kHz and having a pulse fall time less than about 400 ns.

[0043] In some embodiments, the primary absorber is configured to dissipate power in excess of approximately 1 kilowatt.

[0044] In some embodiments, the high voltage switching power supply includes a power supply, at least one switch, and a step-up transformer.

[0045] In some embodiments, the primary absorber handles peak powers greater than 10 kW.

[0046] In some embodiments, the resistance of the resistor in the primary absorber is less than about 400 ohms.

[0047] In some embodiments, the primary absorber includes an inductor and a resistor, and wherein the inductance L of the inductor and the resistance R of the resistor are set to satisfy L / R≈tp, wherein tp is a pulse width of the pulse.

[0048] In some embodiments, the resistor in the primary absorber comprises a resistor R, and the output is coupled to a load having a capacitance C such that Among them, t f is the pulse fall time, and

[0049] In some embodiments, the high voltage switching power supply establishes a potential for accelerating ions into a plasma in the surface.

[0050] In some embodiments, when the high voltage switching power supply is not providing a high voltage pulse, the output generates a negative potential difference greater than -2 kV with respect to the electrode or substrate (or wafer and plasma) relative to ground.

[0051] Some embodiments include a high-voltage, high-frequency switching circuit. In some embodiments, the high-voltage, high-frequency switching circuit includes: a high-voltage switching power supply that generates pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz; a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; and a primary absorber electrically coupled to the primary side of the transformer and connected in parallel with the output of the high-voltage switching power supply, the primary absorber comprising at least one resistor, at least one inductor, and a switch arranged in series. In some embodiments, the output can generate high-voltage pulses having a voltage greater than 1 kV, a frequency greater than 10 kHz, and a pulse fall time less than approximately 400 ns, and wherein the output is electrically coupled to a plasma-type load.

[0052] In some embodiments, the plasma type load may be modeled as having a capacitive element of less than 20 nF, 10 nF, 100 pF, 10 pF, 1 pF, 0.5 pF, etc.

[0053] In some embodiments, the plasma-type load is designed to accelerate ions into a surface.

[0054] In some embodiments, the potential is established by the action of the high voltage high frequency switching power supply to accelerate ions into the surface.

[0055] In some embodiments, the plasma type is primarily capacitive in nature.

[0056] In some embodiments, the plasma-type load comprises a dielectric barrier discharge.

[0057] In some embodiments, the high voltage high frequency switching power supply delivers a peak power greater than 100 kW.

[0058] In some embodiments, the high voltage switching power supply includes a power supply, at least one switch, and a step-up transformer.

[0059] These illustrative embodiments are not intended to limit or qualify the present disclosure, but rather to provide examples to aid understanding thereof. Additional embodiments are discussed in the detailed description, and further description is provided herein. Advantages provided by one or more of the various embodiments may be further understood by examining this specification or by practicing one or more of the embodiments presented. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] These and other features, aspects, and advantages of the present disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings.

[0061] Figure 1 is a circuit diagram of a nanosecond pulse generator system with an energy recovery circuit driving a capacitive load, according to some embodiments.

[0062] Figure 2 Show Figure 1 The voltage and current waveforms within the circuit diagram are shown.

[0063] Figure 3 is a circuit diagram of a nanosecond pulse generator system including a nanosecond pulse generator having an energy recovery circuit with an energy recovery switch, according to some embodiments.

[0064] Figure 4 is a circuit diagram of a nanosecond pulse generator system including a passive bias compensation circuit with an energy recovery circuit, according to some embodiments.

[0065] Figure 5 is a circuit diagram of a nanosecond pulse generator system including an active bias compensation circuit with an energy recovery circuit, according to some embodiments.

[0066] Figure 6 is a circuit diagram of a nanosecond pulse generator system including an active bias compensation circuit with an energy recovery circuit, according to some embodiments.

[0067] Figure 7 is a circuit diagram of an RF driver system including an RF driver, an active bias compensation circuit, and an energy recovery circuit, according to some embodiments.

[0068] Figure 8 are the waveforms of voltage and current within the nanosecond pulse generator system.

[0069] Figure 9 is a schematic diagram of a spatially variable wafer bias system according to some embodiments.

[0070] Figure 10 is a circuit diagram of a nanosecond pulse generator system with an energy recovery circuit according to some embodiments.

[0071] Figure 11 The waveforms of voltage and current within the nanosecond pulse generator system are shown.

[0072] Figure 12 is a circuit diagram of a nanosecond pulse generator system with an energy recovery circuit driving a capacitive load, according to some embodiments.

[0073] Figure 13The waveforms of voltage and current within the nanosecond pulse generator system are shown.

[0074] Figure 14 is a block diagram of a high voltage switch with isolated power according to some embodiments.

[0075] Figure 15 is a block diagram of a process for operating a nanosecond pulse generator system with active energy recovery circuitry and active bias compensation circuitry, according to some embodiments.

[0076] Figure 16 An illustrative computing system is shown for performing functions to facilitate implementation of the embodiments described herein.

[0077] Figure 17 is a schematic diagram of a spatially variable wafer bias system according to some embodiments.

[0078] Figure 18 is a circuit diagram of an RF driver system including an RF driver, an active bias compensation circuit, and an energy recovery circuit, according to some embodiments.

[0079] Figure 19 is a circuit diagram of a nanosecond pulse generator system with a primary absorber according to some embodiments.

[0080] Figure 20 is a circuit diagram of a nanosecond pulse generator system with a primary absorber according to some embodiments.

[0081] Figure 21 is a circuit diagram of a nanosecond pulse generator system with a primary absorber according to some embodiments.

[0082] Figure 22 is a circuit diagram of a nanosecond pulse generator system with a primary absorber according to some embodiments.

[0083] Figure 23 It is a waveform produced by a nanosecond pulse generator system.

[0084] Figure 24 is a circuit diagram of a nanosecond pulse generator system with a primary absorber, a bias compensation circuit, and a plasma load, according to some embodiments.

[0085] Figure 25 is a circuit diagram of a nanosecond pulse generator system with a primary absorber, a bias compensation circuit, and a plasma load, according to some embodiments.

[0086] Figure 26 is a circuit diagram of a nanosecond pulse generator system with a primary absorber, a bias compensation circuit, and a plasma load, according to some embodiments.

[0087] Figure 27 is a circuit diagram of a nanosecond pulse generator system with a primary absorber, a bias compensation circuit, and a plasma load, according to some embodiments.

[0088] Figure 28 It is a waveform produced by a nanosecond pulse generator system. DETAILED DESCRIPTION

[0089] Some embodiments include a nanosecond pulse generator system that uses an energy recovery circuit to provide energy recovery from a load (e.g., a capacitive load). In some embodiments, the nanosecond pulse generator system can include a high-voltage, high-frequency nanosecond pulse generator that can, for example, drive a plasma deposition system, a plasma etching system, a plasma sputtering system, an electron beam system, an ion beam system, or the like (the load).

[0090] In some embodiments, an energy recovery circuit can recover charge from a load to charge an energy storage capacitor. For example, the energy recovery circuit can recover energy stored or charge held by various circuit elements, including capacitors or inductors. For example, these elements can include stray or parasitic capacitance or inductance that would normally be dissipated or wasted. For example, the energy recovery circuit can recover energy by performing an action to recharge the energy storage capacitor and / or inductor. This energy can be captured and / or reused by the circuit.

[0091] Figure 1 is a circuit diagram of a nanosecond pulse generator system 100 , which includes a nanosecond pulse generator stage 101 with an energy recovery circuit 110 , a transformer T1 , a lead stage 103 , a DC bias circuit 104 , and a load stage 106 .

[0092] In some embodiments, load stage 106 can represent an idealized or effective circuit for a semiconductor processing chamber (e.g., such as a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.). For example, capacitor C2 can represent the capacitance of an electrostatic clamp on which a semiconductor process wafer can be seated. For example, the clamp can include a dielectric material (e.g., alumina or other ceramic material and a conductor contained within the dielectric material). For example, capacitor C1 can have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0093] For example, capacitor C3 can represent the sheath capacitance between the plasma and the wafer. For example, resistor R6 can represent the sheath resistance between the plasma and the wafer. For example, inductor L2 can represent the sheath inductance between the plasma and the wafer. For example, current source I2 can represent the ion current through the sheath. For example, capacitor C1 or capacitor C3 can have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0094] For example, capacitor C9 can represent the capacitance within the plasma between the chamber wall and the top surface of the wafer. For example, resistor R7 can represent the resistance within the plasma between the chamber wall and the top surface of the wafer. For example, current source I1 can represent the ion current in the plasma. For example, capacitor C1 or capacitor C9 can have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0095] In some embodiments, the plasma voltage can be the voltage measured from ground to circuit point 123; the wafer voltage is the voltage measured from ground to circuit point 122 and can represent the voltage at the surface of the wafer; the clamping voltage is the voltage measured from ground to circuit point 121; the electrode voltage is the voltage measured from ground to the circuit point marked 124 (e.g., on the electrode); and the input voltage is the voltage measured from ground to circuit point 125.

[0096] In this example, DC bias circuit 104 does not include any bias compensation. DC bias circuit 104 includes an offset supply voltage V5, which can, for example, bias the output voltage positively or negatively. In some embodiments, offset supply voltage V5 can be adjusted to change the potential between the wafer voltage and the clamping voltage. In some embodiments, offset supply voltage V5 can have a voltage of approximately ±5 kV, ±4 kV, ±3 kV, ±2 kV, ±1 kV, etc.

[0097] In some embodiments, bias capacitor C12 can isolate (or separate) the DC bias voltage from other circuit elements. For example, bias capacitor C12 can allow for a potential shift from one portion of the circuit to another. In some embodiments, this potential shift can ensure that the electrostatic force holding the wafer in place on the clamp remains below a voltage threshold. Resistor R2 can isolate the DC bias supply from the high voltage pulsed output from pulse generator stage 101.

[0098] For example, bias capacitor C12 may have a capacitance of less than approximately 100 pF, 10 pF, 1 pF, 100 μF, 10 μF, 1 μF, etc. For example, resistor R2 may have a high resistance (e.g., such as a resistance of approximately 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm, etc.).

[0099] For example, resistor R13 may represent the resistance of a lead or transmission line connected from the output of the high voltage power system to an electrode, such as load stage 106. For example, capacitor C1 may represent stray capacitance in a lead or transmission line.

[0100] In some embodiments, the nanosecond pulse generator stage 101 can generate pulses with high pulse voltage (e.g., a voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high frequency (e.g., a frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), fast rise time (e.g., a rise time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), fast fall time (e.g., a fall time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.) and / or short pulse width (e.g., a pulse width less than approximately 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0101] For example, the nanosecond pulse generator stage 101 may include: all or any portion of any device described in U.S. patent application serial number 14 / 542,487, entitled “High Voltage Nanosecond Pulser,” which is incorporated into this disclosure for all purposes; all or any portion of any device described in U.S. patent application serial number 14 / 635,991, entitled “Galvanically Isolated Output Variable Pulse Generator Disclosure,” which is incorporated into this disclosure for all purposes; or all or any portion of any device described in U.S. patent application serial number 14 / 798,154, entitled “High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency,” which is incorporated into this disclosure for all purposes.

[0102] In some embodiments, the nanosecond pulse generator stage 101 may include one or more nanosecond pulse generators coupled together in various ways.

[0103] In some embodiments, the nanosecond pulse generator stage 101 may include a DC power supply that provides a consistent DC voltage, which is switched by switch S6 and provides the switched power to transformer T1. The DC power supply may include a voltage source V5 and an energy storage capacitor C7. If transformer T1 has a 1:10 turns ratio, the transformer can generate 10 kV across load C1.

[0104] In some embodiments, if the load capacitance (e.g., capacitors C3 and C9) is small compared to the capacitance of energy storage capacitor C7, voltage doubling can occur at the transformer input. For example, if energy storage capacitor C7 provides 500V, 1kV can be measured at the input of transformer T1.

[0105] For example, switch S6 may include one or more solid-state switches (e.g., such as IGBTs, MOSFETs, SiC MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc.) Switch S6 may be switched based on signals from the controller labeled Sig6+ and Sig6-.

[0106] In some embodiments, the nanosecond pulse generator stage 101 can include a snubber circuit, which can include a snubber resistor R3 and a snubber capacitor C5 in parallel with a snubber diode D4. The snubber circuit can also include stray inductance. In some embodiments, the snubber resistor R3 and / or the snubber diode D4 can be placed between the collector of the switch S6 and the primary winding of the transformer T1. The snubber diode D4 can be used to buffer any overvoltages during switching. A large and / or fast capacitor C5 can be coupled to the emitter side of the switch S6. A freewheeling diode D2 is also coupled to the emitter side of the switch S1. Various other components not shown in the figure can be included. One or more switches and / or circuits can be arranged in parallel or in series.

[0107] In some embodiments, switch S6 can be switched very quickly so that the switched voltage may never be at full voltage (e.g., the voltage of energy storage capacitor C7 and / or voltage source V5). In some embodiments, the gate resistor coupled to switch S6 can be provided with a short turn-on pulse.

[0108] In some embodiments, the nanosecond pulse generator stage 101 can include a freewheeling diode D2. In some embodiments, the freewheeling diode D2 can be used in combination with an inductive load to ensure that energy stored in the inductive load can be dissipated after the switch S6 is opened by allowing the current to continue flowing in the same direction through the inductor, and the energy is dissipated in the resistive elements of the circuit. If the freewheeling diode D2 is not included, this can result in a large reverse voltage across the switch S6, for example.

[0109] In some embodiments, the nanosecond pulse generator stage 101 may include a stray inductance L1 and / or a stray resistance R1. For example, the stray inductance L1 may be less than approximately 10 nH, 100 nH, 1,000 nH, 10,000 nH, etc. For example, the stray resistance R1 may be less than approximately 1 ohm, 100 m ohm, 10 m ohm, etc.

[0110] In some embodiments, the energy recovery circuit 110 can be electrically coupled to the secondary side of the transformer and / or to the energy storage capacitor C7. For example, the energy recovery circuit 110 can include a diode 130 (e.g., a crowbar diode) across the secondary side of the transformer T1. For example, the energy recovery circuit 110 can include an energy recovery diode 120 and an energy recovery inductor 115 (arranged in series), which can allow current to flow from the secondary side of the transformer T1 to charge the energy storage capacitor C7. The energy recovery diode 120 and the energy recovery inductor 115 can be electrically connected to the secondary side of the transformer T1 and the storage capacitor C7. In some embodiments, the energy recovery circuit 110 can include a diode 130 and / or an inductor 140 electrically coupled to the secondary side of the transformer T1. The inductor 140 can represent a stray inductance and / or can include the stray inductance of the transformer T1.

[0111] In some embodiments, the energy recovery inductor 115 may include any type of inductor (e.g., such as a ferrite inductor or an air core inductor). In some embodiments, the energy recovery inductor 115 may have an inductance greater than approximately 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, the energy recovery inductor 115 may have an inductance of approximately 1 μH to approximately 100 mH.

[0112] When the nanosecond pulse generator is on, current can charge the load stage 106 (e.g., capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of transformer T1 rises above the charge voltage on energy storage capacitor C7, some current can flow through the energy recovery inductor 115. When the nanosecond pulse generator is off, current can flow from a capacitor within the load stage 106 (e.g., capacitor C1) through the energy recovery inductor 115 to charge the energy storage capacitor C7 until the voltage across the energy recovery inductor 115 is zero. The diode 130 can prevent the capacitor within the load stage 106 from looping with the inductance in the load stage 106 or the DC bias circuit 104.

[0113] For example, the energy recovery diode 120 may prevent charge from flowing from the energy storage capacitor C7 to capacitors within the load stage 106 .

[0114] The value of the energy recovery inductor 115 can be selected to control the current fall time. In some embodiments, the energy recovery inductor 115 can have an inductance value between 1 μH and 600 μH. In some embodiments, the energy recovery inductor 115 can have an inductance value greater than 50 μH. In some embodiments, the energy recovery inductor 115 can have an inductance value less than approximately 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 350 μH, 400 μH, 400 μH, 500 μH, etc.

[0115] For example, if energy storage capacitor C7 provides 500V, then (e.g., due to voltage doubling as described above) 1kV will be measured at the input of transformer T1. When switch S6 is open, the 1kV at transformer T1 can be distributed among the components of the energy recovery circuit 110. If the values ​​are chosen appropriately (e.g., inductor L3 has an inductance that is less than the inductance of energy recovery inductor 115), the voltage across energy recovery diode 120 and energy recovery inductor 115 can be greater than 500V. Current can then flow through energy recovery diode 120 and / or charge energy storage capacitor C7. Current can also flow through diode D3 and inductor L6. Once energy storage capacitor C7 is charged, current can no longer flow through diode D3 and energy recovery inductor 115.

[0116] In some embodiments, the energy recovery circuit 110 can transfer energy (or charge) from the load stage 106 (e.g., at a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The stray resistance of the energy recovery circuit can be low to ensure that the pulse across the load stage 106 has a fast fall time t f For example, the stray resistance of the energy recovery circuit 110 can have a resistance of less than approximately 1 ohm, 100 m ohms, 10 m ohms, etc. In some embodiments, the resistive dissipation of energy from the load stage 106 can be low (e.g., such as less than approximately 60%, 70%, 80%, or 90%, etc.).

[0117] May or may not be needed Figure 1 Any number of components shown (eg, diode 135 or diode 130 or inductor 140).

[0118] In some embodiments, a diode may be placed between the voltage source V1 and the point where the energy recovery circuit 110 is connected to the voltage source V1 and / or the energy storage capacitor C7. For example, such a diode may be arranged to allow current to flow from the voltage source V1 to the energy storage capacitor C7, but may not allow current to flow from the energy recovery circuit to the energy storage capacitor C7.

[0119] Figure 2 Show Figure 1 Waveforms of voltage and current within the nanosecond pulse generator system 100 are shown. Waveform 205 represents the voltage measured at the point labeled 124 (e.g., on the electrode) into the load stage 106 in the nanosecond pulse generator system 100. Waveform 220 represents the voltage at the point labeled 122 (e.g., on the wafer). Waveform 215 represents the current through the energy recovery inductor 115. Waveform 215 shows the current through the energy recovery inductor 115 when the nanosecond pulse generator stage 101 is turned on (e.g., as shown by the rising light blue waveform). When the nanosecond pulse generator stage 101 is turned off, the current through the energy recovery inductor 115 continues to rise to a maximum value and then falls. When the voltage across the energy recovery inductor 115 reaches zero, the current should stop flowing through the energy recovery inductor 115; however, in this example, the nanosecond pulse generator stage 101 is turned on again before the voltage across the energy recovery inductor 115 reaches zero.

[0120] In some embodiments, Figure 1 The potential at the point marked 121 in FIG. 5 is shown as negative, however, the clamping potential can also be positive.

[0121] Figure 3 is a circuit diagram of a nanosecond pulse generator system 300 including a nanosecond pulse generator stage 101 having an active energy recovery circuit 111 with an energy recovery switch S5 according to some embodiments. Switch S6 can be switched based on signals from a controller labeled Sig5+ and Sig5-.

[0122] exist Figure 3, the active energy recovery circuit 111 may include an energy recovery switch S5, which may be used to control the flow of current through the energy recovery inductor 115. In some embodiments, the energy recovery switch S5 may include a freewheeling diode arranged across the energy recovery switch. For example, the energy recovery switch S5 may be placed in series with the energy recovery inductor 115. In some embodiments, the energy recovery switch S5 may be opened and closed based on a signal from a switch input V5. In some embodiments, when the switch S1 is open and / or no longer pulses occur, the switch input V5 may close the energy recovery switch to allow current to flow from the load stage 106 back to the high voltage load C7. In some embodiments, when the switch S1 is closed and / or pulses occur, the switch input V5 may open the energy recovery switch to limit the current flow to the high voltage load C7.

[0123] Figure 3 The energy recovery switch S5 in FIG is shown as being connected in series with the energy recovery diode 120 and the energy recovery inductor 115 and placed between the secondary side of the transformer T1 and the energy recovery diode 120 and the energy recovery inductor 115. In some embodiments, both the energy recovery diode 120 and the energy recovery inductor 115 can be placed between the energy recovery switch S5 and the secondary side of the transformer T1. In some embodiments, the energy recovery switch S5 can be placed between the energy recovery diode 120 and the energy recovery inductor 115. The energy recovery diode 120, the energy recovery inductor 115, and the energy recovery switch S5 can be arranged in any order.

[0124] For example, the energy recovery switch S5 may include a high voltage switch (eg, such as the high voltage switch 1400 ).

[0125] In some embodiments, when the energy recovery switch S5 is open, the load stage 106 can be charged by the nanosecond pulse generator stage 101. For example, it may be beneficial to remove charge from the load stage 106 (e.g., at a fast time scale (e.g., less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.)). To remove charge from the load stage 106, the energy recovery switch S5 can be closed.

[0126] Figure 4 is a circuit diagram of a nanosecond pulse generator system 400 having an energy recovery circuit 110 including a passive bias compensation circuit 114 according to some embodiments.

[0127] In this example, the passive bias compensation circuit 114 is a passive bias compensation circuit and may include a bias compensation diode 405 and a bias compensation capacitor 410. The bias compensation diode 405 may be arranged in series with the offset supply voltage V5. The bias compensation capacitor 410 may be arranged across one or both of the offset supply voltage V5 and the resistor R2. The bias compensation capacitor 410 may have a capacitance of less than 100 nF to 100 μF (e.g., approximately 100 μF, 50 μF, 25 μF, 10 μF, 2 μF, 500 nF, 200 nF, etc.).

[0128] In some embodiments, the bias compensation diode 405 can conduct a current between 10A and 1 kA at a frequency between 10 Hz and 500 kHz.

[0129] In some embodiments, bias capacitor C12 can allow for a voltage offset between the output of the nanosecond pulse generator stage 101 (e.g., at the location labeled 125) and the voltage on the electrode (e.g., at the location labeled 124). In operation, for example, the electrode can be at a DC voltage of -2 kV during a burst (a burst can include multiple pulses), while the output of the nanosecond pulse generator alternates between +6 kV during a pulse and 0 kV between pulses.

[0130] For example, bias capacitor C12 is 100nF, 10nF, 1nF, 100μF, 10μF, 1μF, etc. For example, resistor R2 can have a high resistance (e.g., a resistance such as approximately 1k ohm, 10k ohm, 100k ohm, 1M ohm, 10M ohm, 100M ohm, etc.).

[0131] In some embodiments, the bias compensation capacitor 410 and the bias compensation diode 405 can allow a voltage offset between the output of the nanosecond pulse generator stage 101 (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124) to be established at the beginning of each burst to achieve a desired equilibrium state. For example, charge is transferred from the capacitor C12 to the bias compensation capacitor 410 over a plurality of pulses (e.g., approximately 5-100 pulses) at the beginning of each burst to establish the correct voltage in the circuit.

[0132] In some embodiments, the pulse repetition frequency (e.g., the frequency of pulses within a burst) can be between 200 kHz and 800 MHz (e.g., such as 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz). In some embodiments, the burst repetition frequency (e.g., the frequency of the burst) can be approximately 10 kHz, 50 Hz, 100 kHz, 500 kHz, 1 MHz, etc. (e.g., such as 400 kHz).

[0133] The energy recovery circuit 110 may or may not include Figure 3 Energy recovery switch shown.

[0134] Figure 5 is a circuit diagram of a nanosecond pulse generator system 500 including an active bias compensation circuit 134 with an energy recovery circuit 110 according to some embodiments.

[0135] The active bias compensation circuit 134 may include any bias and / or bias compensation circuit known in the art. For example, the active bias compensation circuit 134 may include any bias and / or bias compensation circuit described in U.S. Patent Application No. 16 / 523,840, entitled “NANOSECOND PULSER BIAS COMPENSATION,” which is incorporated herein in its entirety for all purposes.

[0136] In some embodiments, Figure 5 The active bias compensation circuit 134 of the illustrated nanosecond pulse generator system 500 may include a bias capacitor C7, a blocking capacitor C12, a blocking diode D8, a bias compensation switch S8 (e.g., a high voltage switch), an offset supply voltage V5, a resistor R2, and / or a resistor R4. In some embodiments, for example, the switch S8 may include a high voltage switch (e.g., such as Figure 14 1400). Switch S6 can be switched based on signals from the controller labeled Sig8+ and Sig8-.

[0137] In some embodiments, the offset supply voltage V5 can include a DC voltage source that can bias the output voltage either forward or negative. In some embodiments, capacitor C12 can isolate / decouple the offset supply voltage V5 from other circuit components. In some embodiments, active bias compensation circuit 134 can allow for potential transfer of power from one portion of the circuit to another. In some embodiments, active bias compensation circuit 134 can be used to maintain a constant clamping force between the process wafer and the electrostatic clamp. For example, resistor R2 can protect / isolate the DC bias supply from the driver. As another example, resistor R2 can be used to ensure that the DC supply V5 does not enter an overcurrent fault.

[0138] In some embodiments, the bias compensation switch S8 can be open while the nanosecond pulse generator stage 101 is not actively generating pulses at a frequency greater than 10 kHz or providing pulse bursts, and closed when the nanosecond pulse generator stage 101 is not generating pulses. While closed, for example, the bias compensation switch S8 can allow current to flow in a direction blocked by the blocking diode D8. Short-circuiting this current can allow the bias between the wafer and the clamp to be less than 2 kV, which can be within acceptable tolerances.

[0139] In some embodiments, the load stage 106 may be coupled to an active bias compensation circuit 134. In some embodiments, the energy recovery circuit 110 may or may not include: Figure 3 Energy recovery switch shown.

[0140] Figure 6 is a circuit diagram of a nanosecond pulse generator system 600 including an active bias compensation circuit 134 with an active energy recovery circuit 111 according to some embodiments.

[0141] Figure 7 is a circuit diagram of a matchless driver system 700 including an RF driver 705 , an active bias compensation circuit 134 , and an energy recovery circuit 110 , according to some embodiments.

[0142] In this example, the unmatched driver system 700 may include an RF driver 705 instead of the nanosecond pulse generator stage 101. For example, the RF driver 705 may be a half-bridge driver or a full-bridge driver. The RF driver 705 may include a voltage source V1, which may be a DC voltage source (e.g., a capacitive source, an AC-DC converter, etc.). In some embodiments, the RF driver 705 may include four switches S1, S2, S3, and S4. In some embodiments, the RF driver 705 may include a plurality of switches S1, S2, S3, and S4 connected in series or in parallel. For example, the switches S1, S2, S3, and S4 may include any type of solid-state switch (e.g., such as an IGBT, a MOSFET, a SiC MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc.). The switches S1, S2, S3, and S4 may switch at high frequencies and / or may generate high voltage pulses. For example, these frequencies may include frequencies around 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0143] Each of switches S1, S2, S3, and S4 can be coupled in parallel with a corresponding diode D1, D2, D3, and D4, and can include stray inductance represented by inductors L1, L2, L3, and L4. In some embodiments, the inductances of inductors L1, L2, L3, and L4 can be equal. In some embodiments, the inductances of inductors L1, L2, L3, and L4 can be less than approximately 50nH, 100nH, 150nH, 500nH, 1,000nH, etc. The combination of a switch (S1, S2, S3, or S4) and a corresponding diode (D1, D2, D3, or D4) can be coupled in series with the corresponding inductor (L1, L2, L3, or L4). Inductors L3 and L4 are connected to ground. Inductor L1 is connected to switch S4 and resonant circuit 710. Inductor L2 is connected to the opposite side of switch S3 and resonant circuit 710.

[0144] Switches S1, S2, S3, and S4 may include high voltage switches (e.g., such as Figure 14 High voltage switch 1400 shown).

[0145] In some embodiments, the RF driver 705 can be coupled to a resonant circuit 710. The resonant circuit 710 can include a resonant inductor L5 and / or a resonant capacitor C2 coupled to a transformer T1. The resonant circuit 710 can include a resonant resistor R5, which can, for example, include the stray resistance of any leads between the RF driver 705 and the resonant circuit 710 and / or any components within the resonant circuit 710 (e.g., such as the transformer T1, the capacitor C2, and / or the inductor L5). In some embodiments, the resonant resistor R5 includes only the stray resistance of the wires, traces, or circuit elements. While the inductance and / or capacitance of other circuit elements can affect the drive frequency, the drive frequency can be largely set by selecting the resonant inductor L5 and / or the resonant capacitor C2. Given the stray inductance or stray capacitance, further refinement and / or tuning may be required to create the correct drive frequency. In addition, the rise time across the transformer T1 can be adjusted by varying L5 and / or C2, provided that:

[0146]

[0147] In some embodiments, large inductance values ​​for L5 may result in slower or shorter rise times. These values ​​may also affect the burst envelope. Figure 17 As shown, each burst can include transient and steady state pulses. The transient pulse within each burst can be set by L5 and / or Q of the system until full voltage is reached during the steady state pulse.

[0148] If the switches in the RF driver 705 are at the resonant frequency f resonantBy switching, the output voltage at the transformer T1 will be amplified. In some embodiments, the resonant frequency can be approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0149] In some embodiments, the resonant capacitor C2 may include the stray capacitance of the transformer T1 and / or a physical capacitor. In some embodiments, the resonant capacitor C2 may have a capacitance of approximately 10 μF, 1 μF, 100 nF, 10 nF, etc. In some embodiments, the resonant inductor L5 may include the stray inductance of the transformer T1 and / or a physical inductor. In some embodiments, the resonant inductor L5 may have an inductance of approximately 50 nH, 100 nH, 150 nH, 500 nH, 1,000 nH, etc. In some embodiments, the resonant resistor R5 may have a resistance of approximately 10 ohms, 25 ohms, 50 ohms, 100 ohms, 150 ohms, 500 ohms, etc.

[0150] In some embodiments, the resonant resistor R5 can represent the stray resistance of wires, traces, and / or transformer windings within the physical circuit. In some embodiments, the resonant resistor R5 can have a resistance of approximately 10 mOhms, 50 mOhms, 100 mOhms, 200 mOhms, 500 mOhms, etc.

[0151] In some embodiments, transformer T1 may comprise a transformer as disclosed in U.S. Patent Application No. 15 / 365,094, entitled "High Voltage Transformer," which is incorporated herein for all purposes. In some embodiments, the output voltage of resonant circuit 710 can be varied by changing the duty cycle (e.g., the switch "on" time or the time the switch is conducting) of switches S1, S2, S3, and / or S4. For example, a longer duty cycle results in a higher output voltage; a shorter duty cycle results in a lower output voltage. In some embodiments, the output voltage of resonant circuit 710 can be varied or tuned by adjusting the duty cycle of the switching action in RF driver 705.

[0152] For example, the duty cycle of the switches can be adjusted by changing the duty cycle of the signal Sig1 that opens and closes the switch S1; changing the duty cycle of the signal Sig2 that opens and closes the switch S6; changing the duty cycle of the signal Sig3 that opens and closes the switch S3; and changing the duty cycle of the signal Sig4 that opens and closes the switch S4. For example, by adjusting the duty cycle of the switches S1, S2, S3, or S4, the output voltage of the resonant circuit 710 can be controlled.

[0153] In some embodiments, each switch S1, S2, S3, or S4 in the resonant circuit 710 can be switched independently or in combination with one or more other switches. For example, the signal Sig1 can be the same signal as the signal Sig3. As another example, the signal Sig2 can be the same signal as the signal Sig4. As another example, each signal can be independent and can control each switch S1, S2, S3, or S4 independently or separately.

[0154] In some embodiments, the resonant circuit 710 may be coupled to a half-wave rectifier 715 , which may include a blocking diode D7 .

[0155] The active bias compensation circuit 134 may include a combination of Figure 5 Active bias compensation circuit described.

[0156] The matchless driver system 700 does not include a conventional matching network (e.g., a 50 ohm matching network or an external matching network or a standalone matching network). In some embodiments, the matchless driver system 700 does not require a 50 ohm matching network to tune the switching power applied to the wafer chamber. In some embodiments, the matchless driver system 700 can include a variable output impedance RF generator without a conventional matching network. This can allow for rapid changes in the power drawn by the plasma chamber. Typically, such tuning of the matching network takes at least 100 μs to 200 μs. In some embodiments, the power change can occur within one or two RF cycles (e.g., 2.5 μs to 5.0 μs at 400 kHz).

[0157] In this example, the energy recovery circuit 110 can be positioned on or electrically coupled to the secondary side of the transformer T1. For example, the energy recovery circuit 110 can include a diode 130 (e.g., a crowbar diode) across the secondary side of the transformer T1. For example, the energy recovery circuit 110 can include an energy recovery diode 120 and an energy recovery inductor 115 (arranged in series), which can allow current to flow from the secondary side of the transformer T1 to charge the storage capacitor C7 and allow current to flow to the load stage 106. The energy recovery diode 120 and the energy recovery inductor 115 can be electrically connected to the secondary side of the transformer T1 and coupled to the energy storage capacitor C7. In some embodiments, the energy recovery circuit 110 can include a diode 130 and / or an inductor 140 electrically coupled to the secondary side of the transformer T1. The energy recovery inductor 115 can represent the stray inductance of the transformer T1 and / or can include stray inductance.

[0158] When the nanosecond pulse generator is on, current can charge capacitors in the load stage 106 (e.g., capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of transformer T1 rises above the charge voltage on energy storage capacitor C7, some current can flow through energy recovery inductor 115. When the nanosecond pulse generator is off, current can flow from capacitors within the load stage 106 (e.g., capacitor C1) through energy recovery inductor 115 to charge energy storage capacitor C7 until the voltage across energy recovery inductor 115 reaches zero. Diode 130 can prevent capacitors within the load stage 106 from looping with the inductance of the load stage 106 or the active bias compensation circuit 134.

[0159] For example, the energy recovery diode 120 may prevent charge from flowing from the energy storage capacitor C7 to capacitors within the load stage 106 .

[0160] The value of the energy recovery inductor 115 may be selected to control the current fall time. In some embodiments, the energy recovery inductor 115 may have an inductance value between 1 μH and 500 μH.

[0161] In some embodiments, the energy recovery circuit 110 can include a switch that can be used to control the flow of current through the energy recovery inductor 115. For example, the switch can be placed in series with the energy recovery inductor 115. In some embodiments, when the switch S1 is open and / or no longer pulsing, the switch can be closed to allow current to flow from the load stage 106 back to the energy storage capacitor C7.

[0162] For example, the switches in the energy recovery circuit 110 may include high voltage switches (e.g., such as Figure 14 High voltage switch 1400 shown).

[0163] Figure 8 8 are waveforms of voltage and current within the unmatched driver system 700. Waveform 805 represents the voltage on the wafer measured at the point labeled 124 (e.g., on the electrode). Waveform 810 represents the voltage into the load stage 106 measured at the location labeled 122 (e.g., on the wafer). Waveform 815 represents the current through the energy recovery diode 120.

[0164] Figure 9FIG2 is a schematic diagram of a spatially variable wafer bias system 900 according to some embodiments. The spatially variable wafer bias system 900 may include a first high-voltage pulse generator 925 coupled to a first energy recovery circuit 926 and a second high-voltage pulse generator 930 coupled to a second energy recovery circuit coupled to a plasma chamber 935. One or both of the first energy recovery circuit 926 and the second energy recovery circuit 931 may include all or some components of the energy recovery circuit 110 or the active energy recovery circuit 111.

[0165] In this example, the first high voltage pulse generator 925 is coupled with the first energy recovery circuit 926 and the first bias capacitor 915 , and / or the second high voltage pulse generator 930 is coupled with the second energy recovery circuit 931 and the second bias capacitor 921 .

[0166] A first electrode 950 and a second electrode 955 can be disposed in the plasma chamber 935. In this example, the first electrode 950 is disk-shaped and disposed within the central aperture of the second electrode 955. A first high-voltage pulse generator 925 is electrically coupled to the first electrode 950, and a second high-voltage pulse generator 930 is electrically coupled to the second electrode 955. In some embodiments, a stray coupling capacitance 965 may exist between the first high-voltage pulse generator 925 and the second high-voltage pulse generator 930. For example, the stray coupling capacitance 965 may be less than approximately 100 pF, approximately 1 nF, approximately 10 nF, etc.

[0167] In some embodiments, one or both of the first high voltage pulse generator 925 and the second high voltage pulse generator 930 may be coupled to a bias circuit (such as, for example, the DC bias circuit 104 , the passive bias compensation circuit 114 , or the active bias compensation circuit 134 ).

[0168] In some embodiments, the energy storage capacitor C7 in the first nanosecond pulse generator 925 can be coupled to a first DC power source, and the energy storage capacitor C7 in the second nanosecond pulse generator 930 can be coupled to a second DC power source.

[0169] In some embodiments, the energy storage capacitor C7 in the first nanosecond pulse generator 925 and the energy storage capacitor C7 in the second nanosecond pulse generator 930 can be coupled to a single DC power supply.

[0170] In some embodiments, both the first nanosecond pulse generator 925 and the second nanosecond pulse generator 930 can be coupled to the same energy storage capacitor, which can be coupled to a DC power source.

[0171] In some embodiments, switch S6 can be open for a different period of time than switch S7. The amount of time a switch is closed can correspond to the voltage applied to the corresponding electrode. In order to provide different voltages to different electrodes, each switch can be open for a different period of time.

[0172] One or both of the first nanosecond pulse generator 925 and the second nanosecond pulse generator 930 may include the passive bias compensation circuit 114 , the active bias compensation circuit 134 , or the DC bias circuit 104 .

[0173] Figure 10 FIG1 is a circuit diagram of a nanosecond pulse generator system 1000 with an energy recovery circuit 110, according to some embodiments. In this example, nanosecond pulse generator system 1005 is similar to nanosecond pulse generator system 100, with nanosecond pulse generator stage 101 switching the polarity of energy storage capacitor C7. When switch S6 is open, charge on capacitor C1 flows through energy recovery circuit 110 to high-voltage energy storage capacitor C7, charging high-voltage energy storage capacitor C7. When the charge on capacitor C1 becomes less than the charge on high-voltage energy storage capacitor C7, current stops flowing through energy recovery circuit 110. In some embodiments, DC bias circuit 104 can be replaced with passive bias compensation circuit 114 or active bias compensation circuit 134. In some embodiments, energy recovery circuit 110 can be replaced with active energy recovery circuit 111.

[0174] In some embodiments, including a ground side (see, e.g., Figure 1 ) or the positive side of the power supply V1 and / or C7 (see e.g. Figure 10 ) for switching. Either arrangement may be used. A diagram showing one arrangement may be substituted for a diagram showing another arrangement.

[0175] Figure 11 Show Figure 10 Figure 1 shows waveforms of voltage and current within nanosecond pulse generator system 1000. Waveform 1105 represents the current through energy recovery inductor 115. Waveform 1110 represents the voltage entering load stage 106 measured at the location labeled 124 (e.g., on the electrode). Waveform 1115 represents the wafer voltage measured at the location labeled 122 (e.g., on the wafer). As shown, when the pulse is off, current flows through energy recovery inductor 115, which charges high-voltage energy storage capacitor C7. In this specific example, the capacitive load is 500 pF and the energy recovery inductor 115 is 10 μH.

[0176] Figure 12is a circuit diagram of a nanosecond pulse generator system 1200 with an energy recovery circuit 110 driving a capacitive load 1205, according to some embodiments. In this example, the nanosecond pulse generator system 1200 is similar to the nanosecond pulse generator system 100, without the DC bias circuit 104, and is driving a capacitive load 1205. The capacitive load 1205 can include any type of load (e.g., such as a plasma load, multiple grids, multiple electrodes, etc.).

[0177] Figure 13 Show Figure 12 Figure 1 shows waveforms of voltage and current within nanosecond pulse generator system 1200. Waveform 1305 represents the voltage at capacitive load 1205, and waveform 1310 represents the current through energy recovery inductor 115. As shown, when the pulse is off, current flows through energy recovery inductor 115 to charge high-voltage energy storage capacitor C7. In this specific example, load C1 is 500 pF and energy recovery inductor 115 is 10 μH.

[0178] Figure 14 1 is a block diagram of a high voltage switch 1400 with isolated power according to some embodiments. The high voltage switch 1400 may include a plurality of switch modules 1405 (collectively or individually 1405, and individually 1405A, 1405B, 1405C, and 1405D) that may switch a voltage from a high voltage source 1460 with a fast rise time and / or high frequency and / or variable pulse width. Each switch module 1405 may include a switch 1410 (e.g., such as a solid-state switch).

[0179] In some embodiments, the switch 1410 can be electrically coupled to a gate driver circuit 1430, which can include a power supply 1440 and / or an isolated fiber optic trigger 1445 (also referred to as a gate trigger or switch trigger). For example, the switch 1410 can include a collector, an emitter, and a gate (or a drain, a source, and a gate), and the power supply 1440 can drive the gate of the switch 1410 via the gate driver circuit 1430. For example, the gate driver circuit 1430 can be isolated from other components of the high voltage switch 1400.

[0180] In some embodiments, for example, an isolation transformer can be used to isolate power supply 1440. The isolation transformer can include a low-capacitance transformer. For example, the low capacitance of the isolation transformer can allow power supply 1440 to charge quickly without requiring significant current. For example, the isolation transformer can have a capacitance of less than approximately 100 pF. As another example, the isolation transformer can have a capacitance of less than approximately 30-100 pF. In some embodiments, the isolation transformer can provide voltage isolation of up to 1 kV, 5 kV, 10 kV, 25 kV, 50 kV, etc.

[0181] In some embodiments, the isolation transformer can have low stray capacitance. For example, the isolation transformer can have a stray capacitance of less than approximately 1,000 pF, 100 pF, 10 pF, etc. In some embodiments, the low capacitance can minimize electrical coupling to low-voltage components (e.g., a source of input control power) and / or can reduce EMI generation (e.g., electrical noise generation). In some embodiments, the transformer stray capacitance of the isolation transformer can include the capacitance measured between the primary winding and the secondary winding.

[0182] In some embodiments, the isolation transformer can be a DC to DC converter or an AC to DC transformer. In some embodiments, for example, the transformer can include a 110V AC transformer. Regardless, the isolation transformer can provide a power supply that is isolated from other components in the high-voltage switch 1400. In some embodiments, the isolation can be galvanic so that conductors on the primary side of the isolation transformer do not pass through or come into contact with the secondary side of the isolation transformer.

[0183] In some embodiments, the transformer may include a primary winding that may be tightly wound or wrapped around the transformer core. In some embodiments, the primary winding may include a conductive sheet wrapped around the transformer core. In some embodiments, the primary winding may include one or more windings.

[0184] In some embodiments, the secondary winding can be wound around the core as far away from the core as possible. For example, the winding bundle comprising the secondary winding can be wound through the center of the aperture in the transformer core. In some embodiments, the secondary winding can include one or more windings. In some embodiments, the wire bundle comprising the secondary winding can include a circular or square cross-section, for example, to minimize stray capacitance. In some embodiments, an insulator (e.g., oil or air) can be disposed between the primary winding, the secondary winding, or the transformer core.

[0185] In some embodiments, keeping the secondary winding away from the transformer core can have several benefits. For example, it can reduce stray capacitance between the primary side of the isolation transformer and the secondary side of the isolation transformer. As another example, it can allow high voltages between the primary side of the isolation transformer and the secondary side of the isolation transformer to be isolated so that corona and / or breakdown do not form during operation.

[0186] In some embodiments, the spacing between the primary side of the isolation transformer (e.g., the primary winding) and the secondary side of the isolation transformer (e.g., the secondary winding) can be approximately 0.1", 0.5", 1", 5", or 10". In some embodiments, a typical spacing between the core of the isolation transformer and the secondary side of the isolation transformer (e.g., the secondary winding) can be approximately 0.1", 0.5", 1", 5", or 10". In some embodiments, the gap between the windings can be filled with the lowest dielectric material possible (e.g., such as a vacuum, air, any insulating gas or liquid, or a solid material with a relative dielectric constant less than 3).

[0187] In some embodiments, power supply 1440 may include any type of power supply that can provide high voltage isolation (for example, less than approximately 1,000 pF, 100 pF, 10 pF, etc.) or low capacitance. In some embodiments, the control voltage power supply may provide 1420V AC or 240V AC at 60 Hz.

[0188] In some embodiments, each power supply 1440 can be electrically coupled inductively to a single control voltage source. For example, power supply 1440A can be electrically coupled to the power source via a first transformer; power supply 1440B can be electrically coupled to the power source via a second transformer; power supply 1440C can be electrically coupled to the power source via a third transformer; and power supply 1440D can be electrically coupled to the power source via a fourth transformer. For example, any type of transformer that can provide voltage isolation between the various power supplies can be used.

[0189] In some embodiments, the first transformer, the second transformer, the third transformer, and the fourth transformer may include different secondary windings around the core of a single transformer. For example, the first transformer may include a first secondary winding, the second transformer may include a second secondary winding, the third transformer may include a third secondary winding, and the fourth transformer may include a fourth secondary winding. Each of these secondary windings may be wound around the core of a single transformer. In some embodiments, the first secondary winding, the second secondary winding, the third secondary winding, the fourth secondary winding, or the primary winding may include a single winding or multiple windings wound around the transformer core.

[0190] In some embodiments, power supply 1440A, power supply 1440B, power supply 1440C, and / or power supply 1440D may not share a return reference ground or local ground.

[0191] For example, the isolated fiber optic trigger 1445 can also be isolated from other components of the high voltage switch 1400. The isolated fiber optic trigger 1445 can include a fiber optic receiver that allows each switch module 1405 to float relative to the other switch modules 1405 and / or other components of the high voltage switch 1400 and / or, for example, simultaneously allows active control of the gate of each switch module 1405.

[0192] In some embodiments, the return reference grounds for each switching module 1405 may be isolated from each other, either locally or commonly, for example, using isolation transformers.

[0193] For example, the electrical isolation of each switch module 1405 from a common ground can allow for multiple switches to be arranged in a series configuration for cumulative high voltage switching. In some embodiments, some hysteresis in the timing of the switch modules can be allowed for or designed in. For example, each switch module 1405 can be configured or rated to switch 1 kV, each switch module can be electrically isolated from each other, and / or the timing of closing each switch module 1405 may not need to be perfectly aligned for a period of time defined by the capacitance of the buffer capacitor and / or the rated voltage of the switch.

[0194] In some embodiments, electrical isolation can provide a number of advantages. For example, one possible advantage may include minimizing switch-to-switch jitter and / or allowing for arbitrary switch timing. For example, each switch 1410 may have a switch transition jitter of less than approximately 500 ns, 50 ns, 20 ns, 5 ns, etc.

[0195] In some embodiments, electrical isolation between two components (or circuits) may imply an extremely high resistance between the two components, and / or may imply a small capacitance between the two components.

[0196] Each switch 1410 may include any type of solid-state switching device (e.g., an IGBT, MOSFET, SiC MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc.). For example, the switches 1410 may be capable of switching high voltages (e.g., voltages greater than approximately 10 ms) at high frequencies (e.g., greater than 1 kHz), at high speeds (e.g., repetition rates greater than approximately 500 kHz), and / or with fast rise times (e.g., rise times less than approximately 25 ns), and / or with long pulse lengths (e.g., greater than approximately 10 ms). In some embodiments, each switch may be individually rated for switching 1,200 V to 1,700 V, while the combined switch may be capable of switching greater than 4,800 V to 6,800 V (for all four switches). Switches with various other voltage ratings may also be used.

[0197] There are some advantages to using a large number of lower-voltage switches rather than a small number of higher-voltage switches. For example, low-voltage switches typically have better performance: they can switch faster, have faster transition times, and / or switch more efficiently than high-voltage switches. However, for example, the greater the number of switches, the greater the need for switch timing accuracy.

[0198] Figure 14 The illustrated high-voltage switch 1400 includes four switch modules 1405. Although four are shown in this figure, any number of switch modules 1405 may be used (e.g., two, eight, twelve, sixteen, twenty, twenty-four, etc.). For example, if each switch in each switch module 1405 is rated at 1200V and sixteen switches are used, the high-voltage switch can switch up to 19.2kV. As another example, if each switch in each switch module 1405 is rated at 1700V and sixteen switches are used, the high-voltage switch can switch up to 27.2kV.

[0199] In some embodiments, the high voltage switch 1400 can switch voltages greater than 5 kV, 10 kV, 14 kV, 20 kV, 25 kV, etc.

[0200] In some embodiments, high voltage switch 1400 may include a flying capacitor 1455. For example, flying capacitor 1455 may include one or more capacitors arranged in series and / or parallel. For example, these capacitors may include one or more polypropylene capacitors. Flying capacitor 1455 may store energy from high voltage source 1460.

[0201] In some embodiments, the flying capacitor 1455 can have a low capacitance. In some embodiments, the flying capacitor 1455 can have a capacitance value of about 1 μF, about 5 μF, between about 1 μF and about 5 μF, between about 100 nF and about 1,000 nF, etc.

[0202] In some embodiments, the high-voltage switch 1400 may or may not include an arc-quenching diode 1450. The arc-quenching diode 1450 may include multiple diodes arranged in series or parallel, which can be beneficial, for example, for driving inductive loads. In some embodiments, the arc-quenching diode 1450 may include one or more Schottky diodes (e.g., such as silicon carbide Schottky diodes). For example, the arc-quenching diode 1450 can sense whether the voltage from the switch in the high-voltage switch is above a specific threshold. If so, the arc-quenching diode 1450 can short-circuit the power from the switching module to ground. For example, the arc-quenching diode can allow an alternating current path to dissipate energy stored in the inductive load after switching. This can, for example, prevent large inductive voltage spikes. In some embodiments, the arc-quenching diode 1450 can have a low inductance (e.g., such as 1 nH, 10 nH, 100 nH, etc.). In some embodiments, the arc-quenching diode 1450 can have a low capacitance (e.g., such as 100 pF, 1 nF, 10 nF, 100 nF, etc.).

[0203] In some embodiments, such as, for example, when the load 1465 is primarily resistive, the crowbar diode 1450 may not be used.

[0204] In some embodiments, each gate driver circuit 1430 can generate jitter of less than approximately 1000 ns, 100 ns, 10.0 ns, 5.0 ns, 3.0 ns, 1.0 ns, etc. In some embodiments, each switch 1410 can have a minimum on-time (e.g., less than approximately 10 μs, 1 μs, 500 ns, 100 ns, 50 ns, 10 ns, 5 ns, etc.) and a maximum on-time (e.g., greater than 25 seconds, 10 seconds, 5 seconds, 1 second, 500 milliseconds, etc.).

[0205] In some embodiments, during operation, each of the high voltage switches may be turned on and / or off within 1 ns of each other.

[0206] In some embodiments, each switch module 1405 can have the same or substantially the same (±5%) stray inductance. Stray inductance can include any inductance within the switch module 1405 that is not associated with the inductor (e.g., such as inductance in leads, diodes, resistors, switches 1410, and / or circuit board traces, etc.). The stray inductance within each switch module 1405 can include low inductance (e.g., such as less than approximately 300nH, 100nH, 10nH, 1nH, etc.). The stray inductance within each switch module 1405 can include low inductance (e.g., such as less than approximately 300nH, 100nH, 10nH, 1nH, etc.).

[0207] In some embodiments, each switch module 1405 can have the same or substantially the same (±5%) stray capacitance. Stray capacitance can include any capacitance within the switch module 1405 that is not associated with a capacitor (e.g., such as capacitance in leads, diodes, resistors, switches 1410, and / or circuit board traces, etc.). The stray capacitance within each switch module 1405 can include low capacitance (e.g., such as less than approximately 1,000 pF, 100 pF, 10 pF, etc.). The stray capacitance within each switch module 1405 can include low capacitance (e.g., such as less than approximately 1,000 pF, 100 pF, 10 pF, etc.).

[0208] For example, imperfections in voltage sharing can be addressed using passive snubber circuits (e.g., snubber diode 1415, snubber capacitor 1420, and / or freewheeling diode 1425). For example, small differences in timing between the on and off of each of switches 1410, or differences in inductance or capacitance, can cause voltage spikes. These spikes can be mitigated using various snubber circuits (e.g., snubber diode 1415, snubber capacitor 1420, and / or freewheeling diode 1425).

[0209] For example, the snubber circuit may include a snubber diode 1415, a snubber capacitor 1420, a snubber resistor 1416, and / or a freewheeling diode 1425. In some embodiments, the snubber circuit may be arranged in parallel with the switch 1410. In some embodiments, the snubber capacitor 1420 may have a low capacitance (e.g., such as a capacitance of less than about 100 pF).

[0210] In some embodiments, the high voltage switch 1400 can be electrically coupled to or include a load 1465 (e.g., a resistive, capacitive, or inductive load). For example, the load 1465 can have a resistance of 50 ohms to 500 ohms. Alternatively or additionally, the load 1465 can be an inductive load or a capacitive load.

[0211] In some embodiments, the energy recovery circuit 110 or the active energy recovery circuit 111 can reduce the energy consumption of a high voltage nanosecond pulse generator system and / or the voltage required to drive a given load with the same energy output performance as a system without the energy recovery circuit. For example, for the same energy output performance as a system without the energy recovery circuit, the energy consumption can be reduced by as much as 10%, 15%, 20%, 25%, 30%, 40%, 45%, 50%, or more.

[0212] In some embodiments, diode 130 , diode 135 , and / or energy recovery diode 120 may include high voltage diodes.

[0213] Figure 15 is a block diagram of a process 1500 for operating a nanosecond pulse generator system with an active energy recovery circuit and an active bias compensation circuit, according to some embodiments. Process 1500 may include additional blocks. The blocks shown in process 1500 may be removed, replaced, skipped, or performed in any order.

[0214] For example, process 1500 may be performed using a nanosecond pulse generator system 600 having an active energy recovery circuit 111 and an active bias compensation circuit 134 or similar circuits.

[0215] In some embodiments, a nanosecond pulse generator can be used to generate multiple bursts, wherein each burst includes multiple pulses. The pulses can be generated by turning the nanosecond pulse generator on and off. For example, the pulse width of each pulse can be varied from 10 seconds to 10 ns. For example, the pulse frequency can be varied from 10 kHz to 1 MHz (e.g., 400 kHz). Each burst can include a set number of pulses. Each burst can have a burst width that defines the time it takes to complete the multiple pulses.

[0216] Process 1500 may begin at block 1505 where a counter n is set to be initialized to 1. Counter n counts the number of pulses in a given burst.

[0217] At block 1510 , a bias compensation switch (eg, switch S8 ) may be opened.

[0218] At block 1515 , a nanosecond pulse generator switch (eg, switch S6 ) may be closed.

[0219] At block 1520 , an energy recovery switch (eg, switch S5 ) may be opened.

[0220] In some embodiments, blocks 1510, 1515, and 1520 may occur substantially simultaneously or within 10 ns or 100 ns, etc. In some embodiments, blocks 1515 and 1520 may occur substantially simultaneously.

[0221] At block 1525, process 1500 may pause (e.g., pulse) for a time period that defines the pulse width of each pulse. In some embodiments, the pulse width of the pulse can define the voltage of the pulse at the load (e.g., such as a capacitive load) by defining the amount of time the load is charged to a particular voltage. For example, the output voltage at the capacitive load generated by the pulse can depend on the amount of time the nanosecond pulse generator switch is closed and, therefore, the amount of time the pulse is charging the capacitive load. Thus, the output voltage at the load of the pulse can be defined by a voltage pause period that is up to the maximum output voltage of the nanosecond pulse generator or some multiple of the maximum output voltage of the nanosecond pulse generator (if it is pulsing into an inductor and / or capacitor, generating some voltage looping). For example, the voltage pause can be from about 10 ns to about 500 ns, or from about 50 ns to about 200 ns, or 500 ns, 73.75 ns, 27 ns, 16 ns, or 12.5 ns.

[0222] At block 1530 , a nanosecond pulse generator switch (eg, switch S6 ) may be opened.

[0223] At block 1535 , an energy recovery switch (eg, switch S5 ) may be closed.

[0224] In some embodiments, blocks 1530 and 1535 may occur substantially simultaneously.

[0225] At block 1540, a determination may be made as to whether counter n is equal to the desired number of pulses N. While there is no limit on the number of pulses in a burst, the desired number of pulses N may be, for example, 5 to 1,000. In some embodiments, the pulses may run continuously. Thus, N may be virtually infinite. If counter n is not equal to the desired number of pulses N (i.e., fewer than the desired number of pulses have occurred in the burst), process 1500 proceeds to block 1545.

[0226] At block 1545, process 1500 may pause for a time period that may partially define the pulse frequency (e.g., a pulse pause). For example, the pulse pause time period may be less than 500ns, 250ns, 100ns, 50ns, 10ns, 5ns, etc. For example, the pulse pause time period may include any time period.

[0227] At block 1550, counter n is incremented, and portions of process 1500 may be repeated to create additional pulses by proceeding to block 1515. At block 1540, if counter n is equal to the desired number of pulses N (i.e., the desired number of pulses has been created), process 1500 proceeds to block 1555. At block 1555, the bias compensation switch (e.g., switch S8) may be closed.

[0228] At block 1560, process 1500 pauses for a time period that defines the amount of time between bursts (e.g., a burst pause). For example, the burst pause time period can be as short as 1 ms or as long as 20 seconds. For example, a pulse pause can include a time period between 2.5 microseconds (for a pulse frequency of 200 Hz) and 100 ms. As another example, a pulse pause can be from 10 ms to several hours. Any other time period can be used. After the time period has elapsed, process 1500 can return to block 1505, where counter n is initialized, and process 1500 can be repeated to create additional bursts with additional pulses.

[0229] When the nanosecond pulse generator switch is closed, the energy recovery switch is open, and the bias compensation switch is open, a high voltage pulse (eg, greater than 1 kV) may be generated at circuit location 124 .

[0230] In some embodiments, the pulse pause period may be smaller than the burst pause period.

[0231] In some embodiments, blocks 1520 and 1535 can be eliminated from process 1500. In these embodiments, a high voltage pulse (e.g., greater than 1 kV) can be generated at circuit location 124 when the energy recovery switch is not used, the nanosecond pulse generator switch is closed, and the bias compensation switch is open.

[0232] In some embodiments, a controller (or processor) (e.g., such as Figure 16 16) executes the blocks of process 1500. For example, the controller can communicate with switch S6 via Sig6+ and Sig6-, with bias compensation switch S8 via Sig8+ and Sig8-, and / or with energy recovery switch S5 via Sig5+ and Sig5-. The controller can provide signals to open and close the nanosecond pulse generator switch, the energy recovery switch, and / or the bias compensation switch.

[0233] Figure 16The computing system 1600 shown may be used to perform any embodiment of the present invention. For example, the computing system 1600 may be used to perform process 1500. As another example, the computing system 1600 may be used to perform any calculation, identification, and / or determination described herein. The computing system 1600 includes hardware elements that may be electrically coupled via a bus 1605 (or, where appropriate, may communicate in other ways). The hardware elements may include: one or more processors 1610, including but not limited to one or more general-purpose processors and / or one or more special-purpose processors (e.g., digital signal processing chips, graphics acceleration chips, etc.); one or more input devices 1615, including but not limited to a mouse, keyboard, etc.; and one or more output devices 1620, including but not limited to a display device, printer, etc.

[0234] The computing system 1600 may also include (and / or communicate with) one or more storage devices 1625, which may include, but are not limited to, local and / or network-accessible storage, and / or may include, but are not limited to, disk drives, drive arrays, optical storage devices, solid-state storage devices (e.g., random access memory ("RAM") and / or read-only memory ("ROM")), which may be programmable, flash-updatable, etc. The computing system 1600 may also include a communication subsystem 1630, which may include, but are not limited to, a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device, and / or a chipset (e.g., a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMax device, a cellular communication facility, etc.). The communication subsystem 1630 may allow data to be exchanged with a network (e.g., the networks described below, to name just one example) and / or any other device described herein. In many embodiments, as described above, the computing system 1600 will also include a working memory 1635, which may include a RAM or ROM device.

[0235] The computing system 1600 may also include software elements, shown as currently located within the working memory 1635, including an operating system 1640 and / or other code (e.g., one or more application programs 1645, which may include computer programs of the present invention and / or may be designed to implement the methods of the present invention and / or configure the systems of the present invention), as described herein. For example, one or more of the processes described with respect to the methods discussed above may be implemented as code and / or instructions executable by a computer (and / or a processor within a computer). A collection of these instructions and / or code may be stored on a computer-readable storage medium (e.g., the storage device 1625 described above).

[0236] In some cases, the storage medium may be incorporated within or in communication with computing system 1600. In other embodiments, the storage medium may be separate from computing system 1600 (e.g., removable media (e.g., a compact disk, etc.)) and / or provided in an installation package such that the storage medium can be used to program a general-purpose computer with instructions / code stored thereon. These instructions may take the form of executable code that can be executed by computing system 1600 and / or may take the form of source code and / or installable code that, when compiled and / or installed on computing system 1600 (e.g., using any of a variety of commonly available compilers, installers, compression / decompression utilities, etc.), then takes the form of executable code.

[0237] Figure 17 is a schematic diagram of a spatially variable wafer bias system 1700 according to some embodiments. The spatially variable wafer bias system 1700 may include a first high-voltage pulse generator 1725, a second high-voltage pulse generator 1730, a first energy recovery circuit 1726, and a second energy recovery circuit 1731. Both the first energy recovery circuit 1726 and the second energy recovery circuit 1731 are coupled to a single energy storage capacitor C7. In some embodiments, each of the energy recovery circuit 1726 or the energy recovery circuit 1731 may include one or more diodes and / or inductors coupled to the secondary side of each transformer. In some embodiments, the energy recovery circuit 1726 or the energy recovery circuit 1731 may include a switch (e.g., as described above) to allow current to flow through the energy recovery circuit after each pulse.

[0238] Figure 18 is a circuit diagram of an RF driver system 1800 including an RF driver 1805, an active bias compensation circuit 134, and an energy recovery circuit 110 according to some embodiments. In this example, the RF driver system 1800 is similar to the unmatched RF system 700, wherein the RF driver 705 and the resonant circuit 710 are replaced by the RF driver 1805. Figure 7 The illustrated RF driver 705 includes a full-wave rectifier and a resonant circuit 710 .

[0239] In some embodiments, the RF driver 1805 may include a plurality of high frequency solid-state switches, an RF generator, an amplifier tube-based RF generator, or a tube-based RF generator.

[0240] The RF driver system 1800 may not include a conventional matching network (e.g., such as a 50 ohm matching network or an external matching network or a standalone matching network). In some embodiments, the RF driver system 1800 does not require a 50 ohm matching network to tune the switching power applied to the wafer chamber. The RF generator without a conventional matching network can allow for rapid changes in the power drawn by the plasma chamber. Typically, such tuning of the matching network takes at least 100 μs to 200 μs. In some embodiments, the power change can occur within one or two RF cycles (e.g., 2.5 μs to 5.0 μs at 400 kHz).

[0241] In some embodiments, the RF driver 1805 may operate at a frequency of approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0242] One or both of the first nanosecond pulse generator 1725 and the second nanosecond pulse generator 1730 may include a passive bias compensation circuit 114 , an active bias compensation circuit 134 , or a DC bias circuit 104 .

[0243] Figure 19 1 is a circuit diagram of a nanosecond pulse generator system 1900 according to some embodiments. The nanosecond pulse generator system 1900 includes a nanosecond pulse generator 105 , a primary absorber 1906 , a transformer T1 , and a load stage 1915 .

[0244] In some embodiments, the nanosecond pulse generator 105 can generate pulses with a high pulse voltage (e.g., a voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high frequency (e.g., a frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., a rise time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), a fast fall time (e.g., a fall time less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.) and / or a short pulse width (e.g., a pulse width less than approximately 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0245] For example, the nanosecond pulse generator 105 may include: all or any portion of any device described in U.S. patent application serial number 14 / 542,487, entitled “High Voltage Nanosecond Pulser,” which is incorporated into this disclosure for all purposes; all or any portion of any device described in U.S. patent application serial number 14 / 635,991, entitled “Galvanically Isolated Output Variable Pulse Generator Disclosure,” which is incorporated into this disclosure for all purposes; or all or any portion of any device described in U.S. patent application serial number 14 / 798,154, entitled “High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency,” which is incorporated into this disclosure for all purposes.

[0246] In some embodiments, the nanosecond pulse generator 105 includes a switch S1 coupled to a power source C7 (e.g., an energy storage capacitor that can be coupled to the power source). The power source C7 can provide a consistent DC voltage that is switched by the switch S1 and provides the switched power to the transformer T1. For example, the switch S1 can include one or more solid-state switches (e.g., such as an IGBT, a MOSFET, a SiC MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc.). In some embodiments, a gate resistor coupled to the switch S1 can be provided with a short turn-on pulse.

[0247] In some embodiments, resistor R8 and / or resistor R5 may represent stray resistance within nanosecond pulse generator 105. In some embodiments, inductor L3 and / or inductor L1 may represent stray inductance within nanosecond pulse generator 105.

[0248] In some embodiments, the nanosecond pulse generator 105 may include a snubber circuit, which may include a snubber resistor R1 and a snubber inductor L3. Both the snubber resistor R1 and the snubber inductor L3 may be arranged in parallel with a snubber diode D2. The snubber circuit may also include a snubber capacitor C5. In some embodiments, the snubber resistor R1 and the snubber inductor L3 and / or the snubber diode D2 may be placed between the collector of the switch S1 and the primary winding of the transformer T1. The snubber diode D2 may be used to buffer any overvoltages during switching. A large and / or fast capacitor C5 may be coupled to the emitter side of the switch S1. A freewheeling diode D1 may also be coupled to the emitter side of the switch S1. Various other components not shown in the figure may be included.

[0249] In some embodiments, a freewheeling diode D1 may be used in conjunction with an inductive load to ensure that the energy stored in the inductor can be dissipated after the switch S1 is opened by allowing the current to continue flowing in the same direction through the inductor, and the energy is dissipated in the resistive elements of the circuit. If they are not used, this may result in a large reverse voltage across the switch S1, for example.

[0250] In some embodiments, the primary absorber 1906 can be deployed in parallel with the switch S1 (and the snubber circuit). For example, the primary absorber 1906 can include an absorber diode D6, a resistor R2, and an absorber inductor L6 arranged in series. In some embodiments, the resistor R2 can include one or more resistors having a resistance of approximately 100 ohms. In some embodiments, the absorber inductor L6 can include one or more inductors having an inductance of approximately 100 μH. In some embodiments, the resistor R2 can include multiple resistors arranged in parallel and / or in series. In some embodiments, the absorber inductor L6 can include multiple inductors arranged in parallel and / or in series.

[0251] In some embodiments, the snubber diode D6 may be arranged to allow current to flow from the transformer T1 to ground.

[0252] In some embodiments, the snubber diode D6 , the resistor R2 , and the snubber inductor L6 are arranged in parallel with the transformer T1 .

[0253] In some embodiments, resistor R2 and snubber inductor L6 are disposed on the primary side of transformer T1 .

[0254] The use of a primary absorber to achieve high voltage pulses at high frequencies with fast rise / fall times and / or short pulse widths can constrain the selection of circuit elements (e.g., R2 and L6) in the resistive output stage. The primary absorber can be selected to handle high average power, high peak power, fast rise and / or fast fall times. For example, the average power rating can be greater than approximately 10 W, 50 W, 100 W, 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., the peak power rating can be greater than approximately 1 kW, 10 kW, 100 kW, 1 MW, etc., and / or the rise and fall times can be less than 1000 ns, 100 ns, 10 ns, or 1 ns.

[0255] High average power and / or peak power requirements may arise from the need to quickly dissipate the energy stored in the load stage 1915, and / or from the need to do so at a high frequency. For example, if the load stage 1915 is capacitive in nature (e.g., Figure 1As shown, with capacitor C12, there is a 1 nF capacitor that needs to be discharged within 20 ns, and if the primary absorber can be purely resistive (e.g., the minimum value of L6), the primary absorber can have a resistance value of about 12.5 m ohms. If the high voltage pulse applied to the load is 100 ns long at 20 kV, each pulse will dissipate about 2 J during the 100 ns pulse width (e.g., E = t p V p 2 / R) and an additional 0.2J of stored energy depleted from the 1nF capacitive load (e.g. E = 1 / 2t p CV s 2 ), where t p is the pulse width, V is the pulse voltage, R2 is the resistance of the primary absorber, C is the capacitance of the load, V p is the voltage on the primary side of the transformer, V s is the voltage on the secondary side of the transformer, and E is the energy. If operated at 10 kHz, a total energy dissipation of 2.2 J per pulse can result in an average power dissipation of 22 kW into the primary absorber. The peak power dissipation in the primary absorber during a pulse can be approximately 20 MW and can be calculated as Power = V2 / R.

[0256] For example, high frequency and high voltage operation combined with the need for low resistance in the primary absorber can result in an example having one or both of high peak power and high average power dissipation within the primary absorber. Standard pull-down resistors (e.g., around 5 volts) used in TTL type circuits and / or data acquisition type circuits typically operate well below 1 W for both average and peak power dissipation.

[0257] In some embodiments, for example, the ratio of power dissipated by primary snubber 1906 compared to the total power dissipated by load stage 1915 can be 10%, 20%, 30%, or more. In standard low voltage electronic circuits, pull-down resistors dissipate less than 1% of the consumed power, and typically much less.

[0258] Fast rise time and / or fast fall time requirements can constrain both the allowable stray inductance and / or stray capacitance within the primary absorber. In the above example, for a 1 nF capacitive load to be discharged within about 20 ns, the series stray inductance in the primary absorber can be less than about 1,000 nH, 500 nH, 300 nH, 100 nH, 30 nH, etc. In some embodiments, L6 / R2 < tf. In some embodiments, for the L / R time of the primary absorber that does not waste significant additional energy attributable to its stray capacitance, such as less than 10% of the capacitive energy stored in the load capacitance, the L / R time of the stray capacitance of the primary absorber can be less than 100 pF. Since the primary absorber may tend to be physically large due to its high power dissipation requirements, achieving both such low stray inductance and stray capacitance can be challenging. The design typically requires a large number of parallel and series operations of a large number of discrete components (e.g., resistors), where the components are closely combined together, and / or spaced far from any ground surface that may significantly increase the stray capacitance.

[0259] In some embodiments, the load stage 1915 can include a dielectric barrier discharge device. The load stage 1915 in a dielectric barrier discharge can be predominantly capacitive. In some embodiments, the load can be modeled as a pure capacitive load CL (e.g., similar to a dielectric barrier discharge). For example, when the power supply P is turned on, the capacitive load CL can be charged, and when the power supply P is not turned on, the charge on the capacitive load CL can be depleted through the resistor R. Additionally, due to high voltage and / or high and / or fast fall time requirements, the primary absorber may need to discharge a significant amount of charge from the capacitive load CL, which may not be the case for low voltage applications (e.g., standard 5V logic levels and / or low voltage data pulse generators).

[0260] For example, a typical dielectric barrier discharge device can have a capacitance of about 10 pF and / or can be driven to about 20 kV with a rise time of about 20 ns and / or a fall time of about 20 ns. In some embodiments, the desired pulse width can be 80 ns long. To match the fall time to the rise time, the resistor R2 can be about 12.5 ohms, which can be used to create the desired fall time. Depending on the load and / or other circuit elements and / or requirements such as rise time, fall time, and / or pulse width, various other values can be used for the circuit element resistor R2.

[0261] In some embodiments, for a capacitive-like load, or a load with an effective capacitance C (e.g., capacitance C12), the characteristic pulse fall time can be designated as tf and the pulse rise time can be designated as tr. In some embodiments, the rise time tr can be set by the specifications of the driver power supply. In some embodiments, by selecting resistor R2, the pulse fall time tf can be approximately matched to the pulse rise time tr, where In some embodiments, R2 can be specifically selected to provide a specific relationship between the pulse rise time tr and the pulse fall time tf. This differs from the concept of a pull-down resistor, where, typically, a pull-down resistor is selected to carry / dissipate voltage / charge over a longer time scale and at a much lower power level. In some embodiments, resistor R2 can be specifically used as a replacement for a pull-down switch to establish a specific relationship between the pulse rise time tr and the pulse fall time tf.

[0262] In some embodiments, the power dissipated in resistor R2 during a pulse with pulse width tp and drive voltage V can be found from P=V2 / R. Because the fall time tf is directly proportional to the resistance R (e.g., ), so as the requirement for fall time tf decreases, so too does the requirement for resistance R, and the power P dissipated in resistor R2 increases according to P=V2C / tf. Therefore, resistor R2 can be designed to ensure the correct fall time tf but be able to handle high power (e.g., such as powers greater than approximately 1.0 kW or 100 kW). In some embodiments, the resistor can handle average power requirements as well as peak power requirements. The need for a fast fall time tf, which results in low resistance values ​​and the resulting high power dissipation, is a challenge that may make the primary absorber undesirable as a means for quickly removing charge from the capacitive load C2. In some embodiments, resistor R can comprise a resistor with a low resistance, but still have a high average power rating and a peak power rating.

[0263] In some embodiments, resistor R2 can include a series and / or parallel stack of resistors that collectively have a desired resistance and power rating. In some embodiments, resistor R2 can include a resistor having a resistance of less than approximately 2,000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 25 ohms, 10 ohms, 1 ohm, 0.5 ohms, 0.25 ohms, etc., and having an average power rating greater than approximately 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., and having a peak power rating greater than approximately 1 kW, 10 kW, 100 kW, 1 MW, etc.

[0264] Using the above example, where tp = 80ns, V = 500kV, and resistor R2 is 12.5k ohms, each pulse applied to the load can dissipate 16mJ once the capacitance in the load is fully charged. Once the pulse is turned off, the charge from the load is dissipated by resistor R2. If operating at 100kHz, resistor R2 can dissipate 1.6kW. If resistor R2 has been selected to create a 10ns t f , the power dissipated in resistor R2 will be 3.2kW. In some embodiments, the high voltage pulse width can be extended to 500ns. At 500ns, where tf=20ns, resistor R2 will dissipate 10kW.

[0265] In some embodiments, the power dissipated in resistor R2 may be considered significant if it exceeds 10% or 20% of the power dissipated by load stage 1915 .

[0266] When a fast fall time tf is required, the power dissipation may be significant (e.g., such as approximately one-third of the total power consumed). For example, if resistor R2 includes resistor R2 in series with absorber inductor L6, absorber inductor L6 may, for example, reduce the power entering resistor R while voltage V is present and / or accelerate the fall time beyond the fall time set by RC decay.

[0267] For example, the time constant L6 / R2 can be set to approximately the pulse width tp (e.g., L6 / R2 ≈ tp). For example, this can reduce energy dissipation and / or shorten the fall time tf (e.g., reduce tf). In some embodiments, R2 ≈ C / tf ≈ C / tr, assuming we want to match tf to tr. In this application, disclosure, and / or claims, the symbol "≈" indicates within ten times.

[0268] In some embodiments, transformer T1 may be part of nanosecond pulse generator 105 .

[0269] Figure 20 2 is a circuit diagram of a nanosecond pulse generator system 2000 according to some embodiments. The nanosecond pulse generator system 2000 includes a nanosecond pulse generator 105 , a primary absorber 2006 , a transformer T1 , and a load stage 1915 .

[0270] In some embodiments, the primary snubber 2006 can include a snubber switch S2 instead of or in addition to the snubber diode D6. In some embodiments, the snubber switch S2 can be arranged in series with the snubber inductor L6 and / or the snubber resistor R2.

[0271] In some embodiments, for example, when the load capacitance C2 is to be discharged through the absorber resistor R2 and / or the absorber inductor L6, the absorber switch S2 can be closed. For example, the absorber switch S2 can be turned on and / or off after each pulse to discharge the charge from the load capacitor C2. For example, during each pulse, the absorber switch S2 can be open. At the end of each pulse, the absorber switch S2 can be closed to discharge the load capacitance into the resistor R2. For example, when the switch S1 is open, the absorber switch S2 can be closed, and / or when the switch S1 is closed, the absorber switch S2 can be open.

[0272] In some embodiments, the absorber switch S2 may include Figure 14 The high voltage switch 1400 described in .

[0273] Figure 21 2 is a circuit diagram of a nanosecond pulse generator system 2100 according to some embodiments. The nanosecond pulse generator system 2100 includes a nanosecond pulse generator 2105 , a primary absorber 2106 , a transformer T1 , and a load stage 1915 .

[0274] In some embodiments, the nanosecond pulse generator 2105 may include a diode D9 disposed between the absorber switch S2 and the primary absorber 2106. The diode D9 may be arranged to allow current to flow through the switch S1 toward the transformer T1 and to limit current flow from the transformer T1 toward the switch S1.

[0275] The primary snubber 2106 can include the components of the primary snubber 1906 except for the snubber diode D6. In some embodiments, the primary snubber 2106 can include the snubber diode D6 and / or the snubber switch S2.

[0276] Figure 22 2 is a circuit diagram of a nanosecond pulse generator system 2200 according to some embodiments. The nanosecond pulse generator system 2200 includes the nanosecond pulse generator 105, a primary absorber 2206, a transformer T1, and a load stage 1915.

[0277] In some embodiments, the primary absorber 2206 can include an absorber switch S2 and an absorber diode D6. In some embodiments, the absorber switch S2 can be arranged in series with the absorber inductor L6 and / or the absorber resistor R2. In some embodiments, a crowbar diode D8 can be included across the absorber switch S2.

[0278] In some embodiments, for example, when the load capacitance C2 is to be discharged through the absorber resistor R2 and / or the absorber inductor L6, the absorber switch S2 can be closed. For example, the absorber switch S2 can be turned on and / or off after each pulse to discharge the charge from the load capacitor C2. For example, during each pulse, the absorber switch S2 can be open. At the end of each pulse, the absorber switch S2 can be closed to discharge the load capacitance into the resistor R2. For example, when the switch S1 is open, the absorber switch S2 can be closed, and / or when the switch S1 is closed, the absorber switch S2 can be open.

[0279] Figure 23 Show use Figure 21 The nanosecond pulse generator system 2100 is shown with a waveform 2305 showing the voltage at the input of the transformer T1 and a waveform 2310 showing the voltage at the load stage 1915 .

[0280] Figure 24 A nanosecond pulse generator system 2400 is shown in accordance with some embodiments. The nanosecond pulse generator system 2400 includes the nanosecond pulse generator 105 , a primary absorber 1906 , a transformer T1 , a bias compensation circuit 2410 , and a load stage 2415 .

[0281] In some embodiments, the bias compensation circuit 2410 may include a high voltage switch S3 coupled across a bias compensation diode D8 and arranged in series with a bias power supply V1 and a bias compensation resistor R9. In some embodiments, the high voltage switch S3 may include a plurality of switches arranged in series to collectively open and close the high voltage. For example, the high voltage switch S3 may include Figure 14 In some embodiments, the high voltage switch S3 can be opened and closed based on the signals Sig3+ and Sig3-.

[0282] The high-voltage switch S3 can be coupled in series with one or both of an inductor L9 and a resistor R11. The inductor L9 can limit the peak current through the high-voltage switch S3. For example, the inductor L9 can have an inductance of less than approximately 100 μH (e.g., such as approximately 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc.). For example, the resistor R11 can transfer power dissipation to the primary absorber. For example, the resistance of the resistor R11 can have a resistance of less than approximately 1000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, etc.

[0283] In some embodiments, the high voltage switch S3 may include a snubber circuit, which may include a resistor R9, a snubber diode D8, a snubber capacitor C15, and a snubber resistor R10.

[0284] In some embodiments, resistor R8 may represent a stray resistance that offsets supply voltage V1. For example, resistor R8 may have a high resistance (e.g., a resistance of approximately 10k ohms, 100k ohms, 1M ohms, 10M ohms, 100M ohms, 1G ohms, etc.).

[0285] In some embodiments, the bias compensation capacitor C8 may have a capacitance of less than 100 nF to 100 μF (eg, such as approximately 100 μF, 50 μF, 25 μF, 10 μF, 2 μF, 500 nF, 200 nF, etc.).

[0286] In some embodiments, the bias compensation capacitor C8 and the bias compensation diode D8 can allow the voltage offset between the output of the pulse generator stage 101 (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124) to be established at the beginning of each burst to achieve a desired equilibrium state. For example, charge is transferred from capacitor C12 to capacitor C8 over a plurality of pulses (e.g., about 5-100) at the beginning of each burst to establish the correct voltage in the circuit.

[0287] In some embodiments, bias capacitor C12 can allow for a voltage offset between the output of the nanosecond pulse generator stage 101 (e.g., at the location labeled 125) and the voltage on the electrode (e.g., at the location labeled 124). In operation, for example, the electrode can be at a DC voltage of -2 kV during a burst, while the output of the nanosecond pulse generator alternates between +6 kV during a pulse and 0 kV between pulses.

[0288] For example, bias capacitor C12 may have a capacitance of approximately 100 nF, 10 nF, 1 nF, 100 μF, 10 μF, 1 μF, etc. For example, resistor R9 may have a high resistance (e.g., such as a resistance of approximately 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm, etc.).

[0289] The bias compensation circuit 2410 may include any number of other elements or be arranged in any number of ways.

[0290] In some embodiments, high-voltage switch S3 can be open while nanosecond pulse generator 105 is pulsing, and closed when nanosecond pulse generator 105 is not pulsing. For example, when high-voltage switch S3 is closed, current is shorted across bias compensation diode D8. Shorting this current can allow the bias between the wafer and the clamp to be less than 2 kV (or another voltage value), which can be within acceptable tolerances. In some embodiments, bias compensation diode D8 can conduct currents between 10 A and 1 kA at frequencies between 10 Hz and 10 kHz.

[0291] In some embodiments, the high voltage switch S3 may include Figure 14 The high voltage switch 1400 described in .

[0292] In some embodiments, load stage 2415 can represent an idealized or effective circuit for a semiconductor processing chamber (e.g., such as a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.). For example, capacitor C2 can represent the capacitance of a clamp on which a wafer can be seated. For example, the clamp can include a dielectric material. For example, capacitor C1 can have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0293] For example, capacitor C3 can represent the sheath capacitance between the plasma and the wafer. For example, resistor R6 can represent the sheath resistance between the plasma and the wafer. For example, inductor L2 can represent the sheath inductance between the plasma and the wafer. For example, current source I2 can represent the ion current through the sheath. For example, capacitor C1 or capacitor C3 can have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0294] For example, capacitor C9 can represent the capacitance within the plasma between the chamber wall and the top surface of the wafer. For example, resistor R7 can represent the resistance within the plasma between the chamber wall and the top surface of the wafer. For example, current source I1 can represent the ion current in the plasma. For example, capacitor C1 or capacitor C9 can have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0295] As used herein, plasma voltage is the voltage measured from ground to circuit point 123; wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer; clamp voltage is the voltage measured from ground to circuit point 121; electrode voltage is the voltage measured from ground to circuit point 124; and input voltage is the voltage measured from ground to circuit point 125.

[0296] Figure 25 A nanosecond pulse generator system 2500 is shown in accordance with some embodiments. The nanosecond pulse generator system 2500 includes the nanosecond pulse generator 105 , a primary absorber 2006 , a transformer T1 , a bias compensation circuit 2410 , and a load stage 2415 .

[0297] Figure 26 A nanosecond pulse generator system 2600 is shown in accordance with some embodiments. The nanosecond pulse generator system 2600 includes a nanosecond pulse generator 2105 , a primary absorber 1906 , a transformer T1 , a bias compensation circuit 2410 , and a load stage 2415 .

[0298] Figure 27 A nanosecond pulse generator system 2700 is shown in accordance with some embodiments. The nanosecond pulse generator system 2700 includes the nanosecond pulse generator 105 , a primary absorber 2206 , a transformer T1 , a bias compensation circuit 2410 , and a load stage 2415 .

[0299] Figure 28 A waveform 2805 of the voltage at the input of transformer T1 using the nanosecond pulse generator system 2700 , a waveform 2810 of the voltage at the clamp (point labeled 121 ), and a waveform 2815 of the voltage at the wafer (point labeled 122 ) are shown.

[0300] In some embodiments, the clamping potential is shown as negative, however, the clamping potential can also be positive.

[0301] In some embodiments, primary absorber 1906, primary absorber 2006, or primary absorber 2206 can reduce the energy consumption of a high voltage nanosecond pulse generator system and / or the voltage required to drive a given load. For example, energy consumption can be reduced by as much as 10%, 15%, 20%, 25%, 30%, 40%, 45%, 50%, or more.

[0302] In some embodiments, diode D9 and / or diode D6 may include high voltage diodes.

[0303] Unless otherwise specified, the term "substantially" means within 5% or 10% of the referenced value or within a manufacturing tolerance. Unless otherwise specified, the term "approximately" means within 5% or 10% of the referenced value or within a manufacturing tolerance.

[0304] The term "or" is inclusive.

[0305] Numerous specific details are set forth herein to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter may be practiced without these specific details. In other instances, methods, devices, or systems well known to those skilled in the art have not been described in detail so as not to obscure the claimed subject matter.

[0306] The embodiments of the methods disclosed herein may be performed in the operation of these computing devices. The order of the blocks presented in the above examples may be changed, for example, the blocks may be reordered, combined and / or decomposed into sub-blocks. Certain blocks or processes may be performed in parallel.

[0307] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps. Furthermore, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more stated conditions or values ​​may actually be based on additional conditions or values ​​beyond those stated. The headings, lists, and numbering included herein are for ease of explanation only and are not intended to be limiting.

[0308] Although the subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that modifications, variations, and equivalents to these embodiments may readily occur to those skilled in the art upon realizing the foregoing understanding. Accordingly, it will be appreciated that the present disclosure has been presented for purposes of illustration and not limitation, and does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter as would be readily apparent to one of ordinary skill in the art.

Claims

1. A nanosecond pulse generator circuit, comprising: a high voltage power supply, the high voltage power supply including an energy storage capacitor; a nanosecond pulse generator electrically coupled to the high voltage power supply and switching a voltage from the high voltage power supply at a high frequency; a transformer having a primary side and a secondary side, the nanosecond pulse generator being electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the high voltage power supply and the secondary side of the transformer, the energy recovery circuit comprising: an energy recovery inductor electrically coupled to the high voltage power supply; a crowbar diode arranged in parallel with the secondary side of the transformer; and a second diode disposed in series with the energy recovery inductor and arranged to conduct current from a load through the energy recovery inductor to the high voltage power supply; The nanosecond pulse generator circuit generates a plurality of pulses at a pulse repetition frequency greater than 10 kHz, the voltage of each pulse is greater than 5 kV, and the rise time of each pulse is less than 100 ns.

2. The nanosecond pulse generator circuit according to claim 1, wherein: The energy recovery inductor includes an inductance greater than 50 μH.

3. The nanosecond pulse generator circuit according to claim 1, wherein: The load includes a capacitive load.

4. The nanosecond pulse generator circuit according to claim 1, wherein: The load includes a plasma deposition chamber.

5. The nanosecond pulse generator circuit according to claim 1, wherein: The energy recovery circuit further includes a high voltage switch connected in series with the second diode and the energy recovery inductor.

6. The nanosecond pulse generator circuit according to claim 1, wherein: The high voltage power supply provides DC power having a voltage greater than 1 kV.

7. A circuit comprising: storage capacitors; a full-bridge switching circuit coupled to the storage capacitor, the full-bridge switching circuit outputting an RF waveform having a voltage greater than 1 kV and a frequency greater than 400 kHz; a transformer having a primary side and a secondary side, the full-bridge switching circuit being electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the secondary side of the transformer and the storage capacitor, the energy recovery circuit comprising: an energy recovery inductor electrically coupled to the storage capacitor, the energy recovery inductor having an inductance greater than 50 μH; and A second diode is disposed in series with the energy recovery inductor and is arranged to conduct current from a load through the energy recovery inductor to the storage capacitor.

8. The circuit of claim 7, wherein: The energy recovery circuit includes an arc-extinguishing diode arranged in parallel with the secondary side of the transformer.

9. The circuit of claim 7, further comprising: The bias compensation circuit includes a bias compensation diode connected in parallel with a bias compensation switch; and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

10. The circuit of claim 7, wherein: The energy recovery inductor includes an inductance greater than 50 μH.

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