Edge-modulated transmitters and digital isolators

Abstract

The present application provides an edge modulation transmitter and a digital isolator, which relate to the field of digital circuit technology. The edge modulation transmitter includes a coding control circuit and a common mode noise detection circuit, the common mode noise detection circuit includes at least one multi-stage buffer, at least one current detector and a detection logic circuit, the coding control circuit includes an input logic circuit and a pulse extension circuit, the connection circuit between the detection logic circuit and the pulse extension circuit, at least one multi-stage buffer connected between the input logic circuit and the driving isolator, each current detector of at least one current detector is used to send a current detection signal of at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and the output end of the detection logic circuit. When the transmitter detects that a large common mode noise appears in the system, adaptive edge modulation is performed through the coding control circuit.

Description

Technical Field

[0001] The present application relates to the technical field of digital circuits, and in particular to an edge modulation transmitter and a digital isolator. Background Art

[0002] As digital isolators are mainly used to transmit digital signals between circuit modules with high voltage differences, there are many noise interferences in their working environment, especially common mode transient (CMT), which poses a significant threat to the transmission reliability of digital isolator signals. The existing pulse-based edge coding technology mainly achieves anti-CMT interference by absorbing the common mode current caused by CMT through circuit design, but the anti-CMT interference range that can be achieved by this method is small, and the signal transmission quality cannot be guaranteed in some environments. Summary of the invention

[0003] In view of this, the purpose of the embodiments of the present application is to provide an edge modulated transmitter and a digital isolator to improve the problem in the prior art that the anti-CMT interference range is small and the signal transmission quality cannot be ensured in some environments.

[0004] The embodiment of the present application provides an edge modulation transmitter, the edge modulation transmitter includes a coding control circuit and a common mode noise detection circuit, the common mode noise detection circuit includes at least one multi-stage buffer, at least one current detector and a detection logic circuit, the coding control circuit includes an input logic circuit and a pulse extension circuit, the connection circuit between the detection logic circuit and the pulse extension circuit, the at least one multi-stage buffer is connected between the input logic circuit and a driving isolator, each current detector of the at least one current detector is used to send a current detection signal of the at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and the output end of the detection logic circuit;

[0005] When the common-mode noise detection circuit detects a common-mode noise signal greater than a preset threshold, the detection logic circuit sends a common-mode noise determination signal to the pulse extension circuit, the pulse extension circuit sends a burst signal to the input logic circuit based on the common-mode noise determination signal and maintains a preset delay, and the input logic circuit sends a pulse signal to the at least one multi-stage buffer at the beginning or end of the burst signal and continues for the preset delay.

[0006] In the above implementation, the common mode noise is detected by the common mode noise detection circuit. When the current detector determines that the common mode noise signal received by the multi-stage buffer exceeds a certain range, the CMT detection output synthesized by the detection logic circuit indicates that the receiver circuit may not be able to process the signal normally. At this time, the transmitter circuit needs to perform adaptive edge modulation. Then, the pulse extension circuit and the input logic circuit are used to adaptively increase the density of the data signal when and / or for a short period of time after the CMT occurs, so that the data pulses are continuously burst for a period of time. This ensures that the receiver's absorption capacity for the common mode current is fully utilized. During the CMT fading process, once the CMT level is lower than the saturation level of the receiver, the normal transmission of the signal can be restored, thereby maintaining the correctness of the signal transmission and minimizing the impact on the signal transmission jitter.

[0007] Optionally, the input logic circuit includes a signal input terminal, a signal output terminal and a detection input terminal, the signal input terminal is used to receive an input signal, the signal output terminal is connected to the input terminal of the at least one multi-stage buffer, the at least one current detector is used to output the current detection signal of the at least one multi-stage buffer to the detection logic circuit, the output terminal of the detection logic circuit is connected to the input terminal of the pulse extension circuit, the output terminal of the pulse extension circuit is connected to the detection input terminal, and the output terminal of the at least one multi-stage buffer is connected to the receiver through the driver isolator.

[0008] In the above implementation, the current values ​​passing through different multi-stage buffers are detected by different current detectors and transmitted to the detection logic circuit, so as to determine whether the strength of common-mode noise will affect system operation under different conduction conditions of the multi-stage buffers.

[0009] Optionally, the at least one multi-stage buffer includes a first multi-stage buffer and a second multi-stage buffer, the first multi-stage buffer includes a first MOS transistor and a second MOS transistor, the second multi-stage buffer includes a third MOS transistor and a fourth MOS transistor, the first MOS transistor and the third MOS transistor are N-type, and the second MOS transistor and the fourth MOS transistor are P-type;

[0010] The first output end of the input logic circuit is respectively connected to the gates of the first MOS tube and the second MOS tube, the source of the first MOS tube is respectively connected to the VDD power supply and the detection input end, the drain of the first MOS tube is respectively connected to the drain of the second MOS tube and the first input end of the driving isolator, and the source of the second MOS tube is connected to the detection input end and grounded; the second output end of the input logic circuit is respectively connected to the gates of the third MOS tube and the fourth MOS tube, the source of the third MOS tube is respectively connected to the VDD power supply and the detection input end, the drain of the third MOS tube is respectively connected to the drain of the fourth MOS tube and the second input end of the driving isolator, and the source of the fourth MOS tube is connected to the detection input end and grounded.

[0011] In the above implementation, each multi-stage buffer is composed of two MOS tubes, which can drive the current of the isolator to be the differential mode current for normal operation when the voltage on the transmitter side rises or falls and no CMT event occurs. When a CMT event occurs, no matter whether the transmitter voltage rises or falls, there is always one current in the four MOS tubes that is higher than the common mode current value during normal operation, thereby realizing common mode noise signal detection under different states.

[0012] Optionally, the at least one current detector includes a first current detector, a second current detector, a third current detector and a fourth current detector;

[0013] The first current detector is connected to the source of the first MOS tube, the second current detector is connected to the source of the second MOS tube, the third current detector is connected to the source of the third MOS tube, and the fourth current detector is connected to the source of the fourth MOS tube. The output ends of the first current detector, the second current detector, the third current detector and the fourth current detector are respectively connected to the first input end, the second input end, the third input end and the fourth input end of the input end of the detection logic circuit.

[0014] In the above implementation, four MOS tubes are matched with four current detectors for current detection, and the detection results are output to the detection logic circuit, which can fully monitor the currents of the four MOS tubes in different conduction states, thereby accurately detecting the common-mode current caused by common-mode noise.

[0015] Optionally, the first current detector includes a first resistor and a first comparator, the first resistor is connected between the source of the first MOS tube and the VDD power supply, two input ends of the first comparator are respectively connected to two ends of the first resistor, and the output end of the first comparator is connected to the first input end of the detection logic circuit;

[0016] The second current detector includes a second resistor and a second comparator, the source of the second MOS tube is grounded through the second resistor, two input ends of the second comparator are respectively connected to the two ends of the second resistor, and the output end of the second comparator is connected to the second input end of the detection logic circuit;

[0017] The third current detector comprises a third resistor and a third comparator. The connection mode of the third current detector is the same as that of the first current detector. The output end of the third comparator is connected to the third input end of the detection logic circuit.

[0018] The fourth current detector comprises a fourth resistor and a fourth comparator. The connection mode of the fourth current detector is the same as that of the second current detector. The output end of the fourth comparator is connected to the fourth input end of the detection logic circuit.

[0019] The first comparator, the second comparator, the third comparator and the fourth comparator have a threshold comparison function, output a first logic when the detection current is greater than or equal to a first threshold, and output a second logic when the detection current is less than a second threshold.

[0020] In the above implementation, each current detector detects the current size of the MOS tube through a resistor connected to the source of the MOS tube, and then determines through a comparator whether the current size is greater than a threshold that affects the normal operation of the system, so that pulse modulation can be performed through the coding control circuit when the common mode noise is large.

[0021] Optionally, the first threshold is greater than or equal to the second threshold.

[0022] Optionally, the detection logic circuit is a four-input OR gate.

[0023] In the above implementation, the detection logic circuit is a four-input OR gate capable of cooperating with the current detection signals output by the above four current detectors to detect the currents of the four MOS tubes to determine the common-mode current.

[0024] The embodiment of the present application further provides a digital isolator, the digital isolator comprising the above-mentioned edge modulation transmitter, a driving isolator and a receiver, the receiver comprising a comparator circuit and a latch, the output end of the driving isolator is connected to the input end of the comparator circuit, the output end of the comparator circuit is connected to the input end of the latch, and the output end of the latch is the output end of the digital isolator;

[0025] The comparator circuit compares the output signal of the driving isolator. When the output signal of the driving isolator is a pulse of a first polarity, the latch is set to a first logic latch state, and the output end of the latch outputs a first logic. When the output signal of the driving isolator is a pulse of a second polarity, the latch is set to a second logic latch state, and the output end of the latch outputs a second logic.

[0026] In the above implementation, the logic latch state is switched by a latch that can be triggered by a single pulse, thereby achieving stable output of digital signals that is resistant to CMT interference.

[0027] Optionally, the driving isolator is a differential capacitor pair consisting of a pair of capacitors, or a transformer consisting of two mutually coupled coils.

[0028] In the above implementation, the input signal is converted and output by driving the isolator, thereby reducing signal interference and transmission distortion.

[0029] Optionally, the receiver further comprises a resistor-capacitor circuit connected between the driver isolator and the comparator circuit.

[0030] In the above implementation, the waveform of the output signal of the driving isolator is adjusted by the resistor-capacitor circuit to improve the output accuracy of the digital signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of the structure of a digital isolator provided in an embodiment of the present application.

[0033] Figure 2 A schematic diagram of the structure of an edge modulation transmitter provided in an embodiment of the present application.

[0034] Figure 3 A schematic diagram of operating signals of an existing transmitter that does not adopt adaptive edge modulation technology is provided in an embodiment of the present application.

[0035] Figure 4 A schematic diagram of working signals of an existing edge modulation transmitter using adaptive edge modulation technology is provided in an embodiment of the present application.

[0036] Figure 5A schematic diagram of the structures of two drive isolators provided in an embodiment of the present application.

[0037] Icons: 10-digital isolator; 11-edge modulated transmitter; 111-encoding control circuit; 1111-input logic circuit; 1112-pulse extension circuit; 112-common mode noise detection circuit; 1121-detection logic circuit; 1122-first multi-stage buffer; 1123-second multi-stage buffer; 1124-first current detector; 1125-second current detector; 1126-third current detector; 1127-fourth current detector; 12-driver isolator; 13-receiver; 131-comparator circuit; 132-latch; 133-resistance-capacitance circuit. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application.

[0039] First, let's start with the digital isolator. The digital isolator is a chip that enables the electronic system to have a very high voltage isolation characteristic when digital signals and analog signals are transmitted in the electronic system, so as to achieve isolation between electronic systems. Common-mode noise will have a great impact on the transmission reliability of the digital isolator signal, and the digital isolator in the prior art has a small range of resistance to CMT interference, and the signal transmission quality cannot be guaranteed in some environments. Therefore, this embodiment provides a digital isolator 10 to solve the above problem.

[0040] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a digital isolator provided in an embodiment of the present application.

[0041] The digital isolator 10 includes an edge modulation transmitter 11 , a driving isolator 12 and a receiver 13 . The edge modulation transmitter 11 is electrically connected to the receiver 13 through the driving isolator 12 .

[0042] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of an edge modulation transmitter provided in an embodiment of the present application.

[0043] The edge modulated transmitter 11 includes a coding control circuit 111 and a common mode noise detection circuit 112 , which includes an input logic circuit 1111 and a pulse extension circuit 1112 . The common mode noise detection circuit 112 includes at least one multi-stage buffer, at least one current detector and a detection logic circuit 1121 .

[0044] A series circuit of the detection logic circuit 1121 and the pulse extension circuit 1112, at least one multi-stage buffer connected in parallel between the input logic circuit 1111 and the driving isolator 12, at least one current detector, each current detector is used to send a current detection signal of at least one multi-stage buffer to the detection logic circuit 1121, and the pulse extension circuit 1112 is connected in series between the input logic circuit 1111 and the output end of the detection logic circuit 1121.

[0045] Specifically, the input logic circuit 1111 includes a signal input terminal, a signal output terminal and a detection input terminal. The signal input terminal is used to receive an input signal. The signal output terminal is connected to the input terminal of at least one multi-stage buffer. At least one current detector is used to output a current detection signal of at least one multi-stage buffer to the detection logic circuit 1121. The output terminal of the detection logic circuit 1121 is connected to the input terminal of the pulse extension circuit 1112. The output terminal of the pulse extension circuit 1112 is connected to the detection input terminal. The output terminal of at least one multi-stage buffer is connected to the receiver 13 through the driver isolator 12.

[0046] Optionally, at least one multi-stage buffer in this embodiment may be two, each multi-stage buffer is connected to a signal output terminal of the input logic circuit 1111, specifically, the first multi-stage buffer 1122 is connected to the first output terminal of the input logic circuit 1111, and the second multi-stage buffer 1123 is connected to the second output terminal of the input logic circuit 1111.

[0047] The first multi-stage buffer 1122 may be composed of a first MOS transistor M1 and a second MOS transistor M2, and the second multi-stage buffer 1123 may be composed of a third MOS transistor M3 and a fourth MOS transistor M4. The first MOS transistor M1 and the third MOS transistor M3 are N-type, and the second MOS transistor M2 and the fourth MOS transistor M4 are P-type.

[0048] Specifically, the first output end of the input logic circuit 1111 is respectively connected to the gates of the first MOS transistor M1 and the second MOS transistor M2, the source of the first MOS transistor M1 is respectively connected to the VDD power supply and the detection input end, the drain of the first MOS transistor M1 is respectively connected to the drain of the second MOS transistor M2 and the first input end of the driver isolator 12, and the source of the second MOS transistor M2 is connected to the detection input end and grounded; the second output end of the input logic circuit 1111 is respectively connected to the gates of the third MOS transistor M3 and the fourth MOS transistor M4, the source of the third MOS transistor M3 is respectively connected to the VDD power supply and the detection input end, the drain of the third MOS transistor M3 is respectively connected to the drain of the fourth MOS transistor M4 and the second input end of the driver isolator 12, and the source of the fourth MOS transistor M4 is connected to the detection input end and grounded.

[0049] The digital isolator 10 may have the following MOS tube states:

[0050] When no CMT event occurs,

[0051] (1) M1 and M4 are turned on, M2 and M3 are turned off, and the current driving the isolator 12 flows from VDD through the isolator 12 and the fourth MOS tube M4 back to GND. The current is the differential mode current Id of normal operation.

[0052] (2) M2 and M3 are turned on, M1 and M4 are turned off, and the current driving the isolator 12 flows from VDD through the third MOS transistor M3, the driving isolator 12, and the second MOS transistor M2 back to GND. The current magnitude is the differential mode current Id of normal operation;

[0053] When a CMT event occurs where the common mode current exceeds the threshold,

[0054] (3) M1 and M4 are turned on, M2 and M3 are turned off,

[0055] 3.1) The voltage on one side of the edge modulated transmitter 11 rises, that is, the common mode current flows from the left side to the right side, so the current of the first MOS tube M1 increases and the current of the fourth MOS tube M4 decreases. This variable is the common mode current Ic;

[0056] 3.2) The voltage on one side of the edge modulation transmitter 11 decreases, that is, the common mode current flows from the right side to the left side, so the current of the first MOS tube M1 decreases and the current of the fourth MOS tube M4 increases. This variable is the common mode current Ic;

[0057] (4) M2 and M3 are turned on, M1 and M4 are turned off,

[0058] 4.1) The voltage on one side of the edge modulated transmitter 11 rises, that is, the common mode current flows from the left side to the right side, so the current of the third MOS tube M3 increases and the current of the second MOS tube M2 decreases. This variable is the common mode current Ic;

[0059] 4.2) The voltage on one side of the edge modulation transmitter 11 decreases, that is, the common mode current flows from the right side to the left side, so the current of the third MOS tube M3 decreases and the current of the second MOS tube M2 increases. This variable is the common mode current Ic.

[0060] The current conditions corresponding to the above-mentioned situations can be shown in the following table (all in Figure 2 The direction from top to bottom is positive current):

[0061]

[0062] The above table is a schematic diagram. When the CMT current is very large, the body diode of the disconnected MOS tube may participate in the conduction of the common-mode current. However, this phenomenon does not affect the working principle of this embodiment, nor does it limit the content of this embodiment.

[0063] By observing the above table, it can be seen that no matter what the combination of the conducting MOS tubes is, and no matter what the direction of the CMT current is, there is always a MOS tube whose current is higher than Ic compared to normal operation, that is, it reaches the level of Id+Ic. When the CMT current is small, Ic is small, and within the processing range of the receiver 13, it will not affect the operation of the system. However, when the CMT current is large (the value of dV / dt is large, such as tens or hundreds of kV / us), the receiver 13 may not be able to process the signal normally, and the edge modulation transmitter 11 needs to perform adaptive edge modulation.

[0064] In conjunction with the multi-stage buffer composed of the above-mentioned MOS transistors provided in this embodiment, at least one current detector may include a first current detector 1124 , a second current detector 1125 , a third current detector 1126 and a fourth current detector 1127 .

[0065] Specifically, the first current detector 1124 is connected in series with the source of the first MOS tube M1, the second current detector 1125 is connected in series with the source of the second MOS tube M2, the third current detector 1126 is connected in series with the source of the third MOS tube M3, and the fourth current detector 1127 is connected in series with the source of the fourth MOS tube M4. The output ends of the first current detector 1124, the second current detector 1125, the third current detector 1126 and the fourth current detector 1127 are respectively connected to the first input end, the second input end, the third input end and the fourth input end of the input end of the detection logic circuit 1121.

[0066] It should be understood that the current detector in this embodiment only needs to measure the current passing through the source of the MOS tube, and the position shown in the figure is only a schematic and not a limitation to the implementation method.

[0067] The specific structure of the current detector is described below. Figure 2 The square dotted box in the middle is a schematic diagram of the specific structure of the current detector. In this embodiment, the specific structures of the first current detector 1124, the second current detector 1125, the third current detector 1126 and the fourth current detector 1127 can be the same, only the different input terminals of the final output input detection logic circuit 1121. The following only takes the first current detector 1124 as an example, and other current detectors are not repeated.

[0068] The first current detector 1124 includes a first resistor R1 and a first comparator C1. The first resistor R1 is connected in series between the source of the first MOS tube M1 and the VDD power supply. The two input ends of the first comparator C1 are respectively connected to the two ends of the first resistor R1. The output end of the first comparator C1 is connected to the first input end of the detection logic circuit 1121.

[0069] The first comparator C1, the second comparator C2, the third comparator C3 and the fourth comparator C4 have a threshold comparison function, outputting a first logic when the detection current is greater than or equal to a first threshold, and outputting a second logic when the detection current is less than a second threshold.

[0070] The first logic and the second logic are level logic 0 or 1 in a digital circuit. If one of the first logic and the second logic is 0, the other is 1. This embodiment is described with the first logic being 1 and the second logic being 2.

[0071] Optionally, the first threshold is greater than or equal to the second threshold. When the output value of the current detector is greater than the first threshold, it indicates that the common-mode current may affect the normal signal processing of the receiver 13, and the edge modulation transmitter 11 needs to perform adaptive edge modulation. When the output value of the current detector is less than or equal to the second threshold, it indicates that the common-mode current is within the processing range of the receiver 13 and will not affect the operation of the system.

[0072] Optionally, the first threshold may be a value where the dV / dt value exceeds the normal operating range of the electronic system. The first threshold may be flexibly adjusted according to the actual situation of the electronic system, such as 10 kV / us, 20 kV / us, 50 kV / us, 100 kV / us, 200 kV / us, etc.

[0073] Optionally, in this embodiment, the detection outputs of the first current detector 1124, the second current detector 1125, the third current detector 1126 and the fourth current detector 1127 are processed by the detection logic circuit 1121 to output a common mode noise determination signal, i.e., the first logic (1 in this embodiment) or the second logic (0 in this embodiment). In this embodiment, the first logic can be used as the common mode noise determination signal to indicate that the CMT current value is too large and pulse modulation is required.

[0074] Optionally, the detection logic circuit 1121 may be a 4-input OR gate to output a first logic to the pulse extension circuit 1112 when the current detection result transmitted by any one of the first current detector 1124, the second current detector 1125, the third current detector 1126, and the fourth current detector 1127 is the first logic. It should be understood that those skilled in the art can change the output of the current detector and the logic corresponding to the detection logic circuit 1121 to obtain an equivalent result.

[0075] The common mode noise determination signal enters the pulse extension circuit 1112, and the burst signal (Burst) outputted by the pulse extension circuit controls the input logic circuit 1111 to continuously send a pulse signal to the first output terminal or the second output terminal of the signal output terminal according to the current input level.

[0076] The pulse signal in this embodiment can adopt two modes:

[0077] (1) Start after the common mode noise determination signal ends, maintain a preset delay, and then end, and the preset delay is not less than the width of a data pulse signal;

[0078] (2) It starts when the common mode noise determination signal starts, maintains a preset delay after the common mode noise determination signal ends, and then ends, and the preset delay is not less than the width of a data pulse signal.

[0079] Below through Figure 3 and Figure 4 A comparison is made between the working conditions when the adaptive edge modulation technology is not used and the working conditions when the adaptive edge modulation technology provided by this embodiment is used.

[0080] Please refer to Figure 3 , Figure 3 A schematic diagram of operating signals of an existing transmitter that does not adopt adaptive edge modulation technology is provided in an embodiment of the present application.

[0081] When a CMT event occurs, the first output terminal S1 of the input logic circuit 1111 is transmitting a pulse A1 to the receiver. Since the common mode current caused by the CMT event exceeds the absorption capacity of the receiver 13, the pulse A2 that should appear on the receiver 13 cannot be detected by the receiver 13, and the corresponding output signal is wrong, and the high level A3 of the input terminal is not successfully transmitted to the output terminal. Wherein, S2 represents the second output terminal of the input logic circuit 1111.

[0082] Please refer to Figure 4 , Figure 4 A schematic diagram of working signals of an existing edge modulation transmitter using adaptive edge modulation technology is provided in an embodiment of the present application.

[0083] After the CMT event occurs, the detection logic circuit 1121 outputs the common mode noise determination signal A4 and triggers the corresponding burst signal A5. The duration of A5 is from the beginning of the common mode noise determination signal A4 to the end of the common mode noise determination signal A4 and then maintains the preset delay A6. During the A5 signal period, the first output terminal S1 and the second output terminal S2 of the input logic circuit 1111 will continue to transmit pulse signals, as shown by A7 and A8. During the CMT event, since its common mode current exceeds the absorption capacity of the receiver 13, pulses A9 and A10 are not recognized by the receiver 13. Since the burst signal A5 will maintain the preset delay A6 after the CMT event ends, the pulse A11 transmitted during this period can be recognized by the receiver 13, so it can be correctly output at the output end. It can be seen from here that the delay of the burst signal A5 after the common mode noise determination signal A4 should not be less than the width of 1 signal pulse.

[0084] Optionally, the driving buffer of the driving isolator 12 may also provide a feedback signal to the input logic circuit 1111 , and different embodiments may depend on the logic design of the input logic circuit 1111 and its coordination with the feedback signal of the driving buffer of the driving isolator 12 .

[0085] Next, the driver isolator 12 and the receiver 13 of the digital isolator 10 are described in detail.

[0086] Please refer to Figure 5 , Figure 5 A schematic diagram of the structures of two drive isolators provided in an embodiment of the present application.

[0087] The drive isolator 12 is Figure 5 The differential capacitor pair shown in the left figure, or Figure 5 The transformer shown in the middle right figure is composed of two mutually coupled coils.

[0088] The receiver 13 includes a comparator circuit 131 and a latch 132 . The output of the driver isolator 12 is connected to the input of the comparator circuit 131 . The output of the comparator circuit 131 is connected to the input of the latch 132 . The output of the latch 132 is the output of the digital isolator 10 .

[0089] Optionally, the receiver 13 may further include a resistor-capacitor (RS) circuit 133 connected in series between the driver isolator 12 and the comparator circuit 131 for adjusting the received waveform. The specific adjustment method is not the key point of the present invention and will not be described in detail.

[0090] Specifically, the comparator circuit 131 includes a fifth comparator C5 and a sixth comparator C6, the positive phase input terminal of the fifth comparator C5 is respectively connected to the negative phase input terminal of the sixth comparator C6 and the first output terminal of the resistor-capacitor circuit 133, and the negative phase input terminal of the fifth comparator C5 is respectively connected to the positive phase input terminal of the sixth comparator C6 and the second output terminal of the resistor-capacitor circuit 133.

[0091] The latch 132 may be an RS latch, the output of the fifth comparator C5 is connected to the S terminal of the latch 132 , the output of the sixth comparator C6 is connected to the R terminal of the latch 132 , and the Q terminal of the latch 132 is the signal output terminal of the digital isolator 10 .

[0092] In summary, the embodiments of the present application provide an edge modulation transmitter and a digital isolator, wherein the edge modulation transmitter includes a coding control circuit and a common mode noise detection circuit, wherein the common mode noise detection circuit includes at least one multi-stage buffer, at least one current detector and a detection logic circuit, wherein the coding control circuit includes an input logic circuit and a pulse extension circuit, wherein a series circuit of the detection logic circuit and the pulse extension circuit and the at least one multi-stage buffer are connected in parallel between the input logic circuit and the driving isolator, wherein each current detector of the at least one current detector is used to send a current detection signal of the at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected in series between the input logic circuit and the output end of the detection logic circuit;

[0093] When the common-mode noise detection circuit detects a common-mode noise signal greater than a preset threshold, the detection logic circuit sends a common-mode noise determination signal to the pulse extension circuit, the pulse extension circuit sends a burst signal to the input logic circuit based on the common-mode noise determination signal and maintains a preset delay, and the input logic circuit sends a pulse signal to the at least one multi-stage buffer at the beginning or end of the burst signal and continues for the preset delay.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed devices can also be implemented in other ways. The device embodiments described above are only schematic. For example, the block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices according to the multiple embodiments of this application.

[0095] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0096] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

[0097] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. An edge modulated transmitter, characterized in that: The edge modulation transmitter comprises a coding control circuit and a common mode noise detection circuit, the common mode noise detection circuit comprises at least one multi-stage buffer, at least one current detector and a detection logic circuit, the coding control circuit comprises an input logic circuit and a pulse extension circuit, the series circuit of the detection logic circuit and the pulse extension circuit is connected between the at least one multi-stage buffer and the input logic circuit, the at least one multi-stage buffer is connected between the input logic circuit and the driving isolator, each current detector of the at least one current detector is used to send a current detection signal of the at least one multi-stage buffer to the detection logic circuit, and the pulse extension circuit is connected between the input logic circuit and the output end of the detection logic circuit; When the common mode noise detection circuit detects a common mode noise signal greater than a preset threshold, the detection logic circuit sends a common mode noise determination signal to the pulse extension circuit, the pulse extension circuit sends a burst signal to the input logic circuit based on the common mode noise determination signal and maintains a preset delay, and the input logic circuit sends a pulse signal to the at least one multi-stage buffer and continues the preset delay when the burst signal starts or ends; Wherein, the input logic circuit comprises a signal input terminal, a signal output terminal and a detection input terminal, the signal input terminal is used to receive an input signal, the signal output terminal is connected to the input terminal of the at least one multi-stage buffer, the at least one current detector is used to output the current detection signal of the at least one multi-stage buffer to the detection logic circuit, the output terminal of the detection logic circuit is connected to the input terminal of the pulse extension circuit, the output terminal of the pulse extension circuit is connected to the detection input terminal, and the output terminal of the at least one multi-stage buffer is connected to the receiver through the driver isolator; The at least one multi-stage buffer includes a first multi-stage buffer and a second multi-stage buffer, the first multi-stage buffer includes a first MOS transistor and a second MOS transistor, the second multi-stage buffer includes a third MOS transistor and a fourth MOS transistor, the first MOS transistor and the third MOS transistor are N-type, and the second MOS transistor and the fourth MOS transistor are P-type; The first output end of the input logic circuit is respectively connected to the gates of the first MOS transistor and the second MOS transistor, the source of the first MOS transistor is respectively connected to the VDD power supply and the detection input end, the drain of the first MOS transistor is respectively connected to the drain of the second MOS transistor and the first input end of the driving isolator, and the source of the second MOS transistor is connected to the detection input end and grounded; the second output end of the input logic circuit is respectively connected to the gates of the third MOS transistor and the fourth MOS transistor, the source of the third MOS transistor is respectively connected to the VDD power supply and the detection input end, the drain of the third MOS transistor is respectively connected to the drain of the fourth MOS transistor and the second input end of the driving isolator, and the source of the fourth MOS transistor is connected to the detection input end and grounded; The at least one current detector includes a first current detector, a second current detector, a third current detector, and a fourth current detector; The first current detector is connected to the source of the first MOS transistor, the second current detector is connected to the source of the second MOS transistor, the third current detector is connected to the source of the third MOS transistor, and the fourth current detector is connected to the source of the fourth MOS transistor. The output ends of the first current detector, the second current detector, the third current detector and the fourth current detector are respectively connected to the first input end, the second input end, the third input end and the fourth input end of the input end of the detection logic circuit; The first current detector includes a first resistor and a first comparator, the first resistor is connected between the source of the first MOS tube and the VDD power supply, the two input ends of the first comparator are respectively connected to the two ends of the first resistor, and the output end of the first comparator is connected to the first input end of the detection logic circuit; The second current detector includes a second resistor and a second comparator, the source of the second MOS tube is grounded through the second resistor, two input ends of the second comparator are respectively connected to the two ends of the second resistor, and the output end of the second comparator is connected to the second input end of the detection logic circuit; The third current detector comprises a third resistor and a third comparator. The connection mode of the third current detector is the same as that of the first current detector. The output end of the third comparator is connected to the third input end of the detection logic circuit. The fourth current detector comprises a fourth resistor and a fourth comparator. The connection mode of the fourth current detector is the same as that of the second current detector. The output end of the fourth comparator is connected to the fourth input end of the detection logic circuit. The first comparator, the second comparator, the third comparator and the fourth comparator have a threshold comparison function, output a first logic when the detection current is greater than or equal to a first threshold, and output a second logic when the detection current is less than a second threshold.

2. The edge modulation transmitter according to claim 1, characterized in that: The first threshold is greater than or equal to the second threshold.

3. The edge modulation transmitter according to claim 1, characterized in that: The detection logic circuit is a four-input OR gate.

4. A digital isolator, characterized in that: The digital isolator comprises an edge modulated transmitter, a driving isolator and a receiver as claimed in any one of claims 1 to 3, wherein the receiver comprises a comparator circuit and a latch, the output end of the driving isolator is connected to the input end of the comparator circuit, the output end of the comparator circuit is connected to the input end of the latch, and the output end of the latch is the output end of the digital isolator; The comparator circuit compares the output signal of the driving isolator. When the output signal of the driving isolator is a pulse of a first polarity, the latch is set to a first logic latch state, and the output end of the latch outputs a first logic. When the output signal of the driving isolator is a pulse of a second polarity, the latch is set to a second logic latch state, and the output end of the latch outputs a second logic.

5. The digital isolator according to claim 4, characterized in that: The driving isolator is a differential capacitor pair formed by a pair of capacitors, or a transformer formed by two mutually coupled coils.

6. The digital isolator according to claim 4, characterized in that: The receiver also includes a resistor-capacitor circuit connected between the driver isolator and the comparator circuit.

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