Provides bandwidth extension for memory subsystems that contain a sequencer separate from the controller

Abstract

A processing device may determine configuration parameters to be used for an error correction code (ECC) operation. The configuration parameters are based on a memory type of a memory component associated with a controller. Data may be received from a host system. The processing device may generate a codeword for the data by using the ECC operation based on the configuration parameters. The codeword may be sent to a sequencer external to the controller.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to a controller without a sequencer to provide bandwidth expansion for a memory subsystem. Background Art

[0002] The memory subsystem may be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0005] Figure 2 An example package including multiple sequencers operatively coupled to different memory components having different memory types according to some embodiments of the present disclosure is described.

[0006] Figure 3 is a flowchart of an example method for executing instructions according to some embodiments of the present disclosure.

[0007] Figure 4 is a flow chart of an example method for performing operations on a memory component according to some embodiments of the present disclosure.

[0008] Figure 5 Controllers including a reduced number of pins and a reduced form factor according to some embodiments of the present disclosure are described.

[0009] Figure 6 is a flow chart of an example method for determining configuration parameters to be used for error correction code operations according to some embodiments of the present disclosure.

[0010] Figure 7 is a flow chart of an example method for determining configuration parameters to be used for memory management operations according to some embodiments of the present disclosure.

[0011] Figure 8 is a flow chart of an example method for determining configuration parameters to be used for a memory mapping operation according to some embodiments of the present disclosure.

[0012] Fig. 9 is a flow chart of an example method for determining configuration parameters for sequencer operation and for sending the configuration parameters to the sequencer according to an embodiment of the present disclosure.

[0013] Fig.10 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to a memory subsystem including an in-package sequencer separated from a controller. A memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), and the like. In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem including one or more memory components. The host system may provide data to be stored at the memory subsystem, and may request to retrieve data from the memory subsystem.

[0015] The memory subsystem may include multiple memory components that can store data from the host system. Each memory component may include a different type of media. Examples of media include, but are not limited to, cross-point arrays of non-volatile memory and flash-based memory, such as single-level cell (SLC) memory, triple-level cell (TLC) memory, and quad-level cell (QLC) memory. Characteristics of different types of media may differ between one media type and another media type. One example of a characteristic associated with a memory component is data density. Data density corresponds to the amount of data (e.g., data bits) that can be stored per memory cell of the memory component. Using an example of flash-based memory, a quad-level cell (QLC) can store four data bits, while a single-level cell (SLC) can store one data bit. Another example of a characteristic of a memory component is access speed, which corresponds to the amount of time a memory component takes to access data stored at the memory component.

[0016] The memory subsystem may also include a controller operatively coupled to the memory component. The controller may operate as a "bridge" between the host system and the memory component of the memory subsystem for data transfer and / or management. In some cases, the controller and the associated memory component may be manufactured by different suppliers, and each of the controller and / or the memory component may have a corresponding package. In order to increase the capacity of the memory subsystem, memory components may be added to the memory subsystem. The controller must interface with multiple memory components. In order to interface with the memory components, in conventional systems, the controller includes a large number of pins. The inclusion of a large number of pins may increase the package size of the controller, which may in turn increase the system appearance size.

[0017] In some conventional systems, the controller interfaces with the host system using a serializer / deserializer (SerDes) connection (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), Universal Flash Storage (UFS), etc.) to minimize pin count. A conventional controller may include a sequencer component that interfaces with and instructs the memory component using a protocol and timing requirements (e.g., read / write latency, etc.) specific to the memory type of the memory component. The controller may interface with the memory component via a parallel interface utilizing a double data rate (DDR) to obtain a specific bandwidth and capacity. Increasing the number of memory components that interface directly with the controller may use more space and cause difficulties in routing the parallel interface. As a result, the wiring path (e.g., trace) between the controller and the memory component may be long, thereby compromising signal integrity. In addition, using a longer wiring path to the memory component via a parallel interface may cause a greater load, thereby consuming an undesirable amount of power.

[0018] Aspects of the present disclosure address the above and other deficiencies by separating a sequencer component from a controller and including a sequencer component with one or more memory components in a separate package. The sequencer component may be manufactured in independent silicon, the memory component may be manufactured in an independent die, and the independent silicon and the independent die may be included in the same package. A package may refer to a housing that supports electrical contacts that connect the package to an application board and prevents physical damage and corrosion. An application board may refer to a printed circuit board on which a controller, package, and / or memory component reside. Each sequencer component operates using a certain type of memory component (e.g., a crosspoint array, NAND flash, etc.) and may operate using multiple memory components having the type of memory. The sequencer component may interface with the memory component via a protocol specific to the memory type. Each package may include multiple sequencer components that interface with corresponding different types of memory components. In addition, a memory subsystem may include multiple packages that each include one or more sequencer components that interface with one or more memory components.

[0019] The sequencer component may interface with the controller via a SerDes connection that provides higher bandwidth than a parallel interface. In addition, a SerDes connection uses fewer pins than a parallel connection. Thus, the pin count in the controller may be reduced using the disclosed techniques while still accommodating the same number or more memory components contained in a package coupled to the controller. Reducing the pin count of the controller may result in a reduced form factor for a memory subsystem containing the same capacity (e.g., the same number of memory components) as a previous conventional system containing more pins.

[0020] Additionally, signal integrity can be improved because the distance between the sequencer component and the memory component within the separate package is shorter than in conventional systems where the sequencer component is within the controller. That is, the package is smaller than the application board, and therefore, the traces between the sequencer component and the memory component within the package are shorter than in conventional systems where the traces run on the application board. Shorter traces can improve signal integrity, as well as reduce the load on the package and consume less power than conventional systems where the wiring paths are longer.

[0021] In some embodiments, the sequencer component may attempt to maximize the bandwidth of the interface between the memory component and the sequencer component by enforcing the timing requirements of the memory type of the memory component. The timing requirements may relate to the latency of the read / write operations performed for the memory type. The sequencer component may time the time when it issues the read / write command based on the latency of the memory component of that type. In addition, the sequencer component may reorder the commands based on certain rules related to the commands and the addresses involved in the commands. That is, the sequencer component may reorder the read / write requests by considering the rules that ensure data coherence. For example, if there is a write request and then there is a read request for the same address, then the rules may indicate that the read request cannot be moved before the write request because the read request will return old data. Therefore, the sequencer component may reorder the operations based on the bandwidth of the memory component and enforce the timing of the time when the operations are transmitted to the memory component.

[0022] In some embodiments, a controller lacking a sequencer component may perform one or more operations related to memory management, memory mapping, and / or error correction. Data received by the controller and / or the results of the operations may be stored in a memory buffer of the controller. The controller may transmit the data and / or results to the sequencer component via a number of output pins. Each operation may be adapted via the sequencer component for a specific type of memory component included in a package coupled to the controller.

[0023] The controller may determine one or more configuration parameters to be used for different operations, and the one or more configuration parameters may be based on a memory type of a memory component associated with the controller and coupled to the sequencer component. The memory component may determine the memory type of the memory component by receiving an indication of the memory type from a host system, accessing the memory type previously stored in a local memory of the controller, or querying the sequencer component to obtain the memory type of the memory component coupled to the sequencer component. The controller may perform operations based on configuration parameters specific to the memory type.

[0024] For example, one memory management operation may include performing wear leveling on memory components in a package. Wear leveling may refer to alternating the memory components selected to perform read and / or write operations to ensure that each memory component wears evenly. Due to different properties of memory types, wear leveling schemes may differ based on the type of memory component (e.g., cross point array, flash, etc.). Thus, the memory components may determine first configuration parameters for a first wear leveling scheme for a first memory component having a first memory type and second configuration parameters for a second wear leveling scheme for a second memory component having a second memory type.

[0025] In another example, operations related to error correction may include error correction code operations that may be used to improve the reliability of data stored in the memory subsystem. Error correction code operations may refer to techniques for representing a sequence of data so that errors introduced into the data can be detected and corrected based on other remaining data. The sequence of data may be referred to as a codeword. Types of error correction codes may include block codes (e.g., Hamming codes, Reed Solomon codes, etc.). Typically, an encoder encodes data to be written with extra data bits to form a codeword, and portions of the codeword may be distributed (e.g., partitioned) across memory components of the memory subsystem. When the data is to be read, a decoder decodes the codeword by removing the extra data bits and providing the required original data.

[0026] The configuration parameters for the error correction code operation may include error correction code parameters (e.g., encoding / decoding) for the memory type of the memory component. The controller may receive data from the host system and generate codewords for the data using the error correction code operation based on the configuration parameters. The codewords may then be sent to a sequencer component external to the controller, and the sequencer component may distribute the codewords according to the timing requirements and rules described above.

[0027] In another example, a memory mapping operation may include performing an address translation. The host system may utilize an address space that is different from the actual physical address space of the memory component. Therefore, the memory component may determine the configuration parameters of the memory mapping operation to be used for the memory type of the memory component. The memory component may perform a logical address mapping to a physical address mapping based on the configuration parameters of the type of memory component involved in the operation. The memory component may send the physical address in the command to the sequencer.

[0028] In another embodiment, the controller may determine configuration parameters for operations performed by the sequencer component and send the configuration parameters to the sequencer component. The configuration parameters may include timing requirements for a memory type of a memory component coupled to the sequencer component. As described above, the sequencer component may time issuing commands to the memory component (e.g., read / write operations) based on the timing requirements for the memory type of the memory component.

[0029] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is described. The memory subsystem 110 may include media, such as a memory component 112. The memory component 112 may be a volatile memory component, a non-volatile memory component, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem.

[0030] In some embodiments, memory components 112 may be included in separate corresponding packages 130A to 130N. As depicted, memory components 112A(1) to 112N(1) are coupled to a first sequencer component 140A in a first package 130A, and memory components 112A(2) to 112N(2) are coupled to another sequencer component 140N in another package 130N. Each of sequencer components 140A to 140N may be fabricated in independent silicon, and each of memory components 112 may be fabricated in independent dies. In conventional memory subsystems, sequencer component 140 is typically located within a memory system controller 115 (hereinafter referred to as "controller"). Sequencer component 140 and corresponding memory component 112 may be included in a single package and coupled via short traces 160 to improve the performance of issuing commands from sequencer component 140 to memory component 112. By using shorter traces between the sequencer component 140 and the memory components, power load consumption can be reduced and data signal integrity can be increased compared to conventional arrangements. In addition, as discussed herein, moving the sequencer component 140 to a package 130 separate from the controller 115 can provide many other benefits, such as reducing the physical size of the memory subsystem 110, increasing the bandwidth between the controller 115 and the memory components 112, and so on.

[0031] For example, the sequencer component 140 and the memory component 112 in the package 130 may be coupled to the controller 115 via a SerDes interface 150, as compared to a parallel interface. The SerDes interface 150 provides higher bandwidth than a parallel interface and also uses fewer outgoing pins, thereby reducing the number of pins required by the controller 115 to provide a memory subsystem 110 with the same capacity (e.g., the number of memory components 112). For example, a SerDes interface may use six pins (e.g., two for clock, two for transmit, and two for receive), whereas a parallel interface may operate using more than twenty pins. Reducing the outgoing pin count of the controller 115 may improve the form factor of the entire memory subsystem 110 by reducing the size of the controller 110. In addition, removing the sequencer component 140 from the controller 115 may also reduce the size of the controller 115.

[0032] The sequencer components 140A-140N may perform one or more operations and may be configured based on the type of memory component 112 to which the corresponding sequencer component is coupled. For example, the sequencer component 140A may receive various data from the controller 115 and schedule the time to issue read / write commands to the attached memory components 112A(1)-112A(1) based on the timing requirements of the type of attached memory components 112A(1)-112A(1) and certain rules for ensuring data coherence, etc. In some embodiments, one sequencer component 140 is coupled to a memory component 112 of a single memory type. There may be many sequencer components 140 included in each package 130, and thus, a single package 130 may include memory components 112 of different types coupled to different corresponding sequencer components 140 within the package 140. In additional embodiments, each package 140 may include a memory component 112 having a single memory type, and thus, each package 130 may be dedicated to providing operating characteristics associated with the type of memory component 112 being used.

[0033] In general, the computing environment 100 may include a host system 120 that uses a memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110. The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of the physical host interface include, but are not limited to, a Serial / Serial-to-Parallel Converter (SerDes) interface, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0034] The memory components 112 may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include negative-and (NAND) type flash memory. Each of the memory components 112 may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, the memory components 112 may be based on any other type of memory, such as volatile memory. In some embodiments, the memory component 112 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a negative-or (NOR) flash memory, an electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory may perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, the cross-point non-volatile memory may perform write-in-place operations, where the non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. Furthermore, the memory cells of the memory component 112 may be grouped into memory pages or data blocks, which may refer to cells of a memory component used to store data.

[0035] The controller 115 may communicate with the memory component 112 via the sequencer component 140 to perform operations, such as reading data, writing data, or erasing data at the memory component 112, as well as other such operations. In one example, and as further discussed below, the controller 115 may include an error component 116. Error correction codes may be used to improve the reliability of data stored in the memory subsystem 110. Error correction codes may refer to techniques for representing a sequence of data so that errors introduced into the data can be detected and corrected based on other remaining data. The sequence of data may be referred to as a codeword. Types of error correction codes may include block codes (e.g., Hamming codes, Reed Solomon codes, etc.).

[0036] The error component 116 may perform an error correction code encoding operation that encodes data received by the host system 120 with extra data bits (e.g., parity bits) to form a codeword to be written to the memory component 112 via the sequencer component 140. The error component 116 may also perform an error correction code decoding operation that decodes the codeword by removing the extra data bits. The encoding / decoding operation may use certain configuration parameters based on the type of memory component 112 on which the data is to be stored. The controller 115 may send one or more codewords to the sequencer component 140A. The sequencer component 140A may determine which portions of which codewords are stored on the memory components 112A(1)-112N(1) by considering the bandwidth and availability of the memory components 112A(1)-112N(1), the timing requirements of the memory components 112A(1)-112N(1) (e.g., read / write latency), and rules regarding the sequencing of read / write operations. One goal of the sequencer component 116 may be to maximize the bandwidth of the interface between the sequencer component 116 and the memory components 112A( 1 ) through 112N( 1 ).

[0037] The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communications between the memory subsystem 110 and the host system 120). In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory component 112. The controller 115 may include an error component 116 that performs error correction code operations, a memory mapping component 118 that performs address translation between logical block addresses and physical block addresses associated with the memory component 112, and a memory management component 121 that performs wear leveling operations. The processing device 117 may execute the various components 116, 118, and 121. In addition, the various components 116, 118, and 121 may use configuration parameters specific to the type of memory component 112 included in the memory subsystem 110. The configuration parameters may be received from the host system 120, and the configuration parameters may be pre-stored in the local memory 119 during the manufacturing process, and / or the configuration parameters may be extracted from the package 130 via the sequencer component 140 by querying what type of memory component 112 is included in the package 130. In some cases, the sequencer component 140 may provide a notification indicating the type of memory component 112 with which it is associated.

[0029] Additional details regarding the operation of the error component 116, the memory mapping component 118, and the memory management component 121 are described below.

[0039] The controller 115 may be responsible for other operations, such as garbage collection operations, encryption operations, and / or cache operations. The controller 115 may further include a host interface circuit to communicate with the host system 120 via a physical host interface. The host interface circuit may convert commands received from the host system into command instructions to access the memory component 112 via the sequencer components 140A to 140N, and convert responses associated with the memory component 112 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory component 112.

[0041] Figure 2An example package 130A is illustrated that includes multiple sequencer components 140 operatively coupled to different memory components 112 having different memory types in accordance with some embodiments of the present disclosure. As depicted, a first sequencer component 140A(1) is coupled to first memory components 112A(1.1)-112N(1.2) having a first memory type (e.g., NAND flash), and a second sequencer component 140N(1) is coupled to second memory components 112A(2.1)-112N(2.2) having a second memory type (e.g., cross point array). It should be understood that any number of sequencer components coupled to corresponding memory components having corresponding memory types may be included in a package 130 to meet the desired performance attributes of the package 130.

[0042] Figure 3 is a flow chart of an example method 300 for executing instructions according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 140A. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0043] At block 310, the processing device receives an instruction at a sequencer component 140A. The instruction may be received from a controller 115. The sequencer component 140A may be located in a package 130A that includes the sequencer component 140A coupled to one or more memory components 112A(1) to 112N(1). The sequencer component 140A may be fabricated in its own independent silicon, the memory components 112A(1) to 112N(1) may be fabricated in its own independent die, and the independent silicon and independent die may be included in the package 130A. The sequencer component 140A may be coupled to the controller 115 separate from the package 130A. The sequencer component 140A may be coupled to the controller 115 via a SerDes interface. The traces between the sequencer component 140A and the memory components 112A(1) to 112N(1) may be shorter than the traces between the sequencer component 140A and the controller 115.

[0044] At block 320, the processing device of the sequencer component 140A performs operations on at least one of the one or more memory components 112A(1)-112N(1) based on the instructions. The operations may include interfacing with the one or more memory components 112A(1)-112N(1) via a protocol specific to the type of the memory components 112A(1)-112N(1), enforcing operation timing requirements on the one or more memory components 112A(1)-112N(1) based on the type of the memory components 112A(1)-112N(1), and reordering operations based on rules related to data coherency.

[0045] In some embodiments, the processing device may enforce timing requirements for when to issue commands based on the read / write latency of the various memory components 112A(1)-112N(1). For example, if the latency of how long it takes for a memory component 112A(1)-112N(1) to perform an operation is determined, the processing device may schedule the time to issue subsequent commands to the memory component 112A(1)-112N(1). In some cases, the latency may be determined based on configuration parameters. In another case, the processing device may determine the latency dynamically. In addition, if the latency changes during use of the memory component, the processing device may account for the change when issuing other commands. The processing device may enforce timing requirements to maximize the bandwidth between the sequencer component 140A and the memory components 112A(1)-112N(1).

[0046] In addition, the processing device may reorder operations based on rules related to the commands and addresses involved in the instructions received from the controller 115. In general, the processing device may reorder the read and write operations to maximize the bandwidth between the sequencer component 140A and the memory components 112A(1) to 112N(1). For example, if there is a read operation received for a first address, but the memory component 112A(1) containing the address is busy, then the read operation may be moved with another operation that can be executed earlier to improve performance. If the reordering satisfies the rules, then the reordering may be performed. For example, the instruction may specify a write and a read at the same address of the memory component 112A(1). In this case, the rules may specify that the operations cannot be reordered because if the read operation is reordered first, then the read operation will provide old data before the write operation updates the data.

[0047] In some embodiments, the second sequencer component 140N may receive the second instruction. The second sequencer component 140N may be located in another package 140N, and the second sequencer component 140N may be operatively coupled to one or more second memory components 112A(2) to 112N(2) within the second package 130N. The second sequencer component 140N may be operatively coupled to the controller 115. The memory components 112A(2) to 112N(2) in the second package 130N may include a memory type different from the memory components 112A(1) to 112N(1) in the package 130A. The second sequencer component 140N may interface with the second memory type via a protocol specific to the second memory type.

[0048] Figure 4 is a flow chart of an example method for performing operations on a memory component according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1 140A. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0049] At block 410, a processing device of sequencer component 140A receives instructions from a controller 115 located external to a system that includes sequencer component 140A. In some embodiments, the system may be package 130A. Package 130A may include sequencer component 140A operatively coupled to memory component 112A(1). Sequencer component 140A may be operatively coupled to controller 115 external to package 130A. In some embodiments, a trace between sequencer component 140A and memory component 112A(1) may be shorter than a trace between controller 115 and sequencer component 140A. Sequencer component 140A and controller 115 may be coupled via a SerDes interface.

[0050] At block 420, the processing device determines an operation to be performed on the memory component 112A(1) based on the instruction. The instruction may be to write data to a physical address of the memory component 112A(1) or to read data from a physical address of the memory component 112A(1). For example, the instruction may include a codeword, and the operation may include dividing the codeword into portions and issuing commands to store the portions on one or more data blocks of the memory component 112A(1). The codeword may be encoded by the controller 115 based on configuration parameters specific to the type of memory component 112A(1) included in the package 130A. The processing device may determine the timing of when to perform the operation based on the timing requirements of the memory type of the memory component 112A(1).

[0051] At block 430, the processing device performs an operation on the memory component 112A(1). For example, the processing device may cause the memory component 112A(1) to write a portion of the codeword to one or more data blocks of the memory component 112A(1).

[0052] In some cases, the processing device may also receive a second instruction from a controller 115 external to the system before performing the operation. The processing device may determine the second operation to be performed on the memory component 112A(1) based on the second instruction. The processing device may determine that the second operation is to be performed before the operation based on a rule. For example, the first instruction may be associated with a read operation to an address, and the second instruction may be associated with a write operation to an address. The rule may specify that the write operation is to be performed before the read operation so that the read operation returns current data. The processing device may then perform the second operation on the memory component 112A(1) before the operation, and then perform the operation on the memory component 112A(1).

[0053] Figure 5A controller 115 including a reduced number of pins 500 and a reduced form factor according to some embodiments of the present disclosure is described. The controller is coupled to the package 130A via a connection 150, which may be a SerDes interface in some embodiments. As described above, the SerDes interface may use approximately six outgoing pins of the controller 115 to communicate with the sequencer component 140A. The six outgoing pins may include two pins for clock, two pins for transmission, and two pins for reception. It should be appreciated that in conventional systems, a parallel interface with twenty or more pins is typically used to connect the controller 115 to the memory component 112. However, embodiments of the present disclosure may use a SerDes interface by moving the sequencer component 140A to the package 130A having the memory components 112A to 112N and indirectly connecting the controller 115 to the memory components 112A to 112N through the sequencer component 140A. Thus, the bandwidth between the controller 115 and the memory components 112A- 112N may be increased using the SerDes interface 150 , the size of the controller 115 may be reduced due to the reduced number of pins 500 , and the physical size of the memory subsystem 110 may be reduced, among other things.

[0054] As depicted, controller 115 includes an error component 116, a memory mapping component 118, and a memory management component 121. The various components 115, 116, and 121 may perform various operations based on configuration parameters specific to the type of memory components 112A- 112N included in package 130. Figures 6 to 8 Generally involves controller 115 using configuration parameters for specific types of memory components 112A-112N to perform different operations. Additionally, controller 115 may determine the type of memory components included in package 130A and may provide configuration parameters related to the timing requirements of the specific memory type to sequencer component 140A. Fig. 9 Generally involves the controller determining configuration parameters and transmitting the configuration parameters to the sequencer component 140A.

[0055] Figure 6 6 is a flow chart of an example method 600 for determining configuration parameters to be used for error correction code operation according to some embodiments of the present disclosure. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1116. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0056] At block 610, the processing device determines configuration parameters to be used for error correction code (ECC) operations. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. The memory component 112A(1) may be included in the package 130A with the sequencer component 140A. The sequencer component 140A and the memory component 112A(1) may be communicatively coupled. The controller 115 may be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface. The controller 115 may issue instructions to the sequencer component 140A, and the sequencer component 140A may determine various operations to be performed on the memory component 112A(1) associated with the controller 115.

[0057] The processing device may determine the configuration parameters in several ways. For example, in block 612, the processing device may receive a first data structure (e.g., a table) containing configuration parameters for one or more types of memory components 112 from the host system 120. In some embodiments, the processing device may be informed by the sequencer component 140A about the types of memory components 112A to 112N contained in the package 130A. In another embodiment, the sequencer component 140A may request the sequencer component 140A to provide the types of memory components 112A to 112N contained in the package 130A. The processing device may use the types of memory components 112A to 112N to search the first data structure to determine the configuration parameters to be used for error correction code operation. Specifically, the configuration parameters may relate to the encoding / decoding scheme used, which may change based on the type of memory components used.

[0058] Another way to determine the configuration parameters is shown in block 614, where the processing device may access a second data structure in the local memory 119 that includes the configuration parameters. The second data structure may be stored in the local memory 119 after the controller 115 is manufactured and upon initial setup and data loading to the controller 115. In some embodiments, the second data structure may be stored in the local memory 119 during an update of software, firmware, or the like. Similar to what was described above, the processing device may search the second data structure for the type of memory components 112A-112N being used and determine the configuration parameters to be used for error correction code operations.

[0059] Yet another way to determine configuration parameters is shown in block 616, where the processing device may query sequencer component 140A to obtain configuration parameters. For example, sequencer component 140A may receive a request from controller 115 and determine the configuration parameters by searching local memory of package 130A or based on properties of memory components 112A-112N known to sequencer component 140A. Sequencer component 140A may provide the configuration parameters to be used for error correction code operation to controller 115.

[0060] At block 620, the processing device receives data from the host system 120. The data may include data requested by the host system 120 to be stored in the memory subsystem 110. In one example, the data may be user data.

[0061] At block 630, the processing device generates a codeword for the data by using an ECC operation based on the configuration parameters. As described above, the configuration parameters may include ECC parameters for the memory type of the memory components 112A to 112N in the package 130A. The ECC parameters may specify an encoding / decoding scheme applied to the data during the ECC operation. It should be understood that the controller 115 may be associated with more than one memory component, and the other memory components may be of different types. Using the disclosed techniques, the controller 115 may determine the configuration parameters for the ECC operation to be used for each type of associated memory component, and may use the corresponding configuration parameters to perform the ECC operation.

[0062] At block 640, the processing device sends the codeword to the sequencer component 140A outside the controller 115. In some cases, the codeword to be written may be stored in the local memory 119 (e.g., a storage buffer), and the processing device may transmit the codeword stored at the storage buffer to the sequencer component 140A via a SerDes interface through an output pin of the controller 115.

[0063] In some embodiments, controller 115 may request to read a codeword from sequencer component 140A. Sequencer component 140A may provide the codeword, and controller 115 may decode the codeword based on the determined configuration parameters. In some cases, the decoded data may be transmitted by controller 115 to host system 120.

[0064] Figure 7 700 is a flow chart of an example method 700 for determining configuration parameters to be used for memory management operations according to some embodiments of the present disclosure. The method 700 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by Figure 1 121 of the memory management component 121. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0065] At block 710, the processing device determines configuration parameters to be used for memory management operations. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. In one example, the configuration parameters to be used for the memory management operation may relate to a wear leveling scheme for a particular type of memory component 112A(1). The memory component 112A(1) may be included in the package 130A along with the sequencer component 140A. The sequencer component 140A and the memory component 112A(1) may be communicatively coupled. The controller 115 may be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface. The controller 115 may issue instructions to the sequencer component 140A, and the sequencer component 140A may determine various operations to be performed on the memory component 112A(1) associated with the controller 115.

[0066] Similar to reference Figure 6 Determining Configuration Parameters to be Used for ECC Operations The processing device may determine the configuration parameters to be used for the memory management operation in a number of ways. For example, in block 712, the processing device may receive from the host system 120 a first data structure (e.g., a table) containing configuration parameters to be used for memory management operations for a particular type of memory component 112A(1). In another example, in block 714, the processing device may access a second data structure in the local memory 119 containing the configuration parameters to be used for the memory management operation. In yet another example, in block 716, the processing device may query the sequencer component 140A to obtain the configuration parameters to be used for the memory management operation. Additionally or alternatively, in some embodiments, the processing device may query the sequencer component 140A for the type of memory component 112A(1) and use the received response with any of the techniques described above.

[0067] At block 720, the processing device determines a wear leveling scheme for sequencer component 140A to apply to operations on memory component 112A(1) based on the configuration parameters. Certain types (e.g., cross point arrays, NAND flash, etc.) may include different properties, such as the rate at which the physical media degrades when performing operations. Using the configuration parameters for the type of memory component 112A(1), the processing device may determine a wear leveling scheme that evenly distributes read / write operations, disproportionately distributes read operations or write operations, or some combination thereof to different data blocks of memory component 112A(1) and / or memory components 112A(1)-112N(1) to ensure that the wear of the operations is distributed to increase the useful life of memory components 112A(1)-112N(1).

[0068] At block 730, the processing device sends the wear leveling scheme and / or data to the sequencer component 140A. The wear leveling scheme may refer to a schedule of which memory components are used to perform operations, or actual instructions to perform operations on certain memory components to implement wear leveling. In some cases, the wear leveling scheme and / or any data to be written may be stored in the local memory 119 (e.g., a memory buffer), and the processing device may transmit the wear leveling scheme and / or data stored at the memory buffer to the sequencer component 140A via an output pin of the controller 115.

[0069] The sequencer component 140A may use a wear leveling scheme that determines when to plan which memory components 112A(1)-112N(1) to be used for certain operations and when to perform operations on the memory components 112A(1)-112N(1). The wear leveling scheme that is tailored to the type of memory component 112 provides a flexible architecture in which different types of memory components 112 may be used based on their desired performance characteristics while still maximizing memory component 112 endurance.

[0070] Figure 8 800 is a flow chart of an example method 800 for determining configuration parameters to be used for memory mapping operations according to some embodiments of the present disclosure. The method 800 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 800 is performed by Figure 1118. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0071] At block 810, the processing device determines configuration parameters to be used for a memory mapping operation. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. In one example, the configuration parameters to be used for the memory mapping operation may include a memory mapping of physical addresses of a memory component 112A(1) of a particular type. The memory component 112A(1) may be included in the package 130A along with the sequencer component 140A. The sequencer component 140A and the memory component 112A(1) may be communicatively coupled. The controller 115 may be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface. The controller 115 may issue instructions to the sequencer component 140A, and the sequencer component 140A may determine various operations to be performed on the memory component 112A(1) associated with the controller 115.

[0072] Similar to reference Figure 6 Determining Configuration Parameters to be Used for ECC Operations The processing device may determine the configuration parameters to be used for memory mapping operations in a number of ways. For example, in block 812, the processing device may receive from the host system 120 a first data structure (e.g., a table) containing configuration parameters to be used for a particular type of memory mapping operation of the memory component 112A(1). In another example, in block 814, the processing device may access a second data structure in the local memory 119 containing the configuration parameters to be used for the memory mapping operation. In yet another example, in block 816, the processing device may query the sequencer component 140A to obtain the configuration parameters to be used for the memory mapping operation. Additionally or alternatively, in some embodiments, the processing device may query the sequencer component 140A for the type of the memory component 112A(1) and use the received response with any of the techniques described above.

[0073] At block 820, the processing device uses the memory map to translate the logical address where the data is to be read or written to a physical address on the memory component 112A(1) based on the configuration parameters. In some embodiments, the host system 120 may send data to the controller 115, and the data may include the logical address of where the data is to be stored in the host system 120. Using the memory map, the processing device may translate the logical address to a physical address in the memory component 112A(1).

[0074] At block 830, the processing device sends the physical address and / or data to the sequencer component 140A. In some cases, the physical address and / or data may be stored in the local memory 119 (e.g., a storage buffer), and the processing device may transmit the physical address and / or data stored at the storage buffer to the sequencer component 140A via an output pin of the controller 115.

[0075] The sequencer component 140A may use the physical address to write data to the memory component 112A (1). As can be appreciated, different types of memory components 112 may have different physical addresses. Thus, enabling the memory mapping component 118 to translate the logical address into any physical address specific to the target memory component 112 may provide the benefit of using different types of memory components 112 in the memory subsystem 110 based on the desired performance of the memory subsystem 110.

[0076] Fig. 9 1 is a flow chart of an example method 900 for determining configuration parameters for sequencer component operation and for sending configuration parameters to the sequencer component according to an embodiment of the present disclosure. The method 900 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 900 is performed by Figure 1 115. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0077] At block 910, the processing device determines configuration parameters for one or more operations performed by the sequencer component 140A. The configuration parameters are based on the memory type of the memory component 112A(1) associated with the controller 115. The operation may involve enforcing a timing requirement of a particular type for the memory component 112A(1). Thus, in some embodiments, the configuration parameters may include timing parameters that vary based on the type of memory component 112A(1), different generations of memory component 112A(1), and the like. The configuration parameters may also include rules for reordering operations. The memory component 112A(1) may be included in the package 130A with the sequencer component 140A. The sequencer component 140A and the memory component 112A(1) may be communicatively coupled. The controller 115 may be coupled to the sequencer component 140A external to the controller 115 via a SerDes interface.

[0078] Similar to reference Figure 6 Determining Configuration Parameters to be Used for ECC Operations The processing device may determine configuration parameters to be used for operations performed by sequencer component 140A in a number of ways. For example, in block 912, the processing device may receive from host system 120 a first data structure (e.g., a table) that includes configuration parameters for operations performed by sequencer component 140A based on a particular type of memory component 112A(1). In another example, in block 914, the processing device may access a second data structure in local memory 119 that includes configuration parameters for operations performed by sequencer component 140A. In yet another example, in block 916, the processing device may query sequencer component 140A to obtain the configuration parameters to be used for the operation. Additionally or alternatively, in some embodiments, the processing device may query sequencer component 140A for the type of memory component 112A(1) and use the received response with any of the techniques described above.

[0079] At block 920, the processing device sends the configuration parameters and / or any data to be written to the sequencer component 140A. In some cases, the configuration parameters and / or data may be stored in a local memory 119 (e.g., a storage buffer), and the processing device may transmit the configuration parameters and / or data stored at the storage buffer to the sequencer component 140A via an output pin of the controller 115.

[0080] Sequencer component 140A may use configuration parameters to perform operations. For example, the configuration parameters may include timing requirements for the type of memory component 112A(1), and the processing device may sequence the order of operations performed on memory component 112A(1) based on the timing requirements. In addition, the configuration parameters may include rules based on commands and addresses included in instructions to reorder the order of operations. As described above, sequencer component 140A may maximize the bandwidth between sequencer component 140A and memory component 112A(1) by enforcing the timing requirements and using the rules to reorder the order of operations.

[0081] Fig.10 An example machine of computer system 1000 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 1000 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 A host system (eg, a memory subsystem 110) of Figure 1 host system 120) or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 operation of the error component 116, the memory mapping component 118 and / or the memory management component 121) or Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0082] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0083] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030.

[0084] The processing device 1002 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1002 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1002 is configured to execute instructions 1026 for performing the operations and steps discussed herein. The computer system 1000 may further include a network interface device 1008 to communicate via a network 1020.

[0085] The data storage system 1018 may include a machine-readable storage medium 1024 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. The instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution by the computer system 1000, with the main memory 1004 and the processing device 1002 also constituting machine-readable storage media. The machine-readable storage medium 1024, the data storage system 1018, and / or the main memory 1004 may correspond to Figure 1 Memory subsystem 110.

[0086] In one embodiment, instructions 1026 include instructions for implementing a command corresponding to Figure 1The machine-readable storage medium 1024 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0087] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to other skilled in the art. In this article, and generally, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been demonstrated that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily for commonly used reasons.

[0088] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms that data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0089] The present disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0090] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0091] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0092] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method for a memory device, comprising: determining, by a processing device, configuration parameters to be used for error correction code (ECC) operations, wherein the configuration parameters are based on a memory type of a memory component managed by a memory system controller; receiving data from a host system; generating a codeword of the data by performing the ECC operation using the configuration parameters; identifying a sequencer of a plurality of sequencers collocated within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component; as well as The codeword is sent to the sequencer. 2 . The method of claim 1 , wherein sending the codeword to the sequencer comprises sending the codeword via a serializer / deserializer (SerDes) interface.

3. The method of claim 1 , wherein determining the configuration parameters further comprises: receiving the configuration parameters from the host system; identifying the configuration parameters in a local memory of the memory system controller; or The sequencer is queried to obtain the memory type, wherein the configuration parameters are based on the memory type.

4. The method according to claim 1, further comprising: determining a second configuration parameter to be used for a memory management operation, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; determining a wear leveling scheme of the sequencer to apply to operations performed on the memory component based on the second configuration parameter; as well as Instructions indicative of the wear-leveling scheme are sent to the sequencer.

5. The method according to claim 1, further comprising: determining a second configuration parameter to be used for a memory mapping operation, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; translating a logical address associated with the data into a physical address on the memory component based on the second configuration parameter; as well as The physical address is sent to the sequencer.

6. The method of claim 1, wherein sending the codeword to the sequencer comprises sending the codeword through one or more output pins of the memory system controller.

7. The method according to claim 1, further comprising: determining a second configuration parameter to be used by the sequencer to write the codeword to the memory component, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; as well as The second configuration parameters are sent to the sequencer for use in writing the codeword to the memory component.

8. The method of claim 7, wherein the second configuration parameter comprises a timing requirement for the memory type of the memory component.

9. The method according to claim 1, further comprising: determining, by the processing device, second configuration parameters to be used for the error correction code (ECC) operation, wherein the second configuration parameters are based on a second memory type of a second memory component associated with the memory system controller; generating, by the processing device that performs the ECC operation, a second codeword using the data based on the second configuration parameters; as well as The codeword is sent to the sequencer external to the memory system controller.

10. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determining configuration parameters to be used for error correction code (ECC) operations, wherein the configuration parameters are based on a memory type of a memory component managed by a memory system controller; receiving data from a host system; generating a codeword of the data by performing the ECC operation using the configuration parameters; identifying a sequencer of a plurality of sequencers collocated within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component; as well as The codeword is sent to the sequencer.

11. The computer-readable storage medium of claim 10, wherein to send the codeword to the sequencer external to the memory system controller, the processing device is further configured to send the codeword via a serializer / deserializer (SerDes) interface.

12. The computer-readable storage medium of claim 10, wherein to determine the configuration parameters, the processing device is further configured to: receiving the configuration parameters from a host system; accessing the configuration parameters in a local memory of the memory system controller; or The sequencer is queried to obtain the memory type, wherein the configuration parameters are based on the memory type.

13. The computer-readable storage medium of claim 10, wherein the processing device is further configured to: determining a second configuration parameter to be used for a memory management operation, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; determining a wear leveling scheme of the sequencer to apply to operations performed on the memory component based on the second configuration parameter; as well as Instructions indicative of the wear-leveling scheme are sent to the sequencer.

14. The computer-readable storage medium of claim 10, wherein the processing device is further configured to: determining a second configuration parameter to be used for a memory mapping operation, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; translating a logical address associated with the data into a physical address on the memory component based on the second configuration parameter; and The physical address is sent to the sequencer.

15. The computer-readable storage medium of claim 10, wherein to send the codeword to the sequencer external to the memory system controller, the processing device is further configured to send the codeword through one or more output pins of the memory system controller.

16. The computer-readable storage medium of claim 10, wherein the processing device is further configured to: determining, by the processing device, a second configuration parameter to be used for operations performed by the sequencer, wherein the second configuration parameter is based on the memory type of the memory component associated with the memory system controller; and The second configuration parameters are sent to the sequencer for use in the operations performed by the sequencer.

17. A memory system comprising: Multiple output pins; a memory buffer for storing data; as well as a processing device operatively coupled to the memory buffer and the plurality of output pins to transmit the data stored at the memory buffer through the plurality of output pins to a sequencer of a plurality of sequencers collocated within a single package external to a memory system controller, wherein each of the plurality of sequencers interfaces with a corresponding memory component.

18. The memory system of claim 17, wherein the processing device is further configured to: identifying configuration parameters for error correction operations performed by the memory system controller, wherein the configuration parameters are based on a memory type of one or more memory components operatively coupled to the sequencer; and The error correction operation is performed on the data based on the configuration parameters before transmitting the data to the sequencer.

19. The memory system of claim 17, wherein the processing device is further configured to: identifying configuration parameters for one or more operations performed by the sequencer, wherein the configuration parameters are based on a memory type of one or more memory components operatively coupled to the sequencer; and The configuration parameters are sent to the sequencer for use by the sequencer in the one or more operations.

20. The memory system of claim 17, further comprising a serializer / deserializer (SerDes) interface coupled to the processing device, and wherein the processing device transmits the data to the sequencer through the plurality of output pins via the SerDes interface.

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