Fast activation for memory sensing

Abstract

The present application is directed to fast activation for memory sensing. An operating mode may be configured at a memory device, the operating mode being associated with a command sequence having a reduced duration relative to another operating mode. The operating mode may be configured based on a determination that a test program does not attempt to maintain or is independent of maintaining a logical state of an accessed memory cell and other conditions. When operating in the mode, the memory device may execute a received activation command using a first set of operations having a first duration, rather than a second set of operations having a second, longer duration, to execute the received activation command. The first set of operations may also use less current or introduce less interference into the memory device relative to the second set of operations.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 16 / 686,071 of Majerus, entitled “QUICK ACTIVATE FOR MEMORY SENSING,” which was filed on November 15, 2019, which has been assigned to the assignee of this application, and the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to fast activation for memory sensing. Background Art

[0004] The following relates generally to systems including at least one memory device, and more particularly to executing a fast activate command sequence.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, usually represented by a logical 1 or a logical 0. In other devices, more than two states can be stored. To access the stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memories such as FeRAM can retain their stored logic states for extended periods of time even in the absence of external power. Volatile memory devices such as DRAM can lose their stored states when disconnected from external power. FeRAM can achieve densities similar to volatile memories, but can have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

[0007] Before deploying the memory device, a test program may be performed on the memory device to identify defects and ensure the reliability of the memory device. The test program may also be performed to identify failures of the memory device that may occur when the memory device is deployed. Summary of the invention

[0008] A method is disclosed herein. The method may include configuring a memory device including a memory array to operate in a first mode, the first mode being associated with a command sequence having a reduced duration relative to a second mode; after configuring the memory device to operate in the first mode, receiving an activate command associated with a memory cell of the memory array; and performing a first set of operations for executing the activate command based at least in part on configuring the memory array to operate in the first mode, wherein when the memory device is configured in the second mode, the first set of operations is performed within a shorter duration than a second set of operations for executing the activate command.

[0009] A device is disclosed herein. The device may include a memory unit and a memory controller, the memory controller being coupled to the memory unit and configurable to operate in a first mode, the first mode being associated with an activation sequence having a reduced duration relative to a second mode. The memory controller is operable to perform a first set of operations associated with the first mode to execute an activation command when configured in the first mode, or to perform a second set of operations associated with the second mode to execute the activation command for accessing the memory unit when configured in the second mode, wherein a duration for performing the first set of operations is shorter than a duration for performing the second set of operations.

[0010] Another apparatus is disclosed herein. The apparatus may include a memory array, the memory array including memory cells and a memory controller coupled to the memory array. The memory controller is operable to configure a first mode, the first mode being associated with one or more command sequences having a reduced duration relative to a second mode; receive an activate command associated with the memory cells after configuring the first mode; and perform a first set of operations for executing the activate command based at least in part on configuring the memory array to operate in the first mode, wherein when the second mode is configured, the first set of operations is performed within a shorter duration than a second set of operations for executing the activate command. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system that supports execution of a rapid activation command sequence as disclosed herein is shown.

[0012] Figure 2 An example of a memory die that supports execution of a fast activate command sequence as disclosed herein is shown.

[0013] Figure 3An example of a method for executing the rapid activation command sequence disclosed herein is shown.

[0014] Figure 4 A block diagram of a memory device that supports execution of a fast activate command sequence as disclosed herein is shown.

[0015] Figure 5 and 6 A flow chart illustrating a method for supporting execution of the rapid activation command sequence disclosed herein is shown. DETAILED DESCRIPTION

[0016] Information may be stored in and read from a memory device using an access command that triggers performance at the memory device of a sequence of operations for accessing (e.g., reading or writing) a memory cell addressed by the access command. In some examples, the sequence of operations (or "access command sequence") for executing a received access command differs based on the technology used by the memory device. For example, an access command sequence (e.g., an activate (ACT) command sequence) for accessing a ferroelectric memory cell may include additional operations and have a longer duration than a corresponding access command sequence (e.g., an ACT command sequence) for accessing a dynamic random access memory (DRAM) cell.

[0017] In some examples, access commands are also used to implement a test program for a memory device. That is, the test program may apply a series of voltages to specific components of the memory device in a specific order by providing a specific series of access commands to the memory device. However, as the capacity of the memory device increases, the duration of the test program also increases. This increase in test program duration may be exacerbated for memory devices that use access commands to implement test programs and techniques associated with access command sequences of longer duration. In addition to the increased test program duration, using access command sequences to implement the test program may result in increased current (and therefore power) usage and unexpected interference that may negatively affect the test program, for example, when the access command sequence causes the memory device to perform unnecessary operations that modify the voltage of one or more memory components.

[0018] In order to reduce the test duration, reduce the current draw during the test process, and mitigate the negative effects of unexpected interference, a new access command sequence can be used when testing a memory device. For example, when executing a test program, a set of modified operations can be used to execute an ACT command. In some instances, an ACT command can be executed using a set of operations that omits operations that would otherwise be performed to execute the ACT command, for example, operations associated with exchanging charge between a memory cell and a digital line or with sensing the voltage of a bit line to determine a logical state stored by a corresponding memory cell can be omitted, or both. By omitting certain operations in the set of modified operations, the duration of the ACT command sequence can be reduced, the amount of current drawn by the memory device during the ACT command sequence can be reduced, or the amount of interference caused by the ACT command sequence can be reduced, or any combination thereof. In some instances, a set of modified operations for executing an ACT command is referred to as a fast ACT command sequence, and a set of unmodified operations can be referred to as an ACT command sequence.

[0019] In some instances, a fast ACT command may be used when a test procedure executed on a memory device is independent of the logic state of the memory cells, for example, when the test procedure is unrelated to whether the correct logic state is being read from the memory cells and written back to the memory cells during the test procedure. Additionally or alternatively, a fast ACT command may be used when the duration of the ACT command sequence exceeds a threshold duration, the amount of current drawn by the ACT command sequence exceeds a threshold current, or the amount of disturbance caused by the ACT command sequence exceeds a threshold amount, or any combination thereof. Additionally or alternatively, a fast ACT command sequence may be used to support a test procedure that is intended to test a component without adjusting for additional voltages applied to or removed from the component during the ACT command sequence.

[0020] As reference Figure 1 and 2 As described, the features of the present disclosure are initially described in the context of memory systems and dies. Figure 3 Features of the present disclosure are described in the context of an exemplary method for rapidly activating a command sequence in FIG. Figures 4 to 6 These and other features of the present disclosure are further illustrated and described in the device diagrams and flow charts related to executing a fast activation command sequence.

[0021] Figure 1 An example of a system 100 that supports execution of a rapid activation command sequence as disclosed herein is shown.

[0022] The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110). The system 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, etc. The memory device 110 may be a component of the system that is operable to store data for one or more other components of the system 100.

[0023] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processing, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, or some other fixed or portable electronic device. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0024] Memory device 110 may be a stand-alone device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme to modulate a signal, various pin configurations for transmitting a signal, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0025] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as a slave-type device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). These commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0026] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0027] The processor 125 is operable to provide control or other functions for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such an example, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system on a chip (SoC), etc. In some examples, the external memory controller 120 can be implemented by or as part of the processor 125.

[0028] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of a read-only memory (ROM), flash memory, or other non-volatile memory.

[0029] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired capacity or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more libraries, one or more blocks, one or more sectors), each of which is operable to store at least one data bit. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0030] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0031] In some examples, memory device 110 may receive data or commands or both from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 will store data for host device 105 or a read command indicating that memory device 110 will provide data stored in memory die 160 to host device 105.

[0032] A local memory controller 165 (e.g., local to the memory die 160) is operable to control the operation of the memory die 160. In some examples, the local memory controller 165 is operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0033] The external memory controller 120 is operable to enable communication of one or more of information, data, or commands between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between a component of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105 or their functions described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although in some examples, the external memory controller 120 is depicted as being external to the memory device 110, the external memory controller 120 or its functions described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165) or vice versa.

[0034] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, a channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of the system 100, and the pin may be operable to act as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some instances, communication on channel 115 may be performed using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., at a rising edge or a falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., at both a rising edge and a falling edge of a clock signal).

[0036] In some examples, the channels 115 may include one or more command and address (CA) channels 186. The CA channels 186 are operable to transmit commands between the host device 105 and the memory device 110, the commands including control information associated with the commands (e.g., address information). For example, the CA channels 186 may include a read command with an address of desired data. In some examples, the CA channels 186 may include any number of signal paths to decode one or more of the address or command data (e.g., eight or nine signal paths).

[0037] In other aspects, the reliability or defects of the memory device 110 may be tested, for example, before or while the memory device 110 is deployed. In some examples, a test program running on the host device 105 may provide a memory (or access) command sequence to the memory device 110 (e.g., via the channel 115) to execute the test program on the memory device 110. In some examples, the memory device 110 may be configured to execute the received access command using a modified access command sequence based on being configured in a specific operating mode (e.g., a test mode). For example, when the memory device 110 is configured in a test mode that ignores data stored in the accessed memory cells, the memory device 110 may execute an access command sequence that omits one or more operations that would otherwise be used to execute the received access command. The access command sequence that omits the operations may be shorter, use less current, or introduce less interference (or any combination thereof) than the access command sequence that includes the omitted operations.

[0038] Figure 2 An example of a memory die 200 that supports execution of a fast activate command sequence as disclosed herein is shown.

[0039] Memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store a different logic state (e.g., a programmed one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11).

[0040] Memory cell 205 may store a state (e.g., a polarization state or dielectric charge) in a capacitor representing a programmable state. In a FeRAM architecture, memory cell 205 may include capacitor 240, which includes a ferroelectric material to store a charge and / or polarization representing a programmable state. Memory cell 205 may include a logic storage component (such as capacitor 240) and a switch component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switch component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switch component 245 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0041] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a pattern such as a grid-like pattern. The access lines may be conductive lines coupled to the memory cells 205 and may be used to perform access operations on the memory cells 205. In some instances, the word lines 210 may be referred to as row lines. In some instances, the digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or the like, are interchangeable without loss of understanding or operation. The memory cells 205 may be located at the intersections of the word lines 210, digit lines 215, and / or plate lines 220.

[0042] By activating or selecting access lines such as word lines 210, digit lines 215, and / or plate lines 220, operations such as reading and writing can be performed on memory cells 205. By biasing word lines 210, digit lines 215, and plate lines 220 (e.g., applying voltages to word lines 210, digit lines 215, or plate lines 220), individual memory cells 205 can be accessed at their intersections. Activating or selecting word lines 210, digit lines 215, or plate lines 220 can include applying voltages to the corresponding lines.

[0043] Access to the memory cell 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from the local memory controller 265, and activate the word line 210 based on the received row address. The column decoder 230 may receive a column address from the local memory controller 265, and activate the digit line 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265, and activate the plate line 220 based on the received plate address.

[0044] Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switch component 245. Using switch component 245, capacitor 240 may be in electronic communication with digit line 215. For example, capacitor 240 may be isolated from digit line 215 when switch component 245 is deactivated, and capacitor 240 may be coupled to digit line 215 when switch component 245 is activated.

[0045] The word line 210 may be a conductive line in electronic communication with the memory cell 205, which is used to perform access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching component 245 of the memory cell 205 and may be operable to control the switching component 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

[0046] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during a portion of an access operation. For example, the word line 210 and the switch component 245 of the memory cell 205 can be operated to selectively couple and / or isolate the capacitor 240 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0047] Plate line 220 may be a conductive line in electronic communication with memory cell 205, which is used to perform access operations on memory cell 205. Plate line 220 may be in electronic communication with a node (e.g., the bottom of the cell) of capacitor 240. Plate line 220 may cooperate with digit line 215 to bias capacitor 240 during access operations of memory cell 205.

[0048] The sensing component 250 can determine the state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine the logic state of the memory cell 205 based on the detected state. The sensing component 250 can include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sensing component 250 can compare the signal received from the memory cell 205 across the digital line 215 with the reference line 255 (e.g., a reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., provided to the input / output 260), and the detected logic state can be indicated to another component of the memory device 110 including the memory die 200.

[0049] The local memory controller 265 may control the operation of the memory cell 205 through various components (eg, the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250). The local memory controller 265 may be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 225, column decoder 230, and plate driver 235 and sensing component 250 can be co-located with the local memory controller 265. The local memory controller 265 is operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), convert the command or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transmit data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 265 can generate row signals and column address signals to activate the target word line 210, the target digital line 215, and the target plate line 220. The local memory controller 265 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the magnitude, shape, or duration of applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating memory die 200 .

[0050] The local memory controller 265 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, etc. The local memory controller 265 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0051] The local memory controller 265 is operable to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. The local memory controller 265 may identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled to the target memory cell 205. The local memory controller 265 may activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. During a write operation, the local memory controller 265 may apply a specific signal (e.g., a write pulse) to the digit line 215 to store a specific state (e.g., charge) in the capacitor 240 of the memory cell 205. A pulse used as part of a write operation may include one or more voltage levels for a duration.

[0052] The local memory controller 265 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in a memory cell 205 of the memory die 200 may be determined. The local memory controller 265 may identify a target memory cell 205 on which a read operation is to be performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled to the target memory cell 205. The local memory controller 265 may activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 can activate the sense component 250 (eg, latch the sense component) and thereby compare the signal received from the memory cell 205 to the reference line 255. Based on the comparison, the sense component 250 can determine the logic state stored on the memory cell 205.

[0053] Information can be stored in and read from the memory die 200 using access commands that trigger a set of operations (which may also be referred to as a command sequence or access command sequence) to be performed at the memory die 200. In some examples, the signal used to transmit the access command includes an indication of the type of the access command (e.g., using two bits transmitted in the signal) and the address of the memory cell targeted by the access command (e.g., using the remaining bits transmitted in the signal) to indicate a memory bank, a memory segment, or a memory row, or any combination thereof. The types of access commands may include an activate (ACT) command and a precharge (PRE) command. The ACT command may be used to prepare (or open) an addressed row of memory cells 205 for subsequent read or write operations. For example, the ACT command may be used to connect all memory cells 205 coupled to a word line 210 (e.g., WL_1) to coupled digital lines 215 (e.g., DL_1 to DL_N). In some examples, the ACT command may also be used to sense the logic state of the row of memory cells 205 after the row of memory cells 205 is connected to the digit line 215 , for example, by activating a sense component 250 coupled to the digit line 215 .

[0054] The PRE command may be used to close an opened row of memory cells 205 before opening or accessing or opening and accessing another row of memory cells 205. In some examples, the PRE command may be used to close a memory segment or memory bank including a row of memory cells 205 so that a different row of memory cells 205 in the memory segment or memory bank may be opened. For example, the PRE command may be used to disconnect a row of memory cells 205 (e.g., WL_1) coupled to a word line 210 from coupled digital lines 215 (e.g., DL_1 to DL_N). In some examples, the PRE command may also be used to write a previously sensed logic state (e.g., a logic state sensed by the sense component 250 during an ACT command) back to the row of memory cells 205. In some examples, the output of the sense component 250 is used to write the previously sensed logic state back to the row of memory cells 205. In some examples, the local memory controller 265 at the memory die 200 may receive an access command from an external device (e.g., a host device). In other examples, the access commands may be generated internally by the memory die 200 , for example, the local memory controller 265 may generate the access commands based on a test program installed on the local memory controller 265 or another component on the memory die 200 .

[0055] The local memory controller 265 may execute the received or generated access command. To execute the access command, the local memory controller 265 may execute a set of operations (or access command sequence) corresponding to the access command, for example, the local memory controller 265 may apply a series of voltages to a specific component in a predetermined order. In some instances, the duration for executing an access command sequence for executing an access command for one technology may be longer than the duration for executing the same access command sequence for another technology. For example, an access command sequence for executing an access command for accessing a memory cell of one technology may include a longer timing interval, or additional operations relative to an access command sequence for executing the same access command for accessing a memory cell of another technology, or both. For example, executing an access command sequence to execute an ACT command (or an ACT command sequence) to open a row of ferroelectric memory cells may take longer than executing an ACT command sequence to open a row of DRAM cells. Similarly, executing a set of operations to execute a PRE command (or a PRE command sequence) to close a row of ferroelectric memory cells may take longer than executing a PRE command sequence to close a row of DRAM cells.

[0056] In some examples, executing an ACT command sequence for one or more ferroelectric memory cells 205 can include three sets of operations. That is, the ACT command sequence can include a first set of operations associated with connecting the one or more ferroelectric memory cells 205 to one or more digit lines 215. The ACT command sequence can also include a second set of operations associated with exchanging charge between the one or more ferroelectric memory cells 205 and the one or more digit lines 215, e.g., based on the charge stored in the one or more ferroelectric memory cells 205. And the ACT command sequence can include a third set of operations associated with sensing the voltage of the one or more digit lines 215 to determine the logic state stored in the one or more ferroelectric memory cells 205, e.g., based on the charge exchanged between the one or more ferroelectric memory cells 205 and the one or more digit lines 215.

[0057] The first set of operations in the ACT command sequence can include activating the memory bank or memory segment addressed by the ACT command while decoding the row address contained in the ACT command. After the row address is decoded and the bit line 215 is precharged, a word line 210 can be identified, which is coupled to a row of ferroelectric memory cells 205 located at the row address.

[0058] A second set of operations in the ACT command sequence may include precharging a digit line 215 in a memory bank or memory segment, the digit line 215 being coupled to the row of ferroelectric memory cells 205 addressed by the ACT command. In some instances, the digit line 215 is precharged while the row address is decoded. In other instances, the digit line 215 is precharged after the row address is decoded. In some instances, precharging the digit line 215 may include charging the digit line 215 to a non-zero voltage. In some instances, precharging the digit line 215 includes applying an additional "boost" voltage to the digit line 215 after charging the digit line 215 to an intermediate voltage, for example, to complete precharging the digit line to a sensing voltage. In other instances, precharging the digit line 215 may include connecting the digit line 215 to ground or a virtual ground.

[0059] After decoding the row address and precharging the digit line 215, the second set of operations can include activating the word line 210 coupled to the row of ferroelectric memory cells 205 (e.g., an activation voltage can be applied to the word line 210) so that an access voltage is applied across the row of ferroelectric memory cells 205. After activating the word line 210 and applying the access voltage across the row of ferroelectric memory cells, the second set of operations can include waiting for a predetermined duration to generate a signal on the digit line 215 as charge is exchanged between the row of ferroelectric memory cells 205 and the digit line 215. In some examples, the voltage of the digit line 215 can be held at a sensing voltage while the signal is generated, and an amplifying capacitor can be used to measure the amount of charge used to hold the sensing voltage.

[0060] A third set of operations in the ACT command sequence may be performed after the second set of operations are performed. The third set of operations may include closing a gate that isolates the sensing component 250 from the digital line 215 (or "isolating the gate"), thereby connecting the sensing component 250 to the digital line 215. After connecting the sensing component 250 to the digital line 215, the sensing component 250 may be activated based on the exchange of charge between the row of ferroelectric memory cells 205 and the digital line 215 to sense the logic state stored by the row of ferroelectric memory cells 205. In some examples, the sensing is based on the amount of charge stored by the amplifying capacitor at the end of the signal generation wait period. In some examples, sensing the logic state may include latching the output of the sensing component 250 to store the sensed logic state.

[0061] After sensing and latching the logic state of the row of ferroelectric memory cells 205, a third set of operations may include removing the applied voltage from the row of ferroelectric memory cells 205 (e.g., zero volts may be applied to the row of ferroelectric memory cells 205) to complete the ACT command sequence. In some examples, when no voltage is applied to the ferroelectric memory cells 205, the ferroelectric memory cells 205 may be referred to as being in a zero disturbance state. In some examples, the duration for fully executing the ACT command sequence may be extended to approximately 77.5 nanoseconds. In some examples, the word line 210 remains activated after completing the ACT command sequence. In some examples, removing the voltage from the row of ferroelectric memory cells 205 may cause a logic state originally stored at a portion of the row of ferroelectric memory cells 205 (e.g., the ferroelectric memory cells store "0") to be rewritten to the portion of the ferroelectric memory cells, and an opposite logic state is stored at another portion of the row of ferroelectric memory cells 205 (e.g., the ferroelectric memory cells store "1", or vice versa). In some examples, removing the voltage applied on the row of ferroelectric memory cells 205 can include equalizing the voltage of plate line(s) 220 (eg, PL_1 ) and digit line 215 , for example, by discharging digit line 215 to a virtual ground.

[0062] In some examples, executing a PRE command sequence for one or more ferroelectric memory cells 205 can include two sets of operations. That is, the PRE command sequence can include a first set of operations associated with writing a previously sensed logic state back to the one or more ferroelectric memory cells 205. And the PRE command sequence can include a second set of operations associated with disconnecting the one or more ferroelectric memory cells 205 from the one or more digit lines 215.

[0063] A first set of operations in the PRE command sequence can include closing an isolation gate, for example, by applying an activation voltage to a transistor coupling the sensing component 250 and the digit line 215, the isolation gate isolating the sensing component 250 from the digit line 215, the digit line 215 being coupled to a row of ferroelectric memory cells 205. In some examples, during the first interval, after the sensing component 250 is coupled to the digit line 215, a voltage is applied across the ferroelectric memory cells 205 of the row of ferroelectric memory cells 205, for example, where a latch at the sensing component 250 and associated with the ferroelectric memory cell 205 outputs a high voltage and a low voltage is applied to the plate line 220 coupled to the ferroelectric memory cell 205.

[0064] After closing the isolation gate and during the second interval, the first set of operations can include applying a voltage to the plate line (one or more) 220. In some examples, after applying the voltage to the plate line (one or more) 220, for example, in the case where the sensing component 250 outputs a low voltage and a high voltage is applied to the plate line 220 coupled to the ferroelectric memory cell 205, a voltage is applied to the ferroelectric memory cells 205 of the row of ferroelectric memory cells 205. In some examples, the output (one or more) of the sensing component 250 is based on the logic state of the row of ferroelectric memory cells 205 sensed during a previous operation, such as the logic state sensed in response to an ACT command. By moving the voltage of the plate line (one or more) 200 from a low voltage to a high voltage, or vice versa, the logic state of the row of ferroelectric memory cells 205 previously sensed by the sensing component 250 can be written back to the row of ferroelectric memory cells 205. Moreover, by performing the first set of operations, the logic state of the row of ferroelectric memory cells 205 can be restored after the destructive sensing operation.

[0065] A second set of operations in the PRE command sequence may be performed after the first set of operations are performed. The second set of operations may include equalizing the voltages of the digit line 215 and the plate line(s) 220 so that no voltage (i.e., 0V) is applied to the row of ferroelectric memory cells 205. In some instances, equalizing the voltages of the digit line 215 and the plate line(s) 220 includes applying the same voltage (e.g., a low, medium, or high voltage) to the digit line 215 and the plate line(s) 220. In some instances, equalizing the voltages of the digit line 215 and the plate line(s) 220 includes waiting for a duration associated with removing charge located between the bottom of the row of ferroelectric memory cells 205 and a select component coupling the row of ferroelectric memory cells 205 to the digit line 215. That is, waiting for the duration may prevent residual charge on the bottom of the ferroelectric memory cell 205 from being captured when the select component is deactivated. Once the voltages of the digit line 215 and the plate line(s) 220 have been equalized or the duration has expired (or both), the ferroelectric memory cell 205 may be referred to as being in a zero disturb state.

[0066] After equalizing the voltages of the digit line 215 and the plate line(s) 220, a second set of operations may include applying a deactivation voltage to the word line 210 coupled to the selection component, which may deactivate the selection component and isolate the row of ferroelectric memory cells 205 from the digit line 215. The second set of operations may include deactivating the sensing component 250, which may be deactivated. In some instances, the sensing component 250 is deactivated while the word line 210 is deactivated. In other instances, the sensing component is deactivated after the word line 210 is deactivated. After the sensing component 250 is deactivated, the second set of operations may include equalizing the nodes of the sensing component 250 to complete the PRE command sequence. In some instances, the nodes of the sensing component 250 may correspond to a first input node coupled to the digit line 215 and a second input node coupled to the reference line 255. In some instances, the duration for fully executing the PRE command sequence may be extended to approximately 80 nanoseconds.

[0067] The memory die 200 may be tested to ensure reliability or to identify failures (or both), as well as other causes. In order to test the memory die 200, one or more test procedures may be performed on the memory die 200. Some test procedures include edge testing, burn-in testing, reliability testing, qualification testing, and bench characterization testing. Edge testing may include applying a specific pattern to a component within the memory die 200 while performing timing and voltage measurements on a specific component within the memory die 200. In some instances, edge testing includes applying a pattern that is prone to causing signal interference to the components of the memory die 200. Edge testing can be used to identify areas within the memory die 200 that are susceptible to such interference, for example, by measuring voltages exceeding a threshold voltage at certain components. Burn-in testing may include operating the memory die 200 for an extended period of time under extreme operating conditions (e.g., elevated temperature and / or voltage). During the initial stages of burn-in testing, less robust components may fail (e.g., disconnected access lines, memory cells may be shorted, etc.), and thus may be identified before deployment. Burn-in testing may be used to induce early failures so that the memory die 200 may be configured to avoid failed components before the memory die 200 is deployed.

[0068] Qualification testing may include operating the memory die 200 within the advertised specifications, such as by executing a command sequence within specified timing parameters. Qualification testing may be used to confirm that the memory die 200 meets the advertised specifications. Similarly, bench characterization testing may include operating the memory device within certain parameters, such as by executing a command sequence within experimental timing parameters. Bench characterization testing may be used to determine the specifications of the memory die 200.

[0069] In some examples, a test procedure may be executed by providing a specific access command sequence to the memory die 200, for example, to apply a specific voltage pattern to components within the memory die 200. For example, the test procedure may include applying a series of voltages to specific components within the memory die 200 by providing a specific ACT and PRE command sequence to the local memory controller 265.

[0070] As the capacity of memory devices increases, the duration to complete a test procedure may also increase, e.g., as more memory cells, traces, sensing components, drivers, etc. are tested. Furthermore, for memory devices that use access command sequences to execute the test procedure, the increased duration of the test procedure associated with high capacity memory devices may be exacerbated for memory devices that use technology associated with longer access command sequences, such as FeRAM memory devices.

[0071] Additionally, for memory devices that execute test procedures using access command sequences, certain operations performed to execute the access commands may unnecessarily draw current and / or interfere with other components in the memory device, e.g., when the particular test procedure is not intended to draw high current and / or generate interference.

[0072] To avoid excessive cost and duration, techniques for shortening the test program may be employed. In some examples, to reduce test duration and cost, the memory die 200 may be configured to execute the access command sequence using a modified set of operations (e.g., a shortened set of operations) when executing the test program. Additionally, or alternatively, to avoid unnecessary current draw and interference that is detrimental to the test program, the memory die 200 may be configured to execute the access command sequence using a modified set of operations (e.g., a set of operations that excludes operations for applying and removing voltage) when executing the test program.

[0073] For example, when executing a test program, an ACT command may be executed using a modified set of operations. For example, the local memory controller 265 receives an ACT command targeting (or addressing) a row of memory cells 205, and may omit operations in the ACT command sequence related to exchanging charge between the row of memory cells 205 and corresponding digital lines 215, for example, to establish a sensing operation. The local memory controller 265 may also omit operations for sensing the logic state stored by the row of memory cells 205. Such a command sequence may be referred to as a "fast ACT command sequence".

[0074] In some examples, the fast ACT command sequence can include two operations. A first operation for activating a memory bank including a row of memory cells 205 and a subsequent operation for activating a word line 210 coupled to the row of memory cells 205. In some examples, the fast ACT command sequence can include a third operation for activating a sense component 250 coupled to the row of memory cells 205, which occurs after the word line 210 is activated. In some examples, the duration for fully executing the fast ACT command sequence can extend to approximately 10 nanoseconds.

[0075] Thus, relative to a complete ACT command sequence, a fast ACT command sequence may omit operations for precharging the digit line 215 to a precharge voltage; delay operations to allow for the exchange of charge between the row of memory cells 205 and the digit line 215; operations for connecting the sensing component 250 to the digit line 215; operations for activating the sensing component 250; operations for storing a logic state sensed by the sensing component 250; and / or operations for returning the row of memory cells 205 to a zero-disturb state, for example, because the row of memory cells 205 may be maintained in a zero-disturb state by the fast ACT command sequence. In some instances, a fast ACT command or a series of fast ACT commands may be used to apply a series of voltage pulses to the word line 210 in rapid succession without disturbing other components (e.g., the row of memory cells 205) coupled to the word line. When the fast ACT command sequence includes a third operation for activating the sensing component 250, the ACT command or a series of ACT commands may be used to activate and deactivate the sensing component 250 in rapid succession without disturbing other components (e.g., the row of memory cells 205) coupled to the sensing component 250.

[0076] In some instances, a fast ACT command sequence can be used when the memory die 200 uses a technique associated with a duration exceeding a threshold duration for sensing a logic state, for example, where the ACT command sequence exceeds 40 nanoseconds. In some instances, a fast ACT command sequence can be used when the current drawn during a test procedure exceeds a threshold current, for example, where one or more ACT commands are used to activate multiple memory segments. In some instances, a fast ACT command sequence can be used when the disturbance during the test procedure exceeds a threshold disturbance, for example, where the test procedure wants to make measurements independent of the disturbance. In addition, or alternatively, a fast ACT command sequence can be used when running a specific test, for example, when executing a test procedure that ignores the logic state stored in the memory cell 205.

[0077] By using a fast ACT command sequence, the duration of a test procedure using a command sequence including an ACT command can be significantly reduced, for example, because the duration of the fast ACT command sequence is shorter. Moreover, by using a fast ACT command sequence, the amount of current used during the test procedure can be reduced, for example, because the application and removal of voltage to access lines is reduced, and / or the activation of sensing components is reduced. In addition, by using a fast ACT command sequence, unintended interference with other components can be reduced, because the application and removal of voltage to access lines is reduced, and / or the activation of sensing components is reduced.

[0078] In another example, when executing the test program, a modified set of operations may be used to execute PRE commands. For example, the local memory controller 265 receives a PRE command that targets (or addresses) a (one or more) memory bank, (one or more) memory bank, and / or (one or more) rows of memory cells 205, and operations in the PRE command sequence related to writing the previously sensed logic state back to an open row of memory cells 205 may be omitted. Such a command sequence may be referred to as a "fast PRE command sequence".

[0079] In some instances, the fast PRE command sequence may include three operations. A first operation for deactivating the word line 210 coupled to the row of memory cells 205. A following operation for deactivating the sensing component 250 coupled to the memory cell 205. And a final operation for equalizing the nodes of the sensing component 250 that can be equalized. In some instances, the fast PRE command sequence may include four operations. In this case, the fast PRE command sequence may begin by equalizing the digital line 215 and the (one or more) plate lines 220 coupled to the row of memory cells 205, the equalization occurring before the word line 210 is deactivated. In some instances, the duration for fully executing the fast PRE command sequence may be extended by 15 nanoseconds.

[0080] Thus, relative to a full PRE command sequence, a fast PRE command sequence can omit operations for equalizing the digit line 215 and the plate line(s) 220 coupled to the row of memory cells 205; operations for connecting the activated sense component 250 (or a latch associated with the sense component 250) to the digit line 215; operations for applying a voltage (e.g., a write voltage) to the plate line(s) 220; delay operations to allow a logic state to be written to the row of memory cells 205; and / or delay operations to allow charge to be removed from the bottom of the row of memory cells 205 (e.g., a delay operation). In some examples, a fast PRE command can be used to shut down a row of memory cells 205 for a reduced duration so that a subsequent command (e.g., an ACT command) can be processed more quickly and allow additional voltages to be applied to the row of memory cells 205, components associated with the row of memory cells 205, and / or a different row of memory cells 205.

[0081] In some instances, a fast PRE command sequence may be used when the memory die 200 uses a technique associated with a duration for writing back a logic state that exceeds a threshold duration, for example, where a PRE command sequence exceeds 40 nanoseconds. In some instances, a fast PRE command sequence may be used when a current drawn during a test procedure exceeds a threshold current, for example, where one or more PRE commands are used to shut down multiple memory segments. In some instances, a fast PRE command sequence may be used when a disturbance during a test procedure exceeds a threshold disturbance, for example, where the test procedure wants to make measurements independent of disturbances. Additionally, or alternatively, a fast PRE command sequence may be used when running a specific test, for example, when executing a test procedure that ignores the logic state stored in the accessed memory cell 205.

[0082] By using a fast PRE command sequence, the duration of a test procedure using a command sequence including a PRE command can be significantly reduced, for example, because the duration of the fast PRE command sequence is shorter. Also, by using a fast PRE command sequence, the amount of current used during the test procedure can be reduced, for example, because the application and removal of voltage to the access line is reduced. Additionally, by using a fast PRE command sequence, unintended interference with other components can be reduced because the application and removal of voltage to the access line is reduced.

[0083] In some instances, a fast ACT command sequence can be used in conjunction with a fast PRE command sequence to further reduce the duration of a test procedure. Furthermore, the use of fast ACT and fast PRE command sequences can enable a particular operating mode (e.g., a test mode) to execute a procedure (e.g., a test procedure) without adjusting certain operations included in the ACT and PRE command sequences.

[0084] Figure 3 An example of a method for executing the rapid activation command sequence disclosed herein is shown.

[0085] Flowchart 300 illustrates various aspects of executing a received ACT command by a memory device using a first set of operations that are associated with a shorter duration, less current draw, and / or less disturbance (which may also be referred to as a fast ACT command sequence) relative to a second set of operations (which may also be referred to as an ACT command sequence). In some instances, a fast ACT command sequence may be used when a test program or a portion of a test program ignores logic states stored in memory cells. For such test programs, whether logic states stored in memory cells are correctly read, stored, and / or restored after performing access operations may not be important throughout the test program. Therefore, a fast ACT command sequence may be configured to execute ACT commands within a shortened duration and / or omit steps associated with reliably writing to or reading from memory cells.

[0086] In some examples, the ACT command sequence may be used when executing a test program that monitors the logic state stored in a memory cell or when executing a data access program. For such test and data access programs, the logic state stored in the memory cell is preferably correct after the access operation is performed. Therefore, the ACT command sequence may be configured to reliably read the logic state from the memory cell, store the logic state in the memory cell, and / or restore the logic state read from the memory cell.

[0087] At block 305, a test program may be selected for or by the memory device. In some instances, the test program is selected by an engineer, for example, as part of pre-deployment testing or based on a problem identified during operation. In some instances, the test program is selected by the memory device, for example, based on a portion within a larger test program loaded on the memory device or based on a problem identified during operation of the memory device. In some instances, the selected test program may be a test program that ignores logic states stored by the memory cell before and after performing access operations. The test program that ignores logic states may include stress testing, wafer-level edge testing, wafer-level aging testing, wafer-level reliability testing, package aging testing, unit-level reliability testing, qualification testing, and / or characteristic testing.

[0088] At block 310, the memory device may receive an indication of a selected test program. In some instances, receiving an indication of a selected test program may include receiving an indication of a particular test program or type of test program that has been selected. In some instances, the indication of the selected test program is received from an external device. In other instances, the indication of the selected test program is received from an internal component that is programmed to run one or a series of test programs.

[0089] Additionally, or alternatively, the memory device may receive an indication to use a particular set of operations to execute the received access command. In some instances, the memory device may receive an indication that a fast ACT command sequence is to be used. In some instances, the fast ACT command sequence is used to reduce the duration of a test program, for example, because the fast ACT command sequence can omit operations originally used to execute the ACT command sequence, and subsequent operations can be performed more quickly. Similarly, the fast ACT command sequence can be used to reduce current draw and interference with other memory components, for example, because the fast ACT command sequence can omit operations originally used to change the voltage of one or more access lines and / or activate and deactivate sensing components during the ACT command sequence. The fast ACT command sequence can also be used to reduce current draw in the case where the ACT command addresses multiple memory banks, memory segments, and / or memory rows, or when multiple ACT commands are used to activate multiple memory banks.

[0090] In some instances, a fast ACT command sequence is used to support test programs that are intended to individually control specific memory components. For example, a test program that attempts to control a digital line can use a fast ACT command sequence when the fast ACT command sequence omits operations associated with applying a voltage to or removing a voltage from a digital line. Thus, the test program can avoid causing a digital line disturbance that would otherwise be caused by applying a voltage to the digital line while executing the ACT command sequence. For example, a test program that applies a voltage to a digital line for a predetermined duration can use a fast ACT command sequence to prevent an additional voltage from being applied to the digital line when a row of memory cells is opened and before the voltage is applied, for example, because the additional voltage might defeat the purpose of the test program.

[0091] Similarly, a fast ACT command sequence can be used to support a test program that attempts to control a switch component that is used to connect a sensing component to a digital line and a test program that attempts to control a plate line. Moreover, a fast ACT command sequence can be used to support a test program that attempts to test a sensing component without interfering with a coupled memory component. In some instances, a fast ACT command sequence can also facilitate applying a specific voltage sequence to a specific memory component without regard to the voltage that would otherwise be applied when the ACT command sequence is executed to close the memory cell. In some instances, a test program that applies a specific voltage sequence to a plate line or a digital line (e.g., a cycle) can use a fast ACT command sequence to prevent an additional voltage from being applied to the plate line or the digital line when the memory cell is closed. In some instances, a fast ACT command sequence can be used to discharge the bottom of a memory cell by opening the memory cell to the digital line without applying a voltage to the digital line or the plate line coupled to the memory cell.

[0092] In other examples, the memory device may receive an indication that an ACT command sequence is to be used. In some examples, the duration of executing the ACT command sequence may be longer than the duration of executing the fast ACT command sequence. In some examples, the ACT command sequence may include operations included in the fast ACT command sequence and additional operations. In some examples, the additional operations included in the ACT command sequence may be associated with exchanging charge between a memory cell and a digital line or sensing a logic state of a memory cell, or any combination thereof.

[0093] At block 315, the memory device may be configured for a test mode corresponding to the selected test program. In some examples, the memory device is externally configured for the test mode, for example, by applying a voltage to a test pin, which may activate and / or deactivate certain components within the memory device to support the corresponding test mode. In some examples, after being configured for the test mode, the memory device may process received access commands according to the configured test mode.

[0094] For example, if activating the test pin causes a first test mode associated with a test procedure that ignores the logic state of the memory cell to be configured at the memory device, the memory device may execute a fast ACT command sequence after receiving the ACT command. In other examples, if activating the test pin causes a second test mode that maintains the logic state of the memory cell to be configured at the memory device, the memory device may execute an ACT command sequence after receiving the ACT command.

[0095] In some examples, activating the test pins may cause a first test component within the memory device and storing a first set of operations for executing access commands (e.g., storing a fast ACT command sequence) to be activated, and / or a second test component within the memory device and storing a second set of operations for executing access commands (e.g., storing an ACT command sequence) to be deactivated. In some examples, activating the test pins may cause the sense component to refrain from performing actions associated with sensing a logic state from a memory cell or to be completely disabled.

[0096] In other examples, the memory device configures itself into a test mode, for example, the memory device may activate and deactivate certain components within the memory device based on receiving an indication of a test mode. In some examples, the memory device may configure a test module to execute a received memory command using a first set of operations (or access command sequence, such as a fast ACT command sequence, a fast PRE command sequence, etc.) after receiving an indication that a test program that ignores logic states will be run. In another example, the memory device may configure a test module to execute a received memory command using the first set of access command sequences after receiving an indication that the first set of access command sequences will be used. In some examples, the indication indicates a specific duration for using the indicated set of operations. In other examples, the memory device is configured to use the indicated set of operations until a contrary indication is received.

[0097] In some examples, configuring the test module to use the first set of access command sequences may include activating a first test component storing the first set of access command sequences for executing access commands and / or deactivating a second test component storing a second set of operations (or access command sequences, such as an ACT command sequence, a PRE command sequence, etc.) for executing access commands. In some examples, the memory device may configure the sensing component to avoid performing actions associated with sensing logic states from memory cells, or may completely disable the sensing component based on receiving an indication of the test program.

[0098] In other examples, the memory device may configure the test module to use the second set of access command sequences to execute the received memory commands (e.g., ACT command sequences) after receiving an indication that a test program intended to maintain a logic state is to be run or an explicit indication that the second set of access command sequences is to be used. In some examples, configuring the test module to use the second set of access command sequences may include activating a second test component and / or deactivating a first test component that stores the first set of access command sequences for executing access commands.

[0099] At block 320, the memory device may receive an ACT command as part of a test program. In some instances, the ACT command is used to open a memory bank, a memory segment, and / or a row of memory cells. Opening a memory cell may include preparing a component (e.g., a word line, a sensing component, a digital line, etc.) for accessing the memory cell to perform a sensing operation (e.g., by precharging the digital line). In some instances, opening a memory cell may also include sensing and / or storing a logical state of the memory cell. In some instances, the ACT command is received from an external device (e.g., a host device that is running a test program and generates a command (including an ACT command) to execute the test program). In some instances, the ACT command is generated within the memory device, for example, by an embedded test module that is running the test program. In some instances, the received ACT command includes address information identifying one or more memory cells targeted by the received ACT command. For example, the received ACT command may include a memory bank address, a memory segment address, and / or a row address associated with one or more memory cells.

[0100] In some examples, the ACT command is received along with other access commands (e.g., serially or in parallel) that are also used to perform a test procedure. In some examples, the ACT command is received after receiving a PRE command for one or more memory cells as part of a test procedure, and the ACT command can be used to close a row of memory cells. In some examples, the received ACT command is received after an ACT command, for example, to open multiple rows of memory cells in the same memory segment.

[0101] At box 325, the memory device may select a set of operations (or access command sequence) to execute the received ACT command. In some instances, the memory device selects a fast ACT command sequence as a result of being configured in a first test mode associated with the fast ACT command sequence, i.e., the memory device may automatically execute the fast ACT command sequence based on being previously configured in the first test mode. In other instances, the memory device selects the fast ACT command sequence after determining that the memory device has been configured in the first test mode. In some instances, the memory device selects the fast ACT command sequence based on determining that a particular test program or test program type is being executed.

[0102] In some instances, the fast ACT command sequence omits operations included in the ACT command sequence, such as operations associated with exchanging charge between a memory cell and a digital line or sensing a voltage of a digital line to determine a logic state of a memory cell, or both. By omitting operations associated with exchanging charge between a memory cell and a digital line and / or sensing a voltage of a digital line, the duration of executing an ACT command can be reduced. The omitted operations can include operations for precharging a digital line coupled to a row of memory cells, for example, in preparation for a sensing operation. By omitting operations associated with precharging a digital line, the voltage of the digital line can remain fixed (e.g., at a ground reference) for all or a longer portion of the execution of an ACT command, thereby reducing current drawn and interference with other memory components during execution of the ACT command.

[0103] The omitted operations may also include a wait operation that provides a duration for reliably exchanging charge between a row of memory cells and the precharged digit line. The omitted operations may also include an operation for connecting the sensing component to the digit line after the wait duration has expired. In some instances, connecting the sensing component to the digit line may include activating an isolation gate that couples the sensing component to the digit line. The omitted operations may also include an operation for activating the sensing component. In some cases, activating the sensing component includes connecting the sensing component to a power supply voltage source. Additionally, the omitted operations may include an operation for equalizing the voltages of the digit line and the plate line, for example, because the voltages of the digit line and the plate line do not change during the fast ACT command sequence.

[0104] Similarly, by omitting the operation for connecting the output of the sense component to the digit line and the voltage to the plate line, the amount of current drawn during an ACT command (e.g., an ACTALL command) that addresses multiple rows of memory cells can be reduced. In some examples, the amount of current drawn can be reduced below a threshold, which can enable such an ACT command to address an increased number of memory rows.

[0105] In other examples, for example, if the memory device is configured in a second test mode associated with the ACT command sequence, the ACT command sequence may be selected. In this case, the memory device may execute the received ACT command by executing the ACT command sequence including the omitted operations described above.

[0106] At box 330, the memory device may execute the received ACT command by executing a fast ACT command sequence, for example, based on the configured first test mode. When executing the fast ACT command sequence, the memory device may start by activating the memory bank or memory segment addressed in the ACT command. When activating the memory bank or memory segment, the memory device may decode the row address contained in the ACT command to identify the location of the corresponding memory cell row and the word line for accessing the memory cell row. Once the memory bank or memory segment is activated and the row address is decoded, the memory device may activate the identified word line, for example, by applying an activation voltage to the word line, which may connect the memory cell row to the corresponding digital line. In some instances, the fast ACT command sequence may terminate after activating the word line.

[0107] In some examples, when executing a fast ACT command sequence, the memory device may also activate the sense component after activating the word line. In this case, the sense component may be tested without interfering with other memory components, for example, because the isolation gate is not activated. In some examples, at the end of the fast ACT command sequence, the logic state stored by the memory cell row is not sensed by the memory device.

[0108] In some examples, the ACT command can address an entire memory bank or memory segment (e.g., an ACTALL command), and the memory device can activate all word lines included in the memory bank or memory segment. In some cases, the memory device can also activate all sensing components coupled to the memory bank or memory segment.

[0109] At block 335, the memory device may receive a PRE command as part of a test program. In some instances, the PRE command may close a memory bank, a memory segment, or a row of memory cells. Closing a memory cell may include writing a previously sensed logic state (e.g., a logic state sensed during an ACT operation) back to the memory cell and / or disconnecting the memory cell from a digital line. In some instances, the PRE command may be directed to a row of memory cells opened by the PRE command. In some instances, the PRE command may be directed to all rows of memory cells opened in the memory device (e.g., if the PRE command is a PREALL command). In some instances, the PRE command is received from an external device running a test program or from an internal device generating commands for the test program.

[0110] At block 340, the memory device may execute a PRE command. In some instances, executing the PRE command includes executing a PRE command sequence, the PRE command sequence including a first set of operations for restoring a logic state of the memory cell, such as by applying an access voltage across the memory cell, and a second set of operations for disconnecting the memory cell from a digital line and deactivating a memory component coupled to the memory cell. In other instances, executing the PRE command includes executing a fast PRE command sequence that omits operations associated with restoring a logic state to the memory cell (e.g., based on the memory device being configured in a first test mode). Executing the received PRE and ACT commands with a fast PRE command sequence and / or a fast ACT command sequence may reduce a duration associated with a test procedure relative to using a PRE command sequence and / or an ACT command sequence. Additionally, using a fast PRE command sequence and / or a fast ACT command sequence may reduce current draw and disturbances during the test procedure. In some examples, after the fast PRE command sequence is completed, a logic state may be written back to the memory cell that is different from the logic state stored by the memory cell prior to an immediately previous sensing operation (e.g., prior to executing the fast ACT command sequence). In some examples, after the fast PRE command sequence is completed, a soft logic state (e.g., a logic state of reduced reliability) may be written back to the memory cell.

[0111] In some examples, the memory device may receive another ACT command and may repeat the operations performed at blocks 320 to 330. In some examples, the memory device may be reconfigured to a new test mode before receiving another ACT command. For example, the memory device may be configured to a second test mode. In this case, the other received ACT commands may be executed using an ACT command sequence that includes operations omitted from the fast ACT command sequence.

[0112] Figure 4 A block diagram of a memory device supporting execution of a fast activate command sequence according to various examples of the present disclosure is shown.

[0113] Memory device 400 may be referred to as an electronic memory apparatus and may include (one or more) memory cells 405, word lines 410, digit lines 415, plate lines 420, sense elements 450, reference lines 455, and memory controller 465, which may be referenced Figure 1 and 2 4. The memory device 400 may include a latch 425 and a reference component 430. The components of the memory device 400 may be in electronic communication with each other and may perform reference operations. Figures 1 to 3 Functionality as described.

[0114] The memory cell(s) 405 may be configured to store logic information. In some examples, the memory cell(s) 405 may be accessed using one or more access commands that trigger sequential application of voltages to components coupled to the memory cell(s) 405.

[0115] Reference component 430 may include various components to generate a reference signal for sensing component 450. Reference component 430 may include a circuit configured to generate a reference signal.

[0116] Sense component 450 may compare the signal from memory cell 405 (via digital line 415) to a reference signal from reference component 430. Once the logic state is determined, the sense component may store the output in latch 425, where the output may be used in accordance with the operation of the electronic device of which memory device 400 is a part.

[0117] The memory controller 465 may be combined with other components to apply voltages throughout the memory device 400, write data to the memory cells 405, read data from the memory cells 405, and generally operate as described above. Figures 1 to 3 4. The memory device 400 operates as described in . The memory controller 465 can be in electronic communication with the word line 410, the digit line 415, the plate line 420, the reference component 430, and the sense component 450. The memory controller 465 can include a bias component 470, a timing component 475, and a configuration component 480. In some examples, the memory controller 465 can include a row decoder, a column decoder, or both, as shown in FIG. Figure 2 This may enable the memory controller 465 to access one or more memory cells 405 .

[0118] In some examples, the memory controller 465 can use bias component 470 to activate the access line by applying voltages to those various nodes. In some examples, the bias component 470 can be configured to apply voltages to operate the memory cell 405 to read or write the memory cell 405 as described above. In some examples, the bias component 470 can be configured to provide a voltage potential to the reference component 430 in order to generate a reference signal for the sense component 450. In addition, the bias component 470 can provide a voltage potential for the operation of the sense component 450.

[0119] The timing component 475 can be configured to control the timing of various word line selections or plate biases, including the timing for switching and voltage application to perform memory functions such as reading and writing discussed herein. In some examples, the timing component 475 can control the operation of the bias component 470. In some examples, the memory controller 465 can also include a reference component 430, a sense component 450, and a latch 425.

[0120] The configuration component 480 can be configured to configure the memory device 400 in an operation mode (e.g., a test mode). For example, the configuration component 480 can configure the memory array in a test mode, wherein a first set of operations (e.g., a fast ACT command sequence) is performed to execute a received ACT command, or a second set of operations (e.g., an ACT command sequence) associated with a longer duration is performed to execute a received ACT command. The configuration component 480 can include a first operation mode component 485, a second operation mode component 490, and a command processing component 495.

[0121] The first operating mode component 485 can be configured to store a first set of command sequences for the first set of commands. In some examples, the first operating mode component 485 is configured to store a fast ACT command sequence. In some examples, when the memory device 400 is configured in the first test mode, the first operating mode component 485 can be used to execute the received command according to a corresponding command sequence of the stored first set of command sequences, such as when the first operating mode component 485 can execute the fast ACT command sequence after receiving an ACT command at the memory controller 465.

[0122] The second operating mode component 490 may be configured to store a second set of command sequences for a second set of commands. In some instances, one or more of the second set of command sequences have a longer duration than a corresponding command sequence in the first set of command sequences. In some instances, the second operating mode component 490 is configured to store an ACT command sequence. In some instances, when the memory device 400 is configured in a second test mode or a data access mode, the second operating mode component 490 may be used to execute the received command according to the corresponding command sequence of the stored second set of command sequences, for example, after receiving an ACT command at the memory controller 465, the second operating mode component 490 may execute the ACT command sequence.

[0123] The command processing component 495 can be configured to receive an access command received, for example, from an external device or another component of the memory controller 465. In some examples, the command processing component 495 can be configured to buffer the received access commands and forward the access commands to other components within the memory controller 465, such as the first operating mode component 485 and the second operating mode component 490. In some examples, the command processing component 495 can be configured to generate access commands, for example, based on a test program installed at the memory controller 465.

[0124] In some examples, the memory controller 465 may be configured to operate in a first mode (e.g., a first test mode) associated with a shorter command sequence than a second mode (e.g., a second test mode). The memory controller 465 may be further configured to perform a first set of operations associated with the first test mode (e.g., a fast ACT command sequence) to execute a first access command (e.g., an ACT command) when configured in the first test mode, or to perform a second set of operations associated with the second test mode (e.g., a fast ACT command sequence) to execute a first access command when configured in the second test mode. In some examples, the memory controller 465 may perform the first set of operations in a shorter duration than the second set of operations. In some examples, the memory controller 465 may use a configuration component 480 to identify a test mode requested by an external device. The memory controller 465 may also use the configuration component 480 to configure the memory device 400 for the identified test mode (e.g., the first or second test mode). In some examples, memory controller 465 uses configuration component 480 to configure sense component 450 to avoid sensing logic states from memory cells after being configured in the first mode.

[0125] In some instances, the memory controller 465 can receive and process access commands. In some instances, when executing the first test program, the memory controller 465 uses the first operating mode component 485 to process the access commands. When the first operating mode component 485 is activated, the memory controller 465 can execute a fast ACT command sequence after receiving the ACT command. In order to execute the fast ACT command sequence, as an initial step, the first operating mode component 485 can use the bias component 470 to activate the memory bank or memory segment. Next, the first operating mode component 485 can use the bias component 470 to apply an activation voltage to the word line 410. In some instances, the first operating mode component 485 can also send a signal (e.g., via the control line 440) to activate the sensing component 450. In some instances, the signal is used to connect the sensing component 450 to a voltage source.

[0126] Figure 5A flow chart illustrating a method 500 for supporting fast activation for memory sensing according to aspects of the present disclosure is shown. The operations of the method 500 may be implemented by a memory array or components thereof as described herein. For example, the operations of the method 500 may be implemented by reference to Figure 4 The memory array described herein performs. In some examples, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the functions described. Additionally, or alternatively, the memory array may use dedicated hardware to perform various aspects of the described functions.

[0127] At 505, a memory array may configure a memory device including the memory array to operate in a first test mode associated with a command sequence having a reduced duration relative to a second mode. The operations of 505 may be performed according to the methods described herein. In some examples, aspects of the operations of 505 may be described by reference to Figure 4 The described configuration components are executed.

[0128] At 510, after configuring the memory device to operate in the first mode, the memory array may receive an activate command associated with a memory cell of the memory array. The operations of 510 may be performed according to the methods described herein. In some examples, aspects of the operations of 510 may be described in detail with reference to Figure 4 The command processing component described is executed.

[0129] At 515, the memory array may perform a first set of operations for executing an activate command based on configuring the memory array to operate in a first mode, wherein when the memory array is configured in a second mode, the first set of operations is performed within a shorter duration than the second set of operations for executing the activate command. The operations of 515 may be performed according to the methods described herein. In some examples, aspects of the operations of 515 may be described by reference to Figure 4 The first operating mode described is performed by the components.

[0130] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for configuring a memory device including a memory array to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode, receiving an activate command associated with a memory cell of the memory array after configuring the memory device to operate in the first mode, and performing a first set of operations for performing the activate command based on configuring the memory array to operate in the first mode, wherein the first set of operations are performed within a shorter duration than a second set of operations for performing the activate command when the memory device is configured in the second mode.

[0131] Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for selecting a first set of operations instead of a second set of operations for executing an activate command based on configuring the memory array to operate in the first mode.

[0132] In some examples of the methods 500 and apparatus described herein, performing the first set of operations may include operations, features, means, or instructions for activating a memory segment in the memory array that includes the memory cell as a first operation in the first set of operations, and activating a word line that may be coupled to the memory cell as a second operation in the first set of operations that occurs after the first operation, wherein a voltage change of a digit line that may be coupled to the memory cell remains below a threshold after activating the word line.

[0133] Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for releasing a charge stored at the bottom of the memory cell to a digit line based on activating a word line.

[0134] In some examples of the methods 500 and apparatus described herein, performing a first set of operations may include operations, features, means, or instructions for activating a sensing component that may be coupled to a memory cell as a third operation in the first set of operations that occurs after a second operation, wherein the sensing component may be activated without applying a voltage across the memory cell.

[0135]

[0066] In some examples of the methods 500 and apparatus described herein, performing the first set of operations may include operations, features, means, or instructions for avoiding sensing a logic state of a memory cell.

[0136] Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for executing a precharge command associated with a memory cell after executing an activate command, wherein executing the precharge command includes avoiding writing a logic state back to the memory cell based on avoiding sensing the logic state.

[0137] In some examples of the methods 500 and devices described herein, a memory cell stores a logic state prior to receiving a precharge command and stores a different logic state after executing the precharge command.

[0138] Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for configuring a memory device to operate in a second mode, receiving a second activation command associated with a memory cell after configuring the memory device to operate in the second mode, and performing a second set of operations to execute the second activation command based on configuring the memory array to operate in the second mode.

[0139] In some examples of the method 500 and apparatus described herein, performing the second set of operations may include operations, features, means, or instructions for activating a memory segment including memory cells in a memory array; precharging a digit line to which the memory cells may be coupled after activating the memory segment; activating a word line to which a selection component may be coupled after precharging the digit line, wherein a voltage change of the digit line exceeds a threshold after activating the word line, and wherein the selection component may be coupled to the memory cell; waiting for a duration associated with an exchange of charge between the memory cell and the digit line based on activating the word line; coupling an input of a sensing component to the digit line after waiting for the duration; activating the sensing component after coupling the input of the sensing component to the digit line; and applying a zero voltage across the memory cell based on activating the sensing component.

[0140] In some examples of the methods 500 and apparatus described herein, an activate command may be associated with a group of memory cells including the memory cells, and wherein a first set of operations may be performed for the group of memory cells.

[0141] In some examples of the methods 500 and apparatus described herein, the memory array includes one or more ferroelectric memory cells, and wherein the memory cells may be ferroelectric memory cells.

[0142] In some examples of the method 500 and apparatus described herein, the first mode may be associated with one or more of wafer-level edge testing, wafer-level burn-in testing, wafer-level reliability testing, package burn-in testing, unit-level reliability testing, qualification testing, or bench characterization testing.

[0143] Some examples of the method 500 and apparatus described herein may further include operations, features, means, or instructions for performing a first set of operations associated with operating a second memory cell, wherein a current level for executing an activate command remains below a threshold based on the first mode being configured.

[0144] In some examples of the methods 500 and apparatus described herein, the first mode may be a first test mode and the second mode may be a second test mode.

[0145] Figure 6 A flow chart illustrating a method 600 for supporting fast activation for memory sensing according to aspects of the present disclosure is shown. The operations of the method 600 may be implemented by a memory array or components thereof as described herein. For example, the operations of the method 600 may be implemented by reference to Figure 4 The memory array described herein performs. In some examples, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the functions described. Additionally, or alternatively, the memory array may use dedicated hardware to perform various aspects of the described functions.

[0146] At 605, the memory array may configure a memory device including the memory array to operate in a first mode, the first test mode being associated with a command sequence having a reduced duration relative to a second mode. The operations of 605 may be performed according to the methods described herein. In some examples, aspects of the operations of 605 may be described by reference to Figure 4 The described configuration components are executed.

[0147] At 610, after configuring the memory device to operate in the first mode, the memory array may receive an activate command associated with a memory cell of the memory array. The operations of 610 may be performed according to the methods described herein. In some examples, aspects of the operations of 610 may be performed as described in reference to Figure 4 The command processing component described is executed.

[0148] At 615, the memory array may perform a first set of operations for executing an activate command based on configuring the memory array to operate in a first mode, wherein when the memory array is configured in a second mode, the first set of operations is performed within a shorter duration than the second set of operations for executing the activate command. The operations of 615 may be performed according to the methods described herein. In some examples, aspects of the operations of 615 may be performed as described in reference to Figure 4 The first operating mode described is performed by the components.

[0149] At 620, as a first operation in the first set of operations, the memory array may activate a memory segment containing memory cells in the memory array. The operations of 620 may be performed according to the methods described herein. In some examples, aspects of the operations of 620 may be performed as described in reference to Figure 4 The first operating mode component is implemented by (e.g., in combination with a biasing component).

[0150] At 625, as a second operation in the first set of operations occurring after the first operation, the memory array may activate a word line coupled to the memory cell, wherein a voltage change in a digit line coupled to the memory cell remains below a threshold after activating the word line. The operation of 625 may be performed according to methods described herein. In some examples, aspects of the operation of 625 may be described in detail with reference to Figure 4 The first operating mode component is implemented by (e.g., in combination with a biasing component).

[0151] It should be noted that the methods described herein are possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, portions from two or more methods may be combined.

[0152] A device is described. The device may include a memory unit and a memory controller coupled to the memory unit and configurable to operate in a first mode, the first mode being associated with an activation sequence having a reduced duration relative to a second mode, the memory controller being operable to perform a first set of operations associated with the first mode to execute an activation command when configured in the first mode, or a second set of operations associated with the second mode to execute an activation command when configured in the second mode, wherein a duration for performing the first set of operations is shorter than a duration for performing the second set of operations.

[0153] In some examples, the memory controller may include operations, features, devices, or instructions for configuring a component operable to identify a test mode requested by an external device and configure the device for the identified test mode, the test mode including a first mode or a second mode.

[0154] In some examples, the configuration component is operable to select the first set of operations or the second set of operations based on the identified test mode.

[0155] In some instances, the memory controller may include operations, features, devices, or instructions for a first mode component and a second mode component, wherein the first mode component is operable to store a first command sequence corresponding to an activation command and the second mode component is operable to store a second command sequence corresponding to the activation command, wherein the first command sequence is executable in a shorter period of time than the second command sequence.

[0156] Some examples of the apparatus may include a sensing component coupled with the memory cell and operable to avoid sensing a logic state from the memory cell during execution of the activate command when the first mode is configurable.

[0157] An apparatus is described. The apparatus may include a memory array including memory cells and a memory controller coupled to the memory array, the memory controller operable to configure a first mode associated with one or more command sequences having a reduced duration relative to a second mode, receive an activate command associated with the memory cells after configuring the first mode, and perform a first set of operations for executing the activate command based on configuring the memory array to operate in the first mode, wherein when the second mode is configured, the first set of operations are performed within a shorter duration than a second set of operations for executing the activate command.

[0158] Some examples may further include selecting the first set of operations instead of the second set of operations for executing the activate command based on configuring the memory array to operate in the first mode.

[0159] Some examples may further include activating a memory segment including the memory cell in the memory array as an initial operation of the first set of operations, and activating a word line that may be coupled to the memory cell as a next operation of the first set of operations after activating the memory segment.

[0160] Some examples may further include activating a sensing component that may be coupled to the memory cell after activating the word line.

[0161] Some examples may further include executing a precharge command after activating the word line and without sensing the logic state of the memory cells.

[0162] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may show a signal as a single signal; however, it should be understood by one of ordinary skill in the art that a signal may represent a signal bus, where the bus may have various bit widths.

[0163] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or conductive contact, connection, or coupling) with each other if there is any conductive path between the components that is capable of supporting the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication (or conductive contact or connection or coupling) with each other may be open or closed based on the operation of the device containing the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0164] The term "coupling" refers to the situation of moving from an open circuit relationship between components, in which signals cannot currently be passed between components through conductive paths, to a closed circuit relationship between components in which signals can be passed between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components through conductive paths that previously did not allow signals to flow.

[0165] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch located between the components are isolated from one another when a switch is open. When a controller isolates two components from one another, the controller uses the conductive path that previously allowed a signal to flow to effect a change that prevents the signal from flowing between the components.

[0166] The devices discussed herein (including memory arrays) may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0167] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated".

[0168] The description set out herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that can be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description contains specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0169] In the accompanying drawings, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0170] Any of a variety of different technologies and processes can be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols and chips that can be described throughout the above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles or any combination thereof. Various illustrative blocks and modules described in conjunction with the disclosure herein can be implemented or executed by designing a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof that performs the functions described herein. A general-purpose processor can be a microprocessor, but in an alternative, the processor can be any processor, controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0171] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on a computer-readable medium or transmitted by the computer-readable medium as one or more instructions or codes. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the characteristics of software, the above functions can be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features that implement the functions can also be physically located in various locations, including being distributed so that partial functions are implemented in different physical locations. In addition, as used herein, included in the claims, such as "or" used in the list of items (for example, a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates a list of inclusions, so that, for example, a list of at least one of A, B, or C represents A or B or C or AB or AC or BC or ABC (that is, A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0172] Computer-readable media includes non-transitory computer storage media and communication media, and communication media includes any media that promotes computer programs to be transmitted from one place to another.Non-transitory storage media can be any available media that can be accessed by a general or special computer.As an example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store required program code device and any other non-transitory media that can be accessed by a general or special computer or a general or special processor in the form of an instruction or data structure.In addition, any connection is appropriately referred to as computer-readable media.For example, if coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0173] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: configuring a memory device including a memory array to operate in a first mode associated with command sequences having a reduced duration relative to a second mode; receiving an activate command associated with a memory cell of the memory array after configuring the memory device to operate in the first mode; as well as performing a first set of operations for executing the activate command based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations are performed within a shorter duration than a second set of operations for executing the activate command when the memory device is configured in the second mode, wherein performing the first set of operations comprises: activating, as a first operation in the first set of operations, a memory segment of the memory array that includes the memory cell; as well as As a second operation of the first set of operations occurring after the first operation, a word line coupled to the memory cell is activated, wherein a voltage change of a digit line coupled to the memory cell remains below a threshold after activating the word line.

2. The method of claim 1, wherein charge stored at a bottom of the memory cell is released to the digit line based at least in part on activating the word line.

3. The method of claim 1 , wherein performing the first set of operations comprises: As a third operation of the first set of operations occurring after the second operation, a sensing component coupled to the memory cell is activated, wherein the sensing component is activated without applying a voltage across the memory cell.

4. A method comprising: configuring a memory device including a memory array to operate in a first mode associated with command sequences having a reduced duration relative to a second mode; receiving an activate command associated with a memory cell of the memory array after configuring the memory device to operate in the first mode; as well as A first set of operations for executing the activate command is performed based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations are performed within a shorter duration than a second set of operations for executing the activate command when the memory device is configured in the second mode, wherein performing the first set of operations includes avoiding sensing a logic state of the memory cell.

5. The method according to claim 4, further comprising: The first set of operations rather than the second set of operations is selected for executing the activate command based at least in part on configuring the memory array to operate in the first mode.

6. The method according to claim 4, further comprising: A precharge command associated with the memory cell is executed after executing the activate command, wherein executing the precharge command includes avoiding writing the logic state back to the memory cell based at least in part on avoiding sensing the logic state.

7. The method of claim 6, wherein the memory cell stores the logic state prior to receiving the precharge command and stores a different logic state after executing the precharge command.

8. The method according to claim 4, further comprising: configuring the memory device to operate in the second mode; receiving a second activate command associated with the memory unit after configuring the memory device to operate in the second mode; as well as The second set of operations is performed based at least in part on configuring the memory array to operate in the second mode to execute the second activate command.

9. The method of claim 8, wherein performing the second set of operations comprises: activating a memory segment in the memory array that includes the memory cell; precharging a digit line coupled to the memory cell after activating the memory segment; activating a word line coupled to a selection component after precharging the digit line, wherein a voltage change of the digit line exceeds a threshold after activating the word line, and wherein the selection component is coupled to the memory cell; waiting a duration associated with exchanging charge between the memory cell and the digit line based at least in part on activating the word line; coupling an input of a sensing component to the digital line after waiting the duration; activating the sensing component after coupling the input of the sensing component to the digit line; as well as A zero voltage is applied across the memory cell based at least in part on activating the sensing component.

10. The method of claim 4, wherein the activate command is associated with a plurality of memory cells including the memory cell, and wherein the first set of operations is performed for the plurality of memory cells.

11. The method of claim 4, wherein the memory array comprises one or more ferroelectric memory cells, and wherein the memory cells are ferroelectric memory cells.

12. A method comprising: configuring a memory device including a memory array to operate in a first mode associated with command sequences having a reduced duration relative to a second mode; receiving an activate command associated with a memory cell of the memory array after configuring the memory device to operate in the first mode; as well as A first set of operations for executing the activate command is performed based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations is performed for a shorter duration than a second set of operations for executing the activate command when the memory device is configured in the second mode, wherein the first mode is associated with one or more of a wafer level edge test, a wafer level burn-in test, a wafer level reliability test, a package burn-in test, a unit level reliability test, a qualification test, or a bench characterization test.

13. A method comprising: configuring a memory device including a memory array to operate in a first mode associated with command sequences having a reduced duration relative to a second mode; receiving, after configuring the memory device to operate in the first mode, an activate command associated with a memory cell of the memory array, wherein the memory cell is located in a first memory segment of a first memory bank and coupled to a first word line, and wherein the activate command is further associated with a second memory cell located in a second memory segment of the first memory bank or coupled to a second word line; as well as A first set of operations for executing the activate command is performed based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations is performed for a shorter duration than a second set of operations for executing the activate command when the memory device is configured in the second mode, wherein the first set of operations is associated with operating the second memory cell, and wherein a current level for executing the activate command remains below a threshold based at least in part on the first mode being configured.

14. An apparatus comprising: Memory unit; as well as a memory controller coupled to the memory unit and configurable to operate in a first mode associated with an activation sequence having a reduced duration relative to a second mode, the memory controller being operable to: performing a first set of operations associated with the first mode to execute an activate command when configured in the first mode, or performing a second set of operations associated with the second mode to execute the activate command for accessing the memory cell when configured in the second mode, wherein a duration for executing the first set of operations is shorter than a duration for executing the second set of operations, The memory controller includes a configuration component operable to identify a test mode requested by an external device and configure the apparatus for the identified test mode, the test mode including the first mode or the second mode.

15. The apparatus of claim 14, wherein the configuration component is operable to select the first set of operations or the second set of operations based at least in part on the identified test pattern.

16. The apparatus of claim 14, wherein the memory controller comprises: a first operating mode component operable to store a first command sequence corresponding to the activation command; as well as A second operating mode component is operable to store a second command sequence corresponding to the activation command, wherein the first command sequence is executable within a shorter period of time than the second command sequence.

17. The apparatus of claim 14, further comprising: A sensing component is coupled to the memory cell and is operable to avoid sensing a logic state from the memory cell during execution of the activate command when the first mode is configured.

18. An apparatus comprising: a memory array comprising memory cells; a memory controller coupled to the memory array, the memory controller being operable to: configuring a first mode associated with one or more command sequences having a reduced duration relative to a second mode; receiving an activate command associated with the memory unit after configuring the first mode; as well as A first set of operations for executing the activate command is performed based at least in part on configuring the memory array to operate in the first mode, wherein when the second mode is configured, the first set of operations are performed within a shorter duration than a second set of operations for executing the activate command, wherein to perform the first set of operations, the memory controller is further operable to avoid sensing a logic state of the memory cell.

19. The apparatus of claim 18, wherein the memory controller is further operable to: The first set of operations rather than the second set of operations is selected for executing the activate command based at least in part on configuring the memory array to operate in the first mode.

20. The apparatus of claim 18, wherein the memory controller is further operable to: As an initial operation in the first set of operations, activating a memory segment in the memory array that includes the memory cell; and As a next operation of the first set of operations, a word line coupled to the memory cell is activated after activating the memory segment.

21. The apparatus of claim 20, wherein the memory controller is further operable to: A sensing component coupled to the memory cell is activated after activating the word line.

22. The apparatus of claim 20, wherein the memory controller is further operable to: A precharge command is executed after activating the word line and without sensing the logic state of the memory cell.

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