A power management chip adaptive load power regulation method and system

Abstract

The present invention belongs to the field of power regulation of power management chips, and specifically relates to a method and system for power regulation of power management chips for adaptive loads. A method proposed by the present invention includes: S1. Grouping the power tubes in the power management chip; S2. Real-time detection of the power required by the load; S3. Turning on the grouped power tubes according to the load size; a system includes a power management chip, a sampling module, a selection module and a control signal module; the sampling module is connected to the FB end of the power management chip; the selection module is respectively connected to the sampling module, the control signal module and the power tubes in the power management chip. The present invention can realize automatic adjustment of the output power of the power management chip according to the different load sizes; thereby completing the power regulation of the power management chip for adaptive loads, and enabling the power management chip to output the power required by the load at the current moment in real time.

Description

Technical Field

[0001] The present invention belongs to the field of power regulation of power management chips, and in particular relates to a method and system for regulating power of a power management chip for adaptive loads. Background Art

[0002] The power management chip is the energy management center in the electronic device system, responsible for the distribution of chips or output power, voltage conversion, detection and battery protection. The power management chip is an important support for the power consumption performance of electronic systems. Good power management can greatly reduce the power consumption of electronic devices, increase battery life, and improve user experience. At the same time, good power management can enhance the performance indicators of electronic devices. Existing electronic systems are becoming more and more complex, and the requirements for power management chips are also getting higher and higher.

[0003] Traditional methods for regulating the power of power management chips are mostly based on the software level. Through a program pre-set in the MCU, the sampled load data is analyzed to adjust the power of the power management chip. Summary of the invention

[0004] The problem to be solved by the present invention is to provide a method and system for power regulation of a power management chip for adaptive load, which can adjust the power size of the power management chip in real time according to different loads, thereby realizing power regulation of the power management chip for adaptive load.

[0005] The technical solution adopted by the present invention is:

[0006] A method for adjusting power of a power management chip to adapt to loads, comprising the following steps:

[0007] S1. Group the power tubes in the power management chip;

[0008] S2. Real-time detection of the power required by the load;

[0009] S3. Turn on the grouped power tubes according to the load size;

[0010] Furthermore, the power tubes in the power management chip are grouped in any one of the following ways: average grouping, unequal grouping and exponential grouping.

[0011] The present invention also provides a power regulation system for a power management chip adaptive load, comprising: a power management chip; a sampling module, a selection module and a control signal module; the sampling module is connected to the FB end of the power management chip; the selection module is respectively connected to the sampling module, the control signal module and the power tube in the power management chip.

[0012] Furthermore, the control signal module includes a frequency dividing circuit, and the clock signal passes through the frequency dividing circuit to output a plurality of control signals.

[0013] Furthermore, the sampling module includes a voltage divider circuit and a comparator; each different voltage node of the voltage divider circuit is respectively connected to the negative input terminal of the comparator; the positive input terminal of the comparator is connected to the reference voltage; the output terminal of the comparator outputs a selection signal; and the reference voltage is generated by the reference voltage circuit.

[0014] Furthermore, the selection module includes an AND gate and an NOR gate; the AND gate is used to identify the control signal and select the power tube driving signal corresponding to the control signal; the NOR gate is used to transmit the control signal.

[0015] Furthermore, the sampling module may include a first resistor, a second resistor, a third resistor, a first comparator, a second comparator, a first selection signal, a second selection signal and a reference voltage; the end of the chip is connected to the first resistor; the other end of the first resistor is connected to the second resistor, the other end of the second resistor is connected to the third resistor, and the other end of the third resistor is grounded; the negative input end of the first comparator is connected to the node formed by the first resistor and the second resistor; the negative input end of the second comparator is connected to the node formed by the second resistor and the third resistor; the reference voltage is input into the positive input ends of the first comparator and the second comparator respectively; the output end of the first comparator outputs the first selection signal, and the output end of the second comparator outputs the second selection signal.

[0016] Furthermore, the reference voltage may be 1.2V to 2.4V, and may be generated by a reference voltage circuit.

[0017] Furthermore, the selection module may include: a first logic gate, a second logic gate, a third logic gate, a fourth logic gate, and a fifth logic gate; the first logic gate, the second logic gate, the third logic gate, and the fourth logic gate are all AND gates, and the fifth logic gate is a NOR gate; the first control signal is input into the input end of the first logic gate, the second control signal is input into the input end of the second logic gate, the third control signal is input into the input end of the third logic gate, and the fourth control signal is input into the input end of the fourth logic gate; the first selection signal is respectively input into the input ends of the second logic gate and the fourth logic gate, and the first selection signal is respectively input into the input ends of the first logic gate and the third logic gate through an inverter; the second selection signal is respectively input into the input ends of the third logic gate and the fourth logic gate, and the second selection signal is input into the input ends of the first logic gate and the second logic gate through an inverter; the output ends of the first logic gate, the second logic gate, the third logic gate, and the fourth logic gate are all connected to the input end of the fifth logic gate; the output end of the fifth logic gate is connected to the power tube on the chip through an inverter.

[0018] Furthermore, the control signal module may include a frequency division circuit, and the clock signal generates a first control signal, a second control signal, a third control signal and a fourth control signal through the frequency division circuit.

[0019] The beneficial effects of the present invention are as follows: a power regulation method for a power management chip that is adaptive to the load is proposed, based on which the output power of the power management chip can be automatically adjusted according to the size of the load; different voltage signals corresponding to different loads are detected by a sampling circuit to select the control signal required by the power tube in the power management chip under different load conditions, and the selection module selects different power tube control signals according to the control signal given by the sampling circuit; thereby, the power regulation of the power management chip that is adaptive to the load can be realized, and the power management chip can output the power required by the load in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a method for power regulation of a power management chip for adaptive load according to the present invention;

[0021] Figure 2 This is an overall structural diagram of a power regulation system for a power management chip adaptive load according to the present invention;

[0022] Figure 3 A circuit diagram of a sampling module of a power regulation system of a power management chip for adaptive load according to the present invention;

[0023] Figure 4 A circuit diagram of a power regulation system selection module for a power management chip adaptive load according to the present invention;

[0024] Figure 5 The present invention is a circuit diagram of a control signal module of a power regulation system of a power management chip adaptive load.

[0025] Markings in the figure: first resistor R1, second resistor R2, third resistor R3, VREF reference voltage, Vsel1 first selection signal, Vsel2 second selection signal, D1 first comparator, D2 second comparator, T1 first control signal, T2 second control signal, T3 third control signal, T4 fourth control signal, K1 first logic gate, K2 second logic gate, K3 third logic gate, K4 fourth logic gate, K5 fifth logic gate, CK clock terminal, D enable terminal, Q output terminal, QB reverse output terminal. DETAILED DESCRIPTION

[0026] The present invention will be further described below in conjunction with the accompanying drawings and specific implementation methods.

[0027] Example 1

[0028] This embodiment provides a power regulation method for a power management chip to adapt to a load, comprising the following steps:

[0029] S1. Group the power tubes in the power management chip;

[0030] S2. Real-time detection of the power required by the load;

[0031] S3. Turn on the grouped power tubes according to the load size;

[0032] Example 2

[0033] The power tube grouping method in the first embodiment may be any one of the three methods: average grouping, unequal grouping and exponential grouping.

[0034] For example, if the total number of power tubes is 100, they can be evenly grouped so that the number of power tubes in each group is equal; divided into two groups of 50 each, divided into four groups of 25 each, and so on; this grouping situation is suitable for the situation where the load size changes linearly.

[0035] For example, if the total number of power tubes is 100, they can be divided into 30 in the first group, 30 in the second group, 30 in the third group, 10 in the fourth group, etc. according to the experience of the designer. This is suitable for situations where the load changes unevenly.

[0036] For example, if the total number of power tubes is 85, the exponential grouping makes the number of power tubes in the latter group exponentially times that of the former group. For example, the first group has 1, the second group has 4, the third group has 16, and the fourth group has 64. This grouping is suitable for situations where the load changes dramatically.

[0037] Example 3

[0038] This embodiment provides a power regulation system for a power management chip adaptive load, including: a power management chip, a sampling module, a selection module and a control signal module; the sampling module is connected to the FB end of the power management chip; the selection module is respectively connected to the sampling module, the control signal module and the power tube in the power management chip.

[0039] Furthermore, the control signal module includes a frequency dividing circuit, and the clock signal passes through the frequency dividing circuit to output a plurality of control signals.

[0040] At the same time, the sampling module includes a voltage divider circuit and a comparator; each different voltage node of the voltage divider circuit is respectively connected to the negative input terminal of the comparator; the positive input terminal of the comparator is connected to the reference voltage (VREF); the output terminal of the comparator outputs a selection signal; the reference voltage (VREF) is generated by the reference voltage circuit.

[0041] Furthermore, the selection module includes an AND gate and an NOR gate; the AND gate is used to identify the control signal and select the power tube drive signal corresponding to the control signal; and the NOR gate is used to transmit the control signal.

[0042] When in use, the FB end of the power management chip can reflect the current power load condition in the form of voltage at this port. The sampling module detects the load condition in real time by collecting the voltage data of the FB port, and outputs different selection signals according to the real-time load size; the control signal module is used to generate a driving signal for adjusting the power, which is used to control the power tube located in the power management chip; the selection module makes a selection according to the selection signal given by the adoption module, selects the power tube control signal suitable for the current load, and outputs and controls the power tube on the power management chip.

[0043] In order to adapt to different load requirements and control accuracy, the power tubes in the power management chip can be grouped, and the control signal module also corresponds to different power tube groups to generate different numbers of power tube control signals. The sampling module can sample the voltage at the FB end of the power management chip that reflects the load level with different accuracy, and reflect the sampling results through binary numbers to meet the load control requirements of different accuracy; for example: three resistors are divided into 2-bit binary numbers, four resistors are divided into 3-bit binary numbers, five resistors are divided into 4-bit binary numbers, etc.; at the same time, the selection module can also select the power tube control signal corresponding to the selection signal of different bits of binary numbers output by the sampling module.

[0044] Example 4

[0045] Furthermore, the sampling module includes a first resistor R1, a second resistor R2, a third resistor R3, a first comparator D1, a second comparator D2, a first selection signal Vsel1, a second selection signal Vsel2 and a reference voltage VREF; the FB terminal of the chip is connected to the first resistor R1; the other end of the first resistor is connected to the second resistor R2, the other end of the second resistor R2 is connected to the third resistor R3, and the other end of the third resistor R3 is grounded; the negative input terminal of the first comparator D1 is connected to the node formed by the first resistor R1 and the second resistor R2; the negative input terminal of the second comparator D2 is connected to the node formed by the second resistor R2 and the third resistor R3; the reference voltage VREF is respectively input to the positive input terminals of the first comparator D1 and the second comparator D2; the output terminal of the first comparator D1 outputs the first selection signal Vsel1, and the output terminal of the second comparator D2 outputs the second selection signal Vsel2.

[0046] The voltage signal reflecting the load weight output by the FB terminal of the power management chip is divided by the first resistor R1, the second resistor R2 and the third resistor R3 and then passed through the comparator to the reference voltage VREF to determine the load size; at the same time, the first selection signal Vsel1 and the second selection signal Vsel2 that can reflect the current load size are given.

[0047] When the voltage at the negative input terminal of the first comparator D1 is greater than the reference voltage VREF at the positive input terminal, the first selection signal Vsel1 is output as "0", and when the voltage at the negative input terminal of the second comparator D2 is greater than the reference voltage VREF at the positive input terminal, the second selection signal Vsel2 is "0", which corresponds to a power tube working state.

[0048] Furthermore, the reference voltage VREF is 1.2V to 2.4V and is generated by a reference voltage circuit.

[0049] The reference voltage is used to compare with the voltage signal in the sampling circuit that can reflect the load, so as to obtain a selection signal that can reflect the current load size.

[0050] Furthermore, the selection module includes: a first logic gate K1, a second logic gate K2, a third logic gate K3, a fourth logic gate K4, and a fifth logic gate K5; the first logic gate K1, the second logic gate K2, the third logic gate K3, and the fourth logic gate K4 are all AND gates, and the fifth logic gate K5 is a NOR gate; the first control signal T1 is input to the input end of the first logic gate K1, the second control signal T2 is input to the input end of the second logic gate K2, the third control signal T3 is input to the input end of the third logic gate K3, and the fourth control signal T4 is input to the input end of the fourth logic gate K4; the first selection signal Vsel1 is respectively input to the input ends of the second logic gate K2 and the fourth logic gate K4, and the first selection signal Vsel1 is respectively input to the input ends of the first logic gate K1 and the third logic gate K3 through an inverter; the second selection signal Vsel2 is respectively input to the input ends of the third logic gate K3 and the input end of the fourth logic gate K4, the second selection signal Vsel2 is input to the input ends of the first logic gate K1 and the second logic gate K2 through the inverter; the output ends of the first logic gate K1, the second logic gate K2, the third logic gate K3 and the fourth logic gate K4 are all connected to the input end of the fifth logic gate K5; the output end of the fifth logic gate K5 is connected to the power tube on the chip through the inverter.

[0051] The selection module can select different power tube driving signals through different selection signals, and different power tube driving signals control different types of power tube working modes; for example, when the first selection signal Vsel1 is "1" and the second selection signal Vsel2 is "1", the selection module will select the fourth control signal T4 to transmit to the power tube of the chip, thereby controlling the chip power tube to start different working states.

[0052] Furthermore, the control signal module includes a frequency division circuit, and the clock signal generates a first control signal T1, a second control signal T2, a third control signal T3 and a fourth control signal T4 through the frequency division circuit; the frequency division circuit includes four sequentially connected triggers, the clock signal is connected to the clock terminal CK of the first trigger, the enable terminal D of the first trigger is connected to the reverse output terminal QB, and is connected to the clock terminal CK of the next trigger, and the output terminals B of the four triggers output the first control signal T1, the second control signal T2, the third control signal T3 and the fourth control signal T4 in sequence.

[0053] Different control signals correspond to different power tube start-up schemes in the power management chip, causing the output power of the power management chip to change, thereby providing the power required by the load in real time.

Claims

1. A power management chip adaptive load power regulation system, comprising: a power management chip; characterized in that: include: A sampling module, a selection module and a control signal module; the sampling module is used to collect voltage data of the FB port and output different selection signals; the control signal module is used to generate a driving signal to control the power tube in the power management chip; the selection module is used to select different driving signals according to the result of the selection signal; the sampling module is connected to the FB end of the power management chip; the selection module is respectively connected to the sampling module, the control signal module and the power tube in the power management chip; The selection module comprises: a first logic gate (K1), a second logic gate (K2), a third logic gate (K3), a fourth logic gate (K4), and a fifth logic gate (K5); the first logic gate (K1), the second logic gate (K2), the third logic gate (K3), and the fourth logic gate (K4) are all AND gates, and the fifth logic gate (K5) is a NOR gate; a first control signal (T1) is input into an input end of the first logic gate (K1), a second control signal (T2) is input into an input end of the second logic gate (K2), a third control signal (T3) is input into an input end of the third logic gate (K3), and a fourth control signal (T4) is input into an input end of the fourth logic gate (K4); a first selection signal (Vsel1) is input into the first and second logic gates, respectively. The first logic gate (K1) and the second logic gate (K2) are connected to the input ends of the second logic gate (K2) and the fourth logic gate (K4); the first selection signal (Vsel1) is respectively input to the input ends of the first logic gate (K1) and the third logic gate (K3) through an inverter; the second selection signal (Vsel2) is respectively input to the input ends of the third logic gate (K3) and the fourth logic gate (K4); the second selection signal (Vsel2) is input to the input ends of the first logic gate (K1) and the second logic gate (K2) through an inverter; the output ends of the first logic gate (K1), the second logic gate (K2), the third logic gate (K3) and the fourth logic gate (K4) are all connected to the input end of the fifth logic gate (K5); the output end of the fifth logic gate (K5) is connected to the power tube on the chip through an inverter.

2. A power regulation system for a power management chip adaptive load as claimed in claim 1, characterized in that: The control signal module includes a frequency dividing circuit, and the frequency dividing circuit is used to process a clock signal and output a plurality of control signals.

3. A power regulation system for a power management chip adaptive load as claimed in claim 1, characterized in that: The sampling module includes a voltage divider circuit and a comparator; each different voltage node of the voltage divider circuit is respectively connected to the negative input terminal of the comparator; the positive input terminal of the comparator is connected to a reference voltage (VREF); the output terminal of the comparator outputs a selection signal; and the reference voltage (VREF) is generated by a reference voltage circuit.

4. A power regulation system for a power management chip adaptive load as claimed in claim 1, characterized in that: The selection module includes an AND gate and an NOR gate; the AND gate is used to identify the control signal and select the power tube driving signal corresponding to the control signal; the NOR gate is used to transmit the control signal.

5. A power regulation system for a power management chip adaptive load as claimed in claim 3, characterized in that: The sampling module comprises a first resistor (R1), a second resistor (R2), a third resistor (R3), a first comparator (D1), a second comparator (D2), a first selection signal (Vsel1), a second selection signal (Vsel2) and a reference voltage (VREF); the FB end of the chip is connected to the first resistor (R1); the other end of the first resistor is connected to the second resistor (R2), the other end of the second resistor (R2) is connected to the third resistor (R3), and the other end of the third resistor (R3) is grounded; the negative input end of the first comparator (D1) is connected to a node formed by the first resistor (R1) and the second resistor (R2); the negative input end of the second comparator (D2) is connected to a node formed by the second resistor (R2) and the third resistor (R3); the reference voltage (VREF) is respectively input to the positive input ends of the first comparator (D1) and the second comparator (D2); the output end of the first comparator (D1) outputs the first selection signal (Vsel1), and the output end of the second comparator (D2) outputs the second selection signal (Vsel2).

6. A power regulation system for a power management chip adaptive to load as claimed in claim 4, characterized in that: The control signal module includes a frequency division circuit, and the clock signal generates a first control signal (T1), a second control signal (T2), a third control signal (T3) and a fourth control signal (T4) through the frequency division circuit; the frequency division circuit includes four sequentially connected triggers, the clock signal is connected to the clock end (CK) of the first trigger, the enable end (D) of the first trigger is connected to the reverse output end (QB), and is connected to the clock end (CK) of the next trigger, and the output ends (B) of the four triggers sequentially output the first control signal (T1), the second control signal (T2), the third control signal (T3) and the fourth control signal (T4).

7. A power regulation system for a power management chip adaptive to load as claimed in claim 3, characterized in that: The reference voltage (VREF) is 1.2V.

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