Vehicle and method of controlling the same

Abstract

A vehicle is provided including a memory configured to store a predetermined time point at which each of a plurality of tasks, including a first task and a second task, is executed, and a detector configured to judge an erroneous operation of at least one processor that executes the plurality of tasks, wherein the detector is configured to control the at least one processor to output a trigger signal of one of the first task and the second task based on whether the other of the first task and the second task is completed at the respective predetermined time point.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0146616, filed with the Korean Intellectual Property Office on November 15, 2019, which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a vehicle and a method for controlling the same. Background Technology

[0004] Autonomous driving technology is a technology in which a vehicle detects road conditions and drives itself without the need for a driver to control the brakes, steering wheel, and accelerator pedals.

[0005] Autonomous driving technology is a key technology for realizing intelligent vehicles, and autonomous vehicles include Highway Driving Assist (HDA, a technology that automatically maintains distance between vehicles), Rear Side Warning (BSD, a technology that senses nearby vehicles and issues warnings when reversing), Automatic Emergency Braking (AEB, a technology that activates the braking device when no vehicle is detected in front), Lane Departure Warning System (LDWS), Lane Keeping Assist System (LKAS, a technology that compensates for lane departure without turn signals), Advanced Smart Cruise Control (ASCC, a technology that maintains distance between vehicles and drives at a constant speed at a set speed), Traffic Jam Assist (TJA), Parking Collision Avoidance Assist (PCA), and more.

[0006] However, when performing autonomous driving tasks, multiple processors may execute multiple tasks, and when each task fails to operate properly, a safe and robust alternative is required. Summary of the Invention

[0007] Embodiments of this disclosure relate to a vehicle capable of performing autonomous driving and a control method thereof.

[0008] In view of the above, embodiments of this disclosure provide a vehicle and its control method that can perform safe alternative operations even when errors occur in the time-series tasks performed by the autonomous vehicle.

[0009] According to an embodiment of the present disclosure, a vehicle includes: a memory configured to store a predetermined time point for the execution of each of a plurality of tasks; and a detector configured to determine erroneous operation of at least one processor executing the plurality of tasks, wherein the detector can control at least one processor to output a trigger signal for another task based on whether one of the plurality of tasks has completed at the predetermined time point.

[0010] Further, when one of the plurality of tasks does not complete at a predetermined time point corresponding to the one task, the detector can control the at least one processor to output a trigger signal of another task.

[0011] Further, the plurality of tasks can include a peripheral task that is continuously executed with the one task, and when the one task does not complete at the predetermined time point, the detector can control the at least one processor to execute the peripheral task based on completion data of the one task completed at a previous cycle time point.

[0012] Further, the plurality of tasks can be operated with a predetermined cycle, and when the one task does not complete at the predetermined time point, the detector can control the at least one processor to execute the peripheral task based on completion data of the one task completed at a previous cycle time point.

[0013] Further, the plurality of tasks can include a start task that is operated with a predetermined cycle.

[0014] Further, the plurality of tasks can be executed in parallel by the at least one processor.

[0015] According to an embodiment of the disclosure, a control method of a vehicle includes storing a predetermined time point at which each of a plurality of tasks is executed, judging an erroneous operation of at least one processor that executes the plurality of tasks, and outputting a trigger signal of another task based on whether one of the plurality of tasks completes at the predetermined time point.

[0016] Further, the method can include outputting the trigger signal of another task when one of the plurality of tasks does not complete at a predetermined time point corresponding to the one task.

[0017] Further, the plurality of tasks can include a peripheral task that is continuously executed with the one task, and the method can further include executing the peripheral task based on completion data of the one task completed at a previous cycle time point when the one task does not complete at a predetermined time point corresponding to the one task.

[0018] Further, the plurality of tasks can be operated with a predetermined cycle, and the method can further include executing the peripheral task based on completion data of the one task completed at a previous cycle time point when the one task does not complete at a predetermined time point corresponding to the one task.

[0019] Further, the plurality of tasks can include a start task that is operated with a predetermined cycle.

[0020] Further, the plurality of tasks can be executed in parallel by the at least one processor. BRIEF DESCRIPTION OF DRAWINGS

[0021] These and / or other aspects of the disclosure will become apparent and more readily appreciated from the following description, considered in connection with the accompanying drawings, in which:

[0022] Figure 1 is a control block diagram according to an embodiment.

[0023] Figure 2 is a diagram illustrating a plurality of tasks according to an exemplary embodiment.

[0024] Figures 3 to 7 is a diagram describing an operation of detecting an error operation of each task according to an embodiment.

[0025] Figure 8 is a flowchart according to an embodiment. DETAILED DESCRIPTION

[0026] In the following description, like reference numerals refer to like elements throughout the specification. Not all elements of an embodiment are described in the present specification, and there is no overlap between general matters or embodiments in the technical field to which the present disclosure pertains. Terms such as "unit", "module", "member", and "block" can be implemented as hardware or software. According to an embodiment, a plurality of "units", "modules", "members", and "blocks" can be implemented as a single component, or a single "unit", "module", "member", and "block" can include a plurality of components.

[0027] It will be understood that when an element is referred to as being "connected" to another element, the element can be directly connected to the other element or indirectly connected to the other element through a wireless communication network, where the indirect connection includes "connection through a wireless communication network".

[0028] In addition, when a part "includes" or "comprises" an element, unless there is a specific description to the contrary, the part can further include other elements, and other elements are not excluded.

[0029] Throughout the specification, when one member is "on" another member, this includes not only when the one member is in contact with the other member, but also when other members exist between the two members.

[0030] The terms "first", "second", and the like are used to distinguish one component from another component, and the components are not limited by the above terms.

[0031] Unless there is a clear distinction in the context, the singular form includes the plural form.

[0032] Reference numerals used in the description are used for convenience of description of operations, and are not intended to describe the order of operations, and unless otherwise specified, the operations can be performed in different orders.

[0033] Hereinafter, embodiments of the disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 is a control block diagram according to an embodiment.

[0035] Referring to Figure 1 The vehicle 1 according to an embodiment can include a memory 110 and a detector 100. The memory 110 can store a predetermined time point at which each of a plurality of tasks is executed.

[0036] The task can mean an operation required for autonomous driving performed by the processors 201, 202, and 203 of the vehicle.

[0037] Meanwhile, Figure 1 The processor illustrated is an exemplary embodiment to describe the operation of the present embodiment, and is not limited to the number or operation of the processor.

[0038] The predetermined time point can mean a time point at which each task is completed by each processor.

[0039] The memory 110 can be a non-volatile memory device such as a cache, a read only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory, or a volatile memory device such as a random access memory (RAM), or a storage medium such as a hard disk drive (HDD) or a CD-ROM, but is not limited thereto. The memory can be a memory implemented as a chip separate from the above-described processor associated with the controller, or can be implemented as a single chip together with the processor.

[0040] The detector 100 can determine an erroneous operation of at least one processor that executes a plurality of tasks.

[0041] The detector 100 can control the at least one processor to output a trigger signal of another task based on whether one task of the plurality of tasks is completed.

[0042] The trigger signal can mean a signal that guides to start execution of each task.

[0043] The detector 100 can control the at least one processor to output a trigger signal of another task based on whether one task of the plurality of tasks is completed at a predetermined time point corresponding to the one task.

[0044] In detail, when the one task is not completed at the predetermined time point, the detector 100 can control the at least one processor to forcibly transmit a trigger signal that can command to start execution of another task to a processor that executes the another task.

[0045] The plurality of tasks can include a peripheral task that is continuously executed with one task. The peripheral task can refer to a task that continuously performs an operation of one task.

[0046] When one task is not completed at a predetermined time point, the detector 100 can control the at least one processor to execute a peripheral task based on completion data of one task completed at a previous cycle time point.

[0047] The plurality of tasks operates in a predetermined cycle, and when one task is not completed at a predetermined time point, the detector 100 can control the at least one processor to execute a peripheral task based on completion data of one task completed at a previous cycle time point.

[0048] In more detail, in the operation of each task, completion data of a previous task can be required. However, if the previous task is not completed but a task is executed based on a trigger signal transmission, the completion data of the previous task is received based on completion data of a previous cycle time point rather than completion data of a corresponding time point.

[0049] However, the task can be periodically operated, and the processor can execute the task based on completion data of the task corresponding to a previous cycle.

[0050] The plurality of tasks can include a start task that operates in a predetermined cycle. The start task can refer to a task that operates based on a cycle independently of other related tasks.

[0051] The plurality of tasks can be executed in parallel by a plurality of processors. The parallel execution indicates that the tasks are completed by different routes in concept, rather than a time limit or a correlation limit of each task.

[0052] The detector 100 can be implemented as a memory for storing data about an algorithm for controlling the operation of components in a vehicle or a program for reproducing the algorithm and a processor that performs the above-described operation using the data stored in the memory 110. In this case, the memory 110 and the processor can be implemented as separate chips. Alternatively, the memory 110 and the processor can be implemented in a single chip.

[0053] At least one component can be added or deleted to correspond to Figure 1 In addition, those skilled in the art will easily understand that the mutual positions of the components can be changed to correspond to the performance or structure of the system.

[0054] Meanwhile, Figure 1 Each component illustrated refers to a software and / or a hardware component such as a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC).

[0055] Figure 2is a diagram showing a plurality of tasks according to an exemplary embodiment.

[0056] Figure 2 It is shown that a plurality of tasks are executed by three processors.

[0057] In Figure 2 , a microcontroller unit (MCU) includes three processors, and tasks 1 to 5 are executed by the processors.

[0058] Each task can correspond to a processor having a different function.

[0059] The plurality of tasks can be sequentially or in parallel executed by each processor according to a schedule.

[0060] In Figure 2 , tasks 1 to 5 are executed by three processors. Task 1 is executed by processor 2. In addition, the diagram shows that tasks 2 and 3 are executed by processor 1. Meanwhile, task 4 is executed by processor 3, and task 5 is executed by processor 2.

[0061] Task 1 is a start-up task, and can periodically perform an operation. Figure 2 It is shown that processors 1 to 3 perform operations of tasks within a period TP.

[0062] When task 1 is completed, processor 2 can transmit a trigger signal for executing task 2 to processor 1. In addition, when task 1 is completed, processor 2 can transmit a trigger signal for starting execution of task 4 to processor 3.

[0063] When task 2 is completed, processor 1 can execute task 3.

[0064] Processor 3 can execute task 4. Meanwhile, when task 3 is completed by processor 1 and task 4 is completed by processor 3, processor 1 can transmit a trigger signal for executing task 5.

[0065] Alternatively, the operation can be performed in such a manner that each task receives completion data of a previous task before executing a next task. In one example, tasks are sequentially executed from task 1 to task 5.

[0066] The detector 100 is a system having a multi-task execution scheduling structure. The detector 100 detects an erroneous operation due to an error or an execution time delay in a single software operation.

[0067] On the other hand, the tasks described in the present specification are only examples for explaining the operation of the present embodiment, and are not limited to such tasks.

[0068] Figures 3 to 7 is a diagram describing an operation of detecting an erroneous operation of each task according to an embodiment.

[0069] In Figures 3 to 7 , the scheduled time points T1, T2, T3, T4, and T5 of each task are predicted completion times, and the scheduled time points T1, T2, T3, T4, and T5 can be stored in the memory 110.

[0070] The completion data of the task is updated only when the execution is completed, and when the execution is not completed, the previous cycle data of the task can be transmitted to the peripheral task.

[0071] Referring to Figure 3 , the task 1 is not completed at the scheduled time point T1 corresponding to the task 1.

[0072] In this case, the detector 100 can control the processor 2 to transmit a trigger signal that can start the operation of the tasks 2 and 4 to the processor 1 and the processor 3.

[0073] The detector 100 can also deliver the previous cycle completion data of the task 1 to the tasks 2 and 4 to control the task 5 to output a control signal.

[0074] Referring to Figure 4 , the task 2 is not completed at the scheduled time point T2 corresponding to the task 2.

[0075] In this case, the detector 100 can control the processor 1 to transmit a trigger signal that can start the operation of the task 3.

[0076] The detector 100 can transmit the current completion data of the task 1 and the previous cycle completion data of the task 2 to the task 3 to control the task 5 to output a control signal.

[0077] Figure 5 It is shown that the task 3 is not completed at the scheduled time point T3 corresponding to the task 3.

[0078] When the task 3 is not completed at the scheduled time point corresponding to the task 3, the detector 100 can control the processor 1 or the processor 3 to transmit a trigger signal for executing the task 5 to the processor 2.

[0079] The processor can transmit the current cycle completion data of the tasks 1, 2, and 4 and the previous cycle completion data of the task 3 to the task 5 to output a control signal.

[0080] Figure 6 It is shown that the task 4 is not completed at the scheduled time point T4 corresponding to the task 4.

[0081] When the operation of the task 4 is not completed at the scheduled time point corresponding to the task 4, the detector 100 can control the processor 1 or the processor 3 to transmit a trigger signal for executing the task 5 to the processor 2.

[0082] The detector 100 can transmit the current cycle completion data of tasks 1, 2, and 3 and the previous cycle completion data of task 4 to task 5 to output a control signal.

[0083] Referring to Figure 7 , the operation of task 5 is not completed at a predetermined time point T5 corresponding to task 5.

[0084] Referring to Figure 7 When the operation of task 5 is not completed at a predetermined time point corresponding to task 5, the detector 100 can control the processor 1 or the processor 3 to transmit a trigger signal to start executing task 5.

[0085] Since task 5 is a final task in which there is no task required for a subsequent operation, task 5 can be controlled to transmit a trigger signal capable of starting the execution of the task.

[0086] In this case, each processor can output a control signal based on the previous cycle completion data of tasks 1, 2, 3, and 4.

[0087] However, in the case of task 5, the operation of another processor and module can be implemented based on the previous cycle output value of task 5.

[0088] Meanwhile, referring to Figures 3 to 7 the operation described is only for implementing the embodiments of the disclosure, and the form of operation of the detector 100 is not limited with respect to the time point corresponding to each task and the task that is not completed at the corresponding time point.

[0089] Figure 8 is a flowchart according to an embodiment.

[0090] Referring to Figure 8 , each processor can execute each task (1001).

[0091] In this case, as described above, the predetermined time point corresponding to each task is stored in the memory 110, and the detector 100 can determine whether the operation of the task is completed at the corresponding time point (1002). The completion of the task at the corresponding time point indicates that the task is normally operated, and thus each processor can execute another task (1005).

[0092] However, when the operation of the task is not completed at the corresponding time point (NO in 1002), the detector 100 can control to transmit a trigger signal for starting the operation of another task to the corresponding processor (1003). In addition, in this case, the associated task can receive the previous cycle completion data of each task (1004). Based on this, even if the operation of the task is not completed at the predetermined time point, the processor can perform the operation of the next task (1005).

[0093] On the other hand, the disclosed embodiments can be implemented in the form of a recording medium for storing computer-executable instructions. The instructions can be stored in the form of program codes, and when executed by a processor, can generate program modules to perform the operations of the disclosed embodiments. The recording medium can be implemented as a computer-readable recording medium.

[0094] The computer-readable recording medium includes all types of recording media in which instructions can be decoded by a computer. For example, it can be a read-only memory (ROM), a random access memory (RAM), a magnetic tape, a magnetic disk, a flash memory, an optical data storage device, etc.

[0095] As described above, the disclosed embodiments have been described with reference to the accompanying drawings. Although example embodiments of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made in the embodiments without departing from the principles and spirit of the present disclosure, and the scope of the present disclosure is defined in the claims and their equivalents.

[0096] Despite the presence of errors in performing time-series tasks of an autonomous vehicle, the vehicle of the disclosed embodiments and its control method can perform safe alternative operations.

Claims

1. A vehicle comprising: The memory stores a predetermined time point for the execution of each of a plurality of tasks, including a first task and a second task. as well as The detector identifies erroneous operations by at least one processor executing the plurality of tasks. The detector controls the at least one processor to output a trigger signal for the other task between the first task and the second task based on whether one of the first task and the second task completes at its respective predetermined time point. When one task is not completed at a predetermined time point, the detector controls the at least one processor to execute the other task based on the completion data of the first task at a previous cycle time point.

2. The vehicle according to claim 1, wherein, When the first task is not completed at the predetermined time point corresponding to the first task, the detector controls the at least one processor to output a trigger signal for the second task.

3. The vehicle according to claim 1, wherein, The plurality of tasks includes peripheral tasks that execute sequentially with the first task, and When a task is not completed at a predetermined time point, the detector controls the at least one processor to execute the peripheral task based on the completion data of the task at a previous cycle time point.

4. The vehicle according to claim 1, wherein, Each of the plurality of tasks operates at a predetermined period, and When a task is not completed at a predetermined time point, the detector controls the at least one processor to execute peripheral tasks based on the completion data of the task at a previous cycle time point.

5. The vehicle according to claim 4, wherein, The plurality of tasks includes a startup task that operates at the predetermined period.

6. The vehicle according to claim 1, wherein, The multiple tasks are executed in parallel by the at least one processor.

7. A method for controlling a vehicle, comprising: Store the predetermined time point for the execution of each of a plurality of tasks, including a first task and a second task; Determine an erroneous operation by at least one processor executing the plurality of tasks; The trigger signal for the other task is output based on whether one of the first task and the second task is completed at a predetermined time. as well as If one task is not completed at a predetermined time, the other task is executed based on the completion data of the first task at a previous time point in the cycle.

8. The method according to claim 7, wherein, The output trigger signals include: If the first task is not completed at the predetermined time point corresponding to the first task, the trigger signal for the second task is output.

9. The method according to claim 7, wherein, The multiple tasks include peripheral tasks that are executed sequentially with the one task. The method further includes: If a task is not completed at a predetermined time, the peripheral task is executed based on the completion data of the task at a previous cycle time.

10. The method according to claim 7, wherein, The multiple tasks operate at a predetermined cycle. The method further includes: If a task is not completed at a predetermined time, peripheral tasks are executed based on the completion data of the task at a previous cycle time.

11. The method according to claim 10, wherein, The plurality of tasks includes a startup task that operates at the predetermined period.

12. The method according to claim 7, wherein, The multiple tasks are executed in parallel by the at least one processor.

13. A method for controlling a vehicle, comprising: Execute the first of a series of tasks, which is scheduled to be completed at a predetermined time. Determine whether the first task has not been completed at the predetermined time point; When the first task is completed at the predetermined time point, in response to the completion of the first task at the predetermined time point, the second task among the plurality of tasks is executed; as well as If the first task is not completed at the predetermined time point, the trigger signal for the second task and the completion data of the first task at a previous cycle time point before the predetermined time point are transmitted, and the second task is executed in response to the completion data of the first task at the previous cycle time point.

14. The method according to claim 13, wherein, The multiple tasks include peripheral tasks. The method further includes: If the first task is not completed at the predetermined time point, the peripheral tasks are executed continuously with the first task based on the completion data of the first task.

15. The method according to claim 13, wherein, The multiple tasks operate at a predetermined cycle. The method further includes: If the first task is not completed at the predetermined time point, peripheral tasks are executed based on the completion data of the first task at a previous cycle time point.

16. The method according to claim 15, wherein, The plurality of tasks includes a startup task that operates at the predetermined period.

17. The method according to claim 13, wherein, The multiple tasks are executed in parallel by at least one processor.

18. The method according to claim 13, wherein, The multiple tasks are executed by multiple processors.

19. The method according to claim 13, wherein, The predetermined time point is stored in the memory.

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