Method for forming a common electrode of a plurality of optoelectronic devices

Abstract

The present invention relates to a method for forming a common electrode (190) for a plurality of optoelectronic devices, the method comprising the following steps: a) providing a support substrate (111) on which optoelectronic devices separated by trenches (170) are placed; b) forming a dielectric layer (130) on the front surface, side surfaces and bottom of the trenches, the thicknesses of the dielectric layer formed on the front surface and side surfaces being thickness E1 and thickness E2 less than thickness E1, respectively; c) etching the dielectric layer (130) by a thickness E3 to expose the side surfaces at a first portion (170a) of the trenches; d) forming a metal layer that fills the trenches and covers the front surface; e) performing mechanical chemical polishing on the metal layer, the polishing stopping on a portion of the dielectric layer (130), and the metal remaining in the trenches (170) forms the common electrode (190).

Description

Field of the Invention

[0001] The present invention relates to the fields of microelectronics and optoelectronics. Specifically, the present invention relates to a method for forming electrical contact portions on the sides of devices (more specifically, light-emitting diodes) placed on the main surface of a support substrate.

[0002] Specifically, the present invention is implemented especially to simplify manufacturing and increase the control of electrodes on the sides of LEDs with extremely high aspect ratios. Background Art

[0003] Known light-emitting display devices in the prior art generally include light-emitting diode (LED) assemblies, especially gallium nitride-based light-emitting diode (LED) assemblies.

[0004] An LED includes, from front to back: an N-doped semiconductor layer, a light-emitting layer assembly, and a P-doped semiconductor layer, and the LED is placed on a support substrate provided with a control circuit through the back surface of the LED, and the control circuit is designed to individually address each LED at the P-doped semiconductor layer of the LED.

[0005] The light-emitting display device further includes a common electrode that is in electrical contact with the N-doped semiconductor layer of each LED in the LED. This electrical contact generally occurs on the side of the semiconductor layer.

[0006] Therefore, Figures 1A to 1G shows a method for forming a light-emitting display device known in the prior art.

[0007] This method specifically includes the step of providing a support substrate 111 having an integrated control circuit 110 formed on its main surface as shown in Figure 1A . The integrated circuit specifically includes metal connection posts 113 separated from each other by a dielectric region 114, and the metal connection posts 113 are designed to connect a plurality of LEDs through their back surfaces.

[0008] Figure 1B is a schematic diagram of a stack 150 of layers formed on the main surface of a support substrate 151. Specifically, starting from this main surface, the stack of layers includes an N-doped semiconductor layer 153, a light-emitting layer assembly 155, and a P-doped semiconductor layer 157. Each layer in the layers may include gallium nitride.

[0009] According to the method known in the prior art, the stack 150 of layers is then transferred to the main surface of the support substrate 111 ( Figure 1C ). The transfer may include the following steps: bonding the stack 150 to the integrated circuit 110 and then removing the support substrate 151.

[0010] In addition, before the bonding step, one or two intermediate metal layers 116 and 159 can be formed on the integrated circuit 110 and the stack 150 respectively.

[0011] Then, after the transfer step, the following steps are carried out: forming a trench 170 in the stack 150 starting from the face of the stack exposed to the external environment, and the trench 170 extends through the entire thickness of the stack to define a plurality of LEDs 172( Figure 1D ).

[0012] The formation of the trench generally involves the following successive steps:

[0013] Forming a hard mask layer, such as a dielectric material layer, by covering the exposed surface of the stack 150,

[0014] A lithography step aimed at delineating a pattern 120 in the hard mask layer with a photoresist layer,

[0015] Etching the hard mask layer to form a pattern 120 of the hard mask,

[0016] Removing the photoresist applied in the lithography step,

[0017] Etching the stack 150 through the hard mask to delineate the LEDs.

[0018] The etching step can be continued so as to then remove portions of the layer 116 and the layer 159 from the bottom of the trench 170.

[0019] Thus, at the end of the steps, the support substrate 111 includes a plurality of LEDs separated from each other by the trenches 170.

[0020] In particular, the LEDs are placed on the main surface of the support substrate 111 through the back side of the LEDs, while the front side of each LED, which is opposite to the back side and is connected to the back side through the side, is covered with the hard mask pattern 120. Thus, the trench 170 is defined by the bottom at the main surface of the support substrate and the side of the LED.

[0021] Then, after forming the LEDs, a step of passivating the LEDs is performed ( Figure 1E ). Passivation specifically includes forming a passivation film 190 by covering the hard mask pattern 120, the side surfaces 180 of the LEDs 172, and the bottom of the trench 170.

[0022] Then a step of partially removing the passivation layer is performed. This step specifically includes removing a part of the passivation layer covering the pattern 120 and a first part of the side surface, and this first part of the side surface extends from the front side of the LED to a depth less than the thickness of the N-doped semiconductor layer ( Figure 1F ).

[0023] In other words, at the end of this step, the passivation layer 190 remains on the second part, which extends from the bottom of the trench by a height corresponding at least to the combined thickness of the intermediate metal layer 116, the intermediate metal layer 159, the P-doped semiconductor layer 157, and the light-emitting layer assembly 155.

[0024] The above removal is specifically implemented through a photolithography step, which includes filling the second part of the trench with a photoresist resin and then etching the pattern 120 and the passivation layer at the first part.

[0025] Finally, a common electrode is formed by filling the trench 170 with a metal material.

[0026] In particular, the formation of the common electrode involves the growth of a metal layer, for example, by electrodeposition covering the pattern 120 and filling the trench.

[0027] Next, a mechano-chemical polishing step that stops at the hard mask pattern 120 is performed to leave only the metal in the trench.

[0028] However, the above method is not satisfactory.

[0029] In fact, at the end of the step of forming the trench, the thickness of the hard mask pattern 120 is not well controlled and is particularly non-uniform from one pattern to another.

[0030] The consequence of this non-uniformity is a significant variation between the first part of one trench and the first part of another trench. Therefore, it is difficult to precisely control the range of the contact area between the common electrode and the N-doped semiconductor layer of each LED.

[0031] Therefore, an object of the present invention is to propose a method for forming a common electrode that is easy to implement.

[0032] Another object of the present invention is to propose a method for forming a common electrode that is more reliable and has less variability compared to the methods known in the prior art. Summary of the Invention

[0033] The object of the present invention is at least partially achieved by a method for forming a common electrode for a plurality of optoelectronic devices, wherein each optoelectronic device includes a front surface and a back surface connected by sides, and the method includes the following steps:

[0034] a) Providing a support substrate, on the main surface of which the back surfaces of a plurality of optoelectronic devices separated by trenches are placed, the trenches being defined by the sides of the optoelectronic devices and the bottom at the main surface;

[0035] b) A dielectric layer is formed by covering the front face, side faces, and the bottom of the trench, with the thickness of the dielectric layer on the front face and side faces being thickness E1 and thickness E2 which is less than thickness E1, respectively;

[0036] c) The dielectric layer is wet-etched by a thickness E3 which is less than thickness E1 to expose the side faces at the first part of the trench, and at least partially retain the dielectric layer on the front face;

[0037] d) A metal layer is formed to fill the trench and cover the front face;

[0038] e) Chemical mechanical polishing is performed on the metal layer, and the polishing stops on the part of the dielectric layer retained at the end of step c), and the metal retained in the trench forms a common electrode.

[0039] According to one embodiment, each trench includes, starting from the bottom, a second part and a first part adjacent to each other, the second part and the first part extend according to a second height and a first height, respectively, and the first part leads to the plane formed by the front face of the optoelectronic device.

[0040] According to one embodiment, thickness E1 is at least 2 times greater than thickness E2.

[0041] According to one embodiment, before step b), there is a step b0): a passivation layer is formed by covering the front face, side faces, and the bottom of the trench according to the conformal deposition technique, and step c) can also remove the passivation layer at the first part.

[0042] According to one embodiment, step b0) is performed by atomic layer deposition.

[0043] According to one embodiment, the passivation layer at least includes a material selected from the following: SiO 2 , Al 2 O 3 .

[0044] According to one embodiment, the thickness of the passivation layer is between 5 nm and 30 nm.

[0045] According to one embodiment, the dielectric layer is formed by plasma-activated chemical vapor deposition technique.

[0046] According to one embodiment, the dielectric layer includes at least one material selected from the following materials: SiO 2 , Si 3 N 4 .

[0047] The silicon nitride Si 3 N 4 considered in the present invention does not have to be stoichiometric.

[0048] According to one embodiment, step a) includes transferring a stack of layers formed on a seed substrate onto a main surface of a support substrate.

[0049] According to one embodiment, after transferring the stack of layers, trenches are formed extending through the entire thickness of the stack.

[0050] According to one embodiment, the formation of the trenches uses a hard mask that is removed before performing step b).

[0051] According to one embodiment, the optoelectronic device is a light-emitting diode that includes, from its front face to its back face, a first N-doped semiconductor layer, a light-emitting layer assembly, and a second P-doped semiconductor layer, and a first height that is less than or equal to the thickness of the N-doped semiconductor layer.

[0052] According to one embodiment, an integrated circuit is included on the main surface of the support substrate, and the integrated circuit is designed to individually address each optoelectronic device. Description of the Drawings

[0053] With reference to the following drawings, in a method of forming electrical contacts for a plurality of optoelectronic devices according to the present invention described by way of non-limiting example, other features and advantages of the present invention will become apparent, wherein:

[0054] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F and Figure 1G are schematic views of respective steps implemented in manufacturing a light-emitting display device according to a method known in the prior art, and specifically show views related to the drawings in a cross-section perpendicular to the main surface of the support substrate;

[0055] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D and Figure 2E are schematic views of respective steps implemented in manufacturing a light-emitting display device according to the present invention, and specifically show views related to the drawings in a cross-section perpendicular to the main surface of the support substrate;

[0056] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E and Figure 3F are schematic views of respective steps that may be implemented in performing step a) of the method of the present invention, and specifically show views related to the drawings in a cross-section perpendicular to the main surface of the support substrate. Detailed Description

[0057] In the various figures, the same reference numerals denote the same elements. Additionally, the figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments are shown and described in detail.

[0058] In particular, embodiments of integrated control circuits that are known per se to those skilled in the art are not described in detail.

[0059] The present invention relates to a method for manufacturing a common electrode of an optoelectronic device, which is placed on the main surface of a support substrate through its back surface.

[0060] The remainder of the specification will be limited to optoelectronic devices formed by light-emitting diodes (hereinafter referred to as "LEDs"). However, those skilled in the art can apply the present invention to any other type of device, such as a photodiode.

[0061] Figures 2A to 2E A schematic representation of the various steps of a method for manufacturing a common electrode for a plurality of light-emitting diodes 172 is shown, each light-emitting diode including a front surface 151a and a back surface 151b connected by a side surface 151c.

[0062] Specifically, the method includes step a): providing a support substrate 111, and placing a plurality of light-emitting diodes 172 separated by trenches 170 on the surface of the support substrate called the main surface 111a through their back surfaces 151b ( Figure 2A ).

[0063] Specifically, the trenches 170 are defined by the side surfaces 151c of the light-emitting diodes 172 and the bottom 170a at the main surface 111a.

[0064] The support substrate 111 may include an integrated circuit on its main surface 111a, which is intended to individually address each light-emitting diode 172.

[0065] In particular, the integrated circuit may include metal connection posts 113 separated from each other by a dielectric region 114.

[0066] Specifically, the metal connection posts 113 are intended to be connected to each of the back surfaces 151b of the light-emitting diodes 172, so as to be able to control the light-emitting diodes.

[0067] The integrated circuit may also include a basic unit associated with each light-emitting diode 172, and the basic unit is provided with one or more transistors for controlling the current flowing in the diode.

[0068] As Figures 3A to 3F shown, performing step a) may specifically include the following steps.

[0069] a0) Provide a support substrate 111 having an integrated circuit provided on its main surface 111a ( Figure 3A , only the metal pillars 113 and the dielectric regions 114 are shown).

[0070] a1) Form a stack 150 of layers on the first face of a seed substrate 151, for example by epitaxy ( Figure 3B ).

[0071] a2) Transfer the stack 150 of layers onto the main surface 111a ( Figure 3C ).

[0072] a3) Form trenches 170 ( Figure 3D and 3E ).

[0073] Specifically, step a3) of forming the trenches 170 is carried out by forming a hard mask ( Figure 3D ) and then etching through this mask ( Figure 3E ) to define the light-emitting diodes 172.

[0074] In this regard, the hard mask includes pillars 120, which are made of a dielectric material, for example, and define the imprint of the light-emitting diodes 172 to be formed. Specifically, the thickness of the pillars 120 can be between 500 nm and 1.5 μm, for example 1 μm.

[0075] Finally, after step a3), the pillars 120 forming the hard mask are removed ( Figure 3F ). This final step makes it possible to advantageously reduce the aspect ratio of the structure placed on the main surface 111a of the support substrate 111.

[0076] The stack formed in step a1) can include a first N-doped semiconductor layer 153, a light-emitting layer assembly 155, and a second P-doped semiconductor layer 157 starting from the first face of the seed substrate 151. In other words, the light-emitting diode includes a first N-doped semiconductor layer 153, a light-emitting layer assembly 155, and a second P-doped semiconductor layer 157 from its front face 151a to its back face 151b. According to another variant, the order of the stacked layers can be reversed.

[0077] Step a2) can include bonding the seed substrate (on which the stack is formed) to the main surface 111a of the support substrate 111, then removing the seed substrate and reducing the thickness of the layer 153.

[0078] The first N-doped semiconductor layer 153 can include N-doped GaN, and its thickness is between 0.5 μm and 0.2 μm.

[0079] The second P-doped semiconductor layer 157 can include P-doped GaN, and its thickness is between 0.1 μm and 0.5 μm.

[0080] More specifically, the total thickness of the stack 150 can be between 700 nm and 3 μm.

[0081] Each light-emitting layer in the light-emitting layer assembly 155 may include, for example, quantum wells based on GaN, InN, InGaN, AlGaN, AlN, AlInGaN, GaP, AlGaP, AlInGaP, or a combination of one or more of the above materials.

[0082] Alternatively, the light-emitting layer of the assembly 155 may be, for example, an intrinsic gallium nitride layer with a residual donor concentration between 10 15 and 10 18 atoms / cm 3 (for example, about 10 17 atoms / cm 3 ), that is, without intentional doping.

[0083] Before the transfer step a2), one or two metal layers 116 and 159 may be formed by covering the main surface 111a and the free surface of the stack 150, respectively.

[0084] Specifically, the two metal layers 116 and 159 are configured to contact each other during the transfer step a2) ( Figure 3C ).

[0085] The metal layer 116 may include titanium and aluminum.

[0086] The metal layer 159 may include a stack of an aluminum layer and a titanium layer, and the titanium layer is intended to contact the metal layer 116.

[0087] The thickness of the metal layer 116 may be between 300 nm and 1 μm, for example, 600 nm.

[0088] The thickness of the metal layer 159 may be between 50 nm and 300 nm, for example, 100 nm.

[0089] Once the two metal layers 116 and 159 are considered, it is reasonable that the trench 170 formed in step a3) also extends over the overall combined thickness of these two layers ( Figure 3E ).

[0090] The method according to the invention further includes a step b) carried out after step a).

[0091] Specifically, step b) includes forming a dielectric layer 130 by covering the front face 151a, the side face 151c, and the bottom 170a of the trench 170 ( Figure 2B ).

[0092] Specifically, the thicknesses of the dielectric layer 130 on the front face 151a and the side face 151c are a thickness E1 and a thickness E2 less than the thickness E1, respectively.

[0093] For example, the thickness E1 is at least 2 times greater than the thickness E2.

[0094] As another example, the thickness E1 can be between 100 nm and 500 nm, for example equal to 200 nm.

[0095] The dielectric layer 130 can be formed by plasma-activated chemical vapor deposition technology. This technology is particularly advantageous for the embodiments of the present invention in that it enables the deposition of a non-conformal layer (i.e., having a greater deposition rate on the front face 151a than on the side face 151c). However, the present invention is not limited to this deposition technology, and those skilled in the art can use any other technology that may deposit the layer in a non-conformal manner.

[0096] The dielectric layer 130 can include at least one material selected from the following materials: SiO 2 、Si 3 N 4 .

[0097] Advantageously, according to a variant, step b0) can be included before step b): forming a passivation layer 120 by covering the front face 151a, the side face 151c, and the bottom 170a of the trench 170 according to a conformal deposition technology.

[0098] "Conformal deposition technology" refers to a technology in which the deposition rates on the side face and the front face are substantially equal (advantageously equal). "Substantially equal" means that the relative deviation is less than 10%, advantageously less than 5%.

[0099] The thickness of the passivation layer 120 can be between 5 nm and 30 nm and at least includes a material selected from the following: SiO 2 、Al 2 O 3 .

[0100] The passivation layer 120 can be formed by atomic layer deposition.

[0101] After step b), there is step c): wet-etching the dielectric layer 130 by a thickness E3 less than the thickness E1 to expose the side face at the first portion 171a of the trench, the first portion of the trench extending a first height ( Figure 2C ) from the front face 151a of the light-emitting diode 172.

[0102] In addition, step c) is performed to at least partially retain the dielectric layer 130 on the front face 151a.

[0103] Step c) is also performed to preserve the dielectric layer 130 at the second part 171b of the trench 170 adjacent to the first part 171a, the second part extending from the first part to the bottom 170a of the trench 170.

[0104] The portion of the dielectric layer preserved at the end of step c) will advantageously be used as a layer to stop the mechano-chemical polishing steps described in the rest of the specification.

[0105] If the passivation layer 120 is considered, the passivation layer at the first part 171a is also etched.

[0106] Advantageously, before the wet etching, step c) fills the second part 171b of the trench 170 with a photoresist resin.

[0107] Advantageously, the first height is less than or equal to the thickness of the N-doped semiconductor layer.

[0108] Step c) is followed by the formation of the common electrode 190. Specifically, the method may include step d): forming a metal layer 185 by covering the front face 151a and the trench 170, specifically by electrodeposition or by CVD ( Figure 2D ); and step e): performing mechano-chemical polishing to retain only the metal in the trench 170.

[0109] "Covering the trench" means covering the side walls and the bottom.

[0110] According to the invention, covering the trench does not exclude filling the trench.

[0111] Still according to the invention, in the case where step d) does not cause filling of the trench, a step of filling the voids in the trench with a metal material may be performed.

[0112] Particularly advantageously, step d) can be implemented according to the damascene method.

[0113] In this regard, the portion of the dielectric layer 130 remaining on the front face 151a at the end of step c) serves as a polishing stop layer.

[0114] The metal remaining in the trench 170 at the end of step e) forms the common electrode, which is in electrical contact with the N-doped semiconductor layer of each light-emitting diode at the side of the light-emitting diode.

[0115] The presence of the dielectric layer 130 and optionally the passivation layer at the second part 170b enables the common electrode to be electrically isolated from the second P-doped semiconductor layer 157 and the light-emitting layer assembly 155.

[0116] The implementation of the present invention is advantageous when the aspect ratio of the light-emitting diode is relatively large, especially greater than 2. In fact, once the dielectric layer 130 and the passivation layer are considered, the removal of the hard mask according to the present invention enables the topology to be more easily covered by the dielectric layer 130 and the passivation layer.

[0117] In addition, during the mechano-chemical polishing step, the front face of the light-emitting diode (and thus the first N-doped semiconductor layer 153) is protected by the dielectric layer 130.

Claims

1. A method of forming a common electrode (190) for a plurality of optoelectronic devices, each of the plurality of optoelectronic devices including a front face (151a) and a back face (151b) connected by a side face (151c), the method comprises the following steps: a) providing a support substrate (111), placing the plurality of optoelectronic devices separated by trenches (170) on a surface of the support substrate called the main surface (111a) through the back faces (151b) of the plurality of optoelectronic devices, the trenches (170) being defined by the side faces (151c) of the optoelectronic devices and a bottom at the main surface (111a); b) forming a dielectric layer (130) by covering the front face, the side face (151c), and the bottom of the trench (170), the thicknesses of the dielectric layer (130) at the front face and the side face (151c) being a thickness E1 and a thickness E2 less than the thickness E1, respectively; c) wet-etching the dielectric layer (130) by a thickness E3 less than the thickness E1 to expose the side face (151c) at a first portion (171a) of the trench (170) and at least partially retain the dielectric layer (130) on the front face; d) forming a metal layer (185) by covering the trench (170) and covering the front face; e) performing a mechano-chemical polishing on the metal layer (185), the polishing stopping on a portion of the dielectric layer (130) covering the front face retained at the end of step c), and the metal retained in the trench (170) forms the common electrode (190); each trench includes a second portion (171b) adjacent to the first portion starting from the bottom, the first portion (171a) and the second portion extend according to a first height and a second height, respectively, and the first portion (171a) leads to a plane formed by the front face of the optoelectronic device, before step b) includes step b0): forming a passivation layer (120) by covering the front face, the side face (151c), and the bottom of the trench (170) according to a conformal deposition technique, and step c) further includes removing the passivation layer at the first portion (171a).

2. The method according to claim 1, wherein, the thickness E1 is at least 2 times greater than the thickness E2.

3. The method according to claim 1, wherein, step b0) is performed by atomic layer deposition.

4. The method according to claim 1, wherein, The passivation layer (120) comprises at least a material selected from the following: SiO 2 , Al 2 O 3 .

5. The method according to claim 1, wherein, the thickness of the passivation layer (120) is between 5 nm and 30 nm.

6. The method according to claim 1, wherein, the dielectric layer (130) is formed by plasma-activated chemical vapor deposition technique.

7. The method according to any one of claims 1 to 6, wherein, The dielectric layer (130) comprises at least one material selected from the following materials: SiO 2 , Si 3 N 4 .

8. The method according to claim 1, wherein, step a) includes transferring a stack of layers formed on a seed substrate onto the main surface (111a) of the support substrate (111).

9. The method according to claim 8, in, After transferring the stack of layers, the grooves (170) are formed extending over the entire thickness of the stack.

10. The method according to claim 9, in, The trench (170) is formed using a hard mask, which is removed before performing step b).

11. The method according to claim 1, in, The optoelectronic device is a light-emitting diode (172), which comprises, from the front side (151a) to the back side (151b), a first N-doped semiconductor layer (153), a light-emitting layer assembly (155), and a second P-doped semiconductor layer (157), wherein the first height is less than or equal to the thickness of the first N-doped semiconductor layer.

12. The method according to claim 11, in, The support substrate (111) comprises, on its main surface (111a), an integrated circuit intended to individually address each optoelectronic device of the plurality of optoelectronic devices.

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