Versatile level detector for SerDes

Abstract

Multifunctional level detector for SerDes. An illustrative receiver includes: a decision element that derives a symbol decision from a limiter input signal; an equalizer that converts a received signal into a limiter input signal; an adder that combines the symbol decision with the limiter input signal to produce an error signal; and a level detector that operates on the signal to determine a threshold at which each signal has a given probability of exceeding the threshold. An illustrative level detector circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or second gated output signal to indicate when an input signal exceeds a threshold or falls below a threshold and a programmable condition is satisfied. The asymmetric accumulator adapts the threshold using a rising step size for assertion of a first gated output signal and a falling step size for assertion of a second gated output signal, wherein the rising step size is different from the falling step size.

Description

Background Art

[0001] Digital communication occurs between a transmitting device and a receiving device through an intermediate communication medium or "channel" (e.g., a fiber optic cable or insulated copper wire). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects (possibly corrupted) symbol sequences and attempts to reconstruct the transmitted data. A "symbol" is a state or valid condition of a channel that lasts for a fixed period of time, which is called a "symbol interval." A symbol can be, for example, a voltage or current level, an optical power level, a phase value, or a specific frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol can represent (i.e., encode) one or more binary bits of data. Alternatively, data can be represented by symbol transitions, or by a sequence of two or more symbols.

[0002] Many digital communication links use only one bit per symbol; a binary "0" is represented by one symbol (e.g., an electrical voltage or current signal within a first range), and a binary "1" is represented by another symbol (e.g., an electrical voltage or current signal within a second range), but higher-order signal constellations are known and frequently used. In 4-level pulse amplitude modulation (PAM4), each symbol interval can carry any of four symbols labeled -3, -1, +1, and +3. Two binary bits can thus be represented by each symbol.

[0003] Channel imperfections create dispersion that can cause each symbol to interfere with its neighbors, a result known as inter-symbol interference (ISI). ISI can make it difficult for a receiving device to determine which symbols were sent in each interval, especially when such ISI is combined with additive noise.

[0004] To combat noise and ISI, receiving devices can use various equalization techniques. Linear equalizers usually have to balance between reducing ISI and avoiding noise amplification. Decision feedback equalizers (DFEs) are usually preferred because they can combat ISI without inherently amplifying noise. As the name implies, DFE uses a feedback path to remove the ISI effects of codewords derived from previous decisions. Other potential suitable equalization and demodulation techniques can be found in relevant academic literature, including, for example, peak detectors and partial response equalization. Most of these techniques use some form of channel characterization or receiver adaptation to enhance performance and stability for use under challenging conditions. Although desirable, the implementation of such features must strike a balance between complexity (area and power requirements) and benefits. There are many such implementations, but there is still a lot of room for improvement. Summary of the invention

[0005] Thus, a level detector is provided herein that has relatively low complexity while implementing multiple desired channel characterization and adaptation functions. An illustrative receiver embodiment includes: a decision element that derives a symbol decision from a limiter input signal; an equalizer that converts a received signal into a limiter input signal; an adder that combines the symbol decision with the limiter input signal to produce an error signal; and a level detector that operates on at least one of the received signal, the limiter input signal, and the error signal to determine a threshold at which the at least one signal has a given probability of exceeding the threshold.

[0006] An illustrative level detector circuit embodiment includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first gated output signal only when an input signal exceeds a threshold and satisfies a programmable condition, and asserts a second gated output signal only when the input signal falls below the threshold and satisfies the programmable condition. The asymmetric accumulator adapts the threshold using an increasing step size for assertion of the first gated output signal and a decreasing step size for assertion of the second gated output signal, wherein the increasing step size is different from the decreasing step size.

[0007] An illustrative level detector method includes asserting a first gated output signal only when an input signal exceeds a threshold and satisfies a programmable condition; asserting a second gated output signal only when the input signal falls below the threshold and satisfies the programmable condition; and adapting the threshold using a rising step size for assertion of the first gated output signal and a falling step size for assertion of the second gated output signal, wherein the rising step size is different from the falling step size

[0008] Each of the foregoing embodiments may be implemented individually or in combination, and may be implemented in any suitable combination with any one or more of the following optional features: 1. Each of the decision element, the equalizer, the adder, and the gated comparator component of the level detector is parallelized to provide concurrent processing paths. 2. The probability is subject to the satisfaction of a programmable condition. 3. The programmable condition includes one or more conditions from the list consisting of: the codeword decision has a given value at a selected offset from the current codeword interval, the codeword decision does not have a given value at a selected offset from the current codeword interval, the current codeword has a first specified value, the current codeword has a second specified value, and asserting one or more matching standard bypass signals. 4. The level detector is a dual level detector. 5. The gated comparator compares the input signal to multiple thresholds and conditionally asserts one of two corresponding gated output signals for each threshold, the two corresponding gated output signals indicating whether the input signal exceeds the threshold or falls below the threshold when the corresponding programmable condition is satisfied. 6. The gated comparator is one of a plurality of gated comparators operating in parallel on a parallel set of input signals, asserting a corresponding first gated output signal in the parallel set of first gated output signals only when the corresponding input signal exceeds a threshold and satisfies a programmable condition, and asserting a corresponding second gated output signal in the parallel set of second gated output signals only when the corresponding input signal falls below a threshold and satisfies a programmable condition. 7. A first adder that sums the parallel set of first gated output signals to provide a combined first gated output signal for an asymmetric accumulator; and a second adder that sums the parallel set of second gated output signals to provide a combined second gated output signal for an asymmetric accumulator. 8. The gated comparator includes match logic for verifying the programmable condition. 9. A shift register that provides at least a current symbol and a previous symbol to the gated comparator. 10. An input multiplexer providing as said input signal a selectable one of the following: a received signal, a limiter input signal and an error signal, said received signal, limiter input signal and error signal being provided by an equalizer of a communication receiver. 11. The equalizer is a decision feedback equalizer having at least one pre-calculation unit. 12. The input signal is compared to a plurality of thresholds and conditionally asserting one of a corresponding pair of gated output signals in said group for each threshold, thereby indicating whether the input signal exceeds or falls below the threshold if a corresponding programmable condition is satisfied. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a plan view of a wafer patterned with integrated circuit devices.

[0010] Figure 1B is a block diagram of an illustrative application specific integrated circuit.

[0011] Figure 2A An illustrative decision feedback equalizer (DFE) implementation is shown.

[0012] Figure 2B An illustrative DFE employing a single-tap pre-computation unit is shown.

[0013] Figure 3 An illustrative DFE with a fully expanded pre-computation unit is shown.

[0014] Figures 4A-4E Illustrative eye diagrams are shown with and without consideration of previous symbol decisions.

[0015] Figure 5 An illustrative parallel DFE with a multi-function level detector is shown.

[0016] Figure 6 is a logic diagram of an illustrative dual-level detector.

[0017] Figure 7 is a logic diagram of an illustrative dual-level detector in a parallel equalizer. DETAILED DESCRIPTION

[0018] Although specific embodiments are presented in the drawings and the following description, it should be kept in mind that they do not limit the present disclosure. Instead, they provide a basis for one of ordinary skill in the art to identify alternatives, equivalents, and modifications that are included within the scope of the appended claims.

[0019] Figure 1A A plan view of a semiconductor wafer 100 is shown which is patterned to form an array of integrated circuits 102 which may be segmented into IC chips and packaged as modular components for assembly in electronic devices. The IC chips may be packaged individually or combined into multi-chip modules using interposers and / or package substrates, in either case using a ball grid array or lead frame to provide external contacts for electrical connection with other circuit components, typically via a printed circuit board. Each IC chip may implement digital logic, analog functions, and / or mixed signal circuitry.

[0020] The patterning of wafers is performed by a semiconductor fabrication facility ("fab") using a series of cleaning, alignment, deposition, patterning, etching, implantation, and related processes. The "recipe" (sequence of pattern and process steps) employed determines the functionality of the resulting integrated circuit. The method to be used is specified by the electronic device designer, a customer of the fab or working for the company that owns the fab. As described in the background, the designer facilitates the design process by relying on modular layout design units to achieve the desired elements of the integrated circuit. These modular units may be predefined units obtained from an existing library or from a supplier that specializes in designing the desired type of element.

[0021] Figure 1B An illustrative high-speed serializer / deserializer ("SerDes") retimer chip 110 is shown, which serves as an example of an integrated circuit device here. The chip 110 includes: a SerDes module having contacts 111 for receiving and transmitting a high-speed serial bit stream on four lines in one direction; an additional SerDes module having contacts 112 for receiving and transmitting a high-speed serial bit stream on four lines in the other direction; and core logic 113 for implementing a channel communication protocol when buffering the bit stream between the two directions. Various support modules and contacts 114, 115 are also included, such as power regulation and distribution for control, clock generation, digital input / output lines, and a JTAG module for built-in self-test. A chip designer can design a device by placing predefined modular units of serializers, deserializers, power supplies, clock generators, I / O units, and JTAG, and using some support logic to route the interconnections between the modular units.

[0022] The "deserializer" implements the receive functionality of chip 110, implementing any suitable equalization technique, such as peak detection, linear equalization, partial response equalization, and decision feedback equalization (DFE). In many cases, DFE is preferred and will be used here to provide context for explaining the operation of the multi-function level detector disclosed herein. Regardless, the reader will recognize that the disclosed level detector is suitable for use with other equalizers, or more generally, with other wired or wireless digital signal receivers.

[0023] Figure 2AAn illustrative implementation of a DFE is shown. An analog or digital front-end filter 200 operates on a received signal to shape the overall channel response of the system and minimize the effects of pre-ISI on the current symbol. As part of the shaping of the overall channel response, the front-end filter 200 may alternatively be designed to shorten the channel response of the filtered signal while minimizing any accompanying noise enhancement. An adder 202 extracts a feedback signal from the output of the front-end filter 200 to minimize the effects of post-ISI on the current symbol.

[0024] The decision element 204 employs a set of comparators 206 to digitize the combined signal and produce an output data stream (denoted Ak, where k is a time index). In the example shown, the codewords are assumed to be PAM4 (-3, -1, +1, +3), so the comparators 206A-206C accordingly employ decision thresholds of -2, 0, and +2, respectively. (For generality, the units used to express the codewords and thresholds are omitted, but for purposes of explanation, several volts may be assumed) The comparator outputs may be collectively viewed as a thermometer-coded digital representation of the output codeword decisions, for example, where 000 represents -3, 100 represents -1, 110 represents +1, and 111 represents +3. A textbook embodiment employs a digitizer 208 to convert the comparator outputs into a binary digital representation, for example, where 00 represents -3, 01 represents -1, 10 represents +1, and 11 represents +3. Alternatively, a Gray coded representation may be employed. Here, the digitizer 208 is used only to represent the collected comparator outputs into a unified digital representation,

[0025] DFE uses a memory that stores recent output symbol decisions (A k-1 , A k-2 , …, A k-N A feedback filter 210 of a series of delay elements 212 (e.g., latches, flip-flops, or registers) with a plurality of filter coefficients Fi (N, where N is the number of filter coefficients Fi) generates a feedback signal. A multiplier bank 214 determines the product of each symbol with the corresponding filter coefficient, and a series of adders 216 combine the products to obtain the feedback signal.

[0026] Additionally, we note here that the circuitry of the front-end filter 200 and the feedback filter 210 can operate on analog signals, or conversely, can be implemented using digital circuit elements and / or software in a programmable processor. Further, the timing recovery unit and the filter coefficient adaptation unit enhance the operation of the DFE, but such considerations are dealt with in the literature and are well known to those skilled in the art. However, we note here that at least some contemplated embodiments include one or more additional comparators for comparing the combined signal to one or more of the extreme symbol values ​​(-3, +3) to provide an error signal that can be used for timing recovery with, for example, a "bang-bang" design. We further note that when a known symbol sequence is employed, the adaptation unit can use the error signal to adapt the coefficients of both the front-end filter 200 and the feedback filter 210 during a training phase.

[0027] exist Figure 2A In the embodiment of the present invention, the feedback filter 210 must complete its operation in less than one symbol interval, because the output of the feedback filter 210 depends in part on the immediately previous decision. At very high data rates, one symbol interval does not provide enough time to complete the filter multiplication and feedback subtraction. Accordingly, one solution that has been proposed in the literature is to "unroll" the feedback filter.

[0028] Figure 2B Shows the expansion of the feedback filter by one tap. Figure 2A descriptive changes. Figure 2B The embodiment of the present invention employs the same front-end filter 200, but the adder 202 subtracts the feedback signal to eliminate the subsequent ISI caused by all symbols except the immediately preceding symbol. For each possible value of the immediately preceding symbol, the pre-calculation unit 222 provides decision elements 224A-224D. Decision element 224A speculatively assumes that the previous symbol is -3, and instead of subtracting the ISI that would be caused by this symbol (-3*F1, where F1 is the coefficient of the first tap in the textbook feedback filter 210), the thresholds of comparators 226A-226C have been adjusted relative to the thresholds of comparators 206A-206C by adding -3*F1, thereby enabling decision element 224A to form a tentative symbol decision based on this speculative assumption.

[0029] Similarly, decision elements 224B, 224C, and 224D employ comparators with appropriately adjusted thresholds to make tentative decisions under the speculative assumption that the previous symbol was -1, +1, and +3, respectively. Pre-calculation unit 222 provides these tentative decisions to multiplexer 230, which is based on the decision A of the immediately previous symbol stored by delay element 232. k-1Feedback filter 234 has a reduced number of taps (filter coefficients), but otherwise operates similarly to feedback filter 210.

[0030] Although this unrolling step increases the number of elements in the DFE loop (i.e., in the loop including adder 202, pre-calculation unit 222, multiplexer 230, delay element 232, and feedback filter 234), only the elements of the inner loop (i.e., the loop including multiplexer 230 and delay element 232) need to achieve their operations in less than one symbol interval. The remaining DFE loop elements may take up to two symbol intervals to complete their pipeline operations. If completing the feedback filter operations in a timely manner remains a challenge, further unrolling may be performed.

[0031] like Figure 3 As shown, the disclosed principle can be extended to Figure 3 An illustrative variation is shown in which the 3-tap feedback filter has been fully expanded. This embodiment still employs the front-end filter 200, but because the feedback filter has been fully expanded, the adder 202 is removed. The functionality of the adder 202 has been completely replaced by a pre-calculation unit 302, which provides a separate decision element for each combination of three previous symbols. The digital converters 308A-308M provide a tentative decision 309 to a large multiplexer 310, which selects a tentative decision from the set based on the three previous symbol decisions maintained in the delay elements 312, 313, 314, thereby generating a symbol decision sequence Ak.

[0032] When the cardinality of the symbol set is P and the number of feedback filter parameters is N, the number of decision elements in the pre-calculation unit 302 is M=P N Therefore, for a PAM4 system with a 3-tap feedback filter (ie, P=4), the number of decision elements will be 4 3 =64. Because each decision element uses P-1 comparators, the pre-calculation unit uses L=(P-1)P N Comparators, or for the 3-tap PAM4 DFE example, 192 comparators. Therefore, with each increase in the length of the post-ISI and each increase in the cardinality of the symbol set, the size of the pre-computation unit grows exponentially, and the size of the multiplexer 310 also grows exponentially.

[0033] Figure 3DEF is enhanced using a multi-function level detector. The multi-function level detector shown is a dual level detector 320 having an input multiplexer ("mux") 322 and an output demultiplexer ("demux") 324. Based on a mode select signal, the input multiplexer 322 selects one of the multiple signals from different stages of the equalizer. Figure 3 In, signal is received signal, limiter input signal and error signal.Although signal can be digital or analog, they are assumed to be analog in this example.Therefore, received signal is the output of buffer or amplifier at receiver input, limiter input signal is the received signal modified by front-end filter 200 (and by the output (if present) of feedback filter), and error signal is the difference between limiter input signal and corresponding output symbol decision (in analog form).Adder 323 may include the appropriate delay of limiter input signal to ensure correctly determining error.

[0034] As will become clear, the level detector is an adaptive controller that uses an asymmetric step size to find a threshold at which the cumulative probability distribution function (CDF) of the selected signal reaches a given value. The dual-level detector allows two such thresholds to be determined simultaneously. The dual-level detector 320 operates on the selected signal using input parameters (step size, eye edge and / or ISI selection, accumulator initialization, and symbol decision) to measure the correspondingly adjusted signal level (as further described below). Among other things, the dual-level detector output can represent a received signal range, a selected eye opening size, or an error distribution measurement.

[0035] To determine the receive signal range, the mode select signal causes the multiplexer 322 to forward the receive signal to the dual level detector 320. The dual level detector is programmed to look for a first threshold at which the signal CDF is, for example, 1 / 1024 (meaning that the receive signal exhibits only about 0.098% probability of falling below the threshold) and a second threshold at which the signal CDF is, for example, 1023 / 1024 (meaning that the signal only exceeds the threshold about 0.098% of the time). These two thresholds then represent the signal range in which the signal can be found 99.8% of the time. The thresholds are forwarded by the demultiplexer 324 to appropriate registers and can be used by the receiver's controller (which can be integrated into the core logic 113) to perform adaptive gain control to allow optimal use of the dynamic range of the front end filter 200 (or the optional analog-to-digital converter).

[0036] To characterize the probability distribution function of the error signal, the mode select signal causes the multiplexer 322 to forward the error signal to the dual level detector 320. The level detector may be configured to determine the error signal at multiple CDF values ​​(e.g., 2 -2 , 2 -4, 2 -6 , 2 -8 , 2 -10 , 2 -12 ) at each of the thresholds, allowing the CDF and / or probability distribution function to be measured and extrapolated. The controller can use these measurements alone or in combination with the eye opening measurement to calculate an estimated symbol error rate or bit error rate.

[0037] Figure 4A An illustrative eye diagram of a PAM4 signal at the slicer input (input to comparators 306A-306L) is shown. The diagram shows the eye diagram of a PAM4 signal at the slicer input (input to comparators 306A-306L) from the previous sampling interval T i-1 To the current sampling interval T i The eye diagram reveals three eyes: the first eye E around the -2 decision threshold -2 , a second eye E0 around a 0 decision threshold, and a third eye E2 around a +2 decision threshold. The decision thresholds may be set or adapted to minimize the error rate (typically at a value coinciding with the center of the eye) to maximize immunity to additive noise. A larger eye provides a greater distance between the typical signal level and the decision threshold, thereby making the system more tolerant to noise and thereby providing a reduced error rate. Figure 4A The eye diagram of assumes that the previous symbol value is not taken into account, and thus represents the decision element 204 ( Figure 2A ). However, as the feedback filter expands, the decision element (e.g. Figure 2B For decision elements 224A-224D, the previous codeword is given as a corresponding one of -3, -1, +1, +3, resulting in Figure 4B-4E When conditioned on 4 possible previous symbols, the three eyes become 12 eyes E -2|-3 、E 0|-3 、E 2|-3 、E -2|-1 、E 0|-1 ,…,E 2|3 Typically, the received signal includes some non-linearity (and the digitization process and front-end filters may introduce further distortion) which causes the 4 eyes of each decision threshold to deviate slightly from each other, with the result that the decision threshold for each eye is preferably allowed to vary based on the previous symbol. This principle can be extended by further expanding the feedback filter, albeit usually with diminishing returns.

[0038] return Figure 3, the dual-level detector 320 accepts programmable eye edge selection, so that the controller of the receiver can measure the size of each eye by iterating the level detector 320 through the option. The mode selection signal causes the input multiplexer 322 to forward the limiter input signal to the dual-level detector (and causes the demultiplexer 324 to forward the threshold value determined adaptively by the detector to the register for storing eye opening information). For the selected eye edge, the level detector is operated to find the lower threshold (the limiter input only has a given possibility of falling below the threshold) or the upper threshold (the limiter input only has a given possibility of falling above the threshold). For example, if the previous codeword decision is not considered, there are three eyes. One of these eyes is around the +2 decision threshold, and the upper edge of the eye corresponds to the +3 codeword and the lower edge of the eye corresponds to the +1 codeword. The dual-level detector can be configured to determine that the lower threshold of the limiter input corresponds to the +3 codeword and the upper threshold of the limiter input corresponds to the +1 codeword. The decision threshold can then be set at the midpoint of these values ​​to minimize the error probability.

[0039] If the previous symbol decisions are taken into account, then as previously discussed, the number of eyes increases, but the measurement method remains essentially the same. As discussed further below, this principle can be extended to measure the impact of any arbitrarily specified previous symbol on a given eye, thereby generating a measure of residual intersymbol interference (ISI) from that previous symbol.

[0040] exist Figure 3 In a DFE, only one symbol decision is output per clock cycle. At particularly high data rates, it may be necessary or desirable to apply parallelization techniques to output multiple symbol decisions per clock cycle, as done in U.S. Pat. No. 9,071,479 (“High-speed parallel decision feedback equalizer”) and U.S. Pat. No. 9,935,800 (“Reduced complexity precomputation for decision feedback equalizer”), each of which is incorporated herein by reference in its entirety. Figure 5An illustrative parallel DFE embodiment with a parallelism of Q is shown. An analog receive signal is buffered by an adjustable gain amplifier 500. A set of sample and hold units 501-1 to 501-Q sequentially and periodically capture samples of the buffered analog signal, each sample and hold unit providing a stable output (in a time-interleaved manner) for up to Q clock cycles. A set of analog-to-digital converters 502-1 to 502-Q operate on the sample and hold outputs to obtain digitized values. A parallel front-end filter 503 combines the digitized values ​​to provide a parallel set of limiter input values ​​(i.e., these values ​​will be generated sequentially by the front-end filter 200). A set of pre-calculation units 504-1 to 504-Q operate on the parallel set of limiter inputs to generate Q sets of tentative decisions 309 in parallel. A parallel recursive selection multiplexer arrangement 506, such as disclosed in U.S. Patent 9,071,479 ("High-speed parallel decision feedback equalizer"), operates on Q sets of tentative decisions 309 to produce parallel sets of Q output symbol decisions.

[0041] In this example, dual level detector 520 operates on selected digital signal, and in addition, dual level detector 520 has been parallelized to operate on parallel selected digital signal group. Adder 523 represents parallel adder group, and each adder deducts output symbol judgment from each corresponding limiter input to provide parallel error signal group. Mode signal makes parallel input multiplexer group 522 forward parallel Q received signal group, parallel Q limiter input signal group or parallel Q error signal group. As further explained below, dual level detector 520 operates on parallel selected signal group to perform identical measurement as previously described.

[0042] Figure 6 shows that it is suitable for Figure 2A , Figure 2B or Figure 3 6. The illustrative dual-level detector embodiment is used in conjunction with a non-parallel equalizer embodiment such as a DFE of FIG. The illustrative dual-level detector includes a shift register 602, a gated dual comparator 604, and an asymmetric dual accumulator 606. The shift register 602 stores past symbol decisions for use by the gated dual comparator 604.

[0043] The gated dual comparator 604 includes a first comparator 608 and a second comparator 609. The first comparator 608 converts the selected input signal CMP 输入1 With the first threshold THD A The second comparator 609 compares the selected input signal CMP 输入1 With the second threshold THD BThe comparators each produce an output signal that asserts only when the input is greater than or equal to the threshold, and a complementary output signal that asserts only when the input is less than the threshold. These outputs are gated using some pattern matching logic, which includes first eye edge matching logic 610, second eye edge matching logic 611, and ISI matching logic 612. Gating is performed by gating logic 614.

[0044] The eye edge matching logic 610 accepts the current symbol decision and the previous symbol decision from the shift register and compares them with the first eye edge selection pattern EYE A (Although the symbols are treated as binary values ​​in the figures, in this example they are actually representations of PAM4 symbols.) If the current symbol decision is combined with the previous symbol decision and the selection mode EYE A The AND gate output is asserted if the AND gate output or the AE signal is asserted. The OR gate receives the AND gate output and the AE (“all eyes”) control signal and provides an asserted output if either the AND gate output or the AE signal is asserted. (Thus, when the AE signal is asserted, the eye edge pattern matching criteria is bypassed.) The eye edge matching logic 611 uses the second eye edge selection mode EYE B To operate similarly.

[0045] The ISI matching logic includes a multiplexer that forwards the codeword decision L codeword intervals before the current codeword decision based on the selection input L. (In some embodiments, L is allowed to be negative, allowing the effect of the later codeword decision to be measured on the "current" signal. Delay elements are used for the selected input signal to ensure that the later codeword decision is available in the shift register.) The selected previous codeword decision is compared with a given selection value ("ISI"). (Again, although the drawings show the codeword decisions as binary logic values, this example will use a digital representation of the PAM4 signal.) If the selected previous codeword matches the ISI value, the non-XOR gate asserts its output. An XOR gate is provided to invert the output of the non-XOR gate when the XI (inverted ISI) control signal is asserted. The OR gate asserts its output when the XOR gate output or the AI ​​("ISI") control signal is asserted. (Thus when the AI ​​control signal is asserted, the ISI matching criteria are bypassed.) The output of the ISI matching logic 612 is provided to AND gates in the first eye edge matching logic 610 and the second eye edge matching logic 611, thereby allowing those outputs to be adjusted based on whether the specified ISI matching conditions are met (or bypassed). These AND gates may alternatively be viewed as allowing the output of the ISI matching circuits to be adjusted based on whether the specified eye edge matching conditions are met (or bypassed). The outputs of the logic 610, 611 may be referred to herein as "pattern match signals".

[0046] The gating logic 614 includes a set of AND gates that operate on the comparator outputs. If the first specified eye edge and / or ISI pattern matches, the AND gates will pass the output signal from the first comparator 608. These gated outputs are designated as AP and AN. If the second specified eye edge and / or ISI pattern matches, the AND gates will pass the output signal from the second comparator 609. These gated outputs are designated as BP and BN.

[0047] The asymmetric double accumulator 606 generates a first threshold THD of the first comparator 608 in response to the gated output signals AP and AN. A , and generates a second threshold THD of the second comparator 609 in response to the gated output signals BP and BN B We begin with a discussion of the components that generate the first threshold THDA.

[0048] On each clock cycle, the multiplexer responds to the accumulator load signal LD ​​to provide the initial value ACC to the accumulator register D. A (when LD is asserted) or the output of the adder. The adder accepts feedback from the accumulator register, adds a scaled version of AP, and subtracts a scaled version of AN. The saturation latch SAT detects whether the accumulator register has reached a maximum or minimum value, and if so, the latch continues to provide that value to the adder thereafter, replacing the actual contents of the accumulator register. The latch is not reset until the accumulator is reinitialized (when LD is asserted).

[0049] Typically, the scaling factors for the AP and AN are different (“asymmetric”) so that when THD is exceeded A (subject to the specified pattern match condition), the accumulator register value is incremented by step size μ AP , and when the input value falls within the THD A Below (subject to the specified pattern match condition), the accumulator register value is decremented by a step size μ AN Since the accumulator register value determines the threshold THD via the feedback path A , so the probability that the threshold converges randomly to the signal exceeding the threshold is μ AN / (μ AP +μ AN ), and the probability that the signal falls below the threshold is μ AP / (μ AP +μ AN ). Under similar analysis, THD B Random convergence to signal exceeding THD B The probability is μ BN / (μ BP +μ BN ) value.

[0050] If the step size is chosen to be, for example, μ AP =2 -30 and μ AN =2 -20 , then the threshold will converge to a level below which the probability of the signal falling is about 2 -10 or 0.098%, so this threshold acts as a good indicator of the bottom of the signal range. A potential advantage of using a power of 2 as the selected step size is that the multiplier can be implemented as a simple left or right shift of bits in the binary representation. As another example, if it is desired to find a level that has a probability of being exceeded of about 10 -6 , the step size can be set to μ AP =2 -12 and μ AN =2 -32 In one contemplated embodiment of the dual-level detector, the step size is selected from a set of predetermined values: 2 -32 , 2 -30 , 2 -28 , 2 -26 , …, 2 -10 Although the main feature of interest for step sizes is their ratio, smaller step sizes may be preferred to reduce random variations in the threshold. On the other hand, smaller step sizes also extend convergence time, so if the communication baud rate is slow enough that convergence time becomes a concern, larger step sizes may be desirable (at least initially) to speed up convergence.

[0051] Once the threshold level has been determined by adaptation or calculation, a dual-level detector can be used to more accurately measure the signal probability associated with that threshold. To this end, the threshold THD A and THD B Both are set to the desired threshold level with adaptation disabled (e.g., by latching the threshold input to the comparator). The ISI and eye edge modes of both comparators are set to be the same. The accumulator registers are initially the same (e.g., zero), and the step size is, for example, μ AP =2 -32 , μ AN =0, μ BP =0 and μ BN =2 -32 , so that an accumulator register (ACC A ) tracks the number of times the threshold is exceeded, and another accumulator register (ACC B ) tracks the number of times the signal falls below the threshold. The probability of exceeding the threshold is ACC A / (ACC A +ACC B ) and the probability of falling below the threshold is ACC B / (ACC A +ACC B ). Accuracy increases with longer accumulation times, subject to the saturation limit of the accumulation register.

[0052] Thus, the dual-level detector can determine the upper and lower limits of the range of the selected signal, condition the measurements with specified conditions (if desired) based on the current symbol decision, the previous symbol decision, and / or the selected ISI symbol that may be a selected amount before or after the current symbol interval. When the selected signal is a received signal, the dual-level detector measurements can be used to measure the dynamic range of the signal and adapt the gain control responsively. These measurements can be used for channel characterization, particularly when symbol decision conditioning is employed (e.g., to estimate channel loss for high frequency signal modes and low frequency signal modes).

[0053] When the selected signal is a slicer input signal, the dual-level detector measurement results can be used to measure the eye contour and adapt the threshold level responsively. The measurement results can be used to characterize the residual ISI, which potentially allows improved channel characterization. When the equalizer is provided with floating taps, the residual ISI measurement results are useful for allocating floating taps. When the selected signal is an error signal, the dual-level detector measurement results can be used for bit error rate estimation or symbol error rate estimation or more general characterization of system and receiver performance.

[0054] Figure 7 Shown is applicable to Figure 5 A parallel version of the dual-level detector is used in the parallel DFE embodiment of FIG. Figure 6 The embodiment of the present invention operates in a similar manner, but uses a plurality of gated dual comparators 604-1 to 604-Q, each gated dual comparator responding to a selected parallel input signal group CMP 输入1 To CMP 输入Q When coupled to the shift register 602, the various comparators 604-1 to 604-Q also shift according to what they consider to be the "current" symbol decision. Otherwise, the various inputs (THD A 、THD B 、L、EYE A 、EYE B , ISI, XI, AE, AI) are the same.

[0055] A set of adders 702 sum the gated outputs of the gated dual comparators to provide combined gated outputs ΣAP, ΣAN, ΣBP, ΣBN to the asymmetric dual accumulator 606. As previously described, the asymmetric dual accumulator operates on the combined gated outputs.

[0056] Once the above disclosure is fully understood, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, a DFE is used to provide context for the disclosed level detector, but the level detector is equally applicable to other types of equalizers including linear equalizers, partial response equalizers, and peak detectors. The disclosed level detector is a dual-level detector, but those skilled in the art will recognize that single-level detectors and other multi-level detector embodiments are easily derived from the example embodiments disclosed herein. The pattern matching employed by the disclosed level detector is easily modified to provide longer or shorter pattern matching criteria or different pattern matching criteria. It is intended that the claims be interpreted as covering all such alternatives, equivalents, and modifications contained within the scope of the appended claims.

Claims

1. A level detector circuit comprising: a gated comparator, the gated comparator asserting a first gated output signal only when the input signal exceeds a threshold and satisfies a programmable condition, and the gated comparator asserting a second gated output signal only when the input signal falls below the threshold and satisfies the programmable condition; as well as an asymmetric accumulator that adapts the threshold using a rising step size for assertion of the first gated output signal and a falling step size for assertion of the second gated output signal, the rising step size having a rising step size, the falling step size having a falling step size, and the rising step size being different from the falling step size.

2. The level detector circuit as claimed in claim 1, characterized in that The gated comparator compares an input signal to a plurality of thresholds and conditionally asserts, for each threshold, one of two respective gated output signals indicating whether the input signal exceeds or falls below the threshold if respective programmable conditions are met.

3. The level detector circuit according to claim 1, characterized in that The gated comparator is one of a plurality of gated comparators operating in parallel on a parallel set of input signals, thereby asserting a corresponding first gated output signal in a parallel set of first gated output signals only when a corresponding input signal of the gated comparator exceeds the threshold and satisfies the programmable condition, and asserting a corresponding second gated output signal in a parallel set of second gated output signals only when a corresponding input signal of the gated comparator falls below the threshold and satisfies the programmable condition.

4. The level detector circuit of claim 3, further comprising: a first adder that sums the parallel set of first gated output signals to provide a combined first gated output signal to the asymmetric accumulator; and a second adder that sums the parallel set of second gated output signals to provide a combined second gated output signal to the asymmetric accumulator.

5. The level detector circuit as claimed in claim 1, characterized in that The gated comparator includes match logic for verifying the programmable conditions, the programmable conditions including one or more conditions from the list consisting of: The symbol decision has a given value at a selected offset from the current symbol interval, The symbol decision does not have a given value at a selected offset from the current symbol interval, The current symbol has a first specified value, The previous symbol has a second specified value, and Assert one or more match criteria bypass signals.

6. The level detector circuit of claim 5, further comprising a shift register, the shift register providing at least the current symbol and the previous symbol to the gated comparator.

7. The level detector circuit of claim 1 , further comprising an input multiplexer, the input multiplexer providing an optional one of the following as the input signal: a received signal, a limiter input signal, and an error signal, the received signal, the limiter input signal, and the error signal being provided by an equalizer of a communication receiver.

8. The level detector circuit as claimed in claim 7, characterized in that The equalizer is a decision feedback equalizer having at least one pre-calculation unit.

9. A level detector method comprising: asserting a first gated output signal only when the input signal exceeds a threshold and satisfies a programmable condition; asserting a second gated output signal only when the input signal falls below the threshold and satisfies the programmable condition; as well as The threshold is adapted using a rising step size for assertion of the first gated output signal and a falling step size for assertion of the second gated output signal, the rising step size having a rising step size, the falling step size having a falling step size, and the rising step size being different from the falling step size.

10. The level detector method according to claim 9, characterized in that The first and second gated output signals are one pair in a set of gated output signal pairs, and wherein the method comprises comparing the input signal to a plurality of thresholds and conditionally asserting one of a corresponding pair of gated output signals in the set for each threshold, thereby indicating whether the input signal exceeds or falls below the threshold if a corresponding programmable condition is satisfied.

11. The level detector method of claim 9, wherein: The input signals are in a group of input signals that are processed in parallel such that a corresponding first gated output signal in a parallel group of first gated output signals is asserted only when the corresponding input signal exceeds the threshold and satisfies the programmable condition, and a corresponding second gated output signal in a parallel group of second gated output signals is asserted only when the corresponding input signal falls below the threshold and satisfies the programmable condition.

12. The level detector method of claim 11, further comprising: summing the parallel set of first gated output signals to provide a combined first gated output signal; and summing the parallel set of second gated output signals to provide a combined second gated output signal.

13. The level detector method of claim 9, wherein: Asserting the first or second gated output signal comprises testing the programmable condition, wherein the programmable condition comprises one or more conditions from the list consisting of: The symbol decision has a given value at a selected offset from the current symbol interval, The symbol decision does not have a given value at a selected offset from the current symbol interval, The current symbol has a first specified value, The previous symbol has a second specified value, and Assert one or more match criteria bypass signals.

14. The level detector method of claim 13, further comprising storing at least the current symbol and the previous symbol in a shift register.

15. The level detector method of claim 9, further comprising providing an optional one of the following as the input signal: a received signal, a limiter input signal, and an error signal, the received signal, the limiter input signal, and the error signal being provided by an equalizer of a communication receiver.

16. A receiver comprising: a decision element deriving a symbol decision from the slicer input signal; an equalizer, the equalizer converting a received signal into the limiter input signal; an adder that combines the symbol decisions with the slicer input signal to produce an error signal; as well as A level detector operates on at least one of the received signal, the slicer input signal, and the error signal to determine a threshold at which the at least one signal has a given probability of exceeding the threshold.

17. The receiver according to claim 16, characterized in that Each of the decision element, the equalizer, the adder, and the gated comparator components of the level detector are parallelized to provide concurrent processing paths.

18. The receiver according to claim 16, characterized in that The probability is subject to satisfaction of programmable conditions.

19. The receiver according to claim 18, characterized in that The programmable conditions include one or more conditions from the list consisting of: The symbol decision has a given value at a selected offset from the current symbol interval, The symbol decision does not have a given value at a selected offset from the current symbol interval, The current symbol has a first specified value, The current symbol has a second specified value, and Assert one or more match criteria bypass signals.

20. The receiver of claim 16, wherein: The level detector is a dual-level detector.

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