A self-aligned patterning method for source / drain contact metals

Abstract

The present invention discloses a self-aligned patterning method for source-drain contact metals of a doped-free thin-film transistor. In this method, a source-drain contact metal layer is deposited on a conventional gate structure formed on a substrate, and then an interlayer dielectric layer is deposited thereon, and the interlayer dielectric layer is planarized with the contact metal layer as a stop layer. Subsequently, the interlayer dielectric layer is thinned by a re-etching technique, and the interlayer dielectric layer is retained above the contact region, exposing the outer wall of the gate sidewall and the main gate electrode metal layer on the top of the gate outside the contact region. Windows are opened to define the total pattern sizes of the source-drain regions and the gate, and the remaining interlayer dielectric layer is etched away, and this is used as a self-aligned mask to etch away the exposed metal layer. This method realizes the etching away of the redundant metals on the sidewalls and the top of the gate while protecting the source-drain regions.

Description

Technical Field

[0001] The present invention relates to a carbon nanotube CMOS integrated circuit process, and particularly to a self-aligned patterning technique for source-drain contact metals of undoped thin film transistors. Background Art

[0002] As the integrated circuit technology node reaches 16 nm after two generations downwards, it will reach the limit of silicon materials and physical quantum mechanics. For the continuous development of electronics, it is urgent to find new advantageous materials to replace silicon materials and break through the limit of Moore's Law. Carbon nanotubes (CNTs) have extremely high carrier mobility and mean free path, and a nanoscale tube diameter, and can be used to construct nanoscale field effect transistors with faster speed, lower power consumption, and smaller size. Therefore, carbon nanotube (CNTs) electronics is considered to be one of the future information technologies most likely to replace silicon-based CMOS devices and continue Moore's Law. According to relevant research, although the performance of carbon nanotube hole-type devices is far superior to that of silicon-based devices of the corresponding scale, the performance of electron-type devices prepared by chemical doping methods is far inferior to that of silicon-based devices, and the mainstream semiconductor CMOS technology cannot be realized through carbon nanotube materials.

[0003] By controlling the source-drain contact metal materials scandium (Sc) or palladium (Pd), electrons or holes can be selectively injected into the carbon nanotubes, and high-performance n-type and p-type carbon nanotube field effect transistors can be effectively regulated and fabricated. Specifically, using Pd as the source-drain contact can form a high-performance P-type carbon nanotube FET, and using Sc or Y as the source-drain contact can form a high-performance N-type carbon nanotube FET, thereby realizing the control of the transistor polarity. The entire manufacturing process does not require any doping. Therefore, it is called the "doping free" carbon nanotube CMOS process. This manufacturing method of "doping free" carbon nanotube CMOS devices is different from the current mainstream silicon-based integrated circuits and does not introduce an ion implantation process. When Pd electrodes and Sc electrodes are sputtered on the same carbon nanotube respectively, the device between two Pd electrodes is P-type, and the device between two Sc electrodes is N-type. This method can directly realize the regulation of the transistor device type, greatly saving the process steps and reducing the production cost.

[0004] Currently, the fabrication of carbon nanotube undoped high-performance and perfectly symmetric CMOS circuits has been achieved in the laboratory, and all the circuits required for a nano calculator have been designed and implemented using transfer transistor logic with higher logic efficiency than CMOS. Despite having quite a number of technical advantages, during the formation of the source-drain contact metal in carbon nanotubes, a layer of metal will also be sputtered on the sidewall surface. Different from silicon-based integrated circuits, the metal in the source-drain contact region cannot form an alloy such as silicide with the underlying carbon nanotubes, making it exhibit characteristics similar to the metal on the sidewall surface and unable to remove the metal on the sidewall through a simple cleaning process like silicon-based devices can.

[0005] Therefore, how to solve this problem through an efficient method has become a major obstacle restricting the fabrication of carbon nanotube device integrated circuits. Summary of the Invention

[0006] The object of the present invention is to provide a self-aligned patterning technique for the source-drain contact metal of an undoped thin-film transistor, so as to be able to etch away the excess metal on the sidewall and the top of the gate while protecting the source-drain region.

[0007] According to one aspect of the present invention, a self-aligned patterning method for the source-drain contact metal of an undoped thin-film transistor is proposed, including the following steps:

[0008] S1: Deposit a semiconductor layer on a substrate, and form a gate structure including a gate dielectric layer, a gate electrode, sidewalls, and a main gate electrode on the semiconductor layer;

[0009] S2: Deposit a metal thin film on the above gate structure as the source-drain contact metal layer of the thin-film transistor, leaving a certain thickness of the metal thin film on both the sidewalls and the main gate electrode;

[0010] S3: Deposit an interlayer dielectric layer on the source-drain contact metal layer;

[0011] S4: Use chemical mechanical polishing to planarize the interlayer dielectric layer with the source-drain contact metal layer as the stop layer;

[0012] S5: Use a re-etching technique to thin the interlayer dielectric layer, retain the interlayer dielectric layer above the contact region, and expose the outer wall of the gate sidewall and the main gate electrode metal layer outside the contact region;

[0013] S6: Use a photoresist as a mask, open windows to define the total dimensions of the source-drain region and the gate pattern, and etch away the remaining interlayer dielectric layer;

[0014] S7: Use the remaining interlayer dielectric layer as a mask to etch away the exposed metal layer, and the retained interlayer dielectric layer serves as a self-aligned mask to protect the contact region from being etched.

[0015] Preferably, the semiconductor layer is a carbon nanotube thin film, strained silicon or germanium, quantum well, group III-V compound semiconductor, graphene, two-dimensional material such as molybdenum disulfide, black phosphorus.

[0016] Preferably, the source-drain contact metal layer is selected from metals such as palladium, scandium, nickel-platinum alloy, titanium, titanium-palladium, cobalt, yttrium, aluminum or a stack of multiple metals.

[0017] Preferably, the gate structure may be a dummy gate structure including a gate dielectric, polysilicon dummy gate or amorphous silicon dummy gate, and sidewalls.

[0018] Preferably, the metal thin film is deposited by magnetron sputtering in step S2.

[0019] Preferably, in step S3, silicon oxide is deposited by PECVD or an insulating dielectric SOD is spin-coated to form.

[0020] Preferably, the thickness of the interlayer dielectric layer retained above the contact region in step S5 is 10-20 nanometers.

[0021] Preferably, the gate dielectric is selected from hard materials such as silicon oxide, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide or lanthanum aluminate, silicon nitride, or organic polymer insulating layers such as epoxy resin, PMMA, and the thickness ranges from 2 to 100 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] By describing the embodiments of the present invention with reference to the following drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0023] Figure 1 Shows a flowchart of the source-drain contact self-alignment process of the present invention;

[0024] Figure 2 Shows the formation of a gate and sidewalls on a substrate;

[0025] Figure 3 Shows the deposition of a source-drain contact metal film;

[0026] Figure 4 Shows the formation of an SOD dielectric layer;

[0027] Figure 5 Shows the CMP planarization of the dielectric layer;

[0028] Figure 6 Shows the etch-back of the dielectric layer to the contact layer;

[0029] Figure 7 Shows the etching of the remaining dielectric layer using a photoresist mask;

[0030] Figure 8Illustrates etching the semiconductor layer using the remaining dielectric layer as a mask;

[0031] Figure 9 Illustrates etching the exposed contact metal film using the remaining dielectric layer as a self-aligned mask; Detailed implementation manners

[0032] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals, and the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, a semiconductor structure obtained after several steps may be described in one figure.

[0033] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or region will be "below" or "beneath" the other layer or region.

[0034] If it is to describe the case of being directly above another layer or another region, the expressions "A is directly above B" or "A is above B and adjacent thereto" will be used herein. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0035] Figure 1 Illustrates the process steps of the source-drain contact self-alignment process of the undoped thin-film transistor proposed by the present invention. Below, according to Figure 1 the steps shown and Figures 2 - 9 the specific embodiments of the present invention will be described in detail.

[0036] According to step S1, as Figure 2 shown, a semiconductor layer 102 is deposited on a substrate 101, and a conventional gate structure is formed on the semiconductor layer 102. The gate structure includes a gate dielectric layer 103, a gate electrode 104, sidewalls 105, and a main gate electrode 106. The gate electrode 104 can be polysilicon or metal.

[0037] The substrate 101 mainly serves as a support and can be a hard insulating material such as silicon, silicon oxide, silicon nitride, quartz, glass, alumina, etc., as well as a high-temperature resistant flexible insulating material such as PET, PEN, polyimide, etc., as long as it is very flat and has good uniformity. In this embodiment, a silicon oxide material is used as the substrate, which is not particularly limited. In another embodiment, grooves can be formed on the substrate 101, and then the semiconductor layer 102 is deposited in the grooves, rather than simply depositing the semiconductor layer on a plane.

[0038] In this embodiment, the semiconductor layer 102 is made of a carbon nanotube thin film. A carbon nanotube thin film with a semiconductor ratio of 90%-99.9999% can be preferably used, including a carbon nanotube array thin film with neatly arranged parallel carbon nanotubes, a self-assembled carbon nanotube thin film, a carbon nanotube network array, and a carbon nanotube composite thin film formed by any combination of the above multiple methods. In addition, the semiconductor layer 102 can also be strained silicon or germanium, a quantum well, a III-V material, a two-dimensional material such as graphene, molybdenum disulfide, black phosphorus, etc.

[0039] The above gate structure includes a gate dielectric layer 103, a gate electrode 104, and a main gate electrode 106. The gate dielectric layer 103 can be a traditional gate oxide layer such as silicon oxide or silicon oxynitride, or a high-K material such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, aluminum oxide, lanthanum oxide, or lanthanum aluminate, etc., with a thickness in the range of 1-10 nm. The gate dielectric used in this embodiment is hafnium oxide. The material of the main gate electrode 106 can be various metals such as Pd, Pt, Ti, Cu, Al, W, etc., a conductive metal silicide, a doped polysilicon and other conductive materials, as well as a stacked structure of the above conductive materials, or a high-density carbon nanotube conductive film (transparent electrode), with a thickness range of 20-100 nm. In this embodiment, the main gate electrode is selected to be Pd with a thickness of 30 nm.

[0040] The above gate structure is formed by the front-gate process or can be a dummy gate structure (not shown) formed by the back-gate process. The dummy gate structure includes a gate dielectric, a polysilicon dummy gate or an amorphous silicon dummy gate, and sidewalls.

[0041] Further according to step S2, as Figure 3 shown, a metal thin film is deposited on the above gate structure by magnetron sputtering as the source-drain contact metal layer 107 of the transistor. The sputtering process leaves a certain thickness of the metal thin film on both the gate sidewalls and the gate top.

[0042] The source-drain contact metal layer 107 can be a metal such as palladium, platinum, scandium, nickel-platinum alloy, titanium, titanium-palladium, cobalt, yttrium, aluminum, etc., or a conductive material such as a conductive metal silicide, doped polysilicon, etc., as well as a stacked structure of the above conductive materials, or a high-density carbon nanotube conductive film (transparent electrode), with a thickness range of 20-100 nm. In this embodiment, a platinum / palladium composite layer with a thickness of 30 / 2 nm is used. Further according to step S3, as Figure 4 shown, an interlayer dielectric layer (ILD) 108 is deposited on the source-drain contact metal layer 107, which can be formed by depositing silicon oxide by PECVD or spin-coating an insulating dielectric SOD.

[0043] The interlayer dielectric (ILD) material can be doped or undoped silicon oxide, low-k materials including but not limited to organic low-k materials (such as organic polymers containing aryl or polycyclic rings), inorganic low-k materials, such as amorphous carbon nitride thin films, polycrystalline boron nitride thin films, fluorosilicate glass, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), porous low-k materials (such as disiloxane (SSQ)-based porous low-k materials, porous silicon dioxide, porous SiOCH, carbon-doped silicon dioxide, fluorine-doped porous amorphous carbon, porous diamond, porous organic polymers). In this embodiment, the interlayer dielectric (ILD) is formed by depositing silicon oxide using PECVD.

[0044] Further according to step S4, as Figure 5 shown, chemical mechanical polishing (CMP) is used with the source-drain contact metal layer 107 as the stop layer to planarize the interlayer dielectric (ILD) 108. Further according to step S5, as Figure 5 shown, an etch-back technique is used to thin the interlayer dielectric (ILD) 108, leaving a 10 - 20 nanometer thick dielectric layer above the contact area, exposing the outer wall of the gate sidewall and the main gate electrode metal layer on the top of the gate outside the contact area. Further according to step S6, as Figure 7 shown, a photoresist 109 is used as a mask to open windows to define the total pattern size of the source-drain region and the gate, and the remaining dielectric layer is etched away. Then according to step S7, the exposed metal layer is etched away, and the remaining interlayer dielectric layer 108 serves as a self-aligned mask to protect the contact area from being etched.

[0045] Although the present invention has been described in detail above with general descriptions and specific embodiments, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of the present invention claimed.

Claims

1. A self-aligned patterning method for source-drain contact metals of a doped-free thin film transistor, characterized in that Including the following steps: S1: Deposit a semiconductor layer (102) on a substrate (101), and form a gate structure including a gate dielectric layer (103), a gate electrode (104), sidewalls (105), and a main gate electrode (106) on the semiconductor layer (102); S2: Deposit a metal thin film as a source-drain contact metal layer (107) of the thin-film transistor on the above gate structure, and leave a certain thickness of the metal thin film on both the sidewalls (105) and the main gate electrode (106); S3: Deposit an interlayer dielectric layer (108) on the source-drain contact metal layer (107); S4: Use chemical mechanical polishing to planarize the interlayer dielectric layer (108) with the source-drain contact metal layer (107) as the stop layer; S5: Use an etch-back technique to thin the interlayer dielectric layer (108), retain the interlayer dielectric layer (108) above the contact area, and expose the outer walls of the gate sidewalls and the main gate electrode metal layer on the top of the gate outside the contact area; S6: Use a photoresist as a mask, open a window to define the total pattern dimensions of the source-drain region and the gate, and etch away the remaining interlayer dielectric layer (108); S7: Use the remaining interlayer dielectric layer (108) as a mask to etch away the exposed metal layer, and the retained interlayer dielectric layer (108) serves as a self-aligned mask to protect the contact area from being etched.

2. The self-aligned patterning method of the source-drain contact metal of the undoped thin film transistor according to claim 1, wherein The semiconductor layer (102) is a carbon nanotube thin film, strained silicon or germanium, a III-V compound semiconductor, graphene, molybdenum disulfide, or black phosphorus.

3. The self-aligned patterning method of the source-drain contact metal of the undoped thin film transistor according to claim 1, wherein The source-drain contact metal layer (107) is selected from palladium, scandium, nickel-platinum alloy, titanium, titanium-palladium, cobalt, yttrium, aluminum, or a stack of multiple of the above metals.

4. The self-aligned patterning method of the source-drain contact metal of the undoped thin film transistor according to claim 1, characterized in that, Wherein the gate structure is a dummy gate structure including a gate dielectric, a polysilicon dummy gate or an amorphous silicon dummy gate, and sidewalls.

5. The self-aligned patterning method of the source-drain contact metal of the undoped thin-film transistor according to claim 1, characterized in that In step S2, the metal thin film is deposited by magnetron sputtering.

6. The self-aligned patterning method of the source / drain contact metal of the undoped thin film transistor according to claim 1, wherein In step S3, silicon oxide is deposited by PECVD or a spin-coated insulating medium SOD is formed.

7. The self-aligned patterning method of the source-drain contact metal of the undoped thin film transistor according to claim 1, wherein In step S5, the thickness of the retained interlayer dielectric layer (108) above the contact area is 10 - 20 nanometers.

8. The self-aligned patterning method of the source / drain contact metal of the undoped thin film transistor according to claim 1, wherein The gate dielectric layer (103) is selected from silicon oxide, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, lanthanum aluminate, silicon nitride, epoxy resin, PMMA, and the thickness range is 2 - 100 nm.

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