Gate driver with integrated Miller clamp

Abstract

This application discloses a high-power drive device with an integrated Miller clamp gate driver coupled to a terminal of a package housing an integrated circuit coupled to the terminal. A method includes generating an indication of a signal level at the terminal relative to a predetermined signal level. The method also includes configuring a variable-strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

Description

Technical Field

[0001] The present invention relates to circuits and, more particularly, to control circuits for high power applications. Background Art

[0002] In a typical control application, a processor system provides one or more control signals to control a load system. During normal operation, large DC or transient voltage differences may exist between the processor system's domain and the load system's domain, necessitating an isolation barrier between the processor system and the load system. For example, one domain may be "grounded" with a voltage that switches hundreds or thousands of volts relative to ground. Therefore, intermediate systems include isolation circuitry to prevent damaging currents from flowing between the processor system and the load system. While this isolation prevents the processor system from coupling to the load system via a direct conductive path, isolated communication channels also enable communication between the two systems using optical (opto-isolators), capacitive (capacitive), inductive (transformers), or electromagnetic (EM) techniques. In at least one embodiment, the isolated communication channel blocks DC signals and only passes AC signals. Intermediate systems typically use voltage converters and output drivers to provide control signals at voltage levels appropriate for the load system.

[0003] like Figure 1 As shown, in an exemplary motor control application, a processor 100, which can be a microprocessor, microcontroller, or other suitable processing device, operates within a first domain (i.e., VDD1, e.g., 5 volts (V)) and provides one or more signals to a high-power load system within a second domain (i.e., VDD3, e.g., 600 V). Each system 102 includes an isolation barrier 130 and an isolated communication channel for safely transmitting control signals from the processor 100 to a driver 106, which drives a high-power drive device 108 and a high-power drive device 109 of a three-phase inverter for transmitting three-phase power to a motor 120. Exemplary high-power drive devices include power metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), gallium nitride (GaN) MOSFETs, silicon carbide power MOSFETs, or other suitable devices capable of providing high current for short periods of time.

[0004] Voltage converter 104 converts the available power supply voltage from VDD3 to a voltage level usable by the high-side of system 102 and driver 106 (i.e., VDD2, e.g., approximately 15V). Note that in other embodiments, a single voltage converter 104 converts a power supply voltage from a first voltage level (e.g., VDD3) to multiple other voltage levels (e.g., VDD1 and VDD2) and / or provides multiple outputs of a particular voltage (e.g., multiple VDD2 outputs corresponding to multiple systems 102). Driver 106 provides switching control signals at the levels required by the corresponding high-power drive device 108 or high-power drive device 109 of the three-phase inverter. The load motor requires a three-phase power supply at high power levels. System 102, corresponding to the high-power device (high-side inverter device) coupled to VDD3, is "grounded" at a high voltage level of voltage VDD3, which is switched relative to ground. The high-power drive devices 108 and 109 of the three-phase inverter typically used to drive the motor 120 require a relatively large turn-on voltage (e.g., in the range of tens of volts) and are susceptible to fault conditions that can damage these devices. Therefore, some flexible technical solutions are needed to handle fault conditions without damaging the high-power drive devices or the loads of these devices. Summary of the Invention

[0005] In at least one embodiment, the present invention discloses a method for controlling a high-power driver device coupled to a terminal of a package housing a driver integrated circuit coupled to the terminal. The method includes generating an indication of a signal level at the terminal relative to a predetermined signal level. The method also includes configuring a variable strength driver of the driver integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

[0006] In at least one embodiment, the present invention discloses a driver circuit for controlling a high-power drive device external to a package of the driver circuit. The driver circuit includes an output node and a variable-strength driver circuit coupled to the output node. The driver circuit includes a feedback circuit configured to generate a feedback signal based on a predetermined signal level and a signal level at the output node. The driver circuit includes a driver controller circuit that, in response to a received control signal and a feedback signal, configures the variable-strength driver circuit to charge, discharge, or clamp the output node based on the received control signal and the feedback signal.

[0007] In at least one embodiment, the present invention discloses a method for controlling a high-power driver device located external to a driver circuit package, the method comprising: configuring a variable-strength driver circuit as an output driver circuit in response to a voltage at a terminal of the package being greater than a predetermined voltage level. The output driver circuit is responsive to a received control signal. In response to the signal at the terminal being less than the predetermined voltage level, configuring the variable-strength driver circuit as a Miller clamp circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention may be better understood and its numerous objects, features and advantages may be readily appreciated by those skilled in the art with reference to the accompanying drawings.

[0009] Figure 1 This is the functional block diagram of a typical motor control system.

[0010] Figure 2 for Figure 1 A functional block diagram of a portion of a motor control system including a fault detection circuit and a driver control circuit.

[0011] Figure 3 for Figure 2 Functional block diagram of a part of the driver control circuit.

[0012] Figure 4 is a functional block diagram of a portion of a packaged driver integrated circuit product including a gate driver circuit with an integrated Miller clamp in accordance with at least one embodiment of the present invention.

[0013] Figure 5 A functional block diagram of a portion of a packaged driver integrated circuit product is shown, which includes an exemplary variable strength driver circuit configured as part of a gate driver with an integrated Miller clamp in accordance with at least one embodiment of the present invention.

[0014] The use of the same reference numbers in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0015] like Figure 2As shown, in an exemplary motor control application, processor 100 receives a voltage (i.e., VDD1, e.g., 5V) and provides one or more signals to a high-power load system operating in a second domain (i.e., VDD3, e.g., several hundred volts). Driver product 200 includes an isolation barrier 230 and a communication channel for safely transmitting control signals from processor 100 across isolation barrier 230 to drive a high-power drive device, a three-phase inverter, that delivers three-phase power to motor 120. In one exemplary embodiment, driver product 200 includes multiple integrated circuits configured as a multi-chip module in a single package. For example, driver product 200 includes a primary-side integrated circuit 201 and a secondary-side integrated circuit 203. Primary-side integrated circuit 201 receives control signals from processor 100 and transmits the signals across isolation barrier 230 to secondary-side integrated circuit 203. In such an embodiment, terminals 250 , 252 , 254 , . . . , 270 are package pins of the multi-chip module, and these terminals are coupled to external components such as discrete resistors and discrete capacitors and to processor 100 .

[0016] Driver product 200 includes an isolation barrier 230 that isolates a domain on a first side of driver product 200 (e.g., primary-side integrated circuit 201) that can operate with VDD1 (e.g., a voltage less than ten volts), and isolates a domain on a second side of driver product 200 (e.g., secondary-side integrated circuit 203) that can operate with VDD2 (e.g., a voltage of tens of volts). An isolated communication channel facilitates communication between primary-side integrated circuit 201 and secondary-side integrated circuit 203. Any suitable communication technology that does not utilize a conductive path between the two sides, such as optical, capacitive, inductive, or electromagnetic technologies, may be used. The isolated communication channel facilitates the transmission of control signals from processor 100 to secondary-side integrated circuit 203 via primary-side integrated circuit 201.

[0017] Although other communication protocols may be used, the exemplary isolated communication channel uses digital modulation (e.g., on-off keying modulation) to communicate between the primary side integrated circuit 201 and the secondary side integrated circuit 203 using one or more digital signals. Typically, on-off keying modulation is a form of amplitude shift keying modulation, where the amplitude shift keying modulation uses digital data to represent the presence or absence of a carrier frequency f. cA carrier or oscillating signal (e.g., 500MHz-1GHz). The presence of the carrier for a specified duration is represented by a binary one, while the absence of the carrier for the same duration is represented by a binary zero. Since the signal transmitted in the logical "0" state is the same as the signal transmitted when the primary side is powered off and the device gracefully adopts its default state, this type of signal transmission is robust for isolated applications. This behavior is beneficial in drive applications because the load device being driven will not be accidentally turned on even if the primary side is powered off. However, other types of signals (e.g., pulse width modulated signals or other types of amplitude shift keying modulated signals) can also be used for the isolated communication channel. The digital modulation scheme used can be determined based on the performance specifications of the target application (e.g., signal resolution) and the environment (e.g., the probability of transient events).

[0018] The secondary-side integrated circuit 203 includes a driver 221 that generates one or more output control signals based on a control signal CTL received from the primary-side integrated circuit 201, which can accommodate a control signal terminal 254 from the processor 100. The driver 221 transmits the corresponding signals to terminals 264 and 266. A buffer (BUF) 219 generates a control signal CTLH and a control signal CTLL at appropriate signal levels to control the pull-up device and the pull-down device of the control driver 221, respectively. The buffer 219 can generate a single control signal or two separate control signals for the pull-up device and the pull-down device based on the received control signal CTL. The external resistor R H The pull-up strength can be adjusted by 1 / R H , the adjustment is independent of the external resistor R L , and the external resistor R L Adjustable pull-down strength 1 / R L Although the received control signal CTL is shown as a single-ended signal based on the input control signal CTL received by the processor 100 at terminal 254, it should be noted that in other embodiments, the input control signal IN and the received control signal CTL are differential signals. Generally, signals shown as single-ended signals in the drawings of this specification may be implemented as differential signals in other embodiments, and signals shown as differential signals in the drawings of this specification may be implemented as single-ended signals in other embodiments.

[0019] The on-resistance R of the integrated pull-up output device connected to terminal 264 using one or more passive components Ds(ON) The pull-up strength and pull-down strength of the output control signal provided to the control terminal of the high-power drive device 108 can be adjusted independently.H The pull-up strength can be adjusted. L The pull-up strength of the signal provided to the gate of the high-power driver 108 is adjusted via terminal 266, so that the pull-down strength of the signal provided to the gate of the high-power driver 108 is different from the pull-up strength. In a typical configuration, the pull-up time is slower than the pull-down time, and the resistor R H and resistor R L The power consumption of the high-power driving device 108 may vary depending on the specifications of the device (eg, power MOSFET, IGBT, gallium nitride MOSFET, silicon carbide power MOSFET, etc.).

[0020] In at least one embodiment, an isolated communication channel feeds voltage or fault information from the secondary-side integrated circuit 203 back to the primary-side integrated circuit 201. The primary-side integrated circuit 201 or the processor 100 uses this information to adjust operating parameters or generate one or more fault indicators, which can automatically handle the fault by controlling the output driver 221 accordingly. For example, the secondary-side integrated circuit 203 includes multiple modules that detect fault conditions associated with high-power drive devices, such as the desaturation detector (DESAT) 214, and these modules can also detect user-initiated faults received from the processor 100. The fault indicators can be used by the secondary-side integrated circuit 203 to prevent damage to the high-power drive device, the load system, or users of the load system. Additionally, the secondary-side integrated circuit 203 can send an indication of the fault or associated diagnostic information to the primary-side integrated circuit 201 and / or the processor 100.

[0021] In at least one embodiment, the secondary side integrated circuit 203 includes desaturation fault protection or desaturation fault protection circuitry for the high power semiconductor devices, which is used to prevent short circuit current events that could damage the high power driver device 108. Such faults can be caused by insufficient gate drive signals, which in turn can be caused by abnormal inverter gate driver behavior, driver supply voltage problems, short circuits in the power supply stage, or other excessive current or power dissipation in the high power driver device. These events can substantially increase power consumption, causing the corresponding high power driver device to quickly overheat and be damaged. For example, when Figure 1 and Figure 2When a short-circuit current condition occurs in the exemplary motor drive application (i.e., both devices of a single inverter are conducting), a high current may flow through the high-power drive devices 108, 109 and damage them. Therefore, fault detection techniques can detect such desaturation conditions. System 200 can send an indicator thereof to processor 100, and system 200 or processor 100 can trigger a shutdown of the corresponding device.

[0022] Desaturation fault protection can reduce or shut down excess current during a fault condition. In a typical application, terminal 262 is coupled to an external resistor and diode coupled to a terminal of the high-power driver device 108 (e.g., the collector terminal of an IGBT or the drain terminal of a MOSFET). Desaturation detection circuit 214 can detect when the collector-emitter voltage (or, as the case may be, the drain-source voltage) of the high-power driver device 108 exceeds a predetermined threshold level (e.g., 7V). Note that the predetermined threshold level of desaturation detection circuit 214 can be externally adjusted based on the forward voltage of one or more diodes coupled to the desaturation resistors at terminal 262 or based on the resistance value of the desaturation resistors. Additionally, a delay time can be introduced by coupling a capacitor between terminal 262 and an external power supply node.

[0023] Typically, undervoltage lockout detector (UVLO) 212 prevents insufficient voltage from being applied to the control terminal of high-power driver device 108 by outputting a low level at terminal 264 during the turn-on period of driver product 200. Undervoltage lockout detector 212 can detect when the power supply voltage (e.g., VDD2 sensed using terminal 260) exceeds a first predetermined undervoltage lockout threshold voltage and generate an indication for disabling a lockout condition. Undervoltage lockout detector 212 can also detect when the power supply voltage is below a second undervoltage lockout threshold voltage that is different from the first undervoltage lockout threshold voltage, thereby providing noise margin for undervoltage lockout voltage detection. The indicator generated by undervoltage lockout detector 212 can be provided to processor 100 via terminal 252.

[0024] Miller clamp (MC) 220 can reduce the parasitic turn-on effect of the high-power driver 108 due to the charging of Miller capacitance (e.g., collector-gate parasitic capacitance of an IGBT device or drain-gate parasitic capacitance in other embodiments of the high-power device 108). Gate-collector coupling can cause parasitic turn-on of the device 108 in response to a high transient voltage (e.g., a gate voltage spike) generated when the high-power driver 108 is turned off. When another high-power driver coupled to the high-power driver 108 is turned on, a gate voltage spike can be generated. For example, when the upper high-power driver 109 is turned on, the lower high-power driver 108 corresponding to the upper high-power driver 108 experiences a voltage change dV CE / dt, this voltage change causes current to flow into the gate drive terminal coupled to the lower high-power driver device 108. Miller clamp 220 uses terminal 268, coupled to the gate of the lower high-power driver 108, to sense the current. This current creates a voltage drop across any gate resistor and increases the gate-emitter voltage of the corresponding lower high-power driver device. If the gate-emitter voltage exceeds the device threshold voltage (e.g., 2V), the high-power driver device 108 turns on. A similar parasitic turn-on event occurs when the high-power driver device 108 is turned on and the corresponding upper high-power driver device 109 is turned off. Miller clamp 220 connects terminal 268 to ground via a low-resistance switch, which blocks or prevents the Miller capacitor current from generating a voltage sufficient to turn on the high-power driver device. In some embodiments of driver product 200, Miller clamp 220 is not required because a sufficiently sized gate capacitor coupled between the gate and emitter of each high-power driver device 108 shunts any Miller current and increases the transient level required for parasitic device turn-on. However, such an embodiment increases the gate charge voltage required to reach the threshold voltage of the high-power driver device 108, increasing the driver power and increasing the switching losses of the high-power driver device 108. In other embodiments of the driver product 200 that do not use a Miller clamp circuit, the secondary-side integrated circuit 203 is coupled to a negative power supply (e.g., -5V) via terminal 270, so that the secondary-side integrated circuit is referenced to a negative voltage rather than ground. This configuration provides additional voltage margin to increase the likelihood that parasitic turn-on transients will not raise the control terminal of the high-power driver device 108 above its threshold voltage. However, this configuration requires the additional cost of generating a negative voltage.

[0025] After the module on the secondary-side integrated circuit 203 detects a fault condition, the fault logic circuit 216 generates a control signal FAULT that shuts down the high-power drive device 108. The fault logic circuit 216 may report the fault condition to the processor 100 via the primary-side integrated circuit 201. Alternatively, the fault logic circuit 216 may report the fault condition only to the primary-side integrated circuit 201, and the high-power drive device 108 may continue to operate. The primary-side integrated circuit 201 then reports the fault condition to the processor 100. Because a system may include multiple high-power drive devices (e.g., the six high-power drive devices in the exemplary motor control application described in this specification), shutting down only one of these devices may damage the high-power drive devices or the load. Therefore, in response to detecting a fault, the processor 100 may initiate shutdown of the high-power drive device 108 only after a predetermined number of faults are detected within a specific time period or other conditions are met. In at least one embodiment, processor 100 initiates shutdown of high-power drive device 108 independent of any fault detection by driver product 200 (eg, based on fault detection from another driver product 200 associated with another high-power drive device 108 or 109 ).

[0026] The sudden shutdown of the high-power driver 108 may generate a large di / dt induced voltage. Such a voltage spike may damage the driver circuit or load. Therefore, in response to a fault condition, the processor 100 or the driver product 200 initiates a soft shutdown of the high-power driver 108, wherein the control terminal of the high-power driver 108 is slowly discharged at a rate with a fall time longer than the normal fall time of the output control signal. For example, the fault logic circuit 216 receives indications from the undervoltage lockout detector 212 and the desaturation detection circuit 214 and generates a control signal FAULT based on them to initiate a soft shutdown. Typical implementations of the soft shutdown function in the driver product may use an additional terminal coupled to terminal 264 or terminal 266 or at least one additional external resistor.

[0027] Reference Figure 3In an exemplary embodiment, the Miller clamp 220 includes a comparator 306 that compares the voltage on the gate terminal of the high power driver device 108 with a predetermined reference voltage VREF (e.g., approximately 2V). In response to the voltage level on the gate terminal of the high power driver device 108 falling below the predetermined reference voltage VREF, the output signal of the comparator 306 turns on the device 308, which provides a ground path that fixes the gate terminal of the high power driver device 108 to a low voltage level. When the high power driver device 108 is turned off, the Miller clamp 220 holds the gate terminal low and prevents the gate terminal from being pulled high by the Miller capacitance. Typically, an effective Miller clamp includes a relatively large device (e.g., a device with a sufficiently low on-resistance) that is directly coupled to the gate terminal of the high power driver device via a dedicated terminal of the driver product. Otherwise, the resistor R H or R L The external resistor will make the Miller clamp ineffective. At the same time, the additional terminals and relatively large device of the Miller clamp also increase the cost of the driver product.

[0028] In one technique for implementing a gate driver with an integrated Miller clamp function using a variable strength gate driver, the variable strength gate driver reduces or eliminates the need for an external gate resistor (e.g., a resistor R H or R L The invention provides a method for realizing a gate driver 108 that is coupled to a high power driver 108 and ... that is coupled to a high power driver 108 and a gate driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a high power driver 108 that is coupled to a Figure 2 Compared with the embodiment in FIG, this embodiment can reduce the packaging size and cost of the driver product.

[0029] Reference Figure 4 In at least one embodiment, the driver product 400 includes: a primary side integrated circuit 201, an isolation barrier 230 and an isolation communication channel (although Figure 41 , and includes a secondary-side integrated circuit 403. In at least one embodiment, the secondary-side integrated circuit 403 of the driver product 400 includes the undervoltage lockout detector 212, the desaturation detection circuit 214, and the fault logic circuit 216. As described above, the secondary-side integrated circuit includes a gate driver with an integrated Miller clamp 420 coupled to terminal VO, which in some embodiments is the only terminal of the driver product 400 coupled to the gate terminal of the high-power drive device 108.

[0030] In at least one embodiment, the variable strength driver 402 comprises a segmented driver. In at least one embodiment of the segmented driver, multiple circuit segments are coupled to the output node, and each circuit segment is selectively enabled by a driver controller 404. The driver controller 404 configures the variable strength driver 402 to perform a pull-up having a first predetermined strength in response to a control signal CTL having a first value. The driver controller 404 also configures the variable strength driver 402 to perform a first pull-down having a second predetermined strength in response to a control signal CTL having a second value. Alternatively, the driver controller 404 configures the variable strength driver 402 to perform a second pull-down having a third predetermined strength in response to a control signal CTL having a second value and a feedback signal FB indicating that the voltage on the gate terminal of the high-power driver 108 has dropped below a predetermined voltage level VREF, thereby implementing Miller clamping. In at least one embodiment, the driver controller 404 configures the variable strength driver 402 to implement a third pull-down having a fourth predetermined strength in response to a control signal FAULT indicating a fault condition to achieve a soft shut-down. The first predetermined strength, the second predetermined strength, the third predetermined strength, and the fourth predetermined strength can be independently selected using a predetermined digital code that is used to generate the control signal S that can be stored in the memory 410. 1H , control signal S 1L , control signal S 2H , control signal S 2L , ..., control signal S NH and control signal S NL The predetermined digital code and other configuration parameters may be preloaded into memory 410, received from a serial interface of driver product 400, or provided to memory 410 using other techniques.

[0031] In at least one embodiment, driver controller 404 receives a control signal CTL across isolation barrier 130 from primary-side integrated circuit 201 and a feedback signal from comparator 406, which in some embodiments is a hysteretic comparator. In at least one embodiment, comparator 406 receives a predetermined signal level from a digital-to-analog converter (DAC) 412. This predetermined signal level can be based on the target device type and adjusted during product characterization or testing (e.g., to compensate for process variations). This predetermined signal level code is stored digitally in memory and subsequently converted into an analog signal for use by comparator 406. During manufacturing and testing, or at the customer site, this predetermined signal level code can be user-programmable and can be loaded into memory 410 or stored on secondary-side integrated circuit 403 via a serial interface. The corresponding predetermined signal level varies depending on the device type used for high-power driver device 108. In other embodiments, an analog-to-digital converter digitizes the signal level at terminal VO and uses digital comparison logic to generate feedback signal FB.

[0032] In at least one embodiment of the secondary-side circuit 403, at least one set of digital codes corresponding to the pull-up strength, the first pull-down strength, the second pull-down strength, or the third pull-down strength (if any) is user-selectable and stored in the memory 410. The driver controller 404 accesses these digital codes to determine which segments of the variable strength driver 402 can respond to a condition (e.g., a condition based on the level of the control signal CTL and the level of the feedback signal) and which segments cannot respond. The predetermined digital codes vary depending on the threshold voltage of the high-power driver 108 or high-power driver 109 and the target application.

[0033] Reference Figure 5 In at least one embodiment, the variable intensity driver 402 includes N segments, each of the N segments including: a control signal S in response to a corresponding control signal S Hn An independent controllable pull-up device; and in response to a corresponding control signal S Ln The independent segments may include pull-up devices and pull-down devices. The pull-up devices and pull-down devices of each segment may have the same or different sizes (e.g., binary-weighted sizes) than the pull-up devices and pull-down devices of other segments. Although additional resistors may be coupled between the pull-up devices and the output nodes of the segments and between the pull-down devices and the output nodes of the segments in other embodiments, in at least one embodiment, only channel resistors are included. Thus, the driver controller 404 can digitally control the slew rate of the signal at the output node coupled to the gate terminal of the high-power driver device 108.

[0034] In at least one embodiment of a gate driver with an integrated Miller clamp 420, different numbers of segments can be selectively enabled to charge a node coupled to terminal VO with a predetermined pull-up strength under normal output driver operating conditions; discharge the node coupled to terminal VO with a first pull-down strength under normal output driver operating conditions; slowly discharge the node coupled to terminal VO with a second pull-down strength to perform a soft shutdown under a fault condition; or clamp the node coupled to terminal VO with a third pull-down strength in a Miller clamp configuration. In at least one embodiment, the driver controller 404 generates a control signal S based on the control signal FAULT, the control signal CTL, and the feedback signal FB. Hn In other embodiments, the driver controller 404 generates the control signal S based only on the control signal CTL and the feedback signal FB. Hn In at least one embodiment, the driver controller 404 dynamically controls the gate impedance based on load conditions while switching the voltage at terminal VO. For example, rather than enabling or disabling a predetermined number of segments simultaneously, the driver controller 404 can sequentially turn segments on or off until all predetermined number of segments are turned on or off, respectively. Some embodiments of the driver controller 404 dynamically control the gate impedance to compensate for the effects of process, voltage, or temperature variations, thereby improving the efficiency of the motor 120 or reducing electrical noise (e.g., conducted noise or radiated noise).

[0035] Typically, the on-resistance of a transistor changes with temperature. Therefore, in at least one embodiment, the driver controller 404 can adjust the voltage level applied to the gates of transistors in the variable strength driver 402 to maintain a constant on-resistance (e.g., a constant pull-up resistance or a constant pull-down resistance) as temperature changes. For example, the driver controller 404 can include a temperature sensor or receive temperature information, and as the temperature of the driver product 400 increases, the driver controller 404 can increase the gate voltage applied to each segment of the variable strength driver 402 to maintain a constant pull-up resistance value or a constant pull-down resistance value relative to temperature.

[0036] although Figure 5A variable strength driver 402 is shown that includes N inverter segments that can be controlled digitally, but other embodiments also use variable current sources or other technologies to implement variable strength drivers. In one embodiment, the gate driver with integrated Miller clamp circuit 402 includes one or more variable current sources that are controlled by analog signals based on digital control words provided by the driver controller 404 to achieve variable drive strength. When the gate voltage drops to a predetermined voltage level, the driver controller 404 enables the pull-down transistors in all segments to implement the Miller clamp function. Although the resistor R is integrated in the above embodiment, the gate driver with integrated Miller clamp circuit 402 includes one or more variable current sources that are controlled by analog signals based on digital control words provided by the driver controller 404 to achieve variable drive strength. H , resistor R L and a soft-off resistor, but in other embodiments, only the resistor R H or resistor R L and use an additional output terminal (e.g., terminal VO coupled to an external resistor R H , terminal VL is directly coupled to the control gate of the high power drive device).

[0037] Thus, the present specification has described a gate driver with an integrated Miller clamp. The gate driver omits at least some gate resistors and reduces the number of package pins, i.e., the number of package pins required to implement pull-up, pull-down, and soft-off of the VH pin, VL pin, and CLMP package pin of the driver product 200 is reduced, such as to implement a single package pin VO of the driver product 400, thereby enabling the gate driver to use a smaller package and reduce costs. In some embodiments, the gate driver technology described in the present specification provides customer programmability for slew rate and minimizes oscillations by dynamically controlling the gate impedance while converting the signal on the gate terminal. Control of the waveform shape can improve the efficiency of high-power load systems by making the rise and fall times of the signal on the control terminal of the high-power drive device faster while maintaining the parasitic oscillations on the control terminal at an acceptable level. In contrast, conventional drivers use resistors R H and R L The oscillation specification is met, resulting in slower rise and fall times than required to achieve the target efficiency specification.

[0038] The description of the present invention in the present specification is illustrative, and such description is not intended to limit the scope of protection of the present invention as defined in the claims of the present invention. For example, the present specification describes an embodiment in which the driver product 400 is coupled to an IGBT high-power drive device, but those skilled in the art should understand that the technical inspiration given in the present specification can be used with other types of devices. In addition, although the present specification describes an embodiment in which the driver product 400 is used in a motor application, those skilled in the art should understand that the technical inspiration given in the present specification can be used in other applications. Without departing from the scope of protection of the present invention as set forth in the claims attached to this application, the embodiments disclosed in the present invention can be changed and modified based on the description in the present specification.

Claims

1. A method of controlling a high-power drive device, the high-power drive device being coupled to a terminal of a package, the package housing a driver integrated circuit coupled to the terminal, the method comprising: generating an indication of a level of a signal at the terminal relative to a predetermined signal level; as well as According to the control signal and the indication, the variable intensity driver of the driver integrated circuit is configured, wherein the configuring comprises: in response to the signal on the terminal exceeding the predetermined signal level, configuring the variable intensity driver as an output driver circuit, the output driver circuit being responsive to the control signal; as well as In response to the control signal having a first logic value and the signal on the terminal falling below the predetermined signal level, the variable intensity driver is configured as an active Miller clamp circuit. The method of claim 1 , wherein the terminal is coupled to a control terminal of the high power drive device.

3. The method of claim 1 , wherein configuring the variable intensity driver comprises: In response to the first logic value of the control signal and a second logic value of the indication, a first predetermined number of segments of a plurality of segments of the variable intensity driver are enabled to discharge the terminal.

4. The method of claim 3 , wherein configuring the variable intensity driver further comprises: In response to the first logic value of the control signal and a third logic value of the indication, a second predetermined number of the plurality of segments are enabled to discharge the terminal. The method of claim 4 , wherein the second predetermined number of segments is greater than the first predetermined number of segments.

6. The method of claim 3, wherein configuring the variable intensity driver comprises: In response to a third logic value of the control signal, a third predetermined number of the plurality of segments of the variable intensity driver are enabled to discharge the terminal.

7. The method of claim 6, wherein configuring the variable intensity driver comprises: In response to a fault condition, a fourth predetermined number of the plurality of segments of the variable intensity drive are enabled to discharge the terminal.

8. The method according to claim 1, further comprising: In response to a second logic value of the control signal, charging a node of the high-power driver device for a first length of time; as well as In response to the first logic value of the control signal, a node of the high-power driving device is discharged for a second time length, the second time length being different from the first time length.

9. The method according to claim 1, further comprising: isolating a first portion included within the driver integrated circuit contained within the variable intensity driver from a second portion housed by the package; as well as A control signal from the second part is received from the first part, wherein control is performed by the first part.

10. The method of claim 1, further comprising: The level of a control signal provided to the variable intensity driver is adjusted in response to temperature changes.

11. A driver circuit for controlling a high-power driving device external to a package of the driver circuit, the driver circuit comprising: Output node; a variable intensity driver circuit coupled to the output node; a feedback circuit configured to generate a feedback signal based on a predetermined signal level and a signal level on the output node; as well as a driver controller circuit responsive to a received control signal and the feedback signal, the driver controller circuit configuring the variable intensity driver circuit as an output driver in response to a signal level at the output node exceeding the predetermined signal level, the output driver responsive to the received control signal and configuring the variable intensity driver circuit as an active Miller clamp circuit in response to the received control signal having a first logic value and the signal level at the output node falling below the predetermined signal level.

12. The driver circuit of claim 11 , further comprising: in, The variable intensity driver circuit includes a plurality of segments, and the driver controller circuit is configured to: enabling a first predetermined number of the plurality of segments to discharge the output node in response to the received first logic value of the control signal and the received second logic value of the feedback signal; enabling a second predetermined number of the plurality of segments to discharge the output node in response to the first logic value of the received control signal and a third logic value of the received feedback signal; as well as enabling a third predetermined number of the plurality of segments of the variable intensity driver circuit to charge the output node in response to a fourth logic value of the received control signal, The first predetermined number of segments is less than the second predetermined number of segments.

13. The driver circuit of claim 12 , wherein each of the plurality of segments comprises: An independently controllable pull-up device is responsive to a first respective control signal and an independently controllable pull-down device is responsive to a second respective control signal.

14. The driver circuit according to claim 11, further comprising: a terminal of the package, the terminal coupled to the output node; a first power terminal of the package; as well as a second power supply terminal of the package, wherein the high-power driving device comprises a control terminal coupled to the terminal; and The variable intensity driver circuit is coupled to the first power terminal and the second power terminal.

15. The driver circuit of claim 11 , wherein the variable intensity driver circuit is configured as an output driver, and the variable intensity driver circuit is configured to charge the output node for a first length of time in response to the second logic value of the received control signal, and is configured to discharge the output node for a second length of time in response to the first logic value of the received control signal. 16 . The driver circuit of claim 15 , wherein the first time length and the second time length are based on predetermined values.

17. The driver circuit of claim 15, wherein the second time length is different from the first time length.

18. The driver circuit of claim 15, wherein the driver controller circuit is further responsive to a fault signal, and the variable strength driver circuit is configured to discharge the output node for a third length of time in response to the fault signal, the third length of time being longer than the second length of time.

19. A method of controlling a high-power drive device located external to a package of a driver circuit, the method comprising: in response to a voltage on a terminal of the package being greater than a predetermined voltage level, configuring the variable intensity driver circuit as an output driver circuit, the output driver circuit being responsive to the received control signal; as well as In response to the signal on the terminal being below the predetermined voltage level, the variable intensity driver circuit is configured as a Miller clamp circuit.

20. The method of claim 19, wherein configuring the variable strength driver circuit as an output driver circuit comprises: In response to a first logic value of the received control signal, a first predetermined number of segments of the plurality of segments of the variable intensity driver circuit are enabled to discharge the terminal.

21. The method of claim 20 , wherein configuring the variable strength driver circuit as a Miller clamp circuit further comprises: enabling a second predetermined number of the plurality of segments to discharge the terminal in response to the first logic value of the received control signal, in, The second predetermined number of segments is greater than the first predetermined number of segments.

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