A Remaining Time Sampling Circuit and a Time-to-Digital Converter Based on Differential Sampling

Abstract

The present invention discloses a remaining time sampling circuit and a time-to-digital converter based on differential sampling. The time-to-digital converter includes a CTDC, an FTDC, a remaining time sampling circuit, a thermometer code / binary code conversion circuit, a serial output circuit, and a voltage-controlled phase-locked loop circuit. The remaining time sampling circuit can sample the output of the CTDC through an arbiter based on a sense amplifier and arbitrate to output opposite signals with symmetry as control signals for arbitration between the CTDC output and the Stop signal. The input time interval, that is, the time difference between the rising edges of the Start signal and the Stop signal, is first quantified by the CTDC, and the quantization result is output as the 4 most significant bits through a decoder. The remaining time sampling circuit extracts the remaining time of the CTDC and converts it into the time difference between the rising edges of the signals SE and FE and inputs it into the FTDC for re-quantification. The quantization result generates the 7 least significant bits through a decoder. After the control circuit detects the FTDC quantization end signal, it turns off the FTDC quantization behavior and turns on the output of the serial circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and particularly to a residue time sampling circuit based on differential sampling and a two-stage time-to-digital converter (TDC) based on a gated ring oscillator. Background Art

[0002] The residue time sampling circuit is applied to the design of two-stage or multi-stage time-to-digital converters, and transfers the time margin collected in the coarse quantization TDC to the fine quantization TDC. The time-to-digital converter is used to convert the time interval between signals into corresponding digits and output them. Currently, TDCs are widely used in scientific research fields such as laser ranging, 3D imaging, quantum communication, and nuclear physics, and various structures of TDCs emerge in an endless stream to meet the needs of various engineering and scientific research fields.

[0003] With the significant improvement of semiconductor process levels, the measurement accuracy of time has gradually increased, gradually reaching femtosecond resolution. At the same time, the delay and low power consumption of digital gate circuits are decreasing with the process, so the performance and power consumption of time-domain and digital-domain circuits are constantly improving, which enables us to obtain higher resolution and better linearity in the time domain and digital domain. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides a residue time sampling circuit based on differential sampling with low power consumption and high precision, and a time-to-digital converter with high resolution, high linearity, a relatively large measurement range, and automatic reset, which can accurately quantify the input time interval and output corresponding digital signals. At the same time, specific MOS transistors are added to the rising edge / falling edge arbiter to implement the automatic reset function of the circuit. In addition, a serial output circuit implemented by an improved flip-flop has a simpler circuit structure and a higher output frequency compared with the traditional serial output circuit.

[0005] The object of the present invention is achieved by the following technical solutions: 1. A residue time sampling circuit based on differential sampling, characterized in that: it includes an arbiter based on a sense amplifier, a buffer, and an inverter composed of four MOS transistors connected in series, wherein the outputs of the arbiter and the buffer are used as the input signals of the inverter. In order to ensure that the input signal can be correctly sampled, it is necessary to ensure that the time for the signal to pass through the buffer is greater than the time for the signal to pass through the arbiter; a symmetric structure is adopted to ensure that the delay introduced during the extraction of the output signal of the coarse quantization TDC is equal to the delay introduced during the extraction of the Stop signal, so that the finally collected time margin is equal to the actual remaining time; the arbiter based on the sense amplifier compares the output signal of the coarse quantization TDC and the Stop signal, and outputs symmetric opposite signals as the switch control signals of the inverter composed of four MOS transistors.

[0006] According to another aspect of the present invention, there is provided a time-to-digital converter that performs differential sampling using the aforementioned remaining time sampling circuit, which is characterized by including a coarse quantization TDC, a fine quantization TDC, a remaining time sampling circuit, a thermometer code / binary code conversion circuit, a serial output circuit, and a voltage-controlled phase-locked loop circuit;

[0007] The input time interval, that is, the time difference between the rising edges of the Start signal and the Stop signal, is first quantized by the coarse quantization TDC, and the quantization result is output as the 4 most significant bits through a decoder; the remaining time sampling circuit extracts the remaining time of the coarse quantization TDC and converts it into the time difference between the rising edges of the signals SE and FE, which is input into the fine quantization TDC for re-quantization, and the quantization result generates the 7 least significant bits through a decoder; after the control circuit detects the quantization end signal of the fine quantization TDC, it turns off the quantization behavior of the fine quantization TDC and turns on the output of the serial circuit.

[0008] Furthermore, it includes: using a voltage-controlled delay chain as the high-section TDC structure to expand the measurement range, and the low-section TDC adopts a vernier caliper-type ring oscillator structure to achieve high resolution, and a counter is added to reduce the circuit area. At the same time, the end signal is fed back to the enable signal generation circuit to reduce the circuit power consumption.

[0009] Furthermore, the same buffer unit is added behind the delay units of the coarse quantization TDC and the delay-locked loop circuit to ensure that the loads of the delay units in the two circuits are the same, and it is used to improve the load capacity of the delay units in the coarse quantization TDC, block the influence of different input states of the arbiter on the delay of the delay units in the coarse quantization TDC, and improve the linearity of the coarse quantization TDC.

[0010] Furthermore, the fine quantization TDC includes: a fast ring oscillator, a rising-edge arbiter, a falling-edge arbiter, a slow ring oscillator, and a four-bit counter; before quantization, the reset signal EVEN_R resets the outputs of the even-stage delay units in the fast / slow ring oscillators to zero, and the signal ODD_R sets the odd-stage delay units to one; after the coarse quantization TDC finishes quantization, the generated SE / SB and FE / FB signals are used as the start signals of the fast ring oscillator and the slow ring oscillator respectively; at the same time, the outputs of the fast and slow ring oscillators are input into the rising-edge and falling-edge arbiters to determine whether the rising edge or the falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or the falling edge of the output signal of the slow ring oscillator; the counter starts counting under the trigger of the output S0 of the slow ring oscillator.

[0011] Furthermore, the rising-edge arbiter adds two PMOS transistors to the arbiter based on a sense amplifier and resets the arbiter output to zero at the start of quantization; NMOS transistors are added to the falling-edge arbiter.

[0012] Furthermore, the serial output circuit stores the output of the arbiter in the coarse quantization TDC and the fine quantization TDC after the fine quantization TDC quantization is completed, and outputs data under the trigger of a specified clock; a TSPC register is adopted in the circuit, and two MOS transistors M1 and M2 are added therein for sampling the result of the arbiter. The register input port J is connected to the output of the arbiter, and the input port T is connected to the fine quantization TDC quantization end flag signal R_SIG; when the flag signal R_SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R_SIG is equal to one, the register serially outputs data under the trigger of the clock CLK, and the signal TC is generated by the signal R_SIG.

[0013] Compared with the prior art, the present invention adopts the above technical solutions and has the following technical effects:

[0014] (1) In the present invention, the same buffer unit is added behind the delay unit of the coarse quantization TDC and the delay locked loop circuit, which not only ensures that the loads of the delay units in the two circuits are the same, but also increases the load capacity of the delay unit in the coarse quantization TDC, and blocks the influence of different input states of the arbiter on the delay of the delay unit in the coarse quantization TDC, thereby improving the linearity of the coarse quantization TDC;

[0015] (2) In the present invention, the power consumption of the time digital converter is reduced by feeding back the end signal to the enable signal circuit;

[0016] (3) In the present invention, a specific reset system is adopted, and an additional reset MOS transistor is added to the rising edge / falling edge arbiter to ensure that the output of the arbiter is zero before quantization;

[0017] (4) The remaining time sampling circuit in the present invention adopts a symmetric structure, and at the same time, the control of multiple signals is used to ensure that no path is formed in the circuit, thereby reducing the power consumption of the circuit;

[0018] (5) The serial output circuit of the present invention realizes two modes of data sampling and transmission through a specific control circuit and flip-flop. Compared with the traditional serial output circuit, this circuit structure is simpler and the output frequency is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is the schematic diagram of the overall circuit structure of the time digital converter according to the embodiment of the present invention;

[0020] Figure 2 is the timing schematic diagram of the embodiment of the present invention;

[0021] Figure 3 is the coarse quantization TDC and the remaining time sampling circuit provided by the embodiment of the present invention;

[0022] Figure 4 This is the schematic diagram of the control circuit provided by the embodiment of the present invention. (a) is a schematic diagram of generating a reset signal RST by inverting the Stop signal and performing an AND operation with the Start signal; (b) is a schematic diagram where the time interval Ti between the Stop signal and the Start signal is very small.

[0023] Figure 5 It is a generating circuit for the fine quantization TDC enable signal.

[0024] Figure 6 It is a generating circuit for the end signal R_SIG.

[0025] Figure 7 The schematic diagram of the fine quantization TDC circuit adopting a gated vernier caliper type ring oscillator mechanism.

[0026] Figure 8 The rising edge arbiter circuit and the falling edge arbiter circuit of the present invention. (a) is the rising edge arbiter circuit; (b) is the falling edge arbiter circuit.

[0027] Figure 9 It is the serial output circuit of the present invention. Specific embodiments

[0028] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0029] According to an embodiment of the present invention, a time digital converter based on differential sampling Figure 1 As shown, it includes a coarse quantization TDC (Coarse TDC, CTDC), a fine quantization TDC (Fine TDC, FTDC), a remaining time sampling circuit, a thermometer code / binary code conversion circuit, a serial output circuit, and a voltage controlled phase locked loop circuit.

[0030] The input time interval, that is, the time difference between the rising edges of the Start signal and the Stop signal, is first quantized by the CTDC, and the quantization result is output as 4 most significant bits through a decoder; the remaining time sampling circuit extracts the remaining time of the CTDC and converts it into the time difference between the rising edges of the signals SE and FE and inputs it into the FTDC for re - quantization, and the quantization result generates 7 least significant bits through a decoder; the control circuit closes the FTDC quantization behavior after detecting the FTDC quantization end signal and turns on the output of the serial circuit.

[0031] To avoid the influence of the external environment on the circuit, a voltage-controlled phase-locked loop circuit is added to the system to improve the stability of the system and the accurate delay time. Figure 2 This is the timing schematic diagram of the TDC in the present invention. The time difference between the rising edges of the Start signal and the Stop signal is the input time interval. The voltage-controlled phase-locked loop equally divides the period of the reference clock Fref with a frequency of 100 MHz into fifty parts. Then, the delay value of each delay unit in the CTDC remains at 200 ps. The remaining time sampling circuit transmits the remaining time, that is, the rising edge of the Stop signal and the rising edge of the first delay unit in the CTDC behind the Stop signal, to the FTDC. The FTDC includes two delay chains with different delays, a fast delay chain and a slow delay chain, namely the F chain and the S chain, as Figure 7 shown. Every time the remaining time passes through a delay unit in the F chain, the delay difference t between the two delay units will be subtracted until the rising edge or falling edge of the output signal Fn of the F chain delay unit arrives earlier than the rising edge or falling edge of the output signal Sn (n = 0, 1... 6) of the S chain delay unit, indicating the end of quantization. The calculation method of the quantization result is expressed as:

[0032] T in = T × (N c + 1)-(T1 - T2) × N f (1)

[0033] where N c and N f are the binary codes obtained by decoding the outputs of the CTDC and the FTDC respectively. T is the delay of the delay unit in the CTDC, and T1 and T2 are the delays of the delay units in the slow and fast delay chains in the FTDC respectively. Figure 3 This is the overall principle diagram of the CTDC and the remaining time sampling circuit provided by the embodiment of the present invention. It includes an arbiter based on a sense amplifier, a buffer with a large delay, and an inverter composed of four MOSs connected in series. Among them, the outputs of the arbiter and the buffer serve as the input signals of the inverter. To ensure that the input signal can be correctly sampled, it is necessary to ensure that the time for the signal to pass through the buffer is greater than the time for the signal to pass through the arbiter.

[0034] Before each quantization, the reset signal R of the arbiter turns on MOS transistors M1 and M4, pulling C0 and D0 to high level. After passing through the inverters, the outputs P and Q of the arbiter are reset to low level. Therefore, MOS transistors P1 and P2 in the sampling unit are turned on, pulling StartL and StopL to high level, and the output signals StopN and StartN are also reset to low level accordingly. During quantization, the output In (n = 1, 2... 14) of each delay unit of the CTDC is connected to the D port of the corresponding arbiter and compared with the SP signal input to the C port of the arbiter. When the rising edge of In is after the rising edge of the signal SP, the output Q of the corresponding arbiter rises to high level. Therefore, the connected sampling unit pulls the signal StartL low to low level through MOS transistors N1 and N2, and the output signal StopN also rises to high level accordingly. Since each delay unit in the CTDC is followed by an arbiter and a remaining-time sampling circuit, in order to ensure that the load of the delay unit in the CTDC is the same as that of the delay unit in the voltage-controlled phase-locked loop, a buffer unit is connected after the delay unit in both circuits and connected to other circuits through the buffer unit. At the same time, the addition of the buffer unit increases the load capacity of each delay unit and avoids the influence of different states of the arbiter on the delay. The remaining-time sampling circuit uses a symmetric structure to ensure the balance of the system and reduce errors. In order to ensure that the time margin can be correctly collected, it is necessary to ensure that the time for Stop to reach Y through the arbiter is less than the time t for Stop to reach X through the buffer.

[0035] Before each measurement, it is necessary to ensure that the circuit is in the original state. Therefore, a reset signal is generated before the measurement to reset the FTDC, arbiter, counter, etc. Figure 4 (a), the reset signal RST is generated by inverting the Stop signal and performing an AND operation with the Start signal. Since the reset of the circuit takes a certain amount of time, it is necessary to ensure that the reset pulse of the reset signal is greater than the minimum reset time of the circuit. As Figure 4 (b) shows, when the interval time Ti between the Stop signal and the Start signal is very small, in order to ensure that the circuit can be reset, it is necessary to make the delay T of the inverter greater than the reset time of the circuit.

[0036] Figure 5 For the generation circuit of the FTDC enable signal, in order to ensure that the oscillator can automatically stop oscillating after the FTDC quantization ends to reduce power consumption, a quantization end signal R_SIG is added to the circuit to control the generation of the enable signal, that is, when R_SIG is equal to zero, the StartN and StopN signals can generate the enable signal.

[0037] Figure 6It is a generation circuit for the R_SIG signal. The circuit input signals Qn and Pn (n = 0, 1...6) are the output signals of the arbiter in the FTDC. When the output of one of the arbiters is at a high level, the circuit output becomes high, indicating that the FTDC quantization is completed.

[0038] Figure 7 It is a schematic diagram of the FTDC circuit adopting a gated vernier caliper type ring oscillator mechanism, including: a fast ring oscillator 1, a rising edge arbiter 2, a falling edge arbiter 3, a slow ring oscillator 4, and a four-bit counter 5. Before quantization, the reset signal EVEN_R resets the output of the even-stage delay units in the fast / slow ring oscillator to zero, and the signal ODD_R sets the odd-stage delay units to one. After the CTDC quantization is completed, the SE / SB and FE / FB signals are generated as the start signals for the fast ring oscillator and the slow ring oscillator respectively. At the same time, the outputs Fn and Sn (n = 0...6) of the fast and slow ring oscillators are input into the rising edge and falling edge arbiters to determine whether the rising edge or falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or falling edge of the output signal of the slow ring oscillator. The counter starts counting under the trigger of the output S0 of the slow ring oscillator. When the signal passes through one cycle of the S oscillator, the counter will increment by one. Since the counter will automatically increment by one each time the FTDC starts quantization, the final result needs to be decremented by one. Therefore, the quantization result of the FTDC can be expressed as:

[0039] T FO = ((N C - 1) × 14 + N F ) × (T S - T F ) (2)

[0040] Where N C represents the output of the counter, N F represents the count of the oscillator, T S represents the delay of the delay unit of the S oscillator, and T F represents the delay of the delay unit of the F oscillator.

[0041] The rising edge arbiter 2 adds two PMOS transistors P1 and P2 to the traditional arbiter based on a sense amplifier, as shown in Figure 8 (a). The source of the MOS transistor is connected to the power supply voltage, the drain is connected to C0 or D0, and the gate R2 is connected to the reset signal EVEN_R to reset the arbiter output to zero at the start of quantization. Similarly, in Figure 8An NMOS transistor N1 and an NMOS transistor N2 are added between C0, D0 and ground in the falling-edge arbiter shown in (b), and at the same time, the gate R2 is connected to the reset signal ODD_R. The minimum time difference between input signals that can be detected determines the accuracy of the arbiter. To improve the accuracy of the arbiter, a MOS transistor is added between the arbiter nodes C1 and D1.

[0042] Figure 9 It is the serial output circuit adopted in this article. The serial output circuit stores the outputs of the arbiters in CTDC and FTDC after the FTDC quantization ends, and outputs data under the trigger of a specified clock. The TSPC register is adopted in the circuit, and two MOS transistors M1 and M2 are added thereto for sampling the results of the arbiter. The register input port J is connected to the output of the arbiter, and the input port T is connected to the FTDC quantization end flag signal R_SIG. When the flag signal R_SIG is equal to zero, the register reads the result of the arbiter; when the flag signal R_SIG is equal to one, the register serially outputs data under the trigger of the clock CLK. The signal TC is generated by the signal R_SIG.

[0043] As described above, it is only the best specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A two-stage time-to-digital converter based on a gated ring oscillator, characterized in that, It includes a CTDC, an FTDC, a remaining time sampling circuit, a thermometer code / binary code conversion circuit, a serial output circuit, and a voltage-controlled phase-locked loop circuit; the differential sampling remaining time sampling circuit includes an arbiter based on a sense amplifier, a buffer, and an inverter composed of four MOSs connected in series. Among them, the outputs of the arbiter and the buffer serve as the input signals of the inverter. To ensure that the input signals can be correctly sampled, it is necessary to ensure that the time for the signals to pass through the buffer is greater than the time for them to pass through the arbiter; a symmetric structure is adopted to ensure that the delay introduced during the extraction of the CTDC output signal is equal to the delay introduced during the extraction of the Stop signal, so that the finally collected time margin is equal to the actual remaining time; the arbiter based on the sense amplifier compares the CTDC output signal and the Stop signal, and outputs symmetric opposite signals Q and P as the switch control signals of the inverter composed of four MOS transistors. The input time interval, that is, the time difference between the rising edges of the Start signal and the Stop signal, is first quantified by the CTDC, and the quantization result is output as the 4 most significant bits through a decoder; the remaining time sampling circuit extracts the remaining time of the CTDC and converts it into the time difference between the rising edges of the signals SE and FE and inputs it into the FTDC for re-quantification, and the quantization result generates the 7 least significant bits through a decoder; after the control circuit detects the FTDC quantization end signal, it turns off the FTDC quantization behavior and turns on the output of the serial circuit.

2. The time-to-digital converter according to claim 1, wherein It includes: A voltage-controlled delay chain is used as the high-section TDC structure to expand the measurement range, and the low-section TDC adopts a vernier caliper-type ring oscillator structure to achieve high resolution. At the same time, a counter is added to reduce the circuit area, and the end signal is fed back to the enable signal generation circuit to reduce the circuit power consumption.

3. A time-to-digital converter according to claim 1, characterized in that, The same buffer unit is added behind the delay units of the coarse quantization TDC and the delay-locked loop circuit to ensure that the loads of the delay units in the two circuits are the same, and it is used to improve the load capacity of the delay units in the CTDC, block the influence of different input states of the arbiter on the delay of the delay units in the CTDC, and improve the linearity of the CTDC.

4. A time-to-digital converter according to claim 1, wherein, The FTDC includes a fast ring oscillator, a rising-edge arbiter, a falling-edge arbiter, a slow ring oscillator, and a four-bit counter; before quantization, the reset signal EVEN_R resets the outputs of the even-stage delay units in the fast / slow ring oscillators to zero, and the signal ODD_R sets the odd-stage delay units to one; after the CTDC quantization is completed, the SE / SB and FE / FB signals are generated as the start signals of the fast ring oscillator and the slow ring oscillator respectively; at the same time, the outputs of the fast and slow ring oscillators are input into the rising-edge and falling-edge arbiters to determine whether the rising edge or the falling edge of the output signal of the fast ring oscillator arrives earlier than the rising edge or the falling edge of the output signal of the slow ring oscillator; the counter starts counting under the trigger of the output S0 of the slow ring oscillator.

5. A time-to-digital converter according to claim 4, wherein The rising-edge arbiter adds two PMOS transistors to the arbiter based on the sense amplifier and resets the arbiter output to zero at the start of quantization; NMOS transistors are added to the falling-edge arbiter.

6. The time-to-digital converter according to claim 1, wherein A serial output circuit stores the outputs of the arbitrators in the CTDC and FTDC after the FTDC quantization ends, and outputs data triggered by a specified clock; a TSPC register is adopted in the circuit, and two MOS transistors M1 and M2 are added thereto for sampling the results of the arbitrator; the input port J of the register is connected to the output of the arbitrator, and the input port T is connected to the FTDC quantization end flag signal R_SIG; when the flag signal R_SIG is equal to zero, the register reads the results of the arbitrator; when the flag signal R_SIG is equal to one, the register serially outputs data triggered by the clock CLK, and the signal TC is generated from the signal R_SIG.

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