Over-temperature protection circuit for a low-power chip

Abstract

The present invention provides an over-temperature protection circuit for a low-power chip, comprising: a first current mirror, a second current mirror, a PMOS transistor PM3, NMOS transistors NM1, NM2, NM3, NM4, bipolar transistors Q1, Q2, an operational amplifier AMP, inverters INV1 and INV2. The operational amplifier AMP is used as a comparator. The non-inverting input terminal of the operational amplifier AMP is connected to the gate of the NMOS transistor NM1, the inverting input terminal is connected to a reference voltage Vref independent of temperature, and the output terminal is connected to the inverter INV1. The inverter INV1 and the inverter INV2 are connected in series. The output signal OVT_N of the inverter INV1 is input to the gate of the NMOS transistor NM3, and the output signal OVT_P of the inverter INV2 is input to the gate of the PMOS transistor PM3 and the gate of the NMOS transistor NM4. By comparing the voltage VNTAT at the non-inverting input terminal of the operational amplifier AMP with the voltage Vref at the inverting input terminal, the output signals OVT_N and OVT_P are controlled to be high level or low level, thereby changing the on-off states of the PMOS transistor PM3, the NMOS transistor NM3 and the NMOS transistor NM4, so that the chip operates normally when the temperature does not exceed the over-temperature point, and the chip is protected and turned off when the temperature exceeds the over-temperature point.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more specifically, to an over-temperature protection circuit for a low-power chip. Background Art

[0002] The over-temperature protection circuit of the chip is a commonly used protection circuit that needs to be in the on state all the time. If the chip continues to work in a high-temperature environment, there will be a risk of burning the internal components of the chip. Therefore, the over-temperature protection circuit provides protection action when the temperature is too high, and has a certain hysteresis function. When the temperature drops to a safe value, the chip can work normally again.

[0003] There are two types of over-temperature protection circuits for traditional chips. The first type is Figure 1 As shown, a current (I CTAT) that is positively correlated with temperature flows through two resistors through a current mirror image, thereby generating a voltage (VCTAT) that is negatively correlated with temperature. The operational amplifier AMP used as a comparator is connected to a bandgap reference voltage (VBG) that is independent of temperature at the same phase end, and a voltage with a negative temperature coefficient at the opposite phase end. The output OVT of the operational amplifier is connected to the gate end of the NMOS tube NM1, and OVT also serves as an over-temperature protection signal. When the temperature is relatively low and no over-temperature occurs, VBG <VCTAT,OVT为低电平,NM1截止,电阻R1接入电路当中,芯片正常工作;当温度持续上升并超过过温点时,VBG> VCTAT, OVT jumps from low level to high level, NM1 is turned on, resistor R1 is short-circuited, and the chip is protected and turned off. Since resistor R1 is short-circuited, only when the temperature drops below the over-temperature point, OVT returns to low level, allowing the chip to work normally again.

[0004] The second common chip over-temperature protection circuit, such as Figure 2 As shown, the circuit utilizes the negative temperature characteristic of the base-emitter voltage VBE of the transistor Q1 to replace the VCTAT voltage in the traditional structure, wherein I Bias is required to have a zero-temperature characteristic, thereby generating a reference voltage input to the inverting terminal of the operational amplifier.

[0005] However, the over-temperature protection circuit of the chip in the prior art is not applicable in low-power application environments. In low-power applications, the current must be very small. At this time, a relatively high voltage needs to be generated by flowing through a resistor, which will inevitably require the resistance value of the resistor to become very large, and the area of the layout will inevitably increase dramatically.

[0006] In view of this, in order to solve the problem that in a low-power application environment, that is, the over-temperature protection circuit in a low-power chip, if designed according to the existing technology, the layout area is bound to be too large, the present invention proposes an over-temperature protection circuit with a simple structure, extremely low power consumption, and no need for resistors, which greatly reduces the layout area. Summary of the Invention

[0007] The object of the present invention is to provide an over-temperature protection circuit for a low-power chip, which has a simple structure, extremely low power consumption, no need for resistors, and greatly reduces the layout area.

[0008] An over-temperature protection circuit for a low-power chip, comprising: a first current mirror, a second current mirror, a PMOS transistor PM3, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an NMOS transistor NM4, a bipolar junction transistor Q1, a bipolar junction transistor Q2, an operational amplifier AMP, an inverter INV1 and an inverter INV2. The PMOS transistors PM1 and PM4 form a first current mirror with a cascode structure. The PMOS transistors PM2 and PM5 form a second current mirror with a cascode structure. The first current mirror is connected to the power supply through the source of the PMOS transistor PM1. The first current mirror is connected to the drain of the PMOS transistor PM3 through the source of the PMOS transistor PM4. The source of the PMOS transistor PM3 is connected to the power supply. The second current mirror is connected to the drain of the NMOS transistor NM1 through the drain of the PMOS transistor PM2. The second current mirror is connected to the drain of the PMOS transistor PM4 through the source of the PMOS transistor PM5. The second current mirror is connected to the drain of the NMOS transistor NM1 through the drain of the PMOS transistor PM5. The NMOS transistors NM1, NM2 and NM3 are connected in series. The source of the NMOS transistor NM3 is grounded. The bipolar junction transistors Q1, Q2 and the NMOS transistor NM4 are connected in series. The collector of the bipolar junction transistor Q1 is connected to the source of the NMOS transistor NM1. The source of the NMOS transistor NM4 is grounded. The operational amplifier AMP is used as a comparator. The non-inverting input terminal of the operational amplifier AMP is connected to the gate of the NMOS transistor NM1, with a voltage of VNTAT. The inverting input terminal of the operational amplifier AMP is connected to a reference voltage Vref independent of temperature. The output terminal of the operational amplifier AMP is connected to the inverter INV1. The inverter INV1 and the inverter INV2 are connected in series. The output signal OVT_N of the inverter INV1 is input to the gate of the NMOS transistor NM3. The output signal OVT_P of the inverter INV2 is input to the gate of the PMOS transistor PM3 and the gate of the NMOS transistor NM4. By comparing the voltage VNTAT at the non-inverting input terminal and the voltage Vref at the inverting input terminal of the operational amplifier AMP, the output signals OVT_N and OVT_P are controlled to be high or low levels, thereby changing the on-off states of the PMOS transistor PM3, the NMOS transistor NM3 and the NMOS transistor NM4, so that the chip operates normally when the temperature does not exceed the over-temperature point and the chip is protected and turned off when the temperature exceeds the over-temperature point.

[0009] In some embodiments, all MOS transistors are enhancement-mode MOS transistors, and all MOS transistors operate in the subthreshold region.

[0010] In some embodiments, PMOS transistor PM1 and PMOS transistor PM4 form a first current mirror with a cascode structure, and PMOS transistor PM2 and PMOS transistor PM5 form a second current mirror with a cascode structure, which is used to improve the replication accuracy of the current mirror. The ratio of the aspect ratio of PMOS transistor PM1 to the aspect ratio of PMOS transistor PM4 in the first current mirror is 1:M, and the ratio of the aspect ratio of PMOS transistor PM2 to the aspect ratio of PMOS transistor PM5 in the second current mirror is 1:M, where M > 0. The gates of PMOS transistor PM1 and PMOS transistor PM4 are connected to the voltage bias of VB1, and the gates of PMOS transistor PM2 and PMOS transistor PM5 are connected to the voltage bias of VB2.

[0011] In some embodiments, PMOS transistor PM3, NMOS transistor NM3, and NMOS transistor NM4 are all MOS transistors used as switching transistors. The control signals of PMOS transistor PM3 and NMOS transistor NM4 are OVT_P, and the control signal of NMOS transistor NM3 is OVT_N.

[0012] In some embodiments, NMOS transistor NM1 and NMOS transistor NM2 have the same aspect ratio and are connected in a diode structure, and transistor Q1 and transistor Q2 have the same emitter area and are also connected in a diode structure.

[0013] In some embodiments, signals OVT_N and OVT_P are used to change the on / off states of PMOS transistor PM3, NMOS transistor NM3, and NMOS transistor NM4 to generate hysteresis, and are also input to the backend digital circuit to provide over-temperature protection actions.

[0014] In some embodiments, when the temperature does not exceed the over-temperature point, the voltage at the non-inverting terminal of operational amplifier AMP is greater than the voltage at the inverting terminal, VNTAT > Vref. The output of operational amplifier AMP is high level, signal OVT_N is low level, and signal OVT_P is high level. At this time, NMOS transistor NM4 is conducting, NMOS transistor NM3 and PMOS transistor PM3 are cut off, the branch where NMOS transistor NM2 is located is open (disconnected), and transistor Q1 and transistor Q2 are connected to the circuit. The current flowing through NMOS transistor NM1 is (M + 1)I D , and the chip operates normally.

[0015] Further, when the temperature is relatively low and over-temperature does not occur, the expression of the voltage VNTAT at the non-inverting terminal of operational amplifier AMP is S1:

[0016]

[0017] where V GS1 is the voltage between the gate and source of NMOS transistor NM1, and V BEis the voltage between the emitter and the base of the triode. The voltages between the emitter and the base of triode Q1 and triode Q2 are approximately equal, and are uniformly represented by V BE ; V th1 is the threshold voltage of NMOS transistor NM1, n is the subthreshold slope correction factor, V T is the thermal voltage, I D is the current flowing through NMOS transistor NM1 at this time, W is the conductive channel width of NMOS transistor NM1, L is the conductive channel length of NMOS transistor NM1, μ n is the electron mobility, C OX is the gate oxide capacitance per unit area of NMOS transistor NM1.

[0018] In some embodiments, when the temperature rises above the over-temperature point, the voltage at the non-inverting terminal of the operational amplifier AMP < the voltage at the inverting terminal, VNTAT < Vref. The output of the operational amplifier AMP jumps from high level to low level, the signal OVT_N jumps from low level to high level, and the signal OVT_P jumps from high level to low level, so as to indicate that the system is over-temperature and trigger a protection action. At this time, NMOS transistor NM4 is cut off, NMOS transistor NM3 and PMOS transistor PM3 are turned on, NMOS transistor NM2 is connected to the circuit, and the branches where triode Q1 and triode Q2 are located are open (disconnected). The current flowing through NMOS transistor NM1 is I D , and the chip is protected and shut down.

[0019] Furthermore, when the temperature drops below the over-temperature point, the signal OVT_N is at low level, the signal OVT_P is at high level, and the chip resumes normal operation.

[0020] Furthermore, when the temperature rises above the over-temperature point, the expression of the voltage VNTAT at the non-inverting terminal of the operational amplifier AMP is S2:

[0021]

[0022] wherein, V GS1 is the voltage between the gate and the source of NMOS transistor NM1, V GS2 is the voltage between the gate and the source of NMOS transistor NM2, V th is the threshold voltage of the NMOS transistor. The threshold voltages of NMOS transistor NM1 and NMOS transistor NM2 are approximately equal, and are uniformly represented by V th ; n is the subthreshold slope correction factor, V T is the thermal voltage, M is the ratio of the aspect ratio of PMOS transistor PM1 to PMOS transistor PM4 in the first current mirror or the ratio of the aspect ratio of PMOS transistor PM2 to PMOS transistor PM5 in the second current mirror, μn is the electron mobility. The gate oxide capacitance per unit area of NMOS transistor NM1 is equal to that of NMOS transistor NM2, and is uniformly represented by C OX The conductive channel width of NMOS transistor NM1 is equal to that of NMOS transistor NM2, and is uniformly represented by W. The conductive channel length of NMOS transistor NM1 is equal to that of NMOS transistor NM2, and is uniformly represented by L.

[0023] Furthermore, it can be seen from expression S2 that by controlling the value of M, the amount of hysteresis can be controlled. The larger M is, the smaller the amount of hysteresis; the smaller M is, the larger the amount of hysteresis.

[0024] Furthermore, when the temperature continues to rise and does not exceed the over-temperature point T H , the voltage VNTAT changes according to the expression of VNTAT1, and the chip operates normally. When the temperature continues to rise to the over-temperature point T H , at this time Vref = VNTAT. If the temperature continues to rise, the voltage VNTAT changes according to the expression of VNTAT2, and at the same time indicates that the system has overheated, causing the chip to take corresponding protection actions. If you want to return to the state of Vref = VNTAT again, the temperature must drop to T L , and the chip can operate normally again.

[0025] The circuit proposed by the present invention is entirely composed of common MOS transistors and bipolar transistors, has no special requirements for the process, uses few devices, has few circuit branches, and has a simple structure. In the circuit proposed by the present invention, the currents used by the first current mirror and the second current mirror are both in the nanoampere level, and the operational amplifier also uses a nanoampere-level bias current, so the overall power consumption of the circuit is very low, achieving the purpose of low power consumption. At the same time, no resistor is used in the circuit proposed by the present invention, solving the problem of large resistor layout area in low-power chips. By utilizing the temperature characteristics of MOS transistor VGS and bipolar transistor VBE operating in the subthreshold region, combined with the on-off of the switching transistor, low-power over-temperature protection and hysteresis functions are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is an over-temperature protection circuit of a chip in the prior art.

[0027] Figure 2 is another over-temperature protection circuit of a chip in the prior art.

[0028] Figure 3 is the over-temperature protection circuit of the low-power chip of the present application.

[0029] Figure 4 is the working process schematic diagram of the over-temperature protection circuit of the low-power chip of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following embodiments are described to assist in understanding the present invention. It is not intended and should not in any way be construed as limiting the scope of protection of the present invention.

[0031] In the following description, those skilled in the art will recognize that throughout this discussion, components may be described as separate functional units (which may include sub-units), but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or integrated together (including being integrated within a single system or component).

[0032] In addition, the connections between components or systems within the drawings are not intended to be limited to direct connections. Instead, the data between these components may be modified, reformatted, or otherwise changed by intermediate components. Additionally, additional or fewer connections may be used. It should also be noted that the terms "coupled", "connected", or "input" should be understood to include direct connections, indirect connections through one or more intermediate devices, and wireless connections.

[0033] Embodiment 1:

[0034] An over-temperature protection circuit for a low-power chip, such as Figure 3 - Figure 4As shown, it includes: a first current mirror, a second current mirror, PMOS transistor PM3, NMOS transistors NM1, NM2, NM3, NM4, bipolar transistors Q1, Q2, operational amplifier AMP, inverter INV1, and inverter INV2. PMOS transistors PM1 and PM4 form a first current mirror with a cascode structure. PMOS transistors PM2 and PM5 form a second current mirror with a cascode structure. The first current mirror is connected to the power supply through the source of PMOS transistor PM1. The first current mirror is connected to the drain of PMOS transistor PM3 through the source of PMOS transistor PM4. The source of PMOS transistor PM3 is connected to the power supply. The second current mirror is connected to the drain of NMOS transistor NM1 through the drain of PMOS transistor PM2. The second current mirror is connected to the drain of PMOS transistor PM4 through the source of PMOS transistor PM5. The second current mirror is connected to the drain of NMOS transistor NM1 through the drain of PMOS transistor PM5. NMOS transistors NM1, NM2, and NM3 are connected in series. The source of NMOS transistor NM3 is grounded. Bipolar transistors Q1, Q2, and NMOS transistor NM4 are connected in series. The collector of bipolar transistor Q1 is connected to the source of NMOS transistor NM1. The source of NMOS transistor NM4 is grounded. Operational amplifier AMP is used as a comparator. The non-inverting input terminal of operational amplifier AMP is connected to the gate of NMOS transistor NM1, with a voltage of VNTAT. The inverting input terminal of operational amplifier AMP is connected to a temperature-independent reference voltage Vref. The output terminal of operational amplifier AMP is connected to inverter INV1. Inverter INV1 and inverter INV2 are connected in series. The output signal OVT_N of inverter INV1 is input to the gate of NMOS transistor NM3. The output signal OVT_P of inverter INV2 is input to the gate of PMOS transistor PM3 and the gate of NMOS transistor NM4. By comparing the voltage VNTAT at the non-inverting input terminal and the voltage Vref at the inverting input terminal of operational amplifier AMP, the output signals OVT_N and OVT_P are controlled to be high or low levels, thereby changing the on / off states of PMOS transistor PM3, NMOS transistor NM3, and NMOS transistor NM4, enabling the chip to operate normally when the temperature does not exceed the over-temperature point and protecting and shutting down the chip when the temperature exceeds the over-temperature point.

[0035] All MOS transistors are enhancement-mode MOS transistors, and all MOS transistors operate in the subthreshold region. PMOS transistor PM1 and PMOS transistor PM4 form a first current mirror with a cascode structure, and PMOS transistor PM2 and PMOS transistor PM5 form a second current mirror with a cascode structure to improve the replication accuracy of the current mirror. The ratio of the aspect ratio of PMOS transistor PM1 to the aspect ratio of PMOS transistor PM4 in the first current mirror is 1:M, and the ratio of the aspect ratio of PMOS transistor PM2 to the aspect ratio of PMOS transistor PM5 in the second current mirror is 1:M, where M > 0. The gates of PMOS transistor PM1 and PMOS transistor PM4 are connected to the voltage bias of VB1, and the gates of PMOS transistor PM2 and PMOS transistor PM5 are connected to the voltage bias of VB2. PMOS transistor PM3, NMOS transistor NM3, and NMOS transistor NM4 are all MOS transistors used as switching transistors. The control signals of PMOS transistor PM3 and NMOS transistor NM4 are OVT_P, and the control signal of NMOS transistor NM3 is OVT_N. NMOS transistor NM1 and NMOS transistor NM2 have the same aspect ratio and are connected in a diode structure, and transistor Q1 and transistor Q2 have the same emitter area and are also connected in a diode structure. Signals OVT_N and OVT_P are used to change the on / off states of PMOS transistor PM3, NMOS transistor NM3, and NMOS transistor NM4 to generate hysteresis, and are also input to the subsequent digital circuit to provide over-temperature protection actions.

[0036] When the temperature does not exceed the over-temperature point, the voltage at the non-inverting input terminal of operational amplifier AMP is greater than the voltage at the inverting input terminal, VNTAT > Vref. The output of operational amplifier AMP is at a high level, signal OVT_N is at a low level, and signal OVT_P is at a high level. At this time, NMOS transistor NM4 is conducting, NMOS transistor NM3 and PMOS transistor PM3 are cut off, the branch where NMOS transistor NM2 is located is open (disconnected), and transistor Q1 and transistor Q2 are connected to the circuit. The current flowing through NMOS transistor NM1 is (M + 1)I D , and the chip operates normally. When the temperature is relatively low and over-temperature does not occur, the expression for the voltage VNTAT at the non-inverting input terminal of operational amplifier AMP is S1:

[0037]

[0038] where, V GS1 is the voltage between the gate and source of NMOS transistor NM1, V BE is the voltage between the emitter and base of the transistor. The voltages between the emitter and base of transistor Q1 and transistor Q2 are approximately equal and are uniformly represented by V BE . V th1 is the threshold voltage of NMOS transistor NM1, n is the subthreshold slope correction factor, V Tis the thermal voltage, I D is the current flowing through NMOS transistor NM1 at this time, W is the conductive channel width of NMOS transistor NM1, L is the conductive channel length of NMOS transistor NM1, μ n is the electron mobility, C OX is the gate oxide capacitance per unit area of NMOS transistor NM1.

[0039] When the temperature rises above the over-temperature point, the voltage at the non-inverting input of operational amplifier AMP < the voltage at the inverting input, VNTAT < Vref, the output of operational amplifier AMP jumps from high level to low level, the signal OVT_N jumps from low level to high level, and the signal OVT_P jumps from high level to low level, so as to indicate system over-temperature and trigger a protection action. At this time, NMOS transistor NM4 is cut off, NMOS transistors NM3 and PMOS transistor PM3 are turned on, NMOS transistor NM2 is connected to the circuit, and the branches where transistor Q1 and transistor Q2 are located are open (disconnected). The current flowing through NMOS transistor NM1 is I D , and the chip is protected and turned off. When the temperature drops below the over-temperature point, the signal OVT_N is at low level, the signal OVT_P is at high level, and the chip resumes normal operation. When the temperature rises above the over-temperature point, the expression of the voltage VNTAT at the non-inverting input of operational amplifier AMP is S2:

[0040]

[0041] Among them, V GS1 is the voltage between the gate and source of NMOS transistor NM1, V GS2 is the voltage between the gate and source of NMOS transistor NM2, V th is the threshold voltage of the NMOS transistor. The threshold voltage of NMOS transistor NM1 is approximately equal to the threshold voltage of NMOS transistor NM2, and they are uniformly represented by V th to represent, n is the sub-threshold slope correction factor, V T is the thermal voltage, M is the ratio of the aspect ratio of PMOS transistor PM1 in the first current mirror to the aspect ratio of PMOS transistor PM4 in the first current mirror or the ratio of the aspect ratio of PMOS transistor PM2 in the second current mirror to the aspect ratio of PMOS transistor PM5 in the second current mirror, μ n is the electron mobility. The gate oxide capacitance per unit area of NMOS transistor NM1 is equal to the gate oxide capacitance per unit area of NMOS transistor NM2, and they are uniformly represented by C OX to represent. The conductive channel width of NMOS transistor NM1 is equal to the conductive channel width of NMOS transistor NM2, and they are uniformly represented by W. The conductive channel length of NMOS transistor NM1 is equal to the conductive channel length of NMOS transistor NM2, and they are uniformly represented by L.

[0042] As can be seen from the expression S2, by controlling the value of M, the magnitude of the hysteresis can be controlled. The larger M is, the smaller the hysteresis is; the smaller M is, the larger the hysteresis is. When the temperature continues to rise and does not exceed the over-temperature point T H the voltage VNTAT changes according to the expression of VNTAT1, and the chip works normally. When the temperature continues to rise to the over-temperature point T H at this time, Vref = VNTAT. If the temperature continues to rise, the voltage VNTAT changes according to the expression of VNTAT2, and at the same time indicates that the system has overheated, causing the chip to take corresponding protection actions. If you want to return to the state of Vref = VNTAT again, the temperature must drop to T L before the chip can work normally again.

[0043] Although the present invention has disclosed multiple aspects and embodiments, other aspects and embodiments will be obvious to those skilled in the art. Without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. The multiple aspects and embodiments disclosed in the present invention are only used for illustrative purposes and are not intended to limit the present invention. The actual protection scope of the present invention is subject to the claims.

Claims

1. An over-temperature protection circuit for a low-power chip, characterized in that, Including: A first current mirror, a second current mirror, PMOS transistor PM3, NMOS transistors NM1, NM2, NM3, NM4, bipolar transistors Q1, Q2, operational amplifier AMP, inverter INV1 and inverter INV2. PMOS transistors PM1 and PM4 form a first current mirror with a cascode structure, and PMOS transistors PM2 and PM5 form a second current mirror with a cascode structure. The first current mirror is connected to the power supply through the source of PMOS transistor PM1, and the first current mirror is connected to the drain of PMOS transistor PM3 through the source of PMOS transistor PM4. The source of PMOS transistor PM3 is connected to the power supply. The second current mirror is connected to the drain of NMOS transistor NM1 through the drain of PMOS transistor PM2, the second current mirror is connected to the drain of PMOS transistor PM4 through the source of PMOS transistor PM5, and the second current mirror is connected to the drain of NMOS transistor NM1 through the drain of PMOS transistor PM5. NMOS transistors NM1, NM2 and NM3 are connected in series; the source of NMOS transistor NM3 is grounded; bipolar transistors Q1, Q2 and NMOS transistor NM4 are connected in series. The emitter of bipolar transistor Q1 is connected to the source of NMOS transistor NM1, and the source of NMOS transistor NM4 is grounded. The operational amplifier AMP is used as a comparator. The non-inverting input terminal of the operational amplifier AMP is connected to the gate of NMOS transistor NM1 with a voltage of VNTAT. The inverting input terminal of the operational amplifier AMP is connected to a temperature-independent reference voltage Vref. The output terminal of the operational amplifier AMP is connected to the inverter INV1. The inverter INV1 and the inverter INV2 are connected in series. The output signal OVT_N of the inverter INV1 is input to the gate of NMOS transistor NM3, and the output signal OVT_P of the inverter INV2 is input to the gate of PMOS transistor PM3 and the gate of NMOS transistor NM4. By comparing the voltage VNTAT at the non-inverting input terminal and the voltage Vref at the inverting input terminal of the operational amplifier AMP, the output signals OVT_N and OVT_P are controlled to be high or low levels, thereby changing the on-off states of PMOS transistor PM3, NMOS transistors NM3 and NM4, so that the chip operates normally when the temperature does not exceed the over-temperature point and the chip is protected and turned off when the temperature exceeds the over-temperature point.

2. The over-temperature protection circuit of the low-power chip according to claim 1, characterized in that All PMOS and NMOS transistors are enhancement-mode MOS transistors, and all PMOS and NMOS transistors operate in the subthreshold region.

3. The over-temperature protection circuit of the low-power chip according to claim 1, characterized in that, The ratio of the aspect ratio of PMOS transistor PM1 to the aspect ratio of PMOS transistor PM4 in the first current mirror is 1:M. The ratio of the aspect ratio of PMOS transistor PM2 to the aspect ratio of PMOS transistor PM5 in the second current mirror is 1:M, where M > 0. The gates of PMOS transistor PM1 and PMOS transistor PM4 are connected to the voltage bias of VB1, and the gates of PMOS transistor PM2 and PMOS transistor PM5 are connected to the voltage bias of VB2.

4. The over-temperature protection circuit of the low-power chip according to claim 1, characterized in that, PMOS transistor PM3, NMOS transistors NM3 and NM4 are all MOS transistors used as switching transistors. The control signals of PMOS transistor PM3 and NMOS transistor NM4 are OVT_P, and the control signal of NMOS transistor NM3 is OVT_N.

5. The over-temperature protection circuit of the low-power chip according to claim 1, characterized in that, NMOS transistors NM1 and NM2 have the same aspect ratio and are connected in a diode structure. Transistors Q1 and Q2 have the same emitter area and are also connected in a diode structure.

6. The over-temperature protection circuit of the low-power chip according to claim 1, characterized in that When the temperature does not exceed the overtemperature point, the voltage at the non-inverting terminal of the operational amplifier AMP is greater than the voltage at the inverting terminal, VNTAT > Vref. The output of the operational amplifier AMP is at a high level, the signal OVT_N is at a low level, and the signal OVT_P is at a high level. At this time, the NMOS transistor NM4 is turned on, the NMOS transistor NM3 and the PMOS transistor PM3 are turned off, the branch where the NMOS transistor NM2 is located is open, the triodes Q1 and Q2 are connected to the circuit, and the current flowing through the NMOS transistor NM1 is I D , and the chip operates normally.

7. The over-temperature protection circuit of the low-power chip according to claim 6, characterized in that Furthermore, when the temperature is relatively low and over-temperature has not occurred, the expression for the voltage VNTAT at the non-inverting terminal of operational amplifier AMP is S1: （S1） Among them, V GS1 is the voltage between the gate and the source of the NMOS transistor NM1, V BE is the voltage between the emitter and the base of the triode. The voltages between the emitter and the base of the triode Q1 and the triode Q2 are approximately equal and are uniformly represented by V BE . V th1 is the threshold voltage of the NMOS transistor NM1, n is the subthreshold slope correction factor, V T is the thermal voltage, I D is the current flowing through the NMOS transistor NM1 at this time, W is the conductive channel width of the NMOS transistor NM1, L is the conductive channel length of the NMOS transistor NM1, is the electron mobility, is the gate oxide capacitance per unit area of the NMOS transistor NM1.

8. The over-temperature protection circuit of the low-power chip according to claim 1, characterized in that, When the temperature rises above the overtemperature point, the voltage at the non-inverting terminal of the operational amplifier AMP < the voltage at the inverting terminal, VNTAT < Vref, the output of the operational amplifier AMP jumps from high level to low level, the signal OVT_N jumps from low level to high level, and the signal OVT_P jumps from high level to low level, so as to indicate system overtemperature and trigger a protection action. At this time, the NMOS transistor NM4 is turned off, the NMOS transistor NM3 and the PMOS transistor PM3 are turned on, the NMOS transistor NM2 is connected to the circuit, the branches where the triodes Q1 and Q2 are located are open, and the current flowing through the NMOS transistor NM1 is (M + 1)I D , the chip is protected and shut down.

9. The over-temperature protection circuit of the low-power chip according to claim 8, characterized in that, When the temperature rises above the over-temperature point, the expression for the voltage VNTAT at the non-inverting terminal of operational amplifier AMP is S2: （S2） Among them, V GS1 is the voltage between the gate and the source of the NMOS transistor NM1, V GS2 is the voltage between the gate and the source of the NMOS transistor NM2, V th is the threshold voltage of the NMOS transistor. The threshold voltage of the NMOS transistor NM1 is approximately equal to the threshold voltage of the NMOS transistor NM2, and they are uniformly represented by V th . n is the subthreshold slope correction factor, V T is the thermal voltage, M is the ratio of the aspect ratio of the PMOS transistor PM1 in the first current mirror to the aspect ratio of the PMOS transistor PM4 in the first current mirror or the ratio of the aspect ratio of the PMOS transistor PM2 in the second current mirror to the aspect ratio of the PMOS transistor PM5 in the second current mirror, is the electron mobility. The gate oxide capacitance per unit area of the NMOS transistor NM1 is equal to the gate oxide capacitance per unit area of the NMOS transistor NM2, and they are uniformly represented by C OX . The conductive channel width of the NMOS transistor NM1 is equal to the conductive channel width of the NMOS transistor NM2, and they are uniformly represented by W. The conductive channel length of the NMOS transistor NM1 is equal to the conductive channel length of the NMOS transistor NM2, and they are uniformly represented by L.

10. The over-temperature protection circuit of the low-power chip according to claim 8, characterized in that, By controlling the value of M, the amount of hysteresis can be controlled. The larger M is, the smaller the hysteresis amount is, and the smaller M is, the larger the hysteresis amount is.

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