A method, apparatus, device, and storage medium for obtaining a clock constraint file

Abstract

Embodiments of the present application disclose a method, apparatus, device, and storage medium for obtaining a clock constraint file. The method includes: obtaining the clock architecture of a chip; wherein, the clock architecture includes multiple clock layers, and each of the clock layers includes at least one clock unit; sequentially obtaining the clock definitions of each of the clock layers according to the layer sequence of the clock architecture; and obtaining a clock constraint file according to the clock definitions of each of the clock layers. The technical solution provided by the embodiments of the present application uses the clock definitions of all the clock layers whose layer sequences are before the current clock layer as the main clock of the current clock layer, sequentially obtains the clock definitions of each clock layer, and then obtains a clock constraint file according to the clock definitions of each clock layer, realizing the automatic generation of the clock constraint file, saving the writing time, improving the development efficiency, shortening the R & D cycle of the chip, and at the same time, improving the accuracy and reliability of the writing of the clock constraint file.

Description

Technical Field

[0001] The embodiments of the present application relate to chip technology, and in particular, to a method, apparatus, device, and storage medium for obtaining a clock constraint file. Background Art

[0002] With the continuous progress of technology, chip technology has developed rapidly. While the volume of chips has been continuously reduced, their functionality has become increasingly powerful, and the complexity of chip design has increased exponentially, which poses higher requirements for the R & D efficiency of chips, especially for the R & D efficiency of ultra-large-scale chips.

[0003] As one of the core businesses of chip R & D, the development of clock constraint files occupies an extremely important position in chip R & D. The traditional clock constraint files rely on manual writing, which takes a large amount of writing time and has extremely low development efficiency, resulting in too long data delivery time of chips, increasing the R & D cycle of chips. At the same time, the manual writing method is very prone to writing errors, leading to timing chaos and inability to be used normally. Summary of the Invention

[0004] The embodiments of the present application provide a method, apparatus, device, and storage medium for obtaining a clock constraint file to automatically generate a clock constraint file for a chip.

[0005] In a first aspect, the embodiments of the present application provide a method for obtaining a clock constraint file, including:

[0006] Obtaining the clock architecture of a chip; wherein, the clock architecture includes multiple clock layers, and each clock layer includes at least one clock unit;

[0007] According to the layer sequence of the clock architecture, obtaining the clock definitions of each clock layer in sequence; wherein, if the current clock layer is the first clock layer, obtaining the clock definition of the current clock layer according to the initial startup data and the clock units of the current clock layer; if the current clock layer is a non-first clock layer, obtaining the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer;

[0008] Obtaining a clock constraint file according to the clock definitions of each clock layer.

[0009] In a second aspect, the embodiments of the present application provide an apparatus for obtaining a clock constraint file, including:

[0010] A clock architecture obtaining module, configured to obtain the clock architecture of a chip; wherein, the clock architecture includes multiple clock layers, and each clock layer includes at least one clock unit;

[0011] A clock definition acquisition module, configured to sequentially acquire the clock definitions of each of the clock layers according to the layer sequence of the clock architecture; wherein, if the current clock layer is the first clock layer, the clock definition of the current clock layer is acquired according to the initial startup data and the clock units of the current clock layer; if the current clock layer is a non-first clock layer, the clock definition of the current clock layer is acquired according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer;

[0012] A constraint file acquisition module, configured to acquire a clock constraint file according to the clock definitions of each of the clock layers.

[0013] Thirdly, an embodiment of the present application further provides a device, where the device includes:

[0014] One or more processors;

[0015] A storage device, configured to store one or more programs;

[0016] When the one or more programs are executed by the one or more processors, the one or more processors implement the method for acquiring a clock constraint file according to any embodiment of the present application.

[0017] Fourthly, an embodiment of the present application further provides a storage medium containing computer-executable instructions, and the computer-executable instructions implement the method for acquiring a clock constraint file according to any embodiment of the present application when executed by a computer processor.

[0018] The technical solution provided by the embodiment of the present application realizes the automatic generation of a clock constraint file by acquiring the clock architecture of a chip, using the clock definitions of all clock layers before the current clock layer as the main clock of the current clock layer, sequentially acquiring the clock definitions of each clock layer, and then acquiring the clock constraint file according to the clock definitions of each clock layer, saving the writing time, improving the development efficiency, shortening the R & D cycle of the chip, and at the same time, improving the accuracy and reliability of writing the clock constraint file. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A is a flowchart of a method for acquiring a clock constraint file provided by Embodiment 1 of the present application;

[0020] Figure 1B is a structural block diagram of a clock architecture provided by Embodiment 1 of the present application;

[0021] Figure 1C is a flowchart of a method for acquiring a clock constraint file provided by Specific Application Scenario 1 of the present application;

[0022] Figure 1DThis is a structural block diagram of a clock architecture provided by the specific application scenario 1 of this application;

[0023] Figure 2 This is a flowchart of a method for obtaining a clock constraint file provided in Embodiment 2 of the present application;

[0024] Figure 3 This is a structural block diagram of a device provided in Example 3 of the present application. DETAILED DESCRIPTION

[0025] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only the parts related to the present application, rather than all structures, are shown in the accompanying drawings.

[0026] Embodiment 1

[0027] Figure 1A A flowchart of a method for obtaining a clock constraint file provided in the first embodiment of the present application. The present embodiment can be applied to generating a clock constraint file of a chip. The method can be executed by a device for obtaining a clock constraint file in the embodiment of the present application. The device can be implemented by software and / or hardware and can generally be integrated in a chip. The method specifically includes the following steps:

[0028] S110, obtaining a clock architecture of a chip; wherein the clock architecture includes a plurality of clock layers, and each of the clock layers includes at least one clock unit.

[0029] The clock is a periodic pulse signal that is used to provide a time reference for data transmission between synchronously executed circuits in the chip to ensure that the various components in the chip operate synchronously. Depending on the functional requirements of the chip, the chip's transmission clock path may include different clock units, such as a phase-locked loop (PLL) clock unit, a pin clock unit, a divider clock unit, and an on-chip clock (OCC) unit; and each clock unit may also constitute a different clock layer according to the timing requirements. For example, the phase-locked loop clock unit and the pin clock unit are used as the source clock of the chip clock, and together constitute the first clock layer, that is, the first-layer clock layer. Therefore, the clock units and the clock layers to which the chip's transmission clock path includes constitute the overall clock architecture of the chip.

[0030] like Figure 1BAs shown, optionally, in the embodiments of the present application, the clock architecture includes three clock layers, namely the first-layer clock layer, the middle clock layer, and the last-layer clock layer; the first-layer clock layer includes a phase-locked loop clock unit and a pin clock unit; the middle clock layer includes a frequency divider clock unit; and the last-layer clock layer includes an on-chip clock unit.

[0031] For the chip to work properly, the external input signal needs to be synchronized with the internal oscillation signal. However, due to process reasons, the crystal oscillators commonly used in chips cannot provide high-frequency clock signals. When high-frequency clock signals are required, they can only be generated by corresponding voltage-controlled oscillators (VCOs). However, the high-frequency clock signals generated in this way are not stable. The phase-locked loop clock unit can provide stable and high-frequency clock signals for the chip to ensure the synchronization of the external input signal and the internal oscillation signal. Specifically, a phase-locked loop is a feedback control circuit that uses an externally input reference signal to control the frequency and phase of the oscillation signal inside the loop, realizing the automatic tracking of the output signal frequency to the input signal frequency. When the frequencies of the output signal and the input signal are equal, the output voltage of the phase-locked loop maintains a fixed phase difference with the input voltage, that is, the phases of the output voltage and the input voltage are locked, thus integrating the external clock signal and the internal clock signal to ensure the normal operation of high-frequency devices. The pin clock unit, that is, the interface clock of the chip, is used to obtain external clock signals. Specifically, the chip can be connected to an external signal input device, such as a crystal oscillator or a ceramic resonator, through the pin clock unit to obtain external clock signals. In the embodiments of the present application, the source of the external clock signals obtained by the pin clock unit is not specifically limited. The frequency divider clock unit is a filter network composed of capacitors and inductance coils, which is used to separate sound signals in different frequency bands. The on-chip clock unit, that is, the OCC circuit, is used to select and output high-speed clock signals or low-speed clock signals according to the working mode of the chip.

[0032] S120. According to the layer sequence of the clock architecture, obtain the clock definitions of each clock layer in sequence; among them, if the current clock layer is the first-layer clock layer, obtain the clock definition of the current clock layer according to the initial startup data and the clock unit of the current clock layer; if the current clock layer is a non-first-layer clock layer, obtain the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock unit of the current clock layer.

[0033] The layer sequence is arranged according to the timing of each clock layer and is also the generation order of the clock definitions of each clock layer, which can be set as needed. Taking the clock architecture in the above technical solution including three clock layers, namely the first-layer clock layer, the middle-layer clock layer, and the last-layer clock layer, as an example, the clock definition of the first-layer clock layer is generated first, then the clock definition of the middle-layer clock layer is generated, and finally the clock definition of the last-layer clock layer is generated.

[0034] Specifically, taking the first-layer clock layer including a phase-locked loop clock unit and a pin clock unit, the middle-layer clock layer including a frequency divider clock unit, and the last-layer clock layer including an on-chip clock unit in the above technical solution as an example; optionally, in the embodiment of the present application, if the current clock layer is the first-layer clock layer, then according to the initial startup data and the clock unit of the current clock layer, the clock definition of the current clock layer is obtained, including: if the current clock layer is the first-layer clock layer, then through the first data reading script matching the phase-locked loop clock unit and the pin clock unit, the unit names of the phase-locked loop clock unit and the pin clock unit are obtained, and according to the initial startup data, the clock definition of the first-layer clock layer is obtained. Different types of clock units correspond to different data reading scripts; the initial startup data includes a data coverage netlist and an original clock frequency point; among them, the data coverage netlist is a system file describing the chip structure information, including information such as the constituent units of the chip, the functions of each constituent unit, and the connection relationships between each constituent unit; the frequency point is an absolute frequency value, which is a number assigned to a fixed frequency (for example, 2.4 GHz), and the original clock frequency point is also the original clock frequency of the chip; the initial startup data can be obtained through a table file or through manual input by a programmer. The clock definition, that is, the definition of clock information, is used to describe the characteristics of the clock, such as the clock period and the clock frequency, etc.; the clock definition of the first-layer clock layer includes all the description information of the first-layer clock characteristics.

[0035] The clock definition of a non-first-layer clock layer is to use the clock definitions of all the clock layers before this clock layer in the layer sequence as the master clock, and combine the clock units included in this clock layer to obtain the clock definition of this clock layer; among them, the master clock is the clock in the chip that generates an accurate timing signal to control the frequencies of other clock units, so that the clock units in the chip operate synchronously.

[0036] Optionally, based on the above technical solution, if the current clock layer is not the first clock layer, the clock definition of the current clock layer is obtained according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock unit of the current clock layer, including: if the current clock layer is an intermediate clock layer, the division ratio coefficient and reference name of the frequency divider clock unit are obtained through a second data reading script matching the frequency divider clock unit; the clock definition of the first clock layer and the clock frequency and duty cycle of the frequency divider clock unit are obtained through a preset first anchor point; wherein, the preset first anchor point is located at the output port of the frequency divider clock unit; the clock definition of the intermediate clock layer is obtained according to the division ratio coefficient, reference name, clock frequency and duty cycle of the frequency divider clock unit, and the clock definition of the first clock layer. As shown in Table 1, the information of the frequency divider clock unit is stored in the form of an array, and the corresponding division ratio coefficient can be obtained according to the reference name; an anchor is a positioning device placed at a specific position. Through the link of the anchor, the data information at the specified position can be quickly obtained. In the embodiment of the present application, the preset first anchor point is located at the output port of the frequency divider clock unit. Through the preset first anchor point, the master clock of the intermediate clock layer, that is, the clock definition of the first clock layer, can be obtained, and the clock frequency and duty cycle of the frequency divider clock unit can also be obtained; wherein, the duty cycle is the proportion of the energization time in the total time within a pulse cycle.

[0037] Table 1

[0038] Number Reference Name Frequency Division Coefficient Duty Cycle 1 crm_div4_* 4 {1 5 9} 2 crm_div2_* 2 {1 3 5} 3 crm_div2_4* 2 4 {1 5 9}，{1 3 5} 4 crm_div2_4_8* 2 4 8 {1 9 17}，{1 5 9}，{1 3 5} 5 crm_div2_4_8_16* 2 4 8 16 {1 17 33}，{1 9 17}，{1 5 9}，{1 3 5} 6 crm_div_phase_sync* 2 4 {1 3 5}，{1 5 9} 7 crm_FixEvenDiv_* N {1N+1 2N+1} 8 crm_EvenDiv_vld_* 2 {1 3 5} 9 crm_IntDiv_vld_* 2 3 {1 3 5}，{1 4 7}

[0039] Optionally, based on the above technical solution, if the current clock layer is not the first clock layer, the clock definition of the current clock layer is obtained according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock unit of the current clock layer, further including: if the current clock layer is the last clock layer, the clock name of the on-chip clock unit is obtained through a third data reading script matching the on-chip clock unit; the clock definition of the first clock layer, the clock definition of the intermediate clock layer and the clock frequency and duty cycle of the on-chip clock unit are obtained through a preset second anchor point; wherein, the preset second anchor point is located in the buffer (Buf) and multiplexer (MUX) of the on-chip clock unit; the clock definition of the last clock layer is obtained according to the clock definition of the first clock layer, the clock definition of the intermediate clock layer, and the clock name, clock frequency and duty cycle of the frequency divider clock unit. Through the preset second anchor point, the master clock of the last clock layer, that is, the clock definitions of the first clock layer and the intermediate clock layer, can be obtained.

[0040] S130. Obtain a clock constraint file according to the clock definitions of each of the clock layers.

[0041] Through the output script, according to the clock definitions of each of the described clock layers obtained, a clock constraint file is obtained; wherein, the clock constraint file (SDC) constrains all clock characteristics of the chip, including clock frequency, clock period, duty cycle, and clock cell composition.

[0042] The technical solution provided by the embodiments of the present application, by obtaining the clock architecture of the chip, and using the clock definitions of all clock layers before the current clock layer as the master clock of the current clock layer, sequentially obtaining the clock definitions of each clock layer, and then obtaining the clock constraint file according to the clock definitions of each clock layer, realizes the automatic generation of the clock constraint file, saves the writing time, improves the development efficiency, shortens the R & D cycle of the chip, and at the same time, improves the accuracy and reliability of the writing of the clock constraint file.

[0043] Specific application scenario 1

[0044] Figure 1C Based on the above embodiments, specific application scenario 1 of the present application provides a method for obtaining a clock constraint file, which specifically includes:

[0045] S210. Obtain initial startup data.

[0046] S220. Run a static timing analysis (STA) tool.

[0047] Static timing analysis (STA) is a process of calculating the timing of digital integrated circuits, and the static timing analysis tool is an auxiliary software tool for performing static timing analysis. For example, TimeQuest timing analyzer, PrimeTime timing analyzer, and Timing Analysis View timing analysis device, etc.; in the embodiments of the present application, optionally, the type of the static timing analysis tool used is not specifically limited.

[0048] S230. Through the static timing analysis tool, according to the initial startup data, obtain the clock definition of the first clock layer.

[0049] As Figure 1D shown, the first clock layer includes a phase-locked loop clock unit and a pin clock unit.

[0050] S240. Use the clock definition of the first clock layer as the master clock, and according to the clock units of the intermediate clock layer, obtain the clock definition of the intermediate clock layer.

[0051] The middle clock layer includes a frequency divider clock unit; a multiplexer (MUX) is also connected between the frequency divider clock unit and the phase-locked loop clock unit, and its function is to combine multiple input signals into a single vector output signal.

[0052] S250, Timing update.

[0053] Timing update provides a timing basis for the change of the main clock.

[0054] S260, Define the clocks of the first clock layer and the middle clock layer as the main clock, and obtain the clock definition of the last clock layer according to the clock units of the last clock layer.

[0055] The last clock layer includes on-chip clock units.

[0056] S270, Output the clock constraint file through the output script.

[0057] The technical solution provided by the embodiments of the present application, through the iterative processing of the static timing analysis tool, uses the clock definitions of all clock layers before the current clock layer as the main clock of the current clock layer, obtains the clock definitions of each clock layer in turn, and then obtains the clock constraint file according to the clock definitions of each clock layer, realizing the automatic generation of the clock constraint file, saving the writing time, improving the development efficiency, shortening the R & D cycle of the chip, and at the same time, improving the accuracy and reliability of the writing of the clock constraint file.

[0058] Embodiment 2

[0059] Figure 2 It is a structural block diagram of an apparatus for obtaining a clock constraint file provided by Embodiment 2 of the present application. The apparatus specifically includes: a clock architecture obtaining module 210, a clock definition obtaining module 220, and a constraint file obtaining module 230.

[0060] The clock architecture obtaining module 210 is used to obtain the clock architecture of the chip; wherein, the clock architecture includes multiple clock layers, and each clock layer includes at least one clock unit;

[0061] The clock definition obtaining module 220 is used to sequentially obtain the clock definitions of each clock layer according to the layer sequence of the clock architecture; wherein, if the current clock layer is the first clock layer, obtain the clock definition of the current clock layer according to the initial startup data and the clock units of the current clock layer; if the current clock layer is a non-first clock layer, obtain the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer;

[0062] A constraint file acquisition module 230, configured to obtain a clock constraint file according to the clock definitions of each of the clock layers.

[0063] The technical solution provided by the embodiment of the present application obtains the clock architecture of the chip, uses the clock definitions of all clock layers before the current clock layer as the main clock of the current clock layer, obtains the clock definitions of each clock layer in sequence, and then obtains the clock constraint file according to the clock definitions of each clock layer, realizing the automatic generation of the clock constraint file, saving the writing time, improving the development efficiency, shortening the R & D cycle of the chip, and at the same time, improving the accuracy and reliability of the writing of the clock constraint file.

[0064] Optionally, on the basis of the above technical solution, the initial startup data includes a data coverage netlist and an original clock frequency point.

[0065] Optionally, on the basis of the above technical solution, the clock unit includes at least one of a phase-locked loop clock unit, a pin clock unit, a frequency divider clock unit, and an on-chip clock unit.

[0066] Optionally, on the basis of the above technical solution, the clock architecture includes three clock layers, namely a first-layer clock layer, an intermediate clock layer, and a last-layer clock layer; the first-layer clock layer includes a phase-locked loop clock unit and a pin clock unit; the intermediate clock layer includes a frequency divider clock unit; the last-layer clock layer includes an on-chip clock unit.

[0067] Optionally, on the basis of the above technical solution, the clock definition acquisition module 220 includes:

[0068] A first-layer clock layer clock definition acquisition unit, configured to obtain the unit names of the phase-locked loop clock unit and the pin clock unit through a first data reading script that matches the phase-locked loop clock unit and the pin clock unit, and obtain the clock definition of the first-layer clock layer according to the initial startup data.

[0069] Optionally, on the basis of the above technical solution, the clock definition acquisition module 220 further includes:

[0070] A frequency division coefficient and reference name acquisition unit, configured to obtain the frequency division coefficient and reference name of the frequency divider clock unit through a second data reading script that matches the frequency divider clock unit;

[0071] A first data acquisition unit, configured to obtain the clock definition of the first-layer clock layer and the clock frequency and duty cycle of the frequency divider clock unit through a preset first anchor point; wherein, the preset first anchor point is located at the output port of the frequency divider clock unit.

[0072] The intermediate clock layer clock definition acquisition unit is configured to acquire the clock definition of the intermediate clock layer according to the division coefficient, reference name, clock frequency, and duty cycle of the frequency divider clock unit, and the clock definition of the first clock layer.

[0073] Optionally, on the basis of the above technical solution, the clock definition acquisition module 220 further includes:

[0074] The clock name acquisition unit is configured to acquire the clock name of the on-chip clock unit through a third data reading script that matches the on-chip clock unit;

[0075] The second data acquisition unit is configured to acquire the clock definition of the first clock layer, the clock definition of the intermediate clock layer, and the clock frequency and duty cycle of the on-chip clock unit through a preset second anchor point; wherein, the preset second anchor point is located in the buffer area and data selector of the on-chip clock unit;

[0076] The last layer clock layer clock definition acquisition unit is configured to acquire the clock definition of the last layer clock layer according to the clock definition of the first clock layer, the intermediate layer clock definition, and the clock name, clock frequency, and duty cycle of the frequency divider clock unit.

[0077] The above device can execute the method for acquiring the clock constraint file provided in any embodiment of the present application, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be referred to the method provided in any embodiment of the present application.

[0078] Embodiment III

[0079] Figure 3 FIG. is a schematic structural diagram of a device provided in Embodiment III of the present application. Figure 3 FIG. shows a block diagram of an exemplary device 12 suitable for implementing the embodiments of the present application. Figure 3 The shown device 12 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0080] As Figure 3 shown, the device 12 is presented in the form of a general-purpose computing device. The components of the device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0081] Bus 18 represents one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, an Accelerated Graphics Port, a processor bus, or a local bus using any of the several bus architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0082] Device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by device 12, including both volatile and nonvolatile media, removable and non-removable media.

[0083] System memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Device 12 may further include other removable / non-removable, volatile / nonvolatile computer system storage media. By way of example only, storage system 34 can be used for reading and writing non-removable, nonvolatile magnetic media ( Figure 3 not shown and typically called a "hard disk drive"). Although Figure 3 not shown in the figures, a disk drive for reading and writing removable nonvolatile disks (such as a "floppy disk"), and an optical disk drive for reading and writing removable nonvolatile optical disks (such as a CD-ROM, DVD-ROM, or other optical media) can be provided. In these cases, each drive can be connected to bus 18 by one or more data media interfaces. System memory 28 can include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of the embodiments of the present application.

[0084] A program / utility 40 having a set (at least one) of program modules 42 can be stored, for example, in system memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may include an implementation of a network environment. Program modules 42 typically carry out the functions and / or methods of the embodiments described in the present application.

[0085] Device 12 can also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and can also communicate with one or more devices that enable a user to interact with the device 12, and / or communicate with any device that enables the device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 22. Moreover, the device 12 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the device 12 through the bus 18. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0086] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the method for obtaining a clock constraint file provided in the embodiments of the present application. That is: obtaining the clock architecture of the chip; wherein, the clock architecture includes multiple clock layers, and each of the clock layers includes at least one clock unit; according to the layer sequence of the clock architecture, obtaining the clock definitions of each of the clock layers in turn; wherein, if the current clock layer is the first clock layer, obtaining the clock definition of the current clock layer according to the initial startup data and the clock units of the current clock layer; if the current clock layer is not the first clock layer, obtaining the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer; obtaining the clock constraint file according to the clock definitions of each of the clock layers.

[0087] Embodiment 4

[0088] Embodiment 4 of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the method for obtaining a clock constraint file as described in any embodiment of the present application; the method includes:

[0089] Obtaining the clock architecture of the chip; wherein, the clock architecture includes multiple clock layers, and each of the clock layers includes at least one clock unit;

[0090] According to the layer sequence of the clock architecture, obtain the clock definitions of each clock layer in sequence; wherein, if the current clock layer is the first-layer clock layer, obtain the clock definition of the current clock layer according to the initial startup data and the clock units of the current clock layer; if the current clock layer is a non-first-layer clock layer, obtain the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer;

[0091] Obtain a clock constraint file according to the clock definitions of each clock layer.

[0092] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device.

[0093] The computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries the computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and this computer-readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device.

[0094] The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0095] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0096] Note that the above is only a preferred embodiment of this application and the technical principles applied. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of this application. Therefore, although this application has been described in more detail through the above embodiments, this application is not limited to the above embodiments. Without departing from the concept of this application, more other equivalent embodiments can be included, and the scope of this application is determined by the scope of the appended claims.

Claims

1. A method for obtaining a clock constraint file, characterized in that, Including: Obtain the clock architecture of the chip; wherein, the clock architecture includes multiple clock layers, and each clock layer includes at least one clock unit; According to the layer sequence of the clock architecture, obtain the clock definitions of each clock layer in sequence; wherein, if the current clock layer is the first clock layer, obtain the clock definition of the current clock layer according to the initial startup data and the clock units of the current clock layer; if the current clock layer is a non-first clock layer, obtain the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer; the initial startup data includes a data coverage netlist and an original clock frequency; Obtain a clock constraint file according to the clock definitions of each clock layer.

2. The method according to claim 1, characterized in that, The clock unit includes at least one of a phase-locked loop clock unit, a pin clock unit, a frequency divider clock unit, and an on-chip clock unit.

3. The method according to claim 2, wherein The clock architecture includes three clock layers, namely a first clock layer, an intermediate clock layer, and a last clock layer; the first clock layer includes a phase-locked loop clock unit and a pin clock unit; the intermediate clock layer includes a frequency divider clock unit; the last clock layer includes an on-chip clock unit.

4. The method according to claim 3, characterized in that, If the current clock layer is the first clock layer, obtaining the clock definition of the current clock layer according to the initial startup data and the clock units of the current clock layer includes: If the current clock layer is the first clock layer, obtain the unit names of the phase-locked loop clock unit and the pin clock unit through a first data reading script that matches the phase-locked loop clock unit and the pin clock unit, and obtain the clock definition of the first clock layer according to the initial startup data.

5. The method according to claim 4, characterized in that If the current clock layer is a non-first clock layer, obtaining the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer includes: If the current clock layer is the intermediate clock layer, obtain the division ratio coefficient and reference name of the frequency divider clock unit through a second data reading script that matches the frequency divider clock unit; Obtain the clock definition of the first clock layer, the clock frequency, and the duty cycle of the frequency divider clock unit through a preset first anchor point; wherein, the preset first anchor point is located at the output port of the frequency divider clock unit; Obtain the clock definition of the intermediate clock layer according to the division ratio coefficient, reference name, clock frequency, and duty cycle of the frequency divider clock unit, and the clock definition of the first clock layer.

6. The method according to claim 5, wherein If the current clock layer is a non-first clock layer, obtaining the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock units of the current clock layer further includes: If the current clock layer is the last clock layer, obtain the clock name of the on-chip clock unit through a third data reading script that matches the on-chip clock unit; Obtain the clock definition of the first clock layer, the clock definition of the intermediate clock layer, the clock frequency, and the duty cycle of the on-chip clock unit through a preset second anchor point; wherein, the preset second anchor point is located in the buffer area and data selector of the on-chip clock unit. Obtain the clock definition of the last clock layer according to the clock definition of the first-level clock layer, the clock definition of the intermediate clock layer, and the clock name, clock frequency, and duty cycle of the frequency divider clock unit.

7. An apparatus for obtaining a clock constraint file, characterized in that Including: A clock architecture acquisition module, configured to acquire the clock architecture of the chip; wherein, the clock architecture includes multiple clock layers, and each of the clock layers includes at least one clock unit; A clock definition acquisition module, configured to sequentially acquire the clock definitions of each of the clock layers according to the layer sequence of the clock architecture; wherein, if the current clock layer is the first-level clock layer, obtain the clock definition of the current clock layer according to the initial startup data and the clock unit of the current clock layer; if the current clock layer is a non-first-level clock layer, obtain the clock definition of the current clock layer according to the clock definitions of at least one clock layer before the current clock layer in the layer sequence and the clock unit of the current clock layer; the initial startup data includes a data coverage netlist and an original clock frequency point; A constraint file acquisition module, configured to acquire a clock constraint file according to the clock definitions of each of the clock layers.

8. An apparatus, characterized in that, The device includes: One or more processors; A storage device, configured to store one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method for acquiring a clock constraint file as described in any one of claims 1-6.

9. A storage medium containing computer-executable instructions, the computer-executable instructions being used to execute the method for acquiring a clock constraint file as described in any one of claims 1-6 when executed by a computer processor.

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