Semiconductor device and method of controlling a semiconductor device

Abstract

The present disclosure relates to semiconductor devices and methods for controlling semiconductor devices according to various embodiments. The area occupied by a switching circuit electrically connected to a memory cell is reduced to reduce the size of the semiconductor device. A semiconductor device according to one embodiment includes: a memory cell on a semiconductor substrate; and a semiconductor chip in which a switching circuit electrically connected to the memory cell is formed, wherein the switching circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film, the fourth gate insulating film having a thickness greater than the thickness of the third gate insulating film, wherein when current is applied to the memory cell, a voltage higher than the voltage applied to the second word gate is applied to the second coupling gate of the second transistor.

Description

[0001] Cross-reference to related applications

[0002] The entire disclosure of Japanese Patent Application No. 2019-204402, filed on November 12, 2019, including the specification, drawings and abstract, is incorporated herein by reference. Background Technology

[0003] The present invention relates to a semiconductor device and a method for controlling the semiconductor device, as well as the structure of a non-volatile memory device (such as a flash memory device).

[0004] For example, memory devices have a common source line for connecting the sources of multiple memory cells together.

[0005] In this regard, the following publicly available technologies exist.

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2014-29745 Summary of the Invention

[0007] Typically, high voltage is applied to memory cells of non-volatile memory devices (such as flash memory devices).

[0008] Recently, with the miniaturization of semiconductor devices, the power supply voltage of transistors used in logic circuits has been reduced.

[0009] Therefore, when using the output voltage of a common transistor in the control circuit, the following problem exists: even if the gate drive voltage is applied to the gate of a transistor with a high withstand voltage, it is not possible to make enough current flow between the source and drain.

[0010] Therefore, in order to allow sufficient current to flow to the transistor when the gate voltage cannot be set high, the gate width needs to be increased, which presents the following problem: the occupied area of ​​the transistor with high breakdown voltage increases.

[0011] In addition, as the area occupied by transistors with high breakdown voltage increases, the area occupied by the source driver circuit 154 also increases, resulting in the following problem: the chip size of non-volatile memory devices cannot be reduced.

[0012] According to one embodiment, the chip area of ​​a semiconductor device including a non-volatile memory device can be reduced. Attached Figure Description

[0013] Figure 1 This is a circuit diagram illustrating the configuration of a semiconductor device including a memory device according to a first embodiment of the present invention;

[0014] Figure 2 These are circuit diagrams of semiconductor devices used for comparison.

[0015] Figure 3 This is a plan view showing a high-voltage transistor as a comparative example;

[0016] Figure 4 This is a cross-sectional view showing a high-voltage transistor as a comparative example, and it is from... Figure 3 A cross-sectional view taken from O to P in the image;

[0017] Figure 5 This is a cross-sectional view of the device structure of the first switch and memory cell of the semiconductor device according to the first embodiment of the present invention, and is from... Figure 9 A cross-sectional view taken from Q to R in the diagram;

[0018] Figure 6 This is a first example of a circuit diagram of a semiconductor device in a previous stage prior to the configuration of the first embodiment;

[0019] Figure 7 This is a second example of a circuit diagram of a semiconductor device in a previous stage prior to the configuration of the first embodiment;

[0020] Figure 8 It is a timing diagram of the voltage applied to each gate electrode and the first switch of the memory cell of the first embodiment of the present invention;

[0021] Figure 9 This is a plan view showing the structure of the first switch and memory unit according to a first embodiment of the present invention;

[0022] Figure 10 This is a circuit diagram illustrating the configuration of a semiconductor device including a memory device according to a second embodiment of the present invention;

[0023] Figure 11 This is a plan view showing the structure of the first switch and memory unit according to a second embodiment of the present invention;

[0024] Figure 12 This is a circuit diagram of a memory device illustrating an example of the background art. Detailed Implementation

[0025] (Example 1)

[0026] <Circuit configuration of the semiconductor device according to the first embodiment>

[0027] Figure 1 This is a circuit diagram illustrating an example configuration of a semiconductor device 1 including a memory device according to a first embodiment of the present invention. Figure 1In the description of the first embodiment shown, the direction indicated by X is described as a horizontal direction (also referred to as the left-right direction or row direction), and the direction indicated by Y is described as a vertical direction (also referred to as the vertical direction or column direction). This also applies to the description of other circuit diagrams and plan views of semiconductor device 1.

[0028] The semiconductor device 1 of the first embodiment has a semiconductor substrate 2. The semiconductor substrate 2 includes a memory cell array 3, a column control circuit 4, a row control circuit 5, a source driver circuit 7, and a source driver control circuit 8.

[0029] The memory cell array 3 includes multiple memory cells 11 and 111, multiple bit lines 9 and 91, multiple source lines 10, multiple word lines 12, multiple coupling gate lines 13, and multiple erase gate lines 14. For ease of explanation, in... Figure 1 Descriptions of source lines 10, word lines 12, coupling gate lines 13, and multiple erase gate lines 14 in other rows are omitted. Multiple memory cells 11 are arranged in the X direction. Multiple memory cells 11 are also arranged in the Y direction. For ease of explanation, Figure 1 The description of the memory cells 11 in another row is omitted. Therefore, multiple memory cells 11 are arranged in a matrix in the memory cell array 3 in the X and Y directions. Each memory cell 11 includes a first transistor 15 formed on the semiconductor substrate 2. The first transistor 15 is composed of a first MOS transistor 16a and a second MOS transistor 17a. The bit electrode 27a of the first MOS transistor 16a is electrically connected to one of the multiple bit lines, bit line 9. The source electrode 18a of the second MOS transistor 17a is electrically connected to one of the multiple source lines, source line 10. An electrode on a side different from the bit electrode 27a of the first MOS transistor 16a is connected to an electrode on a side different from the source electrode 18a of the second MOS transistor 17a. Therefore, the first MOS transistor 16a and the second MOS transistor 17a are electrically connected.

[0030] The first MOS transistor 16a of memory cell 11 includes a word gate 19a. The word gate 19a of memory cell 11 is electrically connected to one of a plurality of word lines 12. The second MOS transistor 17a of memory cell 11 includes a coupling gate 20a. The coupling gate 20a of memory cell 11 is electrically connected to one of a plurality of coupling gate lines 13. For the first MOS transistor 16a, when a voltage equal to or higher than a threshold voltage (e.g., a voltage of 1.0V or greater based on the potential of the ground electrode GND. Unless otherwise stated, the potential will be described based on the ground electrode potential) is applied to the word gate 19a, the semiconductor substrate 2 beneath the word gate 19a becomes conductive. A path for current flow is then formed between the bit electrode 27a and the electrode on the opposite side. For the second MOS transistor 17a, when a voltage equal to or higher than a threshold voltage (e.g., a voltage of 1.5V or higher) is applied to the coupling gate 20a, the semiconductor substrate 2 beneath the coupling gate 20a becomes conductive. Then, a channel for current flow is formed between the source electrode 18a and the electrode on the opposite side. Therefore, the memory cell 11 can apply a current 21 between the bit electrode 27a and the source electrode 18a by applying a voltage equal to or higher than a threshold voltage to the word gate 19a and the coupling gate 20a. In the first embodiment, as described later, the gate insulating film of the second MOS transistor 17a of the memory cell 11 is thicker than the gate insulating film of the first MOS transistor 16a. Therefore, when current is applied to the memory cell 11, the voltage applied to the coupling gate 20a is higher than the voltage applied to the word gate 19a in order to increase the current flowing through the second MOS transistor 17a. The second MOS transistor 17a also includes a floating gate (not shown) between the coupling gate 20a and the semiconductor substrate. In the first embodiment, the current flowing through the second MOS transistor 17a of the memory cell 11 is changed by the charge stored in the floating gate. Therefore, by measuring the current 21 flowing between the bit electrode 27a and the source electrode 18a using the sensing circuit 6, data written to the memory cell 11 can be read.

[0031] The row control circuit 5 is disposed outside the memory cell array 3, for example, on the left side. The row control circuit 5 can be disposed adjacent to the memory cell array 3, and can also be disposed on the right side of the memory cell array 3. The row control circuit 5 includes various types of driver circuits. In a first embodiment, the row control circuit 5 includes a plurality of second word gate drivers D2 and a plurality of coupled gate drivers D3 (for convenience, in...). Figure 1(Descriptions of the second word gate driver D2 and coupling gate driver D3 for other rows are omitted). Multiple word lines 12 are electrically connected to their respective second word gate drivers D2. Therefore, voltage is supplied from the second word gate drivers D2 to the word gate 19a of the memory cell 11. Multiple coupling gate lines 13 are electrically connected to their respective coupling gate drivers D3. Therefore, voltage is supplied from the respective coupling gate drivers D3 to the coupling gate 20a of the memory cell 11.

[0032] Sensing circuit 6 and column control circuit 4 are electrically connected to memory cell array 3. Sensing circuit 6 and column control circuit 4 are disposed adjacent to memory cell array 3. Column control circuit 4 includes various types of driver circuits. In a first embodiment, column control circuit 4 includes multiple current supply circuits C1 and C2. Multiple bit lines 9 and 91 are electrically connected to corresponding current supply circuits C1 and C2, respectively. Therefore, current 21 is supplied from one of the corresponding current supply circuits C1 and C2 to the bit electrode 27a of memory cell 11.

[0033] Multiple source driver circuits 7 are electrically connected to the memory cell array 3. The source driver circuits 7 may be disposed externally adjacent to the memory cell array 3. Multiple source lines 10 are electrically connected to corresponding source driver circuits 7. Each source driver circuit 7 includes at least one first switch 22 and a second switch 23, a level shifting circuit 24, a first voltage terminal 25, and a ground electrode GND. The second switch 23 is electrically connected between the source line 10 corresponding to the first voltage terminal 25 and the source driver circuit 7. The second switch 23 can electrically connect or disconnect the first voltage terminal 25 and the source line 10 depending on the voltage applied to the gate electrode. Since the first voltage terminal 25 is the applied high voltage (e.g., 4.5V), the level shifting circuit 24 is electrically connected to the gate electrode of the second switch 23. Therefore, by applying a control voltage to the gate electrode of the second switch 23 via the level shifting circuit 24, the voltage applied to the first voltage terminal 25 can be applied to the source line 10 electrically connected to the second switch 23.

[0034] The first switch 22 includes a second transistor 26 formed on a semiconductor substrate 2. The second transistor 26 has the same configuration as the first transistor 15 of the memory cell and includes a first MOS transistor 16b and a second MOS transistor 17b. The bit electrode 27b of the first MOS transistor 16b is electrically connected to the ground electrode GND. The source electrode 18b of the second MOS transistor 17b is electrically connected to one of a plurality of source lines 10. An electrode on a side different from the bit electrode 27a of the first MOS transistor 16b is electrically connected to an electrode on a side different from the source electrode 18b of the second MOS transistor 17b. Therefore, by applying a voltage equal to or higher than the threshold voltage of the first MOS transistor 16b (e.g., 1.0V) to the word gate 19b of the first switch 22, the semiconductor substrate below the word gate 19b becomes conductive. Similarly, by applying a voltage equal to or higher than the threshold voltage of the second MOS transistor 17b (1.5V) to the coupling gate 20b of the second MOS transistor 17b of the first switch 22, the semiconductor substrate below the coupling gate 20b becomes conductive, forming a current flow channel between the source electrode 18b and the bit electrode 27b of the first switch 22. By forming this channel in the first switch 22, current 21 flows from the source line corresponding to the first switch 22 to the ground terminal GND.

[0035] In the first embodiment, the coupling gate 20b of the first switch 22 and the coupling gate 20a of the memory cell 11 corresponding to the first switch 22 are electrically connected via the coupling gate line 13. Therefore, in order for current to flow to the memory cell 11, when a voltage equal to or higher than the threshold voltage of the second MOS transistor 17a is applied to the coupling gate 20a of the memory cell 11, a voltage equal to or higher than the threshold voltage of the second MOS transistor 17b is also applied to the coupling gate 20b of the first switch 22. Therefore, when reading data from the memory cell 11, by applying a voltage equal to or higher than the threshold voltage of the first MOS transistor 16a to the word gate 19b of the first switch 22, the first switch 22 is in a conductive state, and the current 21 flowing through the memory cell 11 flows to the ground electrode GND through the source line 10. Furthermore, by applying a voltage lower than the threshold voltage of the first MOS transistor 16b to the word gate 19b of the first switch 22, the semiconductor substrate below the word gate 19b becomes non-conductive, and the first switch 22 becomes non-conductive. Therefore, the current 21 flowing through the source line 10 of the memory cell 11 can be cut off. For ease of explanation of the operation of the first switch 22, the memory cell 11 is described based on the erase state (i.e., the state in which no charge is injected into the floating gate).

[0036] Semiconductor device 1 includes a source driver control circuit 8 for supplying a control voltage to a source driver circuit 7. The source driver control circuit 8 includes a first word gate driver D1 and a second switch driver DH. The first word gate driver D1 supplies a control voltage to the word gate 19b of a first switch 22, and the second switch driver DH supplies a control signal to a second switch 23 via a level shifting circuit 24. Therefore, the word gate 19b of the first switch 22 is electrically connected to the output terminal of the first word gate driver D1, and the first switch 22 is controlled by the first word gate driver D1 to be conductive or non-conductive. Since the input terminal of the level shifting circuit 24, which is electrically connected to the gate of the second switch 23, is also electrically connected to the output terminal of the second switch driver DH, the second switch 23 is also controlled by the second switch driver DH to be conductive or non-conductive.

[0037] In the first embodiment, the first switch 22 has the same configuration as the memory cell 11. Since the memory cell 11 has a high voltage tolerance and a small size, the area occupied by the first switch 22 can be reduced. Therefore, in the first embodiment, the area occupied by the first switch 22 of the semiconductor device 1 can be reduced, and the area occupied by the source driver circuit 7 having the first switch 22 can also be reduced. Thus, in the first embodiment, the source driver circuit 7 of the semiconductor device 1 can be reduced, and the size of the semiconductor device 1 can be reduced.

[0038] <Comparative examples of semiconductor devices>

[0039] Next, a comparative example semiconductor device is described with the high breakdown voltage MOS transistor used as the first switch. Figure 2 This is a circuit diagram of the semiconductor device 1 of the comparative example. In the comparative example, a high breakdown voltage MOS transistor 30 is used in the first switch 221. In the semiconductor device 1 of the comparative example, the gate electrode 31 of the high breakdown voltage MOS transistor 30 is electrically connected to the word gate driver D1b of the first switch. Therefore, by supplying a voltage higher than the threshold voltage of the high breakdown voltage MOS transistor 30 from the word gate driver D1b to the gate electrode 31, the semiconductor substrate under the gate electrode 31 becomes conductive. Therefore, the source electrode 32 and drain electrode 33 of the high breakdown voltage MOS transistor 30 are electrically connected to the conductive power supply line 10 and the ground electrode GND. When a voltage lower than the threshold voltage of the high breakdown voltage MOS transistor 30 is supplied from the word gate driver D1b to the gate electrode 31, the semiconductor substrate under the gate electrode 31 becomes non-conductive. Therefore, since there is no conductivity between the source electrode 32 and the drain electrode 33 of the high breakdown voltage MOS transistor 30, there is insulation between the source line 10 and the ground electrode GND. Further details will be omitted. Figure 2Other descriptions of the circuit diagram for comparison examples are provided because they are different from those of the counterparts. Figure 1 The description is the same as that of the first embodiment.

[0040] Figure 3 This is a planar diagram showing a high breakdown voltage MOS transistor 30 of a comparative example. Figure 4 This is a cross-sectional view of a high breakdown voltage MOS transistor 30, a comparative example. Figure 4 It shows Figure 3 The high breakdown voltage MOS transistor 30 includes a semiconductor substrate 2, a high breakdown voltage gate dielectric film 36 formed on a first main surface 35 of the semiconductor substrate 2, and a gate electrode 31 formed on the high breakdown voltage gate dielectric film 36. The semiconductor substrate 2 is made of a semiconductor material (e.g., silicon) of a first conductivity type (e.g., p-type). The gate electrode 31 may be formed of a conductor (e.g., polysilicon). The high breakdown voltage gate insulating film 36 may be a thick insulator having a film thickness, such as being formed of silicon oxide. A source electrode 32 is disposed in a region near one end of the gate electrode 31 of the semiconductor substrate 2. A drain electrode 33 is disposed in a region near the other end of the gate electrode 31 of the semiconductor substrate 2. The source electrode 32 and the drain electrode 33 are constituted by a diffusion layer of a second conductivity type (e.g., n-type), wherein impurities are doped in the first main surface 35 of the semiconductor substrate. A second source electrode 40 disposed in a region of the source electrode 32 is formed by an impurity diffusion layer of the same second conductivity type as the source electrode 32. Furthermore, in the region of the drain electrode 33, a second drain electrode 41 is provided, which is formed of an impurity diffusion layer of the same second conductivity type as the drain electrode 33.

[0041] For a high breakdown voltage MOS transistor 30, in order to increase the dielectric strength between the source electrode 32 and the drain electrode 33, a sufficiently long length (gate length) L of the gate electrode 31 is required between the source electrode 32 and the drain electrode 33. Therefore, a high breakdown voltage MOS transistor 30 (such as...) Figure 3 As shown in the diagram, the length SX in the gate length direction increases. For a high breakdown voltage MOS transistor 30, in order to increase the dielectric strength between the gate electrode 31 and the semiconductor substrate 34, the thickness 42 of the gate insulating film 36 needs to be sufficiently thick. Therefore, compared with a transistor having a thin gate insulating film and not having a high breakdown voltage, the high breakdown voltage MOS transistor 30 cannot increase the amount of current 93 flowing from the source electrode 32 to the drain electrode 33. Typically, for a high breakdown voltage MOS transistor 30, in order to increase the amount of current flowing from the first source diffusion layer 32 to the first drain diffusion layer 33, the width W of the gate electrode 31 needs to be increased. Therefore, for a high breakdown voltage MOS transistor 30, the length SY in the width direction of the gate electrode 31 increases.

[0042] Therefore, in the comparative example of semiconductor device 1 where a high breakdown voltage MOS transistor 30 is used in the source driver circuit 7, the width and length of the gate electrode of the source driver circuit 7 increase, making it impossible to reduce the occupied area of ​​the semiconductor substrate 2. This results in a problem where semiconductor device 1 cannot be miniaturized.

[0043] <Considerations on semiconductor devices with improved first switches>

[0044] The inventors of this patent application considered making the first switch 22 smaller than a conventional high breakdown voltage MOS transistor 30 while simultaneously giving it high dielectric strength. Therefore, the inventors conceived of a design for arranging the first switch 22 of the semiconductor device 1, wherein the second transistor 26 has the same structure as the first transistor 15 constituting the memory cell 11. Figure 5 It shows Figure 1 A cross-sectional view of the device structure of the memory cell 11 and the first switch 22 in the semiconductor device 1. The semiconductor substrate 34 is made of a semiconductor material (e.g., silicon) of a first conductivity type (e.g., p-type). The memory cell 11 and the first switch 22 of the first embodiment have a first MOS transistor 16 (reference numeral 16 includes reference numerals 16a and 16b). Except as described below... Figure 5 Aside from the suffixes in the description, other references also use the above-described reference numerals (see attached figures 16 and 17). The first MOS transistor 16 comprises a semiconductor substrate 34, a word gate 19 (19 includes 19a and 19b), a first gate insulating film 43, and a bit electrode 27 (27 includes 27a and 27b). The second MOS transistor 17 comprises a semiconductor substrate 34, a floating gate 44, a second gate insulating film 45, a coupling gate 20 (20 includes 20a and 20b), and a source electrode 18 (18 includes 18a and 18b). The side of the first MOS transistor 16 different from the bit electrode 27 is positioned close to the side of the second MOS transistor 17 different from the source electrode 18. Unlike the bit electrode 27 and the source electrode 18, no high-concentration impurity diffusion layer is formed on the side of the first MOS transistor 16 different from the bit electrode 27 or on the side of the second MOS transistor 17 different from the source electrode 18. However, when a voltage equal to or higher than the threshold voltage is applied to each of the gates in the first MOS transistor 16 (word gate 19) and the second MOS transistor 17 (coupled gate 20), the conductive regions formed on the semiconductor substrate 34 below the word gate 19 and on the semiconductor substrate 34 of the coupled gate 20 are connected because the word gate 19 and the coupled gate 20 are close to each other. Therefore, current can flow between the source electrode 18 and the bit electrode 27. Thus, as... Figure 1 As shown, the first transistor 15 and the first switch 22 of the memory cell 11 are equivalent circuits to the circuits electrically connected to the first MOS transistor 16a (16b) and the second MOS transistor 17a (17b). The coupling gate 20 is insulated from the floating gate 44 by an interlayer insulating film 37. The memory cell 11 of the first embodiment stores 1 bit of data based on whether the amount of charge stored in the floating gate exceeds a predetermined amount. The current flowing through the second MOS transistor 17 is changed by the charge stored in the floating gate. Therefore, in the first embodiment, the data written to the memory cell 11 can be read by measuring the current 21 flowing between the in-place electrode 27 and the source electrode 18 in the sensing circuit 6. An erase gate 47 is formed on the source electrode 18 of the second MOS transistor 17 by an interlayer insulating film 46. In the first embodiment, the erase gate 47 is formed to be insulated from the floating gate 44 and the coupling gate 20. Since the erase gate 47 is formed close to the floating gate 44, by applying a high voltage to the erase gate 47, the charge stored in the floating gate 44 can be moved to an external circuit. Therefore, data stored in the memory cell 11 can be erased by applying a voltage to the erase gate 47.

[0045] The word gate 19, coupling gate 20, floating gate 44, and erase gate 47 may be formed of a conductor (e.g., polysilicon). The first gate insulating film 43, the second gate insulating film 45, and the interlayer insulating film 46 may be insulators, such as silicon oxide. The bit electrode 27 is disposed in a region near one end of the word gate 19 of the semiconductor substrate 34. The source electrode 18 is disposed in a region near one end of the coupling gate 20 of the semiconductor substrate 34. The source electrode 18 and the bit electrode 27 are formed of a diffusion layer of a second conductivity type (e.g., n-type) doped with impurities on the first main surface 35 of the semiconductor substrate 34.

[0046] Within the memory cell 11 and the first switch 22, the voltage applied between the source electrode 18 and the bit electrode 27 is distributed and applied to the first MOS transistor 16 and the second MOS transistor 17. Therefore, the memory cell 11 and the first switch 22 have a high dielectric strength between the source electrode 18 and the bit electrode 27. Because the thickness of the second gate insulating film 45 of the second MOS transistor 17 is greater than the thickness of the first gate insulating film 43 of the first MOS transistor 16, the memory cell 11 and the first switch 22 also have a high dielectric strength between the coupling gate 20 and the source electrode 18. Therefore, even when using… Figure 5 The first switch 22 of the device structure shown is replaced by Figure 2 The first switch 221, made of a high breakdown voltage MOS transistor 30 in the comparative example shown, also has its dielectric strength not reduced.

[0047] Because the first gate insulating film 43 is thin, therefore Figure 5 The first MOS transistor 16 shown allows for greater current flow. Therefore, the width of the word gate 19 of the first MOS transistor 16 can be smaller than the width of the high breakdown voltage MOS transistor 30. Within the memory cell 11 and the first switch 22, the voltage applied between the source electrode 18 and the bit electrode 27 is distributed by the first MOS transistor 16 and the second MOS transistor 17. Therefore, the dielectric strength of the first MOS transistor 16 and the second MOS transistor 17 can be reduced. Therefore, the lengths of the word gate 19 and the coupling gate 20 can be shorter than the length of the gate of the high breakdown voltage MOS transistor 30. Therefore, for Figure 5 The memory cell 11 and the first switch 22 shown occupy a significantly smaller area than the high breakdown voltage MOS transistor 30 of the comparative example.

[0048] <Problems when the first switch is configured to be the same as the memory cell>

[0049] However, unlike the high-voltage MOS transistor 30 in the comparative example, the memory cell 11 has two gate electrodes: a word gate 19b and a coupling gate 20. Therefore, as in... Figure 6 In the circuit of the semiconductor device 1 shown, considering that the first switch 22 is simply configured to be the same as the memory cell 11, the word gate 19b of the first switch 22 and the voltage applied to the coupling gate 20 need to be considered. This is because there is a problem that the first switch 22 may not operate properly due to the voltage applied to the word gate 19b and the coupling gate 20 of the first switch 22. In addition, if a voltage exceeding the rated value is applied to the first switch 22 through the voltage applied to the word gate 19b and the coupling gate 20 of the first switch 22, the first switch 22 also has the problem of causing dielectric breakdown or degradation.

[0050] For example, consider simply replacing the first transistor 15 of memory cell 11 Figure 2 The high-voltage MOS transistor 30 of semiconductor device 1 is shown in the figure. Figure 2 In the comparison example shown, since there is only one word gate driver D1b, therefore Figure 7The semiconductor device 1 shown is configured to apply a gate electrode control voltage 50 from the same word gate driver D1 to the word gate 19b and the coupling gate 20. If the voltage for driving the coupling gate 20 of the memory cell is supplied to the gate electrode control voltage 50 of the first switch 22, the same voltage is also applied to the word gate 19b of the first switch 22. Since the first gate insulating film 43 below the word gate 19b is formed to have a film thickness thinner than the second gate insulating film 45 below the coupling gate 20, a voltage equal to or greater than the rated value of the first gate insulating film 43 is applied to the word gate 19b. Therefore, in Figure 7 In the semiconductor device 1 shown, there may be problems such as dielectric breakdown caused by the first gate insulating film 43, or rapid deterioration and reduced reliability of the first gate insulating film 43.

[0051] Furthermore, when the gate electrode control voltage 50 of the first switch 22 is suppressed to a low voltage to protect the first gate insulating film 43, the same voltage is also applied to the coupling gate 20b of the first switch 22. Since the thickness of the second gate insulating film 45 below the coupling gate 20 is greater than the thickness of the first gate insulating film 43, there is a problem that a sufficient conductive region cannot be formed in the semiconductor substrate 34 below the coupling gate 20. Therefore, for Figure 7 The amount of current flowing through the first switch 22 in the semiconductor device 1 shown may also decrease.

[0052] exist Figure 6 In the semiconductor device 1 shown, when data is written to memory cell 11, a control voltage is applied from the source driver control circuit 8 to the gate electrode of the second switch 23 via the level shifting circuit 24, causing the source and drain electrodes of the second switch 23 to become conductive. Therefore, the voltage applied to the first voltage terminal 25 via the second switch 23 is applied to the source electrode 18a of the second MOS transistor 17 in memory cell 11. When data is written to memory cell 11, a current for writing data must be supplied to the memory cell to be written. To allow current to flow through the state cell, a control voltage needs to be applied to the word gate 19a and coupling gate 20 of memory cell 11 to make the memory cell conductive. However, when a control voltage is applied to the word gate 19b and coupling gate of the first switch 22 to make the first switch 22 conductive, a through-current flows between the first switch 22 and the second switch 23 and the first voltage terminal 25 and the ground electrode GND. Therefore, there is a problem that the first switch 22 and the second switch 23 may be damaged by the through-current. Therefore, at least one of the word gate 19b or the coupling gate 20 of the first switch 22 must be able to apply a different control voltage than the word gate 19a or the coupling gate 20a of the memory cell 11.

[0053] <Circuit configuration of the semiconductor device in the first embodiment>

[0054] Therefore, the inventors of this patent application have considered applying a voltage lower than that of the coupling gate 20b to Figure 1 The word gate 19b of the first switch 22 shown in the first embodiment is used to prevent dielectric breakdown of the first gate insulating film 43 beneath the word gate 19b. The inventors also considered forming a sufficient conductive region in the semiconductor substrate 2 beneath the coupling gate 20b by applying a voltage higher than that of the word gate 19b to the coupling gate 20b of the first switch 22 to increase the amount of current flowing through the first switch 22.

[0055] The inventors have also obtained a configuration in which the word gate 19b of the first switch 22 and the word gate 19b of the memory cell 11 are electrically isolated from each other so that different control voltages can be applied to the word gate 19b of the first switch 22 and the word gate 19b of the memory cell 11. Therefore, in the new configuration, when data is written to the memory cell 11, the voltage used to disconnect the first switch 22 can be applied from the source driver control circuit 8 to the word gate 19b of the first switch 22. Therefore, when writing to the memory cell 11 in the new configuration, the through current flows between the ground electrode GND and the first voltage terminal 25 via the first switch 22 and the second switch 23, and there is no problem of damage to the first switch 22 and the second switch 23. In the first embodiment, the control voltage is applied to the word gate 19a of the memory cell 11 from the second word gate driver D2 provided in the row control circuit 5 via the word line 12. The control voltage is applied to the word gate 19b of the first switch from the first word gate driver D1 provided in the source driver control circuit 8. In the first embodiment, control voltages are applied to the word gate 19b of the first switch and the word gate 19a of the memory cell 11 via a first word gate driver D1 and a second word gate driver D2, which are different from each other. Therefore, even if the second switch 23 is in a conductive state to put the memory cell 11 into a write state, the first switch 22 can be controlled to a non-conductive state, and shoot-through current can be prevented from flowing to the first switch 22. Since the first word gate driver D1 applies a voltage lower than the voltage of the coupling gate 20b to the word gate 19b, a small circuit with a low withstand voltage can be used. Therefore, the area occupied by the first word gate driver D1 can be reduced.

[0056] In addition, Figure 6 The first switch 22 shown is merely an example of a configuration identical to memory cell 11. To properly operate the first switch 22, a method for applying voltage to the coupling gate 20b needs to be considered. Therefore, the inventors of this patent application envision a method such as... Figure 1The diagram illustrates an electrical connection between the coupling gate 20b of the first switch 22 and the coupling gate 20a of the memory cell 11. When the current 21 flowing through the memory cell 11 is directed to the ground electrode GND, the first switch 22 is in a conductive state. Therefore, when the first switch 22 is in a conductive state, the coupling gate driver D3 applies a control voltage to the coupling gate 20a of the memory cell 11, causing the second MOS transistor 17a to be in a conductive state. Thus, by electrically connecting the coupling gate 20b of the first switch 22 to the coupling gate 20a of the memory cell 11, the coupling gate driver D3 applies a control voltage to the coupling gate 20b of the first switch 22. Therefore, when current flows through the memory cell 11, the coupling gate driver D3 controls the state gate 20b of the first switch 22 to be conductive. Therefore, the first word gate driver D1 controls the first MOS transistor 16b to be conductive, thereby allowing current to flow to the first switch 22. Furthermore, even when a voltage for conducting the second MOS transistor 17b is applied to the coupling gate 20b of the first switch 22, a voltage for deconducting the first MOS transistor 16b is applied to the word gate 19b, so that the first switch 22 can be controlled to a non-conductive state. Therefore, the inventors of this patent application have discovered that the first switch 22 can operate normally even when the coupling gate 20b of the first switch 22 is electrically connected to the coupling gate 20a of the memory cell 11.

[0057] In the first embodiment, a control voltage is applied to both the coupled gate 20a of the memory cell 11 and the coupled gate 20b of the first switch via the coupled gate driver D3 in the row control circuit 5. Therefore, a driver for supplying voltage to the coupled gate 20b of the first switch 22 is not required, reducing the number of driver circuits and enabling a further reduction in the size of the semiconductor device 1. Specifically, since the second gate insulating film 45 of the second MOS transistor 17a is thicker than the first gate insulating film 43, a control voltage higher than that of the word gate 19b needs to be applied to the coupled gate 20b of the first switch 22. Therefore, the area occupied by the coupled gate driver of the source driver circuit 7 is larger than the area occupied by the word gate driver. The ability to omit the driver for supplying voltage to the coupled gate 20b of the first switch 22 greatly contributes to the miniaturization of the source driver circuit 7.

[0058] <Timing diagram of the voltage applied to each gate of the semiconductor device according to the first embodiment>

[0059] Next, the timing relationship of the voltages applied to each gate electrode of the memory cell 11 and each gate electrode of the first switch 22 in the first embodiment will be described. Figure 8This is a timing diagram of the voltages applied to the memory cell 11 of semiconductor device 1 and each gate electrode of the first switch 22. Note that... Figure 8 This is a timing diagram during the data read mode of memory cell 11. Figure 8 The horizontal axis represents the time process. Figure 8 The vertical axis represents the voltage level. Figure 8 In the above, VWG1 indicates the voltage of the word gate 19a of the memory cell 11, VWG2 indicates the voltage of the word gate 19b of the first switch 22, VCG1 indicates the voltage of the coupling gate 20a of the memory cell 11, and VCG2 indicates the voltage of the coupling gate 20b of the first switch 22.

[0060] In the first embodiment, when the semiconductor device 1 enters the mode of reading data from the memory unit 11 ( Figure 8 At time T1, the voltage VWG2 of the word gate 19b of the first switch 22 changes from 0V (lower than the threshold voltage of the word gate 19b) to V2 (higher than the threshold voltage). At the same time T1, the voltage VCG1 of the coupling gate 20a of the memory cell 11 changes from 0V (lower than the threshold voltage of the coupling gate 20a) to V3 (higher than the threshold voltage). Similarly, at time T1, the voltage VCG2 of the coupling gate 20b of the first switch 22 changes from 0V (lower than the threshold voltage of the coupling gate 20b) to V4 (higher than the threshold voltage). Therefore, when entering the mode of reading data from the memory cell 11, the first switch 22 changes from a non-conductive state to a conductive state at time T1, and the source line 10 and the ground electrode GND are electrically connected to each other. Additionally, a conductive region is formed on the semiconductor substrate below the coupling gate 20a of the memory cell 11. However, at T1, a voltage of 0V, which is lower than the threshold voltage of the word gate 19b, is applied to the word gate 19b of the memory cell 11, so that the memory cell 11 does not become conductive and current does not flow to the memory cell 11.

[0061] Next, when entering the selection... Figure 8 During the specific memory cell 11 time period shown in T2, the voltage VWG1 of the word gate 19a of the memory cell 11 changes from 0V to a voltage V1 higher than the threshold voltage of the word gate 19b of the memory cell 11. Therefore, since a conductive region is formed on the semiconductor substrate below the word gate 19a of the memory cell 11 from time T2 onwards, the first transistor 15 is in a conductive state, and the memory cell 11 is in a conductive state. Therefore, as... Figure 1 As shown, the current 21 generated by the column control circuit 4, the sensing circuit 6, the bit line 9, and the current supply circuit C1 in the selected memory cell 11 flows to the ground electrode GND through the source line 10 and the first switch 22. Therefore, in the first embodiment, when entering the current supply circuit C1 for the selected memory cell 11, the current 21 generated by the column control circuit 4, the sensing circuit 6, the bit line 9, and the current supply circuit C1 in the selected memory cell 11 flows to the ground electrode GND through the source line 10 and the first switch 22. Figure 8 When selecting the memory cell 11 after T2 as shown, the data written to the selected memory cell 11 can be read by measuring the value of the current 21 flowing through the memory cell 11 using the sensing circuit 6.

[0062] Then, when the time period for selecting a specific memory cell 11 ends, as... Figure 8 As shown in T3, the voltage VWG1 of the word gate 19a of memory cell 11 changes from voltage V1 to voltage 0V. Therefore, since voltage 0V is applied to the word gate 19b of memory cell 11 after T3 when the selection period of memory cell 11 is completed, memory cell 11 becomes non-conductive. Because no current flows through memory cell 11, no data is read from memory cell 11.

[0063] Next, when a predetermined time period has elapsed after the time period used to select memory cell 11, such as Figure 8 As shown in T4, the mode for reading data from memory cell 11 ends. Figure 8 At time T4, the voltage VWG2 of the word gate 19b of the first switch 22 changes from voltage V2 to voltage 0V. Additionally, the voltage VCG2 of the coupling gate 20b of the first switch 22 changes from voltage V4 to voltage 0V. Therefore, at... Figure 8 After the time point T4 indicated, after the mode of reading data from memory cell 11 ends, the first switch 22 enters a non-conductive state. Furthermore, the source line 10 and the ground electrode GND are electrically insulated. Figure 8 At time T4, the voltage VCG1 of the coupled gate 20a of memory cell 11 changes from voltage V3 to voltage 0V, and the second MOS transistor 17a becomes non-conductive.

[0064] In the first embodiment, since data in the selected memory cell 11 needs to be read at a high speed, the voltage VWG1 of the word gate 19a of the memory cell 11 needs to be changed at a high speed. Furthermore, the voltage VWG1 of the word gate 19b of the memory cell 11 needs to be as short as possible during the transition from a voltage of 0V (below a threshold voltage) to a voltage of V1 (above a threshold voltage). Therefore, the word gate driver circuit for driving the word gate 19a of the memory cell 11 needs to operate at a high speed. In the first embodiment, voltage V3 can be applied to the coupling gate 20a of the memory cell 11 before time T2 when voltage V1 is applied to the word gate 19a. Furthermore, before time T2, voltage V2 can be applied to the word gate 19b of the first switch 22, and voltage V4 can be applied to the coupling gate 20b. Therefore, there is a margin in the time for increasing the voltage values ​​of the coupling gate 20a, the word gate 19b of the first switch 22, and the coupling gate 20b. This makes voltage control of each gate easier. In the embodiment, after a certain period of time has elapsed since the voltage VCG1 of the coupled gate 20a of memory cell 11 drops to 0V at time T3, the voltage VWG1 of the word gate 19a of memory cell 11 drops to 0V at time T4. Similarly, at T4, the voltage VWG2 of the word gate 19b of the first switch 22 and the voltage VCG2 of the coupled gate 20b decrease to 0V respectively. Therefore, there is a time margin for reducing the voltage value of each gate, further simplifying voltage control of each gate. Therefore, in the first embodiment, the drive capability of the coupled gate driver D3 used to drive the coupled gate 20a of memory cell 11 and the coupled gate 20b of the first switch 22 can be reduced. Therefore, small circuitry can be used for the coupled gate driver D3. In the first embodiment, the drive capability of the first word gate driver D1 used to drive the word gate 19b of the first switch 22 can also be reduced. Therefore, small circuitry can also be used for the first word gate driver D1. Therefore, in the first embodiment, in Figure 8 In the timing diagram shown, by applying a control voltage to each gate electrode of the memory cell 11 and the first switch 22, the semiconductor device 1 can be further miniaturized.

[0065] <Planar structure of the semiconductor device according to the first embodiment>

[0066] Figure 9 This is a plan view showing the structure of the first switch 22 and the memory unit 11 according to a first embodiment of the present invention. Figure 5 yes Figure 9 The diagram shows a cross-sectional view of the first switch 22 and memory unit 11 taken from Q to R. Figure 9In the description of this embodiment shown, the surface viewed from the top of the page is drawn as the first main surface 35 of the semiconductor substrate 34. This also applies to the plan view described below. In the first embodiment, the semiconductor device 1 is formed on the first main surface of the semiconductor substrate 34. Figure 9 This is an enlarged plan view of a portion of a semiconductor device, in which memory cell region 72 and source driver region 71 are adjacent to each other. In a first embodiment, word gate 19a, coupling gate 20a, source electrode 18a, and erase gate 47 extend in the X direction. In a first embodiment, word gate 19b, coupling gate 20a, source electrode 18a, and erase gate 47 are arranged side-by-side in the Y direction. Adjacent to one long side of word gate 19a, a plurality of bit electrodes 27a are arranged in the extension direction (X direction) of word gate 19b. Element isolation region 77a is disposed between two adjacent bit electrodes 27a. In a first embodiment, a memory cell 11 is configured with bit electrodes 27a, word gate 19a, coupling gate 20a, and source electrode 18a. Furthermore, in a first embodiment, a first switch 22 is composed of bit electrode 27b, word gate 19b, coupling gate 20b, and source electrode 18b. Element isolation region 77b is also disposed between two adjacent bit electrodes 27b. In the first embodiment, word gates 19b and 19a, coupling gates 20a and 20b, and erase gate 47 can be formed of a conductive material (e.g., polysilicon). The erase gate 47 is electrically connected to the erase gate driver circuit DE and is supplied with a voltage. Source electrodes 18a and 18b, and the plurality of bit electrodes 27a, can be conductors, for example, formed from a diffusion layer doped with impurities into the semiconductor substrate 34. Additionally, the element isolation regions 77a and 77b can be any material capable of insulating adjacent bit electrodes 27a and 27b. For example, element isolation regions 77a and 77b are formed from a diffusion layer having a conductivity type opposite to that of the bit electrodes 27a and 27b. In the first embodiment, a plurality of memory cells 11 are arranged in a matrix in the X and Y directions to form a memory cell array region 72. A plurality of first switches 22 are electrically connected between the memory cells 11 and the ground electrode GND. Therefore, in the first embodiment, a large current can flow between the memory cells 11 and the ground electrode GND. Multiple first switches 22 are disposed in the source driver region 71 outside the memory cell array region 72.

[0067] In the first embodiment, since the first switch 22 has the same planar configuration as the memory cell 11, the planar size of the first switch 22 can be reduced to the same size as the memory cell 11. Therefore, in the first embodiment, the source driver region 71 can be greatly reduced compared to the comparative example using a high breakdown voltage MOS transistor 30. Therefore, in the first embodiment, the size of the semiconductor device 1 can be greatly reduced.

[0068] In the first embodiment, word gate 19a of memory cell 11 and word gate 19b of first switch 22 are formed respectively. Word gate 19b of first switch 22 is electrically connected to first word gate driver D1 provided in source driver control circuit 8 via common word gate line 80. On the other hand, word gate 19a of memory cell 11 is electrically connected to second word gate driver D2 provided in row control circuit 5.

[0069] In the first embodiment, a coupling gate 20a of the memory cell 11 and a coupling gate 20b of the first switch 22 are formed sequentially. The coupling gate 20a of the memory cell 11 and the coupling gate 20b of the first switch 22 are electrically connected to a coupling gate driver D3 disposed in the row control circuit 5. Therefore, power is supplied from the row control circuit 5 to the coupling gate 20a of the memory cell 11 and the coupling gate 20b of the first switch 22. Thus, the area of ​​the source driver control circuit 8 can be reduced, eliminating the need for an unnecessary control circuit for driving the coupling gate 20b of the first switch 22.

[0070] The source electrodes 18a of memory cell 11 and first switch 22 are formed sequentially. Therefore, the source electrodes 18a of memory cell 11 and first switch 22 are electrically connected to each other. The bit electrode 27a of memory cell 11 is connected to bit line 9. Bit line 9 is electrically connected to column control circuit 4. The bit electrode 27b of first switch 22 is connected to local ground wiring 81. Local ground wiring 81 is electrically connected to common ground wiring 82. Common ground wiring 82 is electrically connected to ground electrode. Therefore, by controlling first switch 22 to a conductive state through row control circuit 5 and source driver control circuit 8, cell current 21 can flow from source electrode 18b to ground electrode GND through first switch 22, local ground wiring 81, and common ground wiring 82. In the first embodiment, multiple memory cells 11 in row 74 and multiple memory cells 11 in adjacent row 75 are arranged symmetrically with source electrode 18a as the center line. Furthermore, with the source electrode 18a as the center, multiple first switches 22 are arranged linearly symmetrically in row 74 and in row 75 adjacent to row 74. Therefore, wiring connecting one source electrode 18a can be shared with multiple memory cells 11 and multiple first switches 22 in row 75 adjacent to row 74, reducing the number of wirings connecting the source electrode 18a. Furthermore, the current 21 flowing from the source electrode 18a to the ground electrode GND flows through multiple first switches 22 in row 74 and multiple first switches 22 in adjacent row 75. Therefore, the number of paths through which the current 21 flows increases.

[0071] <Effects of the First Embodiment>

[0072] The main effects of the first embodiment will be described below. According to the first embodiment, the first switch 22 uses a second transistor having the same configuration as the first transistor of the memory cell. Therefore, the area occupied by the first switch 22 can be reduced, and the size of the entire semiconductor device can be reduced.

[0073] According to the first embodiment, even though the area occupied by the first switch 22 is smaller than that of the high breakdown voltage transistor, it still has a dielectric strength equivalent to that of the high breakdown voltage transistor. Therefore, the area occupied by the source driver circuit 7 can be reduced without compromising reliability, and the size of the semiconductor device can be reduced.

[0074] In addition, since the driving circuits for the coupled gate 20a and coupled gate 20b of the memory cell of the first switch 22 can be common, there is no need to provide a dedicated driving circuit for the coupled gate 22b of the first switch 22, and the semiconductor device 1 can be miniaturized.

[0075] Furthermore, before the voltage VWG1 of word gate 19a becomes a voltage V1 higher than the threshold voltage, the voltage VWG2 of word gate 19b becomes a voltage V3 higher than the threshold voltage. Moreover, after the voltage VWG1 of the first word gate becomes a voltage 0V lower than the threshold voltage, the voltage VWG2 of word gate 19b becomes a voltage 0V lower than the threshold voltage. Therefore, the word gate voltage VWG2 has a time margin in the voltage switching, which helps to control the voltage of word gate 19b. Thus, a small circuit with low driving force can be used for the first word gate driver D1, and it has the effect of further miniaturizing the semiconductor device 1.

[0076] (Example 2)

[0077] <Circuit configuration of the semiconductor device according to the second embodiment>

[0078] Next, refer to Figure 10 The circuit configuration of the semiconductor device 1 according to the second embodiment is described. The semiconductor device 1 of the second embodiment differs from that of the first embodiment in that the coupled gate 20a of the memory cell 11 is electrically separated from the coupled gate 20b of the first switch 22. In the semiconductor device 1 according to the second embodiment, the coupled gate 20a of the memory cell 11 is electrically connected to a first coupled gate driver D3b disposed in the row control circuit 5. Conversely, the coupled gate 20b of the first switch 22 is electrically connected to a second coupled gate driver D4 disposed in the source driver control circuit 8. Therefore, compared to the first embodiment, the chip area of ​​the semiconductor device 1 region required to provide the second coupled gate driver D4 is increased for the semiconductor device 1 according to the second embodiment.

[0079] However, when data is written to memory cell 11, a sufficiently high voltage needs to be applied to the coupling gate 20a of memory cell 11. On the other hand, the coupling gate 20b of the first switch does not need to be written to and can be driven with a lower voltage than the coupling gate 20a of memory cell 11. Therefore, in the semiconductor device 1 according to the second embodiment, a control voltage having a lower voltage value than the coupling gate 20a of memory cell 11 can be applied to the coupling gate 20b of the first switch 22. Therefore, the electric field applied to the first gate insulating film 43 below the word gate 19b adjacent to the coupling gate 20b of the first switch can be further reduced. Therefore, the risk of dielectric breakdown and degradation of the first gate insulating film 43 caused by the first gate insulating film 43 can be further reduced. The second coupling gate driver D4 can also use a circuit with an output voltage lower than the output voltage of the first coupling gate driver D3b. Therefore, the increase in chip area can be suppressed by also setting the second coupling gate driver D4 to a lower value.

[0080] <Planar structure of semiconductor device according to the second embodiment>

[0081] Figure 11 This is a plan view showing the structure of the first switch 22 and the memory unit 11 according to a second embodiment of the present invention. Figure 11 In the second embodiment shown, the coupling gate 20b of the first switch 22 is electrically connected to a common coupling gate wiring 83 via a connection member 84. The common coupling gate wiring 83 can be any conductive material, for example, it can be formed of a metallic material (such as copper or aluminum). The connection member 78 can be made of a metallic material (such as tungsten or titanium).

[0082] The common-coupled gate line 83 is electrically connected to the second coupled gate driver D4 in the source driver control circuit 8. Therefore, in Figure 11 In the second embodiment shown, a control voltage is applied from the second coupled gate driver D4 to the coupled gate 20b of the first switch. Further description of the second embodiment is the same as that of the first embodiment described above, and therefore further description of the second embodiment is omitted.

[0083] (Effects of the second embodiment)

[0084] The main effects of the second embodiment are as follows. According to the semiconductor device 1 of the second embodiment, a control voltage different from that of the memory cell 11 can be applied to the coupling gate 20b of the first switch 22. Therefore, a voltage lower than that of the coupling gate 20a of the memory cell 11 can be supplied to the coupling gate 20a of the first switch 22. Therefore, dielectric breakdown of the first gate insulating film 43 under the word gate 19b adjacent to the coupling gate 20b of the 22 can be prevented.

[0085] In addition, according to the second embodiment, it is not necessary to apply an unnecessary high voltage to the coupling gate 20 of the first switch 22, which can reduce the power consumption of the semiconductor device 1.

Claims

1. A semiconductor device comprising a memory cell and a switching circuit formed on a semiconductor substrate, The switching circuit is located outside the memory cell and is electrically connected to the memory cell. The memory cell includes a plurality of transistors, the plurality of transistors including a first transistor. The switching circuit includes a second transistor electrically connected to the first transistor. The second transistor includes: The first word gate is formed on the first gate insulating film; A first coupling gate is formed on a second gate insulating film, the second gate insulating film having a thickness greater than that of the first gate insulating film. In the second transistor, when current flows through the switching circuit, a first voltage is supplied from outside the switching circuit, causing a first region of the semiconductor substrate below the first word gate to become conductive. In the second transistor, when current flows through the switching circuit, a second voltage is supplied from outside the switching circuit, causing the second region of the semiconductor substrate below the first coupled gate to become conductive. The second voltage is higher than the first voltage.

2. The semiconductor device according to claim 1, The first transistor includes: The second gate is formed on the third gate insulating film; as well as A second coupling gate is formed on a fourth gate insulating film, the fourth gate insulating film having a thickness greater than that of the third gate insulating film. The first transistor includes a first source electrode, which is electrically connected to the second source electrode of the second transistor. In the first transistor, when current flows through the memory cell, a third voltage is supplied from outside the memory cell, causing a third region of the semiconductor substrate below the second word gate to become conductive. In the first transistor, when current flows through the memory cell, a fourth voltage is supplied from outside the memory cell, causing a fourth region of the semiconductor substrate below the second coupled gate to become conductive. The fourth voltage is higher than the third voltage, and The second voltage is lower than the fourth voltage.

3. The semiconductor device according to claim 1, The first transistor includes: The second gate is formed on the third gate insulating film; as well as A second coupling gate is formed on a fourth gate insulating film, the fourth gate insulating film having a thickness greater than that of the third gate insulating film. The first source electrode of the first transistor is electrically coupled to the second source electrode of the second transistor. In the first transistor, when current flows through the memory cell, a third voltage is supplied from outside the memory cell, causing a third region of the semiconductor substrate below the second coupled gate to become conductive. In the first transistor, when current flows through the memory cell, a fourth voltage is supplied from outside the memory cell, causing a fourth region of the semiconductor substrate below the second coupled gate to become conductive. The fourth voltage is higher than the third voltage, and The second voltage is substantially the same as the fourth voltage.

4. The semiconductor device according to claim 3, After the third voltage is stopped being supplied to the second word gate, the second coupling gate is supplied with the fourth voltage, and After the third voltage is stopped being supplied to the second word gate, the first coupling gate is supplied with the second voltage.

5. A semiconductor device comprising a memory cell and a switching circuit formed on a semiconductor substrate. The switching circuit is located outside the memory cell and is electrically connected to the memory cell. The memory cell includes a plurality of transistors, the plurality of transistors including a first transistor. The switching circuit includes a second transistor electrically connected to the first transistor. The first transistor includes: The first word gate is formed on the first gate insulating film; as well as A first coupling gate is formed on a second gate insulating film, the second gate insulating film having a thickness greater than that of the first gate insulating film. The second transistor includes: The second gate is formed on the third gate insulating film; and A second coupling gate is formed on a fourth gate insulating film, the fourth gate insulating film having a thickness greater than that of the third gate insulating film. The first transistor includes a first source electrode, which is electrically connected to the second source electrode of the second transistor. The semiconductor device further includes: A first driver circuit is configured to supply a first voltage to the first word gate; The second driver circuit is configured to supply a second voltage to the second word gate; A third driver circuit is configured to supply a third voltage higher than the first voltage to the first coupled gate; and The fourth driver circuit is configured to supply a fourth voltage higher than the second voltage to the second coupled gate.

6. The semiconductor device according to claim 5, Before the first driver circuit supplies the first voltage to the first word gate, the second driver circuit supplies the second voltage to the second word gate, and After the first driver circuit stops supplying the first voltage to the first word gate, the second driver circuit stops supplying the second voltage to the second word gate.

7. The semiconductor device according to claim 6, The third driver circuit and the fourth driver circuit are configured with a common-coupled gate driver circuit, and A third voltage and a fourth voltage having the same voltage are supplied from the coupled gate driver circuit to the first coupled gate and the second coupled gate, respectively.

8. The semiconductor device according to claim 6, The fourth driver circuit supplies a fourth voltage, having a voltage value lower than the third voltage, to the second coupled gate.

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