Two-step high-speed auto-zero and self-calibration comparator

Abstract

A two-step high-speed auto-zero and self-calibration comparator is provided. A method of controlling a comparator includes enabling, during a first time period, an auto-zero loop to provide an initial mismatch calibration of a differential preamplifier including a differential memory capacitor, and enabling, during a second time period after the first window, a self-calibration circuit to provide a mismatch calibration of the differential preamplifier and to minimize output mismatch of a dynamic latch. Wherein the dynamic latch is configured to latch an output of the differential preamplifier at a sampling frequency, the auto-zero loop includes an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on a voltage across the differential memory capacitor, and the self-calibration circuit includes a charge pump configured to adjust the voltage across the differential memory capacitor based on an output of the dynamic latch.

Description

Technical Field

[0001] This invention generally relates to circuits and methods for automatic zeroing and self-calibrating comparators. Background Technology

[0002] Analog voltage or current comparators are widely used building blocks in electronic circuits, featuring input stages optimized for low-offset operation. For example, comparators are fundamental analog-to-digital interface elements used in wireless and VLSI systems, analog / mixed-signal ICs, and analog-to-digital converters (ADCs).

[0003] A comparator can be a device that converts a signal voltage (V) at an input into a signal voltage (V). IN It compares a signal level to a reference voltage (ground) on its other input, and generates a digital output of logic 1 or 0 when one signal level is greater than the other. The comparator's external pins include a differential pair with a non-inverting input (+) and an inverting input (-), and the comparator generally also includes an output pin. Summary of the Invention

[0004] A comparator circuit includes a differential preamplifier, a dynamic latch, an auto-zeroing loop, a self-calibration circuit, and control logic. The differential preamplifier includes a differential memory capacitor. The dynamic latch is configured to latch the output of the differential preamplifier at a sampling frequency. The auto-zeroing loop includes an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on the voltage across the differential memory capacitor. The self-calibration circuit includes a charge pump configured to adjust the voltage across the differential memory capacitor based on the output of the dynamic latch. The control logic can be configured to send a first signal during a first time period such that the auto-zeroing loop provides initial offset calibration of the differential preamplifier, and to send a second signal during a second time period occurring after the first time period such that the self-calibration circuit provides offset calibration of the differential preamplifier, minimizing the offset of the dynamic latch.

[0005] A method of controlling a comparator includes: during a first time period, enabling an automatic zeroing loop to provide initial offset calibration of a differential preamplifier including a differential memory capacitor; and during a second time period after the first window, enabling a self-calibration circuit to provide offset calibration of the differential preamplifier and minimize the output offset of the dynamic latch.

[0006] A comparator circuit includes a differential preamplifier, a dynamic latch, an auto-zeroing loop, a self-calibration circuit, and control logic. The differential preamplifier includes a differential memory capacitor. The dynamic latch is configured to latch the output of the differential preamplifier at a sampling frequency. The auto-zeroing loop includes an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on the voltage across the differential memory capacitor. The self-calibration circuit includes a charge pump configured to adjust the current to the differential memory capacitor based on the output of the dynamic latch. The control logic can be configured to send a first signal during a first time period such that the auto-zeroing loop provides initial offset calibration of the differential preamplifier, and to send a second signal during a second time period occurring after the first time period such that the self-calibration circuit provides offset calibration of the differential preamplifier, minimizing the offset of the dynamic latch. Attached Figure Description

[0007] Figure 1A This is a block diagram of an amplifier with offset.

[0008] Figure 1B yes Figure 1A A graphical representation of the relationship between the input voltage and output voltage of an amplifier.

[0009] Figure 2A This is a block diagram of a comparator with misalignment.

[0010] Figure 2B yes Figure 2A A graphical representation of the relationship between the input voltage and output voltage of a comparator.

[0011] Figure 3 It is a graphical representation of the analog input signal without offset and the output of the comparator relative to time.

[0012] Figure 4 It is a graphical representation of the analog input signal with offset and the output of the comparator relative to time.

[0013] Figure 5 This is a schematic diagram of a comparator with an automatic zero-adjustment circuit.

[0014] Figure 6 yes Figure 5 The circuit shown is illustrated graphically with respect to the phase and clock signal relative to time.

[0015] Figure 7 This is a schematic diagram of a self-calibrating comparator that uses only a charge pump circuit.

[0016] Figure 8 Is only used Figure 7 A graphical representation of the signal of the self-calibrating comparator in the charge pump circuit relative to time.

[0017] Figure 9 yes Figure 7 A graphical representation of the signal versus time using a self-calibrating charge pump circuit with reduced residual offset.

[0018] Figure 10 This is a schematic diagram of a two-step automatic zeroing and self-calibrating comparator.

[0019] Figure 11A yes Figure 10 The phase and clock signals of the two-step auto-zero self-calibrating comparator are graphically represented relative to time.

[0020] Figure 11B yes Figure 10 A graphical representation of the signal of a two-step auto-zero self-calibrating comparator relative to time.

[0021] Figure 12 This is a schematic diagram of a two-step offset compensation current domain comparator circuit. Detailed Implementation

[0022] As requested, detailed embodiments of the invention are disclosed herein; however, it should be understood that the disclosed embodiments are merely examples of the invention that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be enlarged or minimized to show details of specific components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but only as a representative basis for teaching those skilled in the art to employ the invention in various ways.

[0023] The term "substantially" may be used herein to describe disclosed or claimed embodiments. The term "substantially" may modify values ​​or relative characteristics disclosed or claimed in this disclosure. In such instances, "substantially" may indicate that the value or relative characteristic it modifies is within the range of that value or relative characteristic. Within 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5% or 10%.

[0024] Applications such as automotive LiDAR (optical ranging and detection) require electronic circuitry that operates at both high speed and high precision. This is related to the dynamic range and modulation speed of the received signal used for transmission. Such systems form transceivers where detection capability relies on high-fidelity electronics. Techniques such as phase coding in intensity-modulated laser transmission pulse trains improve overall system performance, but impose conflicting requirements on the electronics in terms of combining low offset and high-speed operation, for example, to prevent information loss. As a result, the received signal path of such systems may require an effective input reference offset level below the noise level. Electronics used in instrumentation applications benefit from lower bandwidth, which allows for trade-offs to improve accuracy, primarily due to mismatches in components such as transistors. Such trade-offs allow for improved matching by increasing device size. Further improvements can be achieved through dynamic error correction techniques such as autozeroing. For high-speed applications, device size must be optimized for speed to minimize parasitic capacitance; however, this results in poor offset performance. Conventional autozeroing schemes can also lead to potentially high residual offset because the offset effects caused by the high-speed dynamic latch used at the comparator output stage are not handled by the autozeroing loop. Comparator offset can also be calibrated; however, factory calibration is not robust enough to guarantee the circuit's performance under automotive conditions. This means that self-calibration techniques beyond conventional autozeroing and calibration should be sought.

[0025] Due to various non-ideal effects such as electronic component mismatch, the practical implementation of an amplifier or comparator will have an effective input offset voltage. Figure 1A This is a block diagram of an amplifier with an offset of 100%. The amplifier's input reference offset (V0) is... OS It can be modeled using a DC voltage source connected in series with its input. Figure 1B This is a graphical representation of the relationship 150 between the input voltage 154 and the output voltage 152 of amplifier 100. With zero input signal, this voltage is required at the input to create a zero output voltage. As a result, the amplifier's input-output characteristics do not exceed zero. The same concept can be applied to comparators, where, in order to accurately distinguish the polarity of the input signal, the comparator includes a net input reference DC voltage (V0) placed in series with its input. OS ). Figure 2A This is a block diagram of a comparator with an offset of 200. Figure 2B This is a graphical representation of the relationship between the input voltage 254 and the output voltage 252 of comparator 200.

[0026] Therefore, offset reduction techniques such as chopping, autozeroing, correlated double sampling, trimming, and calibration methods have been widely used in integrated circuits. Each method has its advantages and disadvantages, and each method has its optimal fit for certain applications. These may involve considerations such as continuous operation that may be important for a particular application, the introduction of interference and glitches, robustness over temperature and lifetime, etc.

[0027] Intensity-modulated phase-coded LiDAR is an example of a system where comparator misalignment can severely impact performance. In this case, time of flight is detected by correlating the comparator's output bitstream with the transmitted phase pattern. Figure 3 It is a graphical representation 300 of the unbiased analog input signal 302 and the resulting comparator output 304 relative to time 306. The analog input signal 302 includes the intended digital signal 308 and the actual analog signal 310 as received. Figure 4 It is a graphical representation 400 of an offset analog input signal 402 and a result comparator output 404 relative to time 406. The analog input signal 402 includes an intended digital signal 408 and an actual analog signal 410 as received.

[0028] The diagram illustrates two hypothetical scenarios—one with low imbalance ( Figure 3 ) and the second type in which the input reference offset is greater than the noise ( Figure 4 The first case ( Figure 3 The diagram illustrates the output of a low-offset comparator given a noisy input. In this case, the signal can be recovered even in the presence of noise. In the second case ( Figure 4 When the offset exceeds the noise, signal detection is interrupted. These examples illustrate that offset control is crucial for ensuring system performance.

[0029] In the case of comparators—where sampling (synchronization) and wideband operation are concerns—autozeroing can be used as an offset reduction technique. Autozeroing is a process in which the comparator's preamplifier is disconnected from the signal path, its input short-circuited, to allow its offset to develop a DC voltage at its output. This DC voltage is then sensed and used to inject a correction signal (usually a current) back into the amplifier to bring the offset to zero. This is done in a closed-loop manner, and therefore the loop gain reduces the residual offset. Once settled to the correction signal level, the autozeroing loop is broken, and the preamplifier is available for normal operation. During normal operation, the correction signal is generated by the correction path, as the value that produces it is stored in a capacitor. This storage can occur at either the preamplifier's output or input.

[0030] Figure 5This is a schematic diagram of an auto-zero comparator 500. The comparator 500 includes a preamplifier 502, a dynamic latch 504, and a feedback loop 506. This can be represented as an amplifier equivalent circuit 508. Figure 6 This is a graphical representation 600 of the phases 602 and 604 of the automatic zeroing comparator 500 and the clock signal 606 relative to time 608.

[0031] The comparator consists of a preamplifier with a finite gain (A), such that A = 5x to 20x. The preamplifier drives a dynamic latch, which responds to an operational adjustment connection (...). Figure 5 The preamplifier and the effective latch input reference offset are respectively determined by V. OS,Preamp and V OS,Latch Indication. Without applying any offset reduction techniques, the effective input reference offset of the comparator will be:

[0032] .

[0033] In most cases, since the primary source of imbalance is V OS,Preamp Therefore, the preamplifier offset is automatically zeroed. This can be achieved by adjusting the phase... During this period (when the signal path is disconnected), its input is short-circuited and its output is stored in a storage capacitor (C). AZ1 and C AZ2 This is achieved on the capacitor (C). AZ1 and C AZ2 voltage (V) X ) drives such as transconductors (gm AZ The auxiliary amplifier then injects a correction signal (such as current) into the main amplifier. This then drives its output to a theoretical zero level. For simplicity, assume an offset-free gm. AZ And assume the transconductance of the preamplifier is gm i = gm AZ This allows us to show the initial offset of the preamplifier along with its gain: A This is reduced. The total residual offset of the comparator relative to the input can then be expressed as follows:

[0034] .

[0035] Equation 2 shows that the auto-zeroing scheme does not suppress effective latch offset. In low-speed applications, this is usually not a problem, as the latch transistor can be appropriately sized for matching, thus reducing its initial offset. In high-speed applications, this is impractical due to increased parasitic capacitance and speed loss.

[0036] In high-speed ADC systems, this limitation can be overcome by introducing a self-calibrating architecture around the entire comparator. In these schemes, the entire comparator is placed in a feedback loop where an auxiliary input stage is configured to inject compensation current into the comparator's preamplifier. The voltage driving this auxiliary pair is generated by means of a voltage produced by injecting current into a capacitor via a charge pump. The charge pump is driven by the comparator output bit through several logic gates. This scheme and its associated timing diagram are shown in... Figure 7 , Figure 8 and Figure 9 As shown in the image.

[0037] Figure 7 This is a schematic diagram of a self-calibrating charge pump circuit 700. The charge pump circuit 700 includes a preamplifier 702, a dynamic latch 704, a feedback amplifier 706, and a charge pump control circuit 708 for controlling the charge pump 710. Figure 8 This is a graphical representation 800 of the signal from the self-calibrating charge pump circuit 700 relative to time 814. The signal includes... 802 804, fs 806, UP810, DN 812 and D out 816. Figure 9 This is a graphical representation of the signal relative to time 814 using a self-calibrating charge pump circuit 700 with reduced residual offset. The signal includes... 802 804, fs 806, UP 810, DN 812 and D out 816 and D out (1 / 2current) 818.

[0038] In principle, this architecture tends to create a relaxor oscillator around the clocked comparator, where the charge pump current I... CHP Memory capacitor C H and comparator input reference offset and comparator sampling clock f s (with period T) s Together, they determine its startup time and oscillation amplitude. At the start of the calibration phase, the input memory (V) of the auxiliary pair... X (Holding capacitor voltage) Reset. Due to the total input reference offset, the comparator is switched to one side, and thus the negative polarity of the loop, designed by the charge pump injection polarity, drives current into the holding capacitor to counteract the offset effect. Through an auxiliary pair, this voltage creates a compensating current flowing into the comparator, and once it overcomes the offset, the comparator output bit begins to switch. Switching the output changes the polarity of the charge pump output current, which reverses the direction of the voltage across the holding capacitor. This continues until the comparator switches again, and the process repeats like a relaxation oscillator. This results in a ripple on the holding capacitor's compensating voltage.

[0039] Assuming the transconductance of the auxiliary pair (gm) AUX ) and the transconductance of the preamplifier (gm) i If the input reference offset is the same as the comparator's and there is no hysteresis, then the ripple corresponds to the residual input reference offset of the comparator after calibration. Once the calibration phase is complete, the charge pump stops injecting, and the memory of the holding capacitor maintains the required amount of compensation current. The minimum residual offset achievable using this scheme can be expressed in Equation 3 as follows:

[0040] .

[0041] One limitation of this technique is that it requires an initial time for the self-calibration loop to reach an oscillating state. This will be the initial input reference offset V. OS,comp The charge pump current and the holding capacitor are functions of each other, which can be expressed in Equation 4 as:

[0042] .

[0043] Furthermore, another drawback of this method is that, for a fixed clock frequency (fixed by the application), the only way to reduce this residual offset (see Equation 3), for example, to a level below the noise level, is by reducing the charge pump current (I0). CHP ) and / or increase holding capacitor C H .like Figure 9 The drawback of this method, as shown and predicted by equation (4), is that the total initial settling time of the self-calibration loop (when starting from a reset) will increase by the same improvement factor. This can be an application-level disadvantage in terms of limiting the effective conversion rate of the system. A potential example of such a case is the previously mentioned automotive LiDAR. In such applications, a high conversion rate is desired because it is associated with the scan rate of the scanning system, which is coupled to the overall LiDAR frame rate.

[0044] Therefore, self-calibration techniques have good potential for use in the case of accurate high-speed comparators because they compensate for the offset of the dynamic latch in the back end of the comparator (as opposed to auto-zeroing methods alone). However, improvements are needed to enable both rapid stabilization and reduction of residual offset.

[0045] This disclosure presents a two-step self-calibration autozeroing method for high-speed comparators to achieve very low residual offset levels while maintaining relatively short calibration times. The system has applications in general high-speed ADCs, where this method is suitable for applications such as pulse-coded dTOF automotive LiDAR. Other potential applications include imager sensors with global shutters, indirect time-of-flight 3D sensors, and generally any data conversion system where a combination of high throughput and low offset is required.

[0046] The combination of the two methods in a two-step scheme involves one method continuing from the end of the first step as a calibration for the second step. Figure 10 The diagram shows the arrangement around the comparator, and... Figure 11A and Figure 11B The diagrams shown are timing diagrams. These diagrams provide an illustration of the voltage domain comparator case. The additional hardware required to implement this is minimal.

[0047] The offset reduction technique proposed here applies the closed-loop automatic zeroing stage as the first step to the preamplifier of the comparator, and at the end of this stage, the initial compensation voltage V is applied. X Stored in auto-zero capacitor C AZ Above. Since the preamplifier is wideband, this step can be achieved relatively quickly by utilizing the amplifier's exponentially stable behavior, which is faster than using... Figure 7 The self-calibrating loop can achieve linear stability much faster, as can be expressed in Equation 5:

[0048] .

[0049] Here, N is the number of time constants considered for stability. Since the second calibration step will deal with the residual offset after autozeroing, there is a possibility that the first step is not completely stable, which helps to further reduce the calibration time.

[0050] At the end of the first step (preamplifier auto-zeroing step), the input reference offset is equal to the residual offset predicted by equation (2) for the auto-zeroing comparator, which is much smaller than that of the uncalibrated comparator. After this, based on... Figure 7 The second step of the self-calibration scheme shown is closed-loop calibration applied to the auto-zero comparator. This second step aims to reduce the contribution of residual offset due to the misalignment of the dynamic latch.

[0051] One improvement is that the auto-zero capacitor C is already stored. AZ (V) X The correction voltage on V is not reset at the start of the self-calibration phase. This value is used as the initial condition for the second closed-loop operation, rather than as a reset voltage. XThe rest of the scheme is similar. Figure 7 The scheme involves a charge pump (in phase) (During operation) and the logic driving it from the comparator output. When the comparator is stuck at a given output due to residual offset, the charge pump to C... AZ An additional correction current is injected into the capacitor until it overcomes the residual offset and the output bit flips. This reverses the polarity of the charge pump, causing bit switching, and thus the relaxation oscillation effect begins.

[0052] The improvement is that the residual offset V of the loop after the auto-zeroing stage described by equation (2) is reduced. OS,res Instead of the loop starting from the initial uncalibrated comparator offset V described by equation (1), OS,comp To begin. Ignoring the effect of latch offset at the reference input, the residual offset can be approximated by the gain factor of the preamplifier. A This is reduced, thus significantly reducing the initial settling time.

[0053] As a result, when the second step—the self-calibration scheme—begins, the additional compensation required is no longer to compensate for the entire comparator offset, but only for the effect of the dynamic latch offset. Because this is smaller, the settling time of the second step will be much shorter for the same conditions as in the prior art (for the holding capacitor and charge pump current). This allows for a trade-off between a longer settling time in the second stage and a reduced residual offset. This can be done, for example, by choosing a smaller charge pump current. In this way, the residual offset can be effectively reduced to a value below the noise level without incurring additional settling time. Figure 11B The timing diagram in the paper compares this trade-off with existing technologies.

[0054] Alternatively, a trade-off can be made by selecting a system with a larger residual offset (if tolerance is applied) and then achieving a shorter calibration time. This can be valuable when the system conversion rate must be increased further.

[0055] It should be noted that Figure 10 The two-step offset compensation method proposed is not limited to the voltage domain comparator architecture shown here, but can also be extended to a current domain comparator, where the preamplifier is replaced by current-in and current-out amplifier stages, thereby injecting the current signal into the dynamic latch. In such an architecture, the output current of the compensated auto-zero transconductance can still be injected into the current domain preamplifier. Figure 8 The configuration is shown in the figure. As can be seen, in terms of the current domain signal path, a slight modification is required for the input switch to perform auto-zeroing (and calibration) in the absence of an input signal. This means that the input should be disconnected instead of creating a short circuit as in the voltage domain comparator.

[0056] Note: The technical terms used here are:

[0057] The two-step offset calibration is based on a first automatic zeroing step of the preamplifier, followed by a global comparator self-calibration loop that further modifies the correction signal on the memory cap using a charge pump.

[0058] The benefit is that it compensates for the offset of the overall comparator (preamplifier + latch), but allows for a shorter overall calibration time when very low residual offset is desired.

[0059] It does this by first rapidly and automatically zeroing the preamplifier offset at a rate determined by the preamplifier bandwidth and therefore not by the charge pump current.

[0060] The remaining offset is then driven to a very low residual offset, thereby closing the self-calibration loop around the comparator and injecting a small correction current with a charge pump in a relatively short time (because most of the offset has been calibrated in the first step).

[0061] Program code embodying the algorithms and / or methods described herein can be distributed individually or collectively as a program product in various different forms. The program code can be distributed using a computer-readable storage medium having computer-readable program instructions thereon for inducing a processor to perform one or more embodiments. Computer-readable storage media, inherently non-transitory, can include volatile and non-volatile, removable and non-removable tangible media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media may further include RAM, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other solid-state memory technologies, portable compact disc read-only memory (CD-ROM) or other optical storage devices, magnetic tape, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and can be read by a computer. Computer-readable program instructions can be downloaded from the computer-readable storage medium to a computer, another type of programmable data processing device, or another device, or downloaded via a network to an external computer or external storage device.

[0062] Computer-readable program instructions stored in a computer-readable medium can be used to direct a computer, other type of programmable data processing apparatus, or other device to operate in a particular manner, causing the instructions stored in the computer-readable medium to produce an article of writing that includes instructions to implement the functions, actions, and / or operations specified in the flowchart or figure. In some alternative embodiments, the functions, actions, and / or operations specified in the flowchart and figure can be reordered, processed sequentially, and / or processed in parallel in accordance with one or more embodiments. Furthermore, any flowchart and / or figure may include more or fewer nodes or blocks than those illustrated in accordance with one or more embodiments.

[0063] While all aspects of the invention have been described through various embodiments, and while these embodiments have been described in considerable detail, the applicant does not intend to limit the scope of the appended claims or restrict them in any way to such details. Additional advantages and modifications will readily become apparent to those skilled in the art. Therefore, the invention, in its broader aspects, is not limited to the specific details, representative apparatuses and methods, and the illustrative examples shown and described. Thus, deviations from such details may be made without departing from the spirit or scope of the overall inventive concept.

Claims

1. A comparator circuit, comprising: a differential preamplifier including a differential memory capacitor; a dynamic latch configured to latch an output of the differential preamplifier at a sampling frequency; an auto-zero loop including an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on a voltage across the differential memory capacitor; a self-calibration circuit including a charge pump configured to adjust the voltage across the differential memory capacitor based on an output of the dynamic latch; and control logic configured to, send a first signal during a first time period to enable the auto-zero loop to provide an initial mis-calibration of the differential preamplifier, send a second signal during a second time period occurring after the first time period to enable the self-calibration circuit to provide a mis-calibration of the differential preamplifier that minimizes a mis-calibration of the dynamic latch, wherein the first time period has a duration based on a bandwidth of the differential preamplifier, and wherein the first and second time periods have a duration that is equal to or less than a self-calibration comparator residual mis-calibration, and a residual mis-calibration of the comparator circuit is less than the self-calibration comparator residual mis-calibration.

2. The comparator circuit of claim 1, wherein the duration is less than or equal to a settling time of a self-calibration comparator, the settling time expressed by 3. The comparator circuit of claim 1, wherein the duration is based on a settling time expressed by ， wherein C H is the average capacitance of the differential memory capacitor, V OS,preamp is the initial input offset of the differential preamplifier, and I CHP is the current of the charge pump.

4. The comparator circuit of claim 3, wherein the number of time constants is between 1 and 10. ， where N is the number of time constants between 1 and 100, C AZ is the auto-zeroed capacitance, and gmi is the transconductance of the preamplifier.

5. The comparator circuit of claim 1, wherein the initial mis-calibration is based on a first correction value stored on the differential memory capacitor, and during the second time period, minimizing a mis-calibration due to the dynamic latch includes adding an additional correction value to the first correction value stored on the differential memory capacitor. The residual mis-calibration of the comparator circuit after the second time period is separated from a calibration time of the circuit.

6. The comparator circuit of claim 1, wherein, 7. A method of controlling a comparator circuit of any of claims 1-6, comprising: during a first time period, enabling an auto-zero loop to provide an initial mis-calibration of a differential preamplifier including a differential memory capacitor; and during a second time period after the first time period, enabling a self-calibration circuit to provide a mis-calibration of the differential preamplifier and to minimize an output mis-calibration of a dynamic latch, wherein the first time period has a duration based on a bandwidth of the differential preamplifier, and wherein the first and second time periods have a duration that is equal to or less than a self-calibration comparator residual mis-calibration, and a residual mis-calibration of the comparator circuit is less than the self-calibration comparator residual mis-calibration. ​ 8. The method of claim 7, wherein the dynamic latch is configured to latch an output of the differential preamplifier at a sampling frequency, the auto-zero loop includes an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on a voltage across a differential memory capacitor, and the self-calibration circuit includes a charge pump configured to adjust the voltage across the differential memory capacitor based on an output of the dynamic latch.

9. The method of claim 7, wherein the duration is less than or equal to a settling time of the self-calibrating comparator, the settling time expressed by ， wherein C H is the average capacitance of the differential memory capacitor, V OS,preamp is the initial input offset of the differential preamplifier, and I CHP is the current of the charge pump.

10. The method of claim 7, wherein the duration is based on a settling time, the settling time expressed by ， where N is the number of time constants between 1 and 100, C AZ is the auto-zeroed capacitance, and gmi is the transconductance of the preamplifier.

11. The method of claim 10, wherein the number of time constants is between 1 and 10.

12. A comparator circuit, comprising: a differential preamplifier including a differential memory capacitor; a dynamic latch configured to latch an output of the differential preamplifier at a sampling frequency; an auto-zero loop including an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on a voltage across the differential memory capacitor, wherein the correction signal is injected when the preamplifier is disconnected from a signal path, and the auto-zero loop is disconnected and the preamplifier is connected when settled to a correction signal level; and a self-calibration circuit including a charge pump configured to adjust a current to the differential memory capacitor based on an output of the dynamic latch.

13. The comparator circuit of claim 12, wherein a duration of the first time period is less than or equal to a settling time of the self-calibrating comparator, the settling time expressed by 14. The comparator circuit of claim 12, wherein a duration of the first time period is based on a settling time, the settling time expressed by 15. The comparator circuit of claim 12, wherein the initial offset calibration is based on a first correction value stored on the differential memory capacitor, and during the second time period, minimizing the offset due to the dynamic latch includes adding an additional correction value to the first correction value stored on the differential memory capacitor. ​ ​ ​ ， wherein, C H is the average capacitance of the differential memory capacitor, V OS,preamp is the initial input offset of the differential preamplifier, and I CHP is the current of the charge pump. ​ ， where N is the number of time constants between 1 and 100, C AZ is the auto-zero capacitance, and gmi is the transconductance of the preamplifier. ​

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