Programming Method of Non-Volatile Memory Cell and Non-Volatile Memory Device

Abstract

The present application relates to a programming method for non-volatile memory cells and a non-volatile memory device. A selective non-volatile memory programming method for selected memory cells in a memory array is described to reduce or avoid programming interference with unselected memory cells. The selective programming method includes: applying a programming pulse to the selected memory cells to be programmed and unselected memory cells, wherein the programming pulse allows the unselected memory cells to vary within a predetermined range; boosting the region of the unselected memory cells; and setting a threshold time of the programming pulse, wherein the threshold time is defined as the time when the absolute value of the voltage difference between the floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a defined threshold.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application Serial No. 62 / 942,086, filed on November 30, 2019, with the title "Accurate Synapse Programming Method". Technical Field

[0003] The present invention relates to non - volatile memory technology. Specifically, the present invention describes a programming pulse width control scheme for logic - compatible flash memory that enables the memory cell current to flow within a predetermined target current range. Background Art

[0004] Flash memory is a typical non - volatile memory that can permanently store information even when the system power is turned off. Logic - compatible flash memory is a type of flash memory constructed only with logic devices. Figure 1 A conventional memory cell array 100 is shown in a 2D form of multiple rows and multiple columns. The structure of the memory cell array 100 includes multiple rows and multiple columns of logic - compatible flash memory cells, namely "cell A1", "cell A2", and "cell A3" to "cell C1", "cell C2", and "cell C3". Bit lines extend beside the multiple cells that make up a column. Each bit line connects multiple cells in the same column to one sense amplifier circuit located at the end of the column. The memory cell can adjust its current level based on the stored information in the cell. The sense amplifier determines the cell state by sensing the current level. Even though not depicted in Figure 1 there is a set of control lines (read lines) connected to the cells A, B, and C arranged in each row for memory operations such as discharging or discharging the memory cells. Given this memory cell array, when a programming operation is selectively performed only on some memory cells and when those cells (i.e., cells A1, B1, and C1) share a common read line, the unselected memory cells (e.g., cell C1) should not be affected by the programming operation of the selected memory cells (e.g., cells A1 and B1) and must maintain their original state. Summary of the Invention

[0005] The present invention discloses a method for selectively programming a non-volatile memory composed of standard logic devices. According to the present invention, a method for programming non-volatile memory cells in a memory array includes: applying a predefined programming pulse to both the selected memory cells to be programmed and the unselected memory cells, and the unselected memory cells will not be changed due to the programming of the selected memory cells or even if changed to some extent, the unselected memory cells will only be changed within a predetermined allowable range; boosting the voltage of the region of the unselected memory cells; setting a threshold time of the predefined programming pulse, wherein the threshold time is defined as the time when the absolute value of the voltage difference between the floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a defined threshold.

[0006] In one embodiment, the method further includes: applying the programming pulse to the unselected memory cells in the memory array until the threshold time; and boosting the voltage potential of the unselected memory cells until the threshold time. In one embodiment, the programming pulse starts to drop to the ground potential at or near the threshold time. Moreover, in another embodiment, the threshold is the maximum voltage difference between the floating gate of the unselected memory cell, which is used to prevent unwanted programming of the unselected memory cell, and the boosted region of the unselected memory cell.

[0007] In one embodiment, the predefined programming pulse is applied to the gate line connected to the selected memory cells and the unselected memory cells. In another embodiment, the boosted region of the unselected memory cells includes the source region, the drain region formed on the corresponding substrate of the unselected memory cells, and the channel region between the source region and the drain region. In one embodiment, the boosted region is boosted to a specific voltage level by the voltage potential on the floating gate of the unselected memory cell. In another embodiment, the voltage level of the predefined programming pulse is set low enough so that while the selected memory cells are being programmed, the voltage difference between the floating gate of the unselected memory cells and the boosted region is low enough to prevent the programming of the unselected memory cells.

[0008] In one embodiment, the duration of a predefined programming pulse after rising and before falling is kept long enough as long as the predefined programming pulse is low to the ground potential or approximately the ground potential at or near the threshold time. In one embodiment of the present invention, a non-volatile memory device includes: a voltage signal pulse generator configured to apply a predefined programming pulse; and an array of non-volatile memory cells. In one embodiment, the voltage signal pulse generator is configured to generate a signal with a predefined programming pulse for non-volatile memory cells in the memory cell array to be sent to both selected memory cells to be programmed and unselected memory cells, where the unselected memory cells will not be changed due to the programming of the selected memory cells, or even if changed to some extent, the unselected memory cells will only change within a predetermined range. In another embodiment, the voltage signal pulse generator is further configured to set the threshold time of the predefined programming pulse, where the threshold time is defined as the time when the absolute value of the voltage difference between the floating gate of the unselected memory cell and the boost region of the unselected memory cell reaches a defined threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The features of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings. It is to be understood that the drawings only depict typical embodiments of the present invention and thus are not to be considered as limiting the scope. The present invention is described with additional specificity and detail by using the drawings, in which:

[0010] Figure 1 An array structure of non-volatile memory cells with multiple rows and multiple columns is shown.

[0011] Figure 2A and Figure 2B A circuit diagram of a bias logic-compatible flash memory cell for selective programming based on a self-boosting inhibit scheme according to an embodiment of the present invention is shown.

[0012] Figures 3A to 3H Another circuit diagram of a bias logic-compatible flash memory cell for selective programming based on a self-boosting inhibit scheme according to an embodiment of the present invention is shown.

[0013] Figure 4 is a flowchart depicting Figures 3A to 3H the method of programming the memory cells shown in

[0014] Figure 5 is a timing diagram depicting various voltage signals for programming the selected row memory cells.

[0015] Figure 6 shows two exemplary pulses applied to the control gate lines CG1, CG2 of the memory cell array in Figure 2A and Figure 2B during the memory cell programming and verification iterations.

[0016] Figure 7 shows a cross-section of a series of transistors of a logic-compatible flash memory cell formed on a P-doped body and an illustration of a programming inhibit bias condition according to an embodiment of the present invention.

[0017] Figure 8A and Figure 8B shows exemplary voltage pulses applied to the floating gate FG and the boost node of unselected memory cells according to one embodiment.

[0018] Figure 9 shows a block diagram of a voltage signal pulse generator and a non-volatile memory cell array according to an embodiment of the present invention.

[0019] Figure 10 shows a chip including a central processing unit (CPU), a volatile memory, and a non-volatile memory implementing a pulse width control programming scheme according to an embodiment of the present invention. Detailed Description

[0020] Figure 2A and Figure 2B shows a circuit diagram depicting two logic-compatible flash memory cells arranged in the same row for erase and program operations. Figure 2A and Figure 2B Each memory cell in Figure 1 can be the memory cell depicted in Figure 2A This flash memory cell is logic-compatible because all the individual devices in the cell are constructed using standard logic devices. Figure 2A shows a memory cell biased for an erase operation. Figure 2B shows a memory cell biased for a program operation.

[0021] Each of memory cells A and B includes a drain select transistor 212 / 232, a source select transistor 216 / 236, and a read transistor 214 / 234 coupled to a pair of control gates 218 and 220 (for cell A) and 238 and 240 (for cell B). Cells A and B share control gate lines CG1 / CG2, select gate lines SG1 / SG2, and a source line SL along a row. However, cells A and B are respectively connected to their respective bit lines BL_A, BL_B. Cell A is connected to bit line BL_A via drain select transistor 212. Cell B is connected to bit line BL_B via drain select transistor 232. The read transistor 214 in cell A is connected to a pair of control gate transistors 218 and 220 that form a floating gate FGA. The read transistor 234 in cell B is connected to a pair of control gate transistors 238 and 240 that form a floating gate FGB. In addition, the upper control gate transistors 218 and 238 connected to the upper control gate line CG1 are larger in size than the lower control gate transistors 220 and 240 connected to the lower control gate line CG2. As a result, the voltage potentials of floating gates FGA and FGB are maintained close to the voltage of the first control gate line CG1.

[0022] The floating gate FGA in cell A and the floating gate FGB in cell B are capacitively coupled to their respective control gates: control gates 218, 220 for cell A, and control gates 238, 240 for cell B. Thus, cells A and B can each store data in the form of a threshold voltage, the lowest voltage at which the respective cell can turn on. The threshold voltage is controlled by the amount of charge retained on the floating gate FGA of cell A, the floating gate FGB of cell B. That is, before the read transistor is turned on to allow conduction between its source and drain, a certain level of voltage must be applied to control gate lines CG1 and CG2 depending on the level of charge on floating gates FGA and FGB, and during a read operation, current flows between the select transistors in each of cells A and B. The floating gates FGA and FGB can store two or more than two states. With respect to these two states, cells A, B can be programmed or erased. When cells A and B are in a fully erased state, a sparse number of electrons are trapped in the floating gate (FG) nodes in each of cells A and B; thus, the cells can conduct a large amount of current during a read operation. When the cells are in a fully programmed state, a large number of electrons are stored in the FG nodes of the logic compatible flash cells; thus, the cells conduct a small amount of current during a read operation.

[0023] Figure 2AShows the bias conditions for both memory cells A and B for an erase operation. The erase operation occurs through a process of removing electrons from the floating gates in each memory cell. For this case, a high positive voltage HV (about +10V) is applied to the select gate line CG2, and a ground voltage is applied to the select gate line CG1. The sizes of the upper control gates 218 and 238, which are both connected to CG1, are significantly larger than the sizes of the lower control gates 220 and 240, which are both connected to CG2. Thus, the voltage of the upper gates causes the FG node voltage potential to approach the ground voltage potential. Therefore, the voltage difference between this near-ground voltage potential of the lower control gate and the floating gate is sufficient to repel the trapped negative charges inside the floating gate through the low control gate.

[0024] Figure 2B Shows the flash memory cell bias conditions for selective programming using a self-boosting inhibition scheme. Here, both memory cells A and B share the row signal lines SG1, CG1, CG2, SG2, SL. Cell A is biased to be programmed and cell B is boosted to be unaffected by the programming of cell A. For this selective programming scheme, a high programming voltage HV is applied to the control gate. A specific power supply voltage VDD is applied to the first select gate line SG1 and the source line SL. The GND level is applied to the second select gate line SG2. To program cell A1, the drain select transistor 212 in cell A1 is set to be conductive, the bit line BL_A is grounded, and the power supply voltage VDD is applied to the gate of the drain select transistor 212 in cell A1. As a result, the drain select transistor 212 in memory cell A1 is biased to the conductive state (i.e., "on"). The source select transistor 216 in cell A is turned off by grounding the gate of the transistor. Then, when the programming voltage HV (i.e., almost 8V) is applied to the control gate lines CG1 and CG2, the voltage difference between the floating gate FGA of cell A and the electron channel of the read transistor 214 in cell A becomes high enough. Thus, electrons are injected into the floating gate FGA through Fowler-Nordheim tunneling, and when the electrons accumulate there, the floating gate becomes negatively charged, and then the threshold voltage of cell A increases. The threshold voltage of cell A1 indicates the programming state in response to the stored electrons.

[0025] Cell B is a memory cell not selected in programming. Thus, cell B is biased to maintain its original memory state (bit information) without being changed by the programming operation of cell A, or even if it is changed to some extent, it is only changed within a predetermined allowable range. For this purpose, the bit line BL_B and the gate of the drain selection transistor 232 in cell B are set to the power supply voltage VDD, so the drain selection transistor 232 is turned off. The source selection transistor 236 in cell B is also set to be turned off. Although the source of the source selection transistor 236 receives VDD which is higher than 0V, the source selection transistor 236 is turned off because its gate is grounded via the second selection gate line SG2. Thus, by turning off the drain selection transistor 232 and the source selection transistor 236, the electron channel under the read transistor 234 is electrically isolated. When this occurs, the source, drain, and electron channel of the read transistor 234 in cell B become electrically isolated from the bit line BL_B and enter a "floating state". The read transistor 234 is capacitively coupled to a large-area floating gate FGB charged by the control gate lines CG1 and CG2. Thus, in response to the programming voltages on the control gate lines CG1 and CG2, the read transistor 234 will be self-boosted to a high enough voltage level to prohibit unwanted programming of cell B by reducing the voltage difference to below the minimum voltage for electron injection into the floating gate FGB. The electron channel is boosted to half or almost half of the programming voltage HV (i.e., almost half of 8 volts: 4 volts). Under this biasing condition, the voltage difference between the floating gate FGB and the electron channel is intended to be small enough to prohibit electron tunneling from the electron channel to the floating gate FGB. However, due to the voltage difference between the floating gate FGB and the electron channel, a certain amount of unwanted electron tunneling may still occur. Thus, the state of cell B can be changed to a certain level (i.e., be disturbed), and when it exceeds the predefined threshold defined by the sense amplifier depicted in ( Figure 1 ), then the sense amplifier circuit may output an incorrect value during the read operation of the cell. However, if the changed level does not exceed the predefined threshold, then the sense amplifier circuit with high enough precision will still output the correct value during the read operation. Note that a sense amplifier circuit with higher precision is more complex and larger than a sense amplifier circuit with lower precision. Thus, it is preferable to limit or reduce the amount of unwanted electron tunneling that causes interference during the programming operation so that during the read operation of the cell, a less complex and compact sense amplifier can be used to sense the correct output from the cell.

[0026] Figures 3A to 3HShows the bias conditions for a series of memory operations: erase, program, and read, for a flash memory cell array. Cells A, B, and C are respectively connected to bit lines BL_A, BL_B, and BL_C. The control gates of the individual cells in each string are connected to a pair of control gate lines CG1 / CG2. The drain select transistor 322 in cell A connects the memory cell A to the bit line BL_A. The drain select transistor 342 in cell B connects the memory cell B to the bit line BL_B. The drain select transistor 362 in cell C connects the memory cell C to the bit line BL_C. The drain select transistor in each memory cell is connected to the first select gate line SG1, and the source select transistor in each cell is connected to the second select gate line SG2. Figure 3A Shows the bias conditions for the erase operation for cells A, B, and C. Before programming, the memory cells A, B, and C are erased by applying a high voltage HV of about 10 volts to the second control gate line CG2. The erased memory transistors can store the data "1".

[0027] Figure 3B Shows the bias conditions for programming only cell C in the array. The memory cell C is programmed towards the current level C flowing on the bit line BL_C by applying a high voltage HV_C to the control gate lines CG1 and CG2 and grounding the bit line BL_C. However, the programming of cell C does not affect cells A and B, and even if cells A and B are changed to some extent, they only vary within a predefined allowable range because when receiving the high voltage HV_C through the control gate lines CG1 / CG2, their bit lines BL_A and BL_B are biased by the power supply voltage VDD.

[0028] Figure 3C Shows the bias conditions for verifying the memory cells of the programmed cell C. Once the programming operation for the memory cell C is executed, an internal check to ensure whether cell C is adequately programmed is performed by sensing the current level Cur_C1 in the bit line BL_C while the control gate lines CG1 and CG2 are biased with a read voltage VRD_C. If the memory cell C conducts a current greater than the target level in response to the read voltage VRD_C, the state of cell C is not programmed correctly. Otherwise, if cell C conducts a current with the target level or less than the target level in response to the read voltage VRD_C, cell C is programmed correctly. As Figure 3B and Figure 3C shown, this program - verify step will be repeated until cell C can conduct a current with the current level C during a read operation. During the execution of this program - verify operation on the memory cell C, the memory cells A and B will be maintained or held close to the erase condition by being prohibited from programming.

[0029] Figure 3D Shows the bias conditions for programming memory cell B after verifying the programmed memory cell C. Then, programming of memory cell B is performed by applying a high voltage HV_B to control gate lines CG1 and CG2 and grounding bit line BL_B. However, when receiving a large positive voltage HV_B through control gate lines CG1 / CG2, programming of memory cells A and C is prohibited by biasing the bit lines of memory cells A and C to the power supply voltage VDD, respectively.

[0030] Figure 3E Shows the bias conditions of the memory cells for verifying memory cell B. Once the programming operation of memory cell B is performed, an internal check to ensure whether memory cell B is sufficiently programmed is carried out by sensing the current level Cur_B1 in bit line BL_B while control gate lines CG1 and CG2 are biased with a read voltage VRD_B. If memory cell B conducts a current greater than the target level in response to the read voltage VRD_B, the state of memory cell B is not programmed correctly. Otherwise, if memory cell B conducts a current with the target level or less than the target level in response to the read voltage VRD_B, memory cell B is programmed correctly. As Figure 3D and Figure 3E shown, this program - verify step will be repeated until memory cell B can conduct a current with a current level B during the read operation. During the program - verify operation of memory cell B, memory cells A and C maintain their conditions (not changed by the operation of cell B), or even if changes occur, they still remain within a predefined allowable range (memory cell A is in the erased state, memory cell C is in the programmed state).

[0031] Figure 3F Shows the bias conditions for programming memory cell A after verifying memory cell B. Similar to other memory cells B and C, programming of memory cell A is performed by applying a high voltage HV_A to control gate lines CG1 and CG2 and grounding bit line BL_A. On the other hand, when receiving a large positive voltage HV_A through control gate lines CG1 / CG2, programming of memory cells B and C is prohibited by biasing the bit lines of memory cells B and C to the power supply voltage VDD, respectively.

[0032] Figure 3GShows the bias conditions of the memory cells for verifying that memory cell A has been programmed correctly. Once the programming of memory cell A is executed, an internal check to ensure whether memory cell A is sufficiently programmed is performed by sensing the current level Cur_A1 on sense bit line BL_A while the control gate lines CG1 and CG2 are biased with read voltage VRD_A. If memory cell A conducts a current greater than the target level in response to read voltage VRD_A, the state of memory cell A is not programmed correctly. Otherwise, if memory cell A conducts a current with the target level or less than the target level in response to read voltage VRD_A, memory cell A is programmed correctly. As Figure 3F and Figure 3G shown, this program-verify step will be repeated until memory cell A can conduct a current with current level A during the read operation. During the program-verify operation on memory cell A, memory cells B and C maintain their conditions (not changed by the operation of cell A), or even if there are changes, they still remain within a predefined allowable range (memory cells B and C are in the programmed state), and are protected from any unwanted (programming) interference caused by the programming of memory cell A.

[0033] Figure 3H Shows the bias states for flash memory cells A, B, and C to perform read operations respectively. After programming all memory cells A, B, and C, the stored cell values can be read by applying read voltage VRD to control gate signals CG1 and CG2. As previously described by Figures 3A to 3G while the unselected memory cells are not affected by the programming, the selected memory cells are programmed, or even if affected, by implementing the programming inhibition bias condition, the unselected memory cells are only affected within an allowable range. And the cell currents from cells A, B, and C should be close to their target current levels Cur_A, Cur_B, and Cur_C respectively.

[0034] Figure 4 is a depiction of Figures 3A to 3HFlowchart of a method for programming non-volatile memory cells shown therein. In step 400, memory cells A, B, and C to be programmed are erased. In step 402, programming of memory cell C is implemented. A first programming voltage is applied to control gate lines CG1 and CG2, and its connected bit line BL_C is grounded. In step 404, the state of memory cell C is verified. To determine whether memory cell C is programmed correctly, the content of memory cell C is read by applying a reference voltage VRD_C to control gate lines CG1 and CG2. In step 406, if memory cell C conducts a current higher than the target level through bit line BL_C, memory cell C is not programmed correctly at the target level. In that case, the programming operation of step 402 and the verification operation of step 404 will be repeated until it is determined that memory cell C is programmed correctly by sensing its conduction current. If memory cell C conducts a current lower than the target level or has a current Cur_C1 at the target level, memory cell C is verified as being programmed correctly.

[0035] In step 408, after it is found that memory cell C is programmed correctly, programming of memory cell B is implemented by biasing bit line BL_B of memory cell B to approximately the ground level. Also, bit lines BL_A and BL_C are biased by power supply voltage VDD to protect other memory cells A and C from any unwanted programming caused by the programming of memory cell B. In step 410, the state of memory cell B is verified. Similar to memory cell C, to determine the state of memory cell B (whether it is programmed or erased), the content of memory cell B is read by applying an approximate reference voltage VRD_B to the control gate line connected to memory cell B.

[0036] In step 412, if memory cell B conducts a current higher than the target level through bit line BL_B, memory cell B is not programmed correctly. In that case, the programming operation and the verification operation of steps 408 and 410 will be repeated until it is determined that memory cell B is programmed correctly by sensing its conduction current. If memory cell B conducts a current lower than the target level or has a current Cur_B1 at the target level, memory cell B is verified as being programmed correctly.

[0037] In step 414, after determining that the memory cell B is programmed correctly, programming of the memory cell A is implemented by biasing the bit line BL_A of the memory cell A to approximately the ground level while biasing the other memory cells B and C to the supply voltage VDD. Thus, the electrons stored in the memory cells B and C are limitedly affected by the programming of the memory cell A. In step 416, the state of the memory cell A is verified. To determine whether the memory cell A is programmed correctly, the content of the memory cell A is read by applying an approximate reference voltage VRD_A to the control gate line connected to the memory cell A.

[0038] In step 418, if the memory cell A conducts a current at or above the target level through the bit line BL_A, the memory cell A is not programmed correctly. In that case, the programming operation and the verification operation of steps 414 and 416 are repeated until the memory cell A is determined to be programmed correctly by sensing its conduction current. If the memory cell A conducts a current Cur_A1 below the target level, the memory cell A is verified as being programmed correctly.

[0039] In step 420, once it is determined that all the selected memory cells A, B, and C are programmed correctly, the programming operation of the row memory array of the logic-compatible flash memory ends. Since different target programming levels are set for each cell, each cell can be selectively programmed and verified while largely protecting the programmed-off cells from unwanted programming through the above-described self-boosting technique.

[0040] Figure 5 is a timing diagram depicting various voltage signals for programming the selected row memory cells. This programming method can selectively program the cells in the row memory array through Figure 2A and Figure 2B and Figures 3A to 3H the self-boosting method shown in. The sequential voltages on the control gate lines CG1 / CG2 include programming voltage pulses and verification voltage pulses. The phase of the programming pulse consists of the times for voltage rise, programming, and voltage fall. Similarly, the phase of the verification pulse consists of the times for voltage rise, verification, and voltage fall. Due to the significant (large) parasitic capacitance of the long wires carrying the control signals in the memory array, these rise and fall times can be a large part of the overall programming time.

[0041] In Figures 3A to 3HThe combined sequence of input voltage signals for programming three memory cells A, B, and C over a certain period of time is as follows: At time t0, a power signal with power supply voltage VDD is applied to the select gate line SG1 and the source line SL, the control gate lines CG1 / CG2 are grounded, and the select gate line SG2 has a ground voltage. After the levels of the control gate lines CG1 / CG2 start to rise from time t0, at time t1, they are raised to the target programming level. At time t2, the levels of the control gate lines CG1 / CG2 start to decrease and, after they have dropped, return to the ground level at time t3. At time t4, the power supply voltage VDD on the source line SL starts to decrease until it reaches zero volts. At time t5, a verify pulse is applied to the control gate lines CG1 / CG2 until it reaches the target level. At time t6, this verify pulse is decreased to the ground level. At time t7, a power signal is applied to the source line SL so that it returns to the power supply voltage VDD. Once the programming of the first memory cell C is completed, after a specified time interval, the next cycle of programming / verify pulses for the next memory cells (i.e., cells B and A) is restarted.

[0042] Figure 6 illustrates two exemplary pulses applied to the control gate lines CG1, CG2 of a memory cell array during a memory cell programming and verification iteration. During Figures 3A to 3H the upper and lower figures both illustrate an exemplary programming pulse sequence for trapping a sufficient number of electrons into the floating gates of the memory cells A, B, and C in Figure 6 Moreover, as discussed in Figures 3A to 3H a verify pulse is applied to the control gate lines CG1, CG2 after some delay following the application of each programming pulse having a pulse high width T1 or T2. Figure 5

[0043] The figure above shows a sequence of three programming / verification pulse cycles. The high time of the total cumulative programming pulses (program pulse high time) is calculated as the product of the high duration of each programming pulse and the number of iterations, which is 3. In contrast, the figure below shows a sequence of six programming / verification pulse cycles, with the high duration of each programming pulse being T2. Therefore, the high time of the total cumulative programming pulses is calculated as the product of the high duration T2 of each programming pulse and the number of iterations, which is 6. As a result, assuming that the duration T1 is approximately twice the duration T2, the high times of the cumulative programming pulses for the two cases (i.e., T1*3 and T2*6) can be approximated. Thus, once the programming-verification pulses for three and six iterations are applied, the programming of the memory cell can be completed. On the other hand, the programming pulses with duration T1 or T2 both require a rising time before programming and a falling time after programming. When programming the memory cell with the programming pulse having duration T1, it is expected that there will be three rising and falling cycle times. On the other hand, when programming the same memory cell with the programming pulse having duration T2, it is expected that there will be six rising and falling cycle times.

[0044] If the rising and falling cycles take the same amount of time regardless of the high width of the programming pulse, compared with the programming / verification iteration with the shorter pulse high width T2, the programming / verification iteration with the longer pulse high width T1, which requires fewer rising and falling cycles and fewer verification pulses, significantly reduces the total programming / verification time. In other words, the total programming time is much shorter in the case of the longer programming pulse width T1 because it can amortize the timing overhead of pulse rising and falling, the verification pulse time, and the related delay between pulses.

[0045] Figure 7 A cross-section of a series of transistors of a logic-compatible flash memory cell formed on a P-doped body and an illustration of the programming inhibit bias condition are shown. In Figure 7 In Figure 2B the memory cell B of "self-boost inhibit programming via" is formed on a P-doped substrate. As previously mentioned, in order to turn off the drain select transistor, both the n+ drain region of the transistor (connected to the bit line BL) and the gate of the transistor (connected to the select gate line SG1) are biased to VDD. Moreover, in order to turn off the source select transistor, the power supply voltage VDD is provided to the n+ source region of the transistor (connected to the source line SL), and the gate of the transistor (connected to the select gate line SG2) is grounded.

[0046] The boost node driven to the boost voltage BV, shown by the dashed line, includes two "conductive lines" mounted on the p-substrate. The first of the conductive lines is located between the drain select transistor (having the select gate line SG1) and the read transistor, and the second of the conductive lines is located between the source select transistor (having the select gate line SG2) and the read transistor. As previously discussed, the floating gate FG of the read transistor is electrically connected in series to the control gate lines CG1, CG2, where the control gate lines CG1, CG2 carry the programming voltage shared with other memory cells in the flash memory array, and the floating gate FG is connected to a specific high voltage HV.

[0047] When both the drain select transistor and the source select transistor are turned off, the region defined as the boost node BV becomes electrically floating. The boost node BV is capacitively connected to the floating gate FG and the P-doped body substrate. Thus, when a high voltage is applied to the floating gate, the boost node will self-boost to a specific voltage level. Ideally, the voltage difference between the floating gate FG and the electron channel is small enough to prohibit electrons from tunneling from the electron channel to the floating gate FG even when the programming voltage is applied to adjacent memory cells in the selected row memory array.

[0048] The boost node voltage at a given time can be approximately determined by the following formula: Boost node voltage (time) = (approx.) Cap_A / (Cap_A + Cap_B) × FG voltage - (i1 + i2)*time / (Cap_A + Cap_B), where Cap_A represents the capacitance between the FG and the boost node, Cap_B represents the capacitance between the boost node and the body (GND), i1 is the junction leakage current from the n+ source and drain regions to the body, and i2 is the subthreshold leakage current from the boost node to the bit line BL through the drain select transistor whose gate is connected to the select gate line SG1. That is, "i1" in the dashed arrow represents the junction leakage current to the body, and "i2" in the dashed arrow represents the subthreshold leakage current through the drain select transistor.

[0049] Assuming that Cap_A can have an approximate value of Cap_B, after the programming pulse rises to the specified high level value, the boost node immediately has a self-boost voltage that rises to approximately 50% of the voltage (= HV) of the floating gate FG of memory cell B. However, when the programming pulse is maintained at a high level, the junction leakage current to the body and the subthreshold leakage current through the drain select transistor can discharge the boost node voltage. As a result, after a certain time, the voltage difference between the floating gate and the electron channel of the read transistor becomes high enough to allow Fowler-Nordheim tunneling from the electron channel to the floating gate FG, which is not desirable for programming the prohibited cell. When tunneling occurs, Figure 2A andFigure 2B Unwanted programming of memory cell B can occur, thus disturbing its original state.

[0050] Figure 8A and Figure 8B shows when Figure 2A and Figure 2B and Figures 3A to 3H the selected memory cells in the array are programmed with the same control gate pulses in, (1) the variation of the control gate voltage pulses on the control gate lines CG1 and CG2 and (2) the variation of the boost node voltage caused by the leakage current of the unselected memory cells described in Figure 7 The shown voltage pulses consist of at least three stages: a voltage rising stage, a programming stage, and a voltage falling stage.

[0051] Between time t1 and time t2 (rise time), the voltage signals applied to the control gate lines CG1 and CG2 increase from 0V to the target programming voltage level, and the voltage of the floating gate FG increases to a specific voltage level through connection with the control gate lines CG1 and CG2. Then, since the boost node of the unselected memory cell enters an electrically isolated state, i.e., a "floating state", as described in Figure 2B the boost node voltage increases to another specific voltage level through connection with the FG node. At time t2, the programming stage begins. After time t2, the control gate lines CG1 / CG2 are maintained at the high programming voltage, and the FG is also maintained at a substantially high voltage level. The target programming voltage level of the control gate lines CG1 and CG2 that connect to pull up the FG node needs to be low enough (i.e., approximately less than 12V) so that the voltage difference between the FG and the boost node is less than the voltage increment threshold (i.e., approximately 6V). As a result, for the prohibited programming cell, the voltage difference between the FG node and the boost node becomes small enough to prevent unwanted electron tunneling in the unselected memory cells at the start of the programming stage.

[0052] However, due to the unwanted leakage current, the boost node voltage can gradually decrease after reaching its peak at time t2. At time t3, the falling stage begins, and the control gate lines CG1 / CG2 start to discharge until it reaches almost 0V at time t4. Also, at time t3, the self-boost voltage applied to the boost node starts to drop and is as low as approximately 0V at time t4. When the shared control gate lines CG1 and CG2 are driven to the high voltage programming voltage level, between time t2 and time Tth, the magnitude (voltage increment) of the voltage difference between the floating gate FG and the boost node is low enough to prohibit unwanted programming of the unselected memory cells, while programming the selected cells in the selected row memory array through Fowler-Nordheim tunneling of electrons.

[0053] Figure 8A It shows that the high-level width of the programming pulse (t3 - t2) is longer than the critical time (Tth - t2), such that during the programming operation, after the threshold time Tth, the voltage difference between the floating gate FG and the boost node becomes greater than the voltage increment threshold. The time Tth is the "threshold time" when the voltage in the boost node is low enough to reach the threshold level, where the threshold level of the boost node is the lowest voltage that prevents electrons from tunneling into the floating gate FG. After the time Tth, the self-boosting effect may become ineffective, and unwanted programming of unselected memory cells may occur after the time Tth. The "voltage increment threshold" represents the maximum magnitude of the voltage difference between the floating gate FG and the boost node that prohibits electron tunneling between them.

[0054] According to an embodiment of the present invention, Figure 8B It shows that the high-level width of the programming pulse (t3 - t2) is shorter than the critical time (Tth - t2), such that during the entire programming operation, the voltage difference between the floating gate FG and the boost node continuously becomes less than the voltage increment threshold. It should be noted that Figure 8A It shows the situation where at time t3 after the threshold time Tth, the voltage level on the unselected memory cells (i.e., the control gate lines CG1 and CG2 connected to the unselected memory cells) starts to drop. On the contrary, Figure 8B It shows the situation where at time t3 before the established threshold time Tth, the voltage level on the unselected memory cells starts to drop.

[0055] On the other hand, when the high-level width of the programming pulse (t3 - t2) becomes shorter, the rise and fall times of the signal may be significant. Since the selected cells (i.e., Figure 2A and Figure 2B cell A in) are not programmed during this overhead time (i.e., the rise and fall times), it is preferable to minimize this part of the overhead time. Therefore, as long as the programming inhibit cell does not reach the threshold time, the high-level width of the programming pulse should be maximized to minimize those parts of the rise and fall time overhead. Thus, according to the present invention, the control gate signals pulses of the control gate lines CG1 and CG2 to the logic-compatible flash memory should be maintained short enough (e.g., less than 10 microseconds) so as not to reach the moment (i.e., the threshold time) where unwanted programming operations can severely occur, while maintaining the pulse high-level width as large as possible so that the rise and fall time overhead can be effectively spread.

[0056] Figure 9 It shows a block diagram of a voltage signal pulse generator and a non-volatile memory cell array according to the present invention. Referring to Figure 2A and Figure 2Band Figures 3A to 3H In the flash memory array, when receiving an input signal (control signal), the voltage signal pulse generator operates the non-volatile memory cell array by sending a set of control signals via the control gate lines CG1 / CG2, the select gate lines SG1 / SG2, and the source line SL. In one embodiment of the present invention, the voltage signal generator generates a target programming voltage for the control gate lines CG1 and CG2 that pulls up the FG node of the non-volatile memory cell through connection, where the target programming voltage level is sufficiently low (i.e., approximately less than 12V), such that while programming the selected memory cells in the array, the magnitude of the voltage difference between the floating gate FG node and the boost node of the unselected memory cells in the array is less than the voltage increment threshold (i.e., approximately 6V). As a result, for the programming inhibited cells, the voltage difference between the floating gate node FG and the boost node becomes small enough to prevent unwanted electron tunneling in the unselected memory cells. Additionally, the voltage signal pulse generator also makes the control gate signal pulses of the control gate lines CG1 and CG2 short enough not to reach the moment (i.e., the threshold time) when unwanted programming operations can severely occur, while the pulse high level width is generated as large as possible to effectively amortize the rise and fall time overheads.

[0057] In one embodiment, even if not specifically described in Figure 9 , the voltage signal pulse generator may include key subblocks, such as a code memory, a timer, a one-time programmable or read-only memory, or a controller circuit. The code memory is configured to store the operation sequence of the non-volatile memory cell array (e.g., the operation sequence shown in Figure 4 ). The timer circuit can check the operation timing and adjust the key signal pulses according to a specified timing (e.g., the timing of the programming operation shown in Figure 5 ). The one-time programmable (OTP) or read-only memory can store the configuration to select the appropriate voltage levels (e.g., HV, HV_A, HV_B, HV_C, VRD, VRD_A, VRD_B, VRD_C, etc.) of the above control gate signals and the timing information (e.g., t0 to t7 in Figure 5 , t1 to t4 in Figure 8A and Figure 8B etc.).

[0058] The information stored in the OTP memory cells can be pre - determined or calibrated in each chip for post - manufacturing fine - tuning. However, the information stored in the read - only memory is pre - determined and cannot be calibrated after manufacturing. The controller circuit retrieves information from the code memory, timer, OTP or read - only memory cells or retrieves an external control signal that enters into the voltage signal pulse generator, and regulates the signal output of the voltage signal pulse generator based on this information. Additionally, the definition and use of such key sub - blocks in the voltage signal pulse generator are well - known to those skilled in the art and should not be limited to the specific description or form described herein.

[0059] Figure 10 An exemplary chip according to the present invention is shown, having various components such as a central processing unit (CPU), volatile memory, and non - volatile memory that deploys a pulse - width control programming scheme. The non - volatile memory cells can be made using standard logic devices, as Figure 2A and Figure 2B depicted. Thus, the entire chip can be cost - effectively constructed using standard logic processes without having any specific manufacturing process steps. Meanwhile, according to the present invention, the non - volatile memory cells can be accurately and effectively programmed to a target level using the above - mentioned pulse - width control programming scheme.

[0060] Although a non - volatile memory cell having five logic devices (i.e., 212, 214, 216, 218, 220 in cell A in Figure 2A and Figure 2B ; 230, 232, 234, 236, 238, 240 in cell B in Figure 2A and Figure 2B ) and five row lines (e.g., SG1, SG2, CG1, CG2, SL in Figure 2A and Figure 2B ) is described in the present disclosure, those skilled in the art should be able to apply the present invention to any other type of logic - compatible non - volatile memory. Therefore, the definition and use of the proposed invention should not be limited to the specific description or form of the logic - compatible non - volatile memory cells shown in the present disclosure. Although the present invention is susceptible to various modifications and alternative forms, it should be understood that the present invention is not limited to the specific forms disclosed.

Claims

1. A method for programming non-volatile memory cells in a memory array defined by input voltage lines and bit lines in a flash memory device, comprising: Applying the same programming voltage to selected memory cells and unselected memory cells, wherein a floating gate of the unselected memory cells is charged within a specified range; Boosting a region of the unselected memory cells, the region including a source, a drain, and a channel between the source and the drain of the unselected memory cells; and Setting a threshold programming time to prevent the unselected memory cells from being accidentally programmed by the programming voltage, wherein the threshold programming time is set to be equal to a time point at which a voltage difference between the floating gate of the unselected memory cells and the boosted region of the unselected memory cells reaches a time when the programming voltage is about to program the unselected memory cells after applying the programming voltage; and wherein the threshold programming time is further set to be equal to a time when an absolute value of the voltage difference between the floating gate of the unselected memory cells and the boosted region of the unselected memory cells reaches a predetermined threshold.

2. The method according to claim 1, further comprising: Applying the programming voltage to the selected memory cells and the unselected memory cells for a duration equal to or less than the threshold programming time.

3. The method according to claim 2, wherein, The programming voltage starts to drop to a ground potential at or near the threshold programming time.

4. The method according to claim 2, wherein The programming voltage is applied to a gate line connected to the selected memory cells and the unselected memory cells.

5. According to the method of claim 2, the duration of the programming voltage after rising and before dropping is maintained long enough as long as the programming voltage drops to a ground potential or a substantially ground potential at or near the threshold programming time.

6. According to the method of claim 1, the degree to which the unselected memory cells are disturbed by the programming of the selected memory cells is limited to or reduced to a range within which a sense amplifier circuit connected to the memory cells in the memory array can output a correct value.

7. The method according to claim 1, wherein The predetermined threshold is the maximum voltage difference between the floating gate of the unselected memory cells and the boosted region of the unselected memory cells for preventing unwanted programming of the unselected memory cells.

8. The method according to claim 1, wherein, The boosted region is boosted to a specific voltage level by a voltage potential on the floating gate of the unselected memory cells.

9. A non-volatile memory device, comprising: A non-volatile memory cell array having a plurality of input voltage lines, a plurality of bit lines, and a plurality of memory cells, the plurality of memory cells being organized into memory blocks having the plurality of input voltage lines and the plurality of bit lines; And A voltage signal pulse generator, the voltage signal pulse generator being connected to the memory cell array, the voltage signal pulse generator being configured to apply the same programming voltage to selected memory cells and unselected memory cells within the memory block, wherein the programming voltage has a threshold programming time, the threshold programming time being set to be equal to the time when the voltage difference between the floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches the time point at which the programming voltage is about to program the unselected memory cell after the application of the programming voltage; and wherein the threshold programming time is further set to be equal to the time when the absolute value of the voltage difference between the floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a predetermined threshold.

Images