Method for manufacturing a sensor device with a buried deep trench structure and sensor device

Abstract

A method for manufacturing a sensor device having a buried deep trench structure, comprising: providing a semiconductor substrate having a sensing region; etching a deep trench structure into the semiconductor substrate through an exposed region of a mask layer for arranging the deep trench structure into the semiconductor substrate laterally with respect to the sensing region and vertically from a main surface region; depositing a doped semiconductor layer on a surface region of the deep trench structure by epitaxy for providing a coated deep trench structure; at least partially removing the mask layer for exposing the main surface region of the semiconductor substrate; depositing a semiconductor capping layer on the main surface region of the semiconductor substrate; and out-diffusing dopants of the doped semiconductor layer into the thickened semiconductor substrate, wherein the out-diffused dopants provide a trench doped region extending from the doped semiconductor layer into the thickened semiconductor substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of manufacturing sensor devices in semiconductor substrates. More specifically, embodiments relate to the field of manufacturing sensor devices with buried deep trench structures, which are particularly beneficial in the field of optical sensor devices, such as image sensor arrays or time-of-flight sensors, by providing crosstalk prevention and drift field generation. BACKGROUND

[0002] Photosensitive components have become an integral part of the semiconductor market. These chips, such as optical sensors, are becoming smaller and must achieve the required luminous efficacy even with a significant reduction in surface area. For image sensor arrays, it is very important to suppress crosstalk between individual pixels of the array, especially for small pixels or in case of high pixel density. Therefore, deep trenches can be used to prevent optical and electrical crosstalk between pixels. Deep trenches can be processed from the wafer front side, e.g. the front side of the semiconductor substrate, which has the disadvantage of surface area consumption. Alternatively, trenches can be processed from the back side of the semiconductor substrate, which leads to a more costly process.

[0003] Furthermore, in e.g. time-of-flight sensor devices, an electrical drift field is required to accelerate the generated charge carriers, e.g. electrons or holes. This can be done by a special arrangement of the doping profile, which leads to a costly process sequence. The doping profile can be introduced into the semiconductor substrate by a sequence of epitaxial deposition, ion implantation and temperature processes. These processes are complex, expensive and almost not reproducible.

[0004] Therefore, there is a need for new methods for efficiently manufacturing sensor devices with effective crosstalk prevention and drift field generation.

[0005] Such a method is provided by the method for manufacturing a sensor device with buried deep trench structures according to claim 1. Furthermore, specific implementations of different embodiments of the method for manufacturing a sensor device are defined in the dependent claims. SUMMARY

[0006] According to an embodiment, a method for manufacturing a sensor device having a buried deep trench structure comprises: providing a semiconductor substrate having a sensing region extending vertically into the semiconductor substrate below a main surface region of the semiconductor substrate, wherein a mask layer is arranged on the main surface of the semiconductor substrate; etching a deep trench structure into the semiconductor substrate through an exposed region of the mask layer for arranging the deep trench structure laterally with respect to the sensing region and vertically from the main surface region into the semiconductor substrate; selectively depositing a doped semiconductor layer on a surface region of the deep trench structure by epitaxy for providing a coated deep trench structure; at least partially removing the mask layer for exposing the main surface region of the semiconductor substrate; depositing a semiconductor capping layer on the main surface region of the semiconductor substrate, wherein the semiconductor capping layer covers and closes the coated deep trench structure and forms a thickened semiconductor substrate having the buried deep trench structure with the semiconductor substrate; and out-diffusing a dopant of the doped semiconductor layer into the thickened semiconductor substrate, wherein the out-diffused dopant provides a trench doped region extending from the doped semiconductor layer into the semiconductor substrate.

[0007] According to another embodiment, a sensor device having a buried deep trench structure comprises: a semiconductor substrate having a sensing region extending vertically into the semiconductor substrate below a main surface region of the semiconductor substrate; a semiconductor capping layer extending vertically into the semiconductor substrate below the main surface region of the semiconductor substrate; a buried deep trench structure extending vertically into the semiconductor substrate below the capping layer and laterally with respect to the sensing region, wherein the buried deep trench structure comprises: a doped semiconductor layer extending from a surface region of the buried deep trench structure into the semiconductor substrate; a trench doped region extending from the doped semiconductor layer of the buried deep trench structure into the semiconductor substrate; an electronic circuit for the sensing region in a capping region of the thickened semiconductor substrate vertically above the buried deep trench structure 50. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of a method for manufacturing a sensor device having a buried deep trench structure are described herein with reference to the accompanying drawings and figures.

[0009] Figure 1 An exemplary process flow (flow chart) of a method for manufacturing a sensor device having a buried trench structure according to an embodiment is shown.

[0010] Figures 2a to 2g Schematic cross-sectional views (schematic snapshots) of a semiconductor substrate and manufactured elements of a sensor device at different stages of a manufacturing method according to an embodiment are shown.

[0011] Figures 3a to 3d schematic top view of a semiconductor substrate and a manufactured element of a sensor device according to an embodiment is shown.

[0012] Figures 4a to 4f schematic top view of a semiconductor substrate and a manufactured element of a sensor device according to an embodiment is shown.

[0013] Figure 5 schematic cross-sectional view of a semiconductor substrate and a manufactured element of a sensor device according to an embodiment is shown.

[0014] Figure 6 schematic cross-sectional view (schematic snapshot) of a semiconductor substrate and elements of a manufactured sensor at different stages of the manufacturing according to another embodiment is shown.

[0015] Figures 7a to 7e schematic cross-sectional view (schematic snapshot) of a semiconductor substrate and elements of a manufactured sensor at different stages of the manufacturing according to another embodiment is shown.

[0016] Figure 8 schematic cross-sectional view (schematic snapshot) of a semiconductor substrate and elements of a manufactured sensor at different stages of the manufacturing according to another embodiment is shown.

[0017] Figure 9 schematic cross-sectional view (schematic snapshot) of a semiconductor substrate and elements of a manufactured sensor at different stages of the manufacturing according to another embodiment is shown.

[0018] Figure 10 schematic cross-sectional view (schematic snapshot) of a semiconductor substrate and elements of a manufactured sensor at different stages of the manufacturing according to another embodiment is shown.

[0019] Figure 11 schematic cross-sectional view (schematic snapshot) of a semiconductor substrate and elements of a manufactured sensor at different stages of the manufacturing according to another embodiment is shown.

[0020] Figure 12 schematic cross-sectional view of a sensor device with a buried deep trench structure according to an embodiment is shown.

[0021] Before the embodiments are discussed in more detail using the drawings, it is pointed out that in the drawings and in the specification, identical elements and elements with the same function and / or the same technical or physical effect are generally provided with the same reference signs or are identified with the same names, such that the description of these elements and their function described in one embodiment can be exchanged or applied to the other embodiments. DETAILED DESCRIPTION

[0022] In the following description, numerous specific details are discussed to provide a thorough understanding of the embodiments. One of ordinary skill in the art, however, will recognize that the embodiments can be practiced without one or more of the specific details. In other instances, well-known implementations have not been described in order to avoid obscuring aspects of the embodiments. The described features, structures, or characteristics can be combined in any suitable manner in various implementations to produce yet further embodiments. In the following description, like numbers refer to like features throughout.

[0023] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other terms of description used herein are similarly construed (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," and "on" versus "directly on," etc.).

[0024] To facilitate the description of different embodiments, the drawings include a Cartesian coordinate system x, y, z, wherein the x-y plane corresponds (i.e., is parallel) to a main surface area of a semiconductor substrate, and wherein a depth direction into the semiconductor substrate and perpendicular to the main surface area corresponds to the "z" direction, i.e., parallel to the z-direction. In the following description, the term "lateral" means a direction parallel to the x-direction, wherein the term "vertical" means a direction parallel to the z-direction.

[0025] The term "above" or "vertically above" or "top" refers to a relative position located in a vertical direction extending from a main surface area of a semiconductor substrate and pointing away from the semiconductor substrate. Similarly, the term "below" or "vertically below" or "bottom" refers to a relative position located in a vertical direction extending from a main surface area of a semiconductor substrate and pointing towards the semiconductor substrate.

[0026] Figure 1 and Figures 2a to 2g An exemplary process flow or flow chart of a method 100 of fabricating a sensor device having a buried trench structure according to an embodiment is shown. To facilitate the representation, Figure 1 The description of Figures 2a to 2g embodiments shown in Figures 2a to 2g The reference signs related to

[0027] As Figure 1As shown in the middle, the method 100 comprises: a step 110 of providing a semiconductor substrate 10, hereinafter referred to as substrate 10 for clarity. The substrate 10 has a sensing region 14 extending vertically into the substrate 10 below a main surface region 12 of the substrate 10, wherein a mask layer 16 is arranged on the main surface region 12 of the substrate 10. In a step 120, a deep trench structure 20 is etched into the substrate 10 through the exposed region 18 of the mask layer 16. The deep trench structure 20 extends vertically into the substrate 10 from the main surface region 12 and is arranged laterally with respect to the sensing region 14. The deep trench structure 20 can be directly adjacent to the sensing region 14 or can be at a distance from the sensing region 14. In a step 130, a doped semiconductor layer 32, hereinafter referred to as doped layer 32, is epitaxially selectively deposited on a surface region 22 of the deep trench structure 20 to provide a coated deep trench structure 30. The doped layer 32 can have a defined thickness and a defined doping concentration. The mask layer 16 prevents the main surface region 12 from being covered by dopants during the selective epitaxial deposition 130. In a step 140, the mask layer 16 is at least partially removed to expose the main surface region 12 of the substrate 10. In a step 150, a semiconductor capping layer 52, hereinafter referred to as capping layer 52, is deposited on the main surface region 12 of the substrate 10 to cover and close the coated deep trench structure 30. The capping layer 52 forms a thickened semiconductor substrate 10’, hereinafter referred to as thickened substrate 10’, together with the substrate 10. The thickened substrate 10’ has the coated deep trench structure 30 buried therein, i.e. has a buried deep trench structure 50. The buried deep trench structure 50 can be configured to form a barrier to optical and electronic signals. In a step 160, the dopants of the doped layer 32 are diffused outwards into the thickened substrate 10’, the diffused outwards dopants providing a trench doped region 60 extending from the doped layer 32 into the thickened substrate 10’.

[0028] Accordingly, embodiments describe a process for manufacturing a sensor device with a buried deep trench structure 50 such that the buried deep trench structure 50 can be etched from the front side of the wafer. The etching 120 of the deep trench structure 20 from the main surface area 12 provides an efficient way to arrange the deep trench structure 20 close to the sensing area 14 which also extends vertically below the main surface area 12. However, after burying the deep trench structure, the main surface area 12’ including the area vertically above the buried deep trench structure 50 can be used in further process steps. This effectively solves the problem of surface consumption of the deep trench structure in the sensor device. In other words, the trench can be etched from the front side, which is a given process, but without any front side area consumption due to overgrowth, e.g. with a silicon epitaxy. Avoiding surface area consumption by the deep trench can be beneficial for further process flows. For example, electronic circuits, such as readout circuits, can be arranged, e.g. placed or directly manufactured, on the main surface area 12’ vertically above the buried deep trench structure 50, e.g. readout circuits for pixels on the surface, e.g. pixel devices forming part of the sensor device. At the same time, maximizing the amount of available surface area is beneficial for the light emitting performance of the optical sensor. In other words, the present disclosure uses a deep trench with a doping profile, e.g. an empty deep trench, and solves the space problem. After closing the deep trench, arbitrary semiconductor process flows can be performed to further process the obtained substrate 10’. For example, the trench of the buried deep trench structure is closed at the top, but can still be empty in depth, which can provide good characteristics for optical components of the sensor device to be manufactured with respect to crosstalk behavior.

[0029] For example, the sensing region 14 and the adjacent sensing region within the substrate each form part of a different pixel device of the sensor device. The deep trench structure can prevent optical crosstalk and / or electronic crosstalk between the different pixel devices. That is, the deep trench structure 20 can attenuate or prohibit the transfer of an electronic signal or an optical signal out of the sensing region 14 and / or can attenuate or prohibit the transfer of an electronic signal or an optical signal into an adjacent region of the substrate (e.g. into an adjacent other sensing region). For example, an electromagnetic signal to be detected in the sensing region 14 can be reflected at the interface between the substrate 10 and the deep trench structure 50. Thus, the electromagnetic signal can remain within the sensing region 14, thus increasing the probability that the electromagnetic signal is detected within the sensing region 14. Furthermore, due to the reflection of the electromagnetic signal, the electromagnetic signal can be prevented from entering an adjacent region of the substrate. For example, the electromagnetic signal can be prevented from entering an adjacent sensing region, thus preventing a false or undesired detection of the electromagnetic signal in another sensing region than the sensing region 14. For example, the reflection of the electromagnetic signal at the interface between the substrate 10 and the deep trench structure 50 can occur due to total internal reflection, such that the electromagnetic signal can be totally reflected or almost totally reflected. Furthermore, the deep trench structure 20 can hinder the movement of charge carriers to an adjacent region of the substrate 10. Thus, the deep trench structure 20 increases the probability that a charge carrier, which is generated by a conversion of the electromagnetic signal, is detected within the sensing region 14. Thus, the deep trench structure 20 can prevent the charge carrier from being falsely or undesirably detected in another sensing region than the sensing region 14. Thus, the deep trench structure 20 can increase the yield of the electromagnetic signal to be detected in the sensing region 14, which enters the sensing region 14 through a region of the main surface region 12 vertically above the sensing region 14.

[0030] By depositing the doped layer 32 on the surface region 22 (such as the wall) of the deep trench structure 30, a tunable doping profile for drift field generation can be created in the sensing region 14. Based on the out-diffusion 160 of the dopant of the doped layer 32 to the thickened substrate 10’, the resulting doping profile can be tuned to provide an electrical drift field in the substrate 10’ and / or in the sensing region 14, 14’. Thus, the method 100 allows a very precise reproduction of the generation of the doping profile by using a selective epitaxial deposition (e.g. a high-doped selective silicon epitaxial deposition on the trench (e.g. on the sidewall of the trench)) and by controlling the doping profile with an annealing process (such as a temperature process) with a low-complexity process sequence.

[0031] Thus, the proposed method 100 is an efficient method for realizing small pixels (e.g. high-resolution small pixels which can be part of a sensor device).

[0032] In the following, reference is made to Figures 2a to 2g An exemplary embodiment of the process flow of the method 100 is described.Figures 2a to 2g A schematic cross-sectional view of the substrate along a vertical plane is shown. Figure 2a The manufactured elements are shown at (at respective process stages of) several process stages of the method 100 for manufacturing a sensor device.

[0033] Figure 2a - The provided substrate: Figure 2b An exemplary embodiment of the substrate 10 provided in step 110 of the method 100 is shown. The substrate 10 can have a rectangular cross-section along a vertical axis, i.e. in a depth direction or z-direction. The substrate 10 can comprise silicon, germanium or any other semiconductor material. The substrate 10 can comprise a bulk or epitaxially (EPI) grown semiconductor material. The substrate 10 can comprise dopants with a doping concentration and a doping type being n-type or p-type.

[0034] The main surface region 12 can be a planar surface and can form a top surface of the substrate 10. The vertical dimension of the sensing region 14 can cover the entire vertical dimension of the substrate 10 or only a portion thereof. The sensing region 14 has a lateral dimension which can be smaller than the lateral dimension of the substrate 10.

[0035] According to embodiments, the sensing region 14 forms a conversion region of an optical sensor to be manufactured, wherein the conversion region converts an electromagnetic signal into photo-generated charge carriers. The sensing region 14 of such an optical sensor can form part of a device, called a pixel, which can comprise further components, e.g. processing circuitry. The pixel itself can form part of a two-dimensional integrated pixel array for receiving electromagnetic radiation, e.g. visible or infrared radiation, wherein the respective pixels provide an electrical output signal according to a parameter to be measured by the optical sensor. The optical sensor can for example be an imaging array or a time-of-flight sensor.

[0036] The exposed region 18 of the mask layer 16 exposes the main surface region 12 of the substrate 10. The lateral structure, i.e. the lateral dimensions and the lateral shape, of the exposed region 18 of the mask layer 16 provides the lateral structure of the deep trench structure formed in the following process steps. The exposed region 18 of the mask layer 16 can have been formed by partially removing the mask layer 16. Such a partial removal of the mask layer 16 can have been performed by a lithography process.

[0037] Figure 2b - Trench etching: In step 120 of the method 100, parts of the substrate 10 are removed by etching, starting from the exposed region 18 of the mask layer 16 and etching into the substrate 10, to form a deep trench structure 20, as shown in Figures 2a to 2g During the etching process 120, the mask layer 16 can be partially removed. The trench etching process 120 is configured to remove material of the substrate 10 at a faster rate than the material of the mask layer 16.

[0038] After step 120, the substrate 10 comprises the deep trench structure 20. The lateral structure of the deep trench structure 20 results from the lateral structure of the exposed area 18 of the masking layer 16.

[0039] The deep trench structure can have a depth 27. The depth 27 of the deep trench structure 20 can be a vertical dimension of the deep trench structure 20.

[0040] According to embodiments, the depth 27 can be in the range between 1 pm and 100 pm, or in another embodiment, in the range between 2 pm and 20 pm.

[0041] The deep trench structure 20 comprises a surface area 22. The surface area 22 of the deep trench structure 20 can be a border between the deep trench structure 20 and the substrate 10. The surface area 22 of the deep trench structure 20 can comprise a wall 24, which can be a border of the deep trench structure 20 in lateral direction. The surface area 22 of the deep trench structure 20 can further comprise a bottom 26, which can be a border of the deep trench structure 20 in vertical direction.

[0042] The deep trench structure 20 has a width 25. The width 25 can be a lateral distance between two directly opposite walls 24, or a lateral distance between two opposite areas of the surface area 22, measured perpendicular to the longitudinal direction of the trench or trench portion of the deep trench structure 25.

[0043] According to embodiments, the width 25 is large enough so that evanescent waves of a total internal reflection of an electromagnetic signal at the interface between the substrate 10 and the deep trench structure 20 can interact with adjacent areas of the substrate 10. Thus, the reflection can be a frustrated total internal reflection.

[0044] According to embodiments, the width 25 is larger than some wavelengths of the electromagnetic signal to be detected, so that a reflection of the electromagnetic signal at the interface between the substrate 10 and the deep trench structure 20 can be a frustrated total internal reflection.

[0045] A trench aspect ratio of the deep trench structure 20 can be defined as a ratio of the trench height 27 and the width 25. According to embodiments, the trench aspect ratio of the deep trench structure 20 is in the range between 1 and 100 or in the range between 5 and 60.

[0046] The trench etching process 120 can have different etching rates for different etching directions of the substrate 10. For example, the trench etching process 120 can mainly etch vertical surfaces of the substrate 10. Thus, the deep trench structure 20 with a high trench aspect ratio can be etched by the trench etching process 120.

[0047] The deep trench structure 20 is arranged laterally with respect to the sensing area 14 of the substrate 10. The deep trench structure 20 is not necessarily adjacent to the sensing area 14, but can also be spaced apart from the sensing area 14 by an area of the substrate 10 which is not part of the sensing area 14.

[0048] The deep trench structure 20 can surround (e.g. completely or only partially enclose) the sensing area 14. Alternatively, thus, the deep trench structure 20 can completely enclose the sensing area 14.

[0049] According to embodiments, the deep trench structure 20 can comprise a plurality of deep trench portions (not shown, see e.g. Figure 3a ), which can be arranged to laterally limit the sensing area 14. In this case, the above-mentioned properties of the deep trench structure 20 apply to each deep trench portion as well, and the arrangement of the plurality of deep trench portions forms the deep trench structure 50. Figure 2c

[0050] Figure 2c - Doped EPI deposition: In step 130 of the method 100, a doped layer 32 is deposited on the surface area 22 of the deep trench structure 20 by selective epitaxy (EPI) deposition, as shown in Figure 2d . The doped layer 32 and the deep trench structure 20 form a coated deep trench structure 30.

[0051] The selective epitaxy deposition is configured to selectively deposit a doped semiconductor material mainly on the surface area 20 of the deep trench structure 20.

[0052] The deposition of the doped layer 32 on the surface of the deep trench structure 20 is an effective way to introduce a doping concentration or doping profile in the substrate. Very reproducible results can be obtained by controlling the thickness and the doping concentration of the doped layer 32.

[0053] The selective epitaxy deposition can comprise exposing the substrate 10 to one or more of the following gases: dichlorosilane, HC1, B2H2, and H2. The selective epitaxy deposition can be performed at a temperature between 600 °C and 1000 °C, e.g. at a temperature of about 760 °C. The selective epitaxy deposition can be configured to achieve a specific doping concentration of the doped layer 32.

[0054] During the selective epitaxy deposition of the doped layer 32, the main surface area 12 of the substrate 10 is still covered by the mask layer 16 to prevent the doped layer 32 from forming on this main surface area 12.

[0055] ​The doped layer 32 can cover the entire surface area 22 of the deep trench structure 20. The doped layer 32 can comprise a thickness 34. The thickness 34 of the doped layer 32 can be the distance between a surface area 36 of the doped layer 32 and the surface area 22 of the deep trench structure 20. The surface area 36 of the doped layer 32 can be the border between the coated deep trench structure 30 and the doped layer 32. The thickness 34 of the doped layer 32 can be in the range between 1 nm and 1 pm.

[0056] The doped layer 32 can comprise a semiconductor material, e.g. silicon. The doping type of the doped layer 32 can be n-type or p-type. The doping concentration of the doped layer 32 can be in the range between 10 16 cm -3 and 10 20 cm -3 .

[0057] According to embodiments, the doping inside the trench, i.e. the deposition of the doped layer 32, is done by selective high-doped silicon epitaxy deposition through the mask layer 16 on the main surface area 12, which can be a cap layer.

[0058] According to embodiments, the material deposited by selective epitaxy deposition is mainly in the deep trench structure 20 and not on the main surface area 12 of the substrate 10.

[0059] According to embodiments, the doped layer 32 is deposited by selective epitaxy deposition on the trench walls and the doped layer 32 is a thin layer and has a high doping concentration. Thus, the width 25 remains almost unchanged after the deposition of the doped layer 32, so that the deep trench structure 20 maintains its beneficial properties with respect to crosstalk prevention and at the same time gives an efficient drift field generation.

[0060] Figure 2d - Pad etching: In step 140 of the method 100, the mask layer 16 is at least partially removed to expose the main surface area 12 of the substrate 10. The removal 140 of the mask layer 16 can comprise an etching process, wherein the etching process is adapted to mainly etch the mask layer 16 and is less or not at all etching efficient on the substrate 10. The removal 140 of the mask layer 16 can be applied to the entire mask layer 16 or only to a portion of the mask layer 16 which is related to the lateral dimension of the mask layer 16. The removal 140 of the mask layer 16 removes at least a portion of the mask layer 16 in its entire vertical dimension, so that the lower main surface area 12 of the substrate 10 is exposed. Thus, the removal 140 of the mask layer 16 at least partially exposes the main surface area 12 of the substrate 10.

[0061] According to embodiments, the removal 140 of the mask layer 16 exposes those portions of the main surface area 12 of the substrate 10 which are arranged adjacent to the coated deep trench structure 30.

[0062] According to other embodiments, the removal 140 of the mask layer 16 exposes the entire main surface area 12 of the substrate 10.

[0063] After step 140, the main surface area 12 of the substrate 10 is at least partially exposed, as Figure 2e shown.

[0064] After step 140 and before step 150, the method 100 can optionally comprise filling the coated deep trench structure 30 with a gas or with a dielectric material. The optional gas or dielectric material filling the coated deep trench structure 30 can be a material that is opaque to the light radiation, in particular to the light radiation to be detected in the sensing area 14. In other words, the gas or dielectric material filling the coated deep trench structure 30 can be adapted to absorb or attenuate the light radiation (i.e. electromagnetic radiation), or can be chosen such that the light radiation is at least partially refracted without passing through the material. Alternatively, the optional gas or dielectric material filling the coated deep trench structure 30 can have a dielectric function that is adapted to implement a total internal reflection or frustrated total internal reflection of electromagnetic signals at the interface between the coated deep trench structure 30 and the substrate 10.

[0065] Figure 2e : Cap layer deposition: In step 150 of the method 100, a cap layer 52 is deposited on the main surface area 12, as Figures 3b to 3d shown in Fig. 1C. The cap layer 52 is also deposited in the vicinity of the coated deep trench structure 30, more particularly in the area located vertically above the coated deep trench structure 30. Thus, the cap layer 52 covers and closes the coated deep trench structure 30, so that during step 150, the coated deep trench structure 30 is buried in the substrate 10. The deposition 150 of the cap layer 52 can comprise an epitaxy (EPI) process, such as an epitaxy (EPI) overgrowth. In one embodiment, the deposition of the semiconductor cap layer 52 comprises an epitaxy (EPI) overgrowth process at atmospheric pressure.

[0066] The cap layer 52 can comprise silicon, germanium or any other semiconductor material. In one embodiment, the cap layer 52 has the same material as the substrate 10. The cap layer 52 can comprise a doping concentration and a doping type, which can be n-type or p-type. The doping type of the cap layer 52 can have the same or a different doping type as the substrate 10.

[0067] The cap layer 52 and the substrate 10 form a thickened substrate 10', which comprises a surface area 12' that can form a top surface of the thickened substrate 10'.

[0068] The capping layer 52 has a thickness 54, which can be the vertical distance between the surface region 12' of the thickened substrate 10' and the main surface region 12 of the substrate 10. In other words, the thickness 54 can be the depth of the capping layer 52. Thus, the thickness 54 can also be the depth of the buried deep trench structure 50 below the main surface region 12' of the thickened substrate 10'. The capping layer 52 can partially or completely cover the main surface region 12 of the substrate 10. The capping layer 52 can comprise a region extending vertically above the capping layer 52 over the sensing region 14, and this region can extend the sensing region 14 to form a sensing region 14' together with the sensing region 14. The sensing region 14' extends vertically into the thickened substrate 10' below the main surface region 12'.

[0069] The buried depth 54, i.e. the thickness of the capping layer 52, can have a selected value. A smaller value of the buried depth 54 can improve the crosstalk suppression of the buried deep trench structure 50. A larger value of the buried depth 54 can provide more space for processing electronic circuits vertically above the buried deep trench structure 50.

[0070] According to embodiments, the thickness 54 of the capping layer 52 can be in the range between 100 nm and 10 pm.

[0071] According to embodiments, the buried deep trench structure 50 can be empty or filled by a gas, or can be partially filled by a dielectric material or any other material. In this context, empty can refer to a filling by any gas, e.g. air or a process gas, or empty can refer to a gas environment with a pressure below ambient pressure. Alternatively, the buried deep trench structure 50 can be filled or partially filled by a solid material, e.g. a dielectric material.

[0072] According to embodiments, the buried deep trench structure 50 is filled by a process gas of an epitaxial overgrowth process.

[0073] According to embodiments, the deposition of the capping layer 52 can comprise depositing a semiconductor material on the surface region 36 of the doped layer 32, such that the capping layer 52 can at least partially cover the doped layer 32.

[0074] The buried deep trench structure 50 is generated from the coated deep trench structure 30, which itself is generated from the deep trench structure 20. Thus, the properties and functions discussed above for the deep trench structure 20 apply equally to the buried deep trench structure 50. The properties and functions discussed in the context of the interface between the deep trench structure 20 or the coated deep trench structure 30 and the substrate 10 apply equally to the interface between the buried deep trench structure 50 and the substrate 10.

[0075] According to embodiments, and as a result of the above indicated, the buried deep trench structure 50 can comprise a plurality of deep trench portions (not shown in Fig. 2, shown in Figures 4a to 4f , Figure 5 , Figure 2f above), the above mentioned properties of the buried deep trench structure 50 apply to the plurality of deep trench portions as well.

[0076] Figure 2f - Out-diffusion of dopants: In step 160 of the method 100, the dopants of the doped layer 32 are out-diffused into the thickened substrate 10'. The step of out-diffusion can comprise an annealing process, which can be a temperature process. The annealing process can comprise exposing the device having the substrate 10 to high temperatures. The out-diffusion of the dopants comprises a drift or movement of the dopants from the doped layer 32 into the thickened substrate 10'. The area in which the dopants are spread forms a trench doped region 60, as shown in Figure 2g . The out-diffusion 160 of the dopants establishes a dopant profile 74, which extends from the doped layer 32 into the thickened substrate 10'.

[0077] The dopant profile 74 describes the local distribution of the dopants in the trench doped region 60. The trench doped region 60 can be laterally adjacent to the sensing region 14', but the trench doped region can also overlap the sensing region 14'. The trench doped region 60 can also laterally confine the sensing region 14'.

[0078] The out-diffusion 160 can be adapted to control the drift or movement of the dopants such that, after step 160, the trench doped region 60 comprises a specific size and / or form with a specific dopant profile 74. The dopant profile 74 can be varied to achieve an optimal adjustment of the electric field. The maximum dopant concentration can be in the range between 10 14 cm -3 and 10 18 cm -3 or between 10 15 cm -3 and 10 17 cm -3 .

[0079] According to embodiments, the dopant profile 74 is configured to efficiently separate charge carriers of opposite electric charge, such as electrons and holes, which are generated by converting an electromagnetic signal into charge carriers.

[0080] According to embodiments, the dopant profile 74 is configured to optimize the path of the charge carriers towards an electronic contact configured for collecting the charge carriers, such that the readout speed can be increased.

[0081] According to an embodiment, the doping distribution 74 is configured to effectively accelerate the movement of charge carriers away from the interface between the buried deep trench structure 50 and the substrate 10', thereby reducing leakage. Leakage may, for example, be the recombination of charge carriers at the interface between the buried deep trench structure 50 and the substrate 10'.

[0082] Figure 2g - Optional electronic circuitry: such as Figure 1 As shown, in optional step 170, electronic circuitry 70 (such as readout circuitry) for sensing region 14' can be created vertically, at least partially, above the buried deep trench structure 50. This circuitry can be at least partially located within the capping region 72 of the thickened substrate 10', or alternatively, on the top surface of the thickened substrate 10'. The creation of circuitry 70 can include a sequence of processing steps, such as one or more of the following: material deposition, material removal, material doping, or chemical or mechanical treatment of material. During the creation of electronic circuitry 70, the thickened substrate 10' can be altered or affected by the processing steps.

[0083] The capping region 72 extends vertically over the buried deep trench structure 50 toward the thickened substrate 10' and the main surface region 12', and may extend vertically over the main surface region 12'. The creation of the electronic circuitry 70 affects the capping region 72, particularly the portion of the main surface region 12' within the capping region 72. The electronic circuitry 70 may extend vertically above and / or below the main surface region 12' of the thickened substrate 10'. The electronic circuitry 70 may extend into the capping region 72 and / or the sensing region 14'. The electronic circuitry may also extend into the trench doped region 60.

[0084] According to an embodiment, the electronic circuitry is partially arranged within the thickened substrate 10'. This arrangement facilitates the fabrication of general-purpose semiconductor circuits, such as the doped regions of readout contacts.

[0085] According to an embodiment, the electronic circuit 70 may include a contact region within a thickened substrate 10'. The contact region may, for example, include a higher doping concentration of the same doping type as the sensing region 14', such that charge carriers from sensing regions 14'-1, 14'-2 can be collected in the contact region.

[0086] According to an embodiment, electronic circuit 70 is a readout circuit to collect electronic charge from sensing region 14'.

[0087] According to embodiments, the sensing region 14’ and the electronic circuit 70 form part of a pixel device, which is part of a sensor device comprising a plurality of pixel devices. The plurality of pixel devices can be separated from each other by the buried deep trench structure 50. More specifically, individual pixel devices of the plurality of pixel devices can be separated from pixel devices adjacent thereto by one or more deep trench portions of the buried deep trench structure 50.

[0088] According to embodiments, the electronic circuit path is placed in a region vertically above the buried deep trench structure.

[0089] In the following, a plurality of different possible implementations of the method 100 are exemplarily described.

[0090] In the present description of embodiments of the method 100, identical or similar elements having identical structure and / or function are provided with identical reference signs or identical names, wherein a detailed description of such elements will not be repeated for each embodiment. Thus, the above description relating to Figures 2a to 2g and Figure 1 applies equally to the other embodiments described in the following. In the following description, differences to the embodiments shown in Figures 2a to 2g and Figures 3a to 3d are discussed in particular detail (e.g. additional elements) as well as the resulting technical effect(s).

[0091] Figure 3a Schematic top views (schematic snapshots) of the substrate 10, 10’ and manufactured elements of the sensor device at two different stages of the method 100 according to embodiments are shown.

[0092] Figure 2b Refers to the step 120 of etching the deep trench structure 20 to the substrate 10, which is also described in the description of Figure 3a .

[0093] According to embodiments, the deep trench structure 20 can comprise a plurality of deep trench portions 20-1, 20-2, …, 20-n, e.g. four deep trench portions 20-1, 20-2, …, 20-4 as shown in Figure 2b . Each of the deep trench portions 20-1, 20-2, …, 20-n can comprise an individual width and depth. For example, the deep trench portions 20-1, 20-2, …, 20-4 can have a common width 25, which is referred to as the width 25 of the deep trench structure 20. According to embodiments, the individual deep trench portions 20-1, 20-2, …, 20-4 can have a common depth, which is referred to as the depth 27 of the deep trench structure (see Figure 3a). The deep trench portions 20-1, 20-2,..., 20-n can have lengths 21-1, 21-2,..., 21-n, which are longitudinal dimensions of the deep trench portions 20-1, 20-2,..., 20-n, perpendicular to the widths 25 of the respective deep trench portions 20-1, 20-2,..., 20-n. Each deep trench portion 20-1, 20-2,..., 20-n can comprise an individual length 21-1, 21-2,..., 21-n. For example, as shown in Figure 3a Fig. 2, the deep trench portions 20-1, 20-2 can comprise lengths 21-1, 21-2. The deep trench portions 20-1, 20-2,..., 20-n can be arranged to partially or completely laterally surround the sensing region 14, as described above. For example, as shown in Figure 3b Fig. 3, four deep trench portions 20-1, 20-2,..., 20-4 can partially surround the sensing region 14. According to embodiments, two adjacent ones of the deep trench portions 20-1, 20-2,..., 20-4 are arranged at an angle of 90°, the four deep trench portions 20-1, 20-2,..., 20-4 are arranged in a rectangular configuration.

[0094] According to embodiments, the deep trench portions 20-1, 20-2,..., 20-n can be arranged in an equiangular polygon configuration, such that two of the n deep trench portions 20-1, 20-2,..., 20-n can be arranged at an angle of 360° / n.

[0095] According to embodiments, the deep trench portions 20-1, 20-2,..., 20-n can be arranged at arbitrary angles in an arbitrary sequence to partially or completely laterally surround the sensing region 14.

[0096] The sensing region 14 can have an arbitrary lateral shape. The lateral dimensions of the sensing region 14 can be defined by one or more lateral sensing region dimensions. For example, according to the embodiment shown in Figures 3b to 3d Fig. 2, the lateral shape of the sensing region 14 is rectangular and defined by two lateral sensing region dimensions 15-1, 15-2.

[0097] Figure 2e A step 150 involving depositing a capping layer 52 for forming a thickened substrate 10' with a buried deep trench structure 50 is described in the description of Figures 3b to 3c Fig. 4.

[0098] According to embodiments, the buried deep trench structure 50 can comprise a plurality of deep trench portions 50-1, 50-2,..., 50-n, which are generated from the deep trench portions 20-1, 20-2,..., 20-n etched in step 120.

[0099] For example, according to the embodiment shown inFigure 3a The buried deep trench structure 50 comprises, in the embodiment shown, four deep trench portions 50-1, 50-2,..., 50-4, which are generated from the deep trench portions 20-1, 20-2,..., 20-4 etched in step 120 (see Figure 3d ). The deep trench portions 50-1, 50-2,..., 50-4 can be arranged to partially or completely laterally surround the sensing region 14', which can be defined by two lateral sensing region dimensions 15-1, 15-2.

[0100] Figures 3a to 3d Another embodiment of an arrangement of eight deep trench portions 50-1, 50-2,..., 50-8 is shown, which are arranged in an octagonal arrangement to partially surround the sensing region 14', wherein the sensing region 14' can have an octagonal shape, which can be defined by the lateral sensing region dimension 15-1.

[0101] As shown in Figures 3b to 3d , the sensing region 14, 14' does not necessarily extend over the entire lateral area between the individual deep trench portions 20-1, 20-2,..., 20-n, 50-1, 50-2,..., 50-n. Thus, the sensing region 14, 14' does not necessarily adjoin the deep trench structure 20 or the buried deep trench structure 50.

[0102] According to embodiments, the sensing region 14' can have an arbitrary shape.

[0103] According to embodiments, for example Figure 2g , the electronic circuit 70, such as a readout circuit, can be created at least partially vertically above the buried deep trench structure 50 for the sensing region 14', as described in Figures 4a to 4f .

[0104] Figures 4a to 4c Schematic top views of a substrate 10' and manufactured elements of a sensor device according to different embodiments are shown.

[0105] According to embodiments, the thickened substrate 10' comprises a plurality of sensing regions 14'-1, 14'-2,..., 14'-n and the buried deep trench structure 50 comprises a plurality of deep trench portions 50-1, 50-2,..., 50-n. The deep trench portions 50-1, 50-2,..., 50-n can be arranged to partially Figure 4e , Figure 4d ) or completely Figure 4f , Figures 4a to 4c) each of the plurality of portions, i.e. the plurality of deep trench portions 50-1, 50-2,..., 50-n, respectively, can be arranged to at least partially surround one of the individual sensing regions 14’-1, 14’-2,..., 14’-n, respectively. For example, in the exemplary arrangement shown in Figure 4d the deep trench portion 50-1, 50-2,..., 50-4 partially encloses the sensing region 14’-4.

[0106] According to embodiments, for example the embodiments shown in Figure 4f the deep trench portions 50-1, 50-2,..., 50-8 are arranged to completely laterally surround the plurality of sensing regions 14’-1, 14’-2, respectively.

[0107] According to embodiments, for example the embodiments shown in Figure 5 the deep trench portions 50-1, 50-2,..., 50-8 are arranged to completely laterally surround the sensing region 14’-2, respectively.

[0108] According to embodiments, the plurality of deep trench portions 50-1, 50-2,..., 50-n can be arranged to separate the individual sensing regions 14’-1, 14’-2,..., 14’-n from each other.

[0109] According to embodiments, the plurality of sensing regions 14’-1, 14’-2,..., 14’-n can be arranged in an array.

[0110] According to embodiments, each of the plurality of sensing regions 14’-1, 14’-2,..., 14’-n forms part of an individual pixel device, the individual pixel device being part of an imaging array or a sensor array.

[0111] Figures 2c to 2g A schematic cross-sectional view of an exemplary embodiment of a thickened substrate 10’ and elements of a sensor device manufactured by the method 100 according to embodiments is shown. The thickened substrate 10’ comprises sensing regions 14’-1, 14’-2 to convert an electromagnetic signal S1 into charge carriers, i.e. into electrons and holes. The thickened substrate 10’ comprises a buried deep trench structure 50 comprising deep trench portions 50-1, 50-2, 50-3 arranged to separate adjacent sensing regions 14’-1, 14’-2. The deep trench portions 50-1, 50-2, 50-3 are surrounded by a trench doped region 60. The trench doped region 60 comprises a doping profile which can be optimized to accelerate charge carriers away from the interface between the buried deep trench portions 50-1, 50-2, 50-3, thereby effectively reducing leakage or noise of the manufactured sensor device during operation.

[0112] The electronic circuit 70 is partly arranged vertically above the deep trench portions 50-1, 50-2, 50-3, such that the buried deep trench structure 50 does not consume surface area.

[0113] According to embodiments, an additional readout circuit 502 is arranged on the main surface area 12’ of the thickened substrate 10’, which is located vertically above the sensing area 14’. The additional readout circuit 502 can be adapted to perform a time-of-flight measurement.

[0114] According to embodiments, the thickened substrate 10’ comprises a buried doped region 501 extending vertically into the substrate 10’ below the sensing areas 14’-1, 14’-2. In embodiments, the buried doped region 501 extends vertically below the sensing areas 14’-1, 14’-2 to an opposite surface area 503 of the thickened substrate 10’, which is opposite to the main surface area 12’.

[0115] According to embodiments, the buried doped region 501 comprises a doping type opposite to the sensing areas 14, i.e. the buried doped region 501 can comprise a p-type doping and the sensing areas 14 can comprise an n-type doping, or the buried doped region 501 can comprise an n-type doping and the sensing areas 14 can comprise a p-type doping. Such embodiments can be beneficial for efficiently separating electrons and holes.

[0116] According to embodiments, the trench doped region 60 comprises the same doping type as the buried doped region 501 of the substrate 10, such that a certain kind of charge carriers is efficiently accelerated towards the main surface area 12’ or the electronic circuit 70.

[0117] According to embodiments, the trench doped region 60 comprises a higher doping concentration than the buried doped region 501.

[0118] According to embodiments, the trench doped region 60 and the buried doped region 501 are p-doped and the sensing areas are n-doped, which embodiments are beneficial for efficient drift of electrons towards the main surface area 12 of the substrate and in particular towards the electronic circuit 70 and / or the additional readout circuit 502.

[0119] In embodiments, the etching 120 of the deep trench structure 20 can comprise arranging the deep trench structure 20 vertically from the main surface area 12 into the substrate 10 and into the buried doped region 501 of the substrate 10.

[0120] According to embodiments, the doped layer 32 (see e.g. Figures 2c to 2g ) can comprise the same doping type as the buried doped region 501 of the substrate 10.

[0121] According to an embodiment, the doped layer 32 (see e.g. Figures 2c to 2g ) further comprises a higher doping concentration than the buried doped region 501.

[0122] According to an embodiment, the doped layer 32 (see e.g. Figure 6 ) and the buried doped region 501 are p-doped and the sensing region is n-doped.

[0123] Figure 6 Schematic cross-sectional views (schematic snapshots) of the substrate 10 and manufactured elements of the sensor device at different stages of the method 100 are shown according to further embodiments. Figure 6 Optional steps 105 and 106 as well as steps 110 and 120 are related to embodiments of the method 100. If not otherwise indicated, the same elements shown in different panels of the figures should be referred to with the same reference signs.

[0124] The optional step 105 can be part of the step 110. In the step 105, the substrate 10 is provided with the sensing region 14 and with a mask layer 16 arranged on the main surface region 12. In the shown embodiment, the mask layer 16 comprises a pad layer 16-1 arranged adjacent to or on top of the main surface region 12. According to an embodiment, the pad layer 16-1 can be a silicon nitride layer. In the shown embodiment, the mask layer 16 further comprises a hard mask layer 16-2 arranged adjacent to or on top of the pad layer 16-1. The hard mask layer 16-2 can comprise a composition of material that is less sensitive to a specific etching process than a composition of material of the substrate 10. Thus, the etching process can be configured to remove material of the substrate 10 at a faster rate than material of the hard mask layer 16-2. In the shown embodiment, an etch resist layer 601 is arranged on top of the hard mask layer 16-2. The etch resist layer 601 comprises an exposed etch resist region 602 that exposes a top surface region 603 of the hard mask layer 16-2, as shown in the left panel of Figure 6 For the provision 110 of the substrate 10, in this embodiment, the method 100 comprises an additional step 106 of etching the exposed region 18 into the mask layer 16 through the exposed etch resist region 602 of the etch resist layer 601. Thus, the lateral structure of the exposed region 18 of the mask layer 16 results from the exposed region 602 of the etch resist layer 601. The step 106 of etching the mask layer 16 can be followed by removing the etch resist layer 601 or can comprise removing the etch resist layer 601 in order to provide the substrate 10 with the mask layer 16 comprising the exposed region 18, as shown in the middle panel of Figure 6 . Figure 6The right panel shows the result of etching 120 of the deep trench structure 20.

[0125] According to one embodiment, the optional pad layer 16-1 has a thickness that is a vertical dimension, ranging from 1 nm to 10 μm, or in another embodiment, ranging from 10 nm to 1 μm.

[0126] According to an embodiment, the mask layer 16 includes a pad layer 16-1 and a hard mask layer 16-2, wherein the hard mask layer 16-2 is configured to be less sensitive to the trench etching process than the substrate 10, such that the trench etching process mainly affects the areas of the substrate 10 that are not covered by the mask layer 16.

[0127] although, Figure 5 The embodiment shown includes a buried doped region 501, such as Figure 6 The feature introduced in [the document] is independent of [the specific context]. Figures 7a to 7e Features introduced in [the document / process].

[0128] Figure 7a Cross-sectional electron microscope images and typical dimensions of substrates 10, 10' at different stages of method 100 according to an embodiment are shown.

[0129] Figure 2b A cross-sectional view of the substrate 10 with a mask layer 16 after etching 120 is shown. The deep trench structure 20 includes a depth 27, which is a vertical dimension from the main surface region 12 to the substrate 10. The depth 27 can be... Figure 7b Within the range described by the context. For example, depth 27 can be approximately 15 μm.

[0130] Figure 7a It shows Figure 2a An enlarged view of the rectangle shown. According to the illustrated embodiment, mask layer 16 includes a pad layer 16-1 and a hard mask layer 16-2, wherein the pad layer 16-1 has a thickness 701. The thickness 701 of the pad layer 16-1 can be... Figure 2b Within the scope described in the context. For example, the pad layer thickness 701 can be approximately 130 nm. The deep trench structure 20 can have a width 25, which can be within the... Figure 7c Within the range described by the context. For example, the width could be approximately 370 nm.

[0131] Figure 7d A cross-sectional view of the thickened substrate 10' with the buried deep trench structure 50 after step 150 is shown. The buried deep trench structure 50 includes deep trench portions 50-1, 50-2, and 50-3.

[0132] Figure 7c It shows Figure 2bAn enlarged view of the center rectangle 710, showing the depth 27 of the buried deep trench portion 50-3. The depth 27 can be in the range described in the context of Figure 7e For example, the depth 27 can be about 13 pm.

[0133] Figure 7c An enlarged view of the center rectangle 720 in Figure 2e showing the depth 54 of the buried deep trench structure 50 under the main surface region 12'. The depth 54 of the buried can be in the range described in the context of Figure 8 For example, the depth 54 of the buried can be about 2 pm.

[0134] Figure 9 An example of a lateral distribution of the dopant in the trench doped region 60 of a sensor device manufactured according to an embodiment of the method 100 is shown. The figure shows the concentration of the dopant along the lateral direction from the doped layer 32 to the thickened substrate 10'. However, other distributions can be obtained as desired.

[0135] Figure 9 An illustrative cross-sectional view (illustrative snapshot) of a substrate and elements of a sensor device at different stages of the manufacturing according to other embodiments is shown, which include an additional step 132 of depositing a trench coating layer 90 on the surface region 36 of the doped layer 32, wherein the selective deposition 130 of the doped layer 32 and the deposition 132 of the trench coating layer 90 collectively provide the coated deep trench structure 30.

[0136] Figures 1 to 8 A stage of the manufacturing process after the steps 130, 132, 140 and 150 is shown. After the step 130, the substrate 10 which can optionally include the buried doped region 501 still has the mask layer 16, and the deep trench structure is coated with the doped layer 32 having the thickness 34 and the surface region 36.

[0137] An additional deposition step 132 follows the step 130 of depositing the doped layer 32. The deposition 132 of the trench coating layer 90 can be, for example, an epitaxy process. For example, the deposition 132 can be a selective epitaxy process configured to deposit a semiconductor material primarily on the doped layer 32, such that the mask layer 16 can remain free of the material. The trench coating layer 90 can comprise a semiconductor material configured to reduce or block outward diffusion of boron. The trench coating layer 90 can comprise an undoped semiconductor material, such as undoped silicon, but the trench coating layer 90 can also comprise a low-doped semiconductor material having a doping concentration lower than the doping concentration of the doped layer 32. For example, the trench coating layer 90 can have a doping concentration less than the doping concentration of the substrate 10. For example, the trench coating layer 90 can have a doping concentration less than 10 15 cm -3 . The trench coating layer 90 can have a thickness 38 that can be less than 1 pm. Alternatively, the trench coating layer 90 can comprise an insulating material, such as silicon nitride, for example in combination with a thickness 38 of the trench coating layer 90 less than 100 nm.

[0138] The trench coating layer 90 can cover a surface region 36 of the doped layer 32. At least, the trench coating layer 90 covers a top surface region 37 of the doped layer 32. For example, the top surface region 37 of the doped layer 32 can be a surface region of the doped layer 32 that extends vertically above the main surface region 12 of the substrate and adjacent to the mask layer 16.

[0139] The selective deposition 130 of the doped layer 32 and the deposition 132 of the trench coating layer 90 collectively provide a coated deep trench structure 30 that can comprise the dimensions and functionalities as described above. After the deposition 132 of the trench coating layer 90, the method 100 can be implemented by the removal 140 of the mask layer 16 and the deposition 150 of the semiconductor capping layer as described with respect to Figure 10 .

[0140] By covering at least the top surface region 37 of the doped layer 32, the extent of the contact region between the doped layer 32 and the capping layer 52 can be reduced. In other words, the trench coating layer 90 is then configured to reduce the surface of the doped layer 32 that will be in contact with the capping layer 52 once formed. Accordingly, the amount of dopant that can diffuse from the doped layer 32 to the capping layer 52 during the deposition 150 of the capping layer 52 or during a subsequent step of outward diffusion 160 of the dopant can be reduced. Reducing such diffusion can prevent the diffused dopant from interfering with elements in or on the capping layer 52, such as the electrical circuit 70, during operation of the sensor device.

[0141] Figures 1 to 9Fig. 6 shows a schematic cross-sectional view (schematic snapshot) of a substrate 10 and elements of a sensor device according to an embodiment of the method 100 after steps 130, 140 and 150 of the manufacturing. Steps 130 and 140 correspond to the steps 130 and 140 described with respect to Figure 10 Fig. 7 shows a schematic cross-sectional view (schematic snapshot) of a substrate 10 and elements of a sensor device according to an embodiment of the method 100 after steps 130, 140 and 150 of the manufacturing. Steps 130 and 140 correspond to the steps 130 and 140 described with respect to Figures 1 to 9 Fig. 8 shows a schematic cross-sectional view (schematic snapshot) of a substrate 10 and elements of a sensor device according to an embodiment of the method 100 after steps 130, 140 and 150 of the manufacturing. Steps 130 and 140 correspond to the steps 130 and 140 described with respect to

[0142] The deposition of the first semiconductor capping layer 55 can be a deposition process similar to the deposition 150 of the capping layer 52 described with respect to Figures 1 to 9 Fig. 7, but the deposition of the first semiconductor capping layer 55 can be performed at a lower temperature or at a processing temperature of the deposition process described with respect to the deposition 150 in the description of Figures 1 to 9 Fig. 8. The deposition of the first semiconductor capping layer 55 closes the coated deep trench structure 30 described with respect to the deposition 150 in the description of Figures 1 to 9 Fig. 7.

[0143] The deposition of the second semiconductor capping layer 57 can be a growth of the second semiconductor capping layer 57 on top of the first semiconductor capping layer 55, for example. The deposition of the second semiconductor capping layer 57 can be a deposition process similar to the deposition 150 described with respect to Figure 11 Fig. 7, and the deposition of the second semiconductor capping layer 57 can be performed at a temperature described with respect to the deposition 150.

[0144] The temperature of the deposition of the first semiconductor capping layer 55 is for example more than 50 °C lower than the temperature of the deposition of the second semiconductor capping layer 57. For example, the temperature difference can exceed 100 °C, or more than 200 °C.

[0145] The deposition of the first semiconductor capping layer 55 at a lower temperature can help to reduce the diffusion of the dopant of the doped layer 32 into the capping layer 52.

[0146] Figures 2a to 2b Fig. 9 shows a schematic cross-sectional view (schematic snapshot) of a substrate 10 and elements of a sensor device according to an embodiment of the method 100 after steps 130, 140 and 150 of the manufacturing. Steps 130 and 140 correspond to the steps 130 and 140 described with respect to Figure 10 Fig. 7. Between the step 120 and the step 130, the embodiment comprises an additional step 122 of widening the deep trench structure 20, the steps of etching 120 and widening 122 together providing the deep trench structure 20.

[0147] The widening of the deep trench structure 20 corresponds to a removal of material of the substrate 10 from the surface 22 of the deep trench structure 20 over all or a portion of the height of the deep trench structure 20.

[0148] The widening 122 can be performed using an isotropic etching process, e.g. a dry etching process. Alternatively, the widening 122 can be performed using an anisotropic etching process, such as a wet etching process.

[0149] The widening 122 can laterally remove material of the substrate 10 from a surface area of the deep trench structure 20 that is adjacent to or vertically below the masking layer 16 for providing an undercut 29 of the deep trench structure 20 relative to the masking layer 16. In other words, in the area vertically below the masking layer 16, the deep trench structure 20 can have a larger lateral dimension than the exposed area 18 of the masking layer 16 (see Figure 9 ), the lateral dimension of the deep trench structure exceeding the exposed area 18 of the masking layer 16 defining the undercut 29. The undercut 29 can also be regarded as an overhang of the masking layer 16 over the deep trench structure 20.

[0150] The size of the undercut 29 can be at least as large as the thickness 34 of the doped layer 32 deposited in the subsequent step 130. The undercut 29 of the deep trench structure 20 leads to a configuration in which, after the doped layer 32 has been deposited in the subsequent step 130, the masking layer 16 capping a top surface area 37 of the doped layer 32 (as introduced with regard to Figures 1 to 9 ). However, in this embodiment, the top surface area 37 does not extend beyond the main surface area 12. In other words, the top surface area 37 of the doped layer 32 can be arranged vertically below the masking layer 16.

[0151] This configuration helps to prevent lateral contact between the doped layer 32 and the capping layer 52, thereby reducing diffusion of dopants from the doped layer 32 to the capping layer 52, e.g. during the deposition 150 of the capping layer 52.

[0152] As mentioned above, the steps of etching 120 and widening 122 jointly provide the deep trench structure 20. After the step 122, subsequent process steps can be performed according to embodiments of Figures 9 to 11 .

[0153] Figure 12 Embodiments of the above can be combined, either according to two out of all possible combinations, or all three.

[0154] ​A schematic cross-sectional view of a sensor device with a buried deep trench structure according to an embodiment is shown. The sensor device comprises a substrate 10' with a sensing region 14', a capping layer 52, a buried deep trench structure 50 comprising a doped layer 32, a trench doped region 60, and an electronic circuit 70 for the sensing region 14' located in a capping region 72 vertically above the buried deep trench structure 50.

[0155] The sensor device provides the functions and advantages described with respect to the method 100 for manufacturing a sensor device.

[0156] In the detailed description it can be seen that various features are grouped together in examples for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the examples require more features than are explicitly recited in each claim. Rather, inventive subject matter can lie in fewer than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the detailed description, where each claim can stand as a separate example. While each claim can stand as a separate example, it is to be noted that each of the claims can be combined in any manner with any of the other claims. In addition, while each of the claims can stand as a separate example, it is to be noted that a specific claim can be combined with an aspect or aspects of any of the other claims or with any of the features of any of the other claims. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the application be defined by the following claims and their equivalents.

[0157] While specific embodiments have been shown and described in detail to illustrate the application, it will be understood by those skilled in the art that various alternative and / or equivalent implementations can be substituted for the specific embodiments shown and described without departing from the scope of the present embodiments. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the application be defined by the following claims and their equivalents.

Claims

1. A method (100) for manufacturing a sensor device having a buried deep trench structure (50), comprising: A semiconductor substrate (10) is provided (110) having a sensing region (14) extending vertically into the semiconductor substrate (10) below a main surface region (12), wherein a mask layer (16) is disposed on the main surface region (12) of the semiconductor substrate (10). The deep trench structure (20) is etched (120) into the semiconductor substrate (10) through the exposed area (18) of the mask layer (16) for laterally arranging the deep trench structure (20) into the semiconductor substrate (10) relative to the sensing area (14) and vertically from the main surface area (12). A doped semiconductor layer (32) is selectively deposited (130) on the surface region (22) of the deep trench structure (20) via epitaxial deposition to provide a coated deep trench structure (30). At least partially remove (140) the mask layer (16) to expose the main surface region (12) of the semiconductor substrate (10). A semiconductor capping layer (52) is deposited (150) on the main surface region (12) of the semiconductor substrate (10), wherein the semiconductor capping layer (52) covers and closes the coated deep trench structure (30) and together with the semiconductor substrate (10) forms a thickened semiconductor substrate (10') having the buried deep trench structure (50), wherein the buried deep trench structure (50) is empty, or filled with gas, or completely filled with dielectric material, and The dopant of the doped semiconductor layer (32) is diffused outward (160) into the thickened semiconductor substrate (10'), wherein the outwardly diffused dopant provides a trench doped region (60) extending from the doped semiconductor layer (32) into the thickened semiconductor substrate (10').

2. The method (100) according to claim 1, wherein the doped semiconductor layer (32) is deposited having a density of 10 16 cm -3 Up to 10 20 cm -3 The doping concentration and thickness range between 1 nm and 100 nm.

3. The method (100) according to claim 1 or 2, wherein the step (150) of depositing the semiconductor capping layer (52) on the main surface region (12) of the semiconductor substrate (10) includes an epitaxial (EPI) overgrowth process, wherein the capping layer thickness (54) of the deposited semiconductor capping layer (52) defines the buried depth of the buried deep trench structure (50) below the main surface region (12') of the thickened semiconductor substrate (10').

4. The method (100) according to claim 1 or 2, further comprising: A trench coating layer (90) is deposited (132) on the surface region (36) of the doped semiconductor layer (32). The selective deposition (130) of the doped semiconductor layer (32) and the deposition (132) of the trench coating layer (90) together provide the deep trench structure (30) of the coating.

5. The method (100) according to claim 1 or 2, wherein the step of depositing (150) the semiconductor capping layer (52) comprises: A first semiconductor capping layer (55) is deposited on the main surface region (12) of the semiconductor substrate (10); A second semiconductor capping layer (57) is deposited on the first semiconductor capping layer (55); The first semiconductor capping layer (55) and the second semiconductor capping layer (57) together form the semiconductor capping layer (52); and The deposition of the first semiconductor capping layer (55) is performed at a lower temperature than the deposition temperature of the second semiconductor capping layer (57) (157).

6. The method (100) according to claim 1 or 2, further comprising: Widen (122) the deep trench structure (20); The etching (120) and widening (122) steps together provide the deep trench structure (20).

7. The method (100) according to claim 1 or 2, further comprising: Before performing the step (150) of depositing the semiconductor capping layer (52), the coated deep trench structure (30) is filled with gas or dielectric material.

8. The method (100) according to claim 7, wherein the dielectric material filling the coated deep trench structure (30) is optically opaque to the light radiation to be detected in the sensing region (14).

9. The method (100) according to claim 1 or 2, wherein during the step (120) of etching the deep trench structure (20), a plurality of deep trench portions (20-1, 20-2, ..., 20-n) are etched into the semiconductor substrate (10) to form the deep trench structure (20), wherein the deep trench portions (20-1, 20-2, ..., 20-n) are formed to at least partially or completely laterally surround the sensing region (14) in the semiconductor substrate (10).

10. The method (100) according to claim 1 or 2, wherein the deep trench structure (20) has a depth (27) in the range of 2 μm to 50 μm and a width (25) in the range of 50 nm to 2 μm.

11. The method (100) according to claim 1 or 2, The semiconductor substrate (10) includes a buried doped region (501) that is vertically disposed below the sensing region (14) in the semiconductor substrate (10). The sensing region (14) and the buried doped region (501) are arranged to have complementary doping types, and The deep trench structure (20) extends vertically from the main surface region (12) of the semiconductor substrate (10) into the buried doped region (501).

12. The method (100) according to claim 1 or 2, further comprising: Electronic circuitry (70) for the sensing areas (14, 14') is arranged in a capping region (72) of the thickened semiconductor substrate, vertically above the buried deep trench structure (50).

13. The method (100) according to claim 1 or 2, wherein the sensor device is manufactured to include optically operable sensing regions (14, 14'), wherein the buried deep trench structure (50) at least partially or completely laterally surrounds each individual optically operable sensing region.

14. The method (100) according to claim 1 or 2, wherein the trench doped region (60) is arranged to provide a defined electrical drift field distribution in the sensing region (14') of the thickened semiconductor substrate (10') under the operable conditions of the sensor device.

15. A sensor device having a buried deep trench structure, the sensor device comprising: A semiconductor substrate (10') has a sensing region (14') that extends vertically into the semiconductor substrate (10') below a main surface region (12'); A semiconductor capping layer (52) extends vertically into the semiconductor substrate (10') below the main surface region (12'); A buried deep trench structure (50) extends vertically into the semiconductor substrate (10') below the capping layer (52) and laterally relative to the sensing region (14'). The buried deep trench structure (50) includes a doped semiconductor layer (32) extending from a surface region (36) of the buried deep trench structure (50) into the semiconductor substrate (10'), wherein the central region of the buried deep trench structure (50) surrounded by the surface region (36) is empty, or filled with gas, or completely filled with dielectric material; The trench doped region (60) extends from the doped semiconductor layer (32) of the buried deep trench structure (50) into the semiconductor substrate (10'); Electronic circuitry (70) for the sensing area (14') is located in a capping region (72) of the semiconductor substrate (10') vertically above the buried deep trench structure (50).

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