Architecture for block-sparse operations on systolic arrays

Abstract

The present application discloses an architecture for block sparse operations on systolic arrays. Embodiments described herein include software, firmware, and hardware logic that provide techniques for performing arithmetic on sparse data via systolic processing units. One embodiment provides data-aware sparsity via a compressed bitstream. One embodiment provides a block sparse dot product instruction. One embodiment provides a deep adapter for systolic arrays.

Description

[0001] This invention patent application is a divisional application of the invention patent application with international application number PCT / US2020 / 022847, international application date March 14, 2020, application number 202080004288.3 entering the Chinese national phase, and name “Architecture for Block Sparse Operations on Systolic Arrays”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application is related to U.S. Provisional Application No. 62 / 819,337 filed on March 15, 2019 by Abhishek Appu et al., entitled “GRAPHICS PROCESSING” (Agent Docket No. AC0271-Z), U.S. Provisional Application No. 62 / 819,435 filed on March 15, 2019 by Lakshminarayanan Striramassarma et al., entitled “GRAPHICS DATA PROCESSING” (Agent Docket No. AC0285-Z), and U.S. Provisional Application No. 62 / 819,435 filed on March 15, 2019 by Subramaniam Maiyuran et al., entitled “SYSTEMS AND METHODS FOR PARTITIONING CACHE TO REDUCE CACHE ACCESS LATENCY (System and Method for Partitioning a Cache to Reduce Cache Access Latency)" and U.S. Provisional Application No. 62 / 819,361 (Agent Docket No. AC0286-Z) filed on November 15, 2019 by Abhishek Appu et al., entitled "SYSTOLIC ARITHMETIC ON SPARSE DATA" (Agent Docket No. AC5197-Z), and claim the benefit of and priority to these applications under 35 U.S.C. § 119(e), the contents of all of which are incorporated herein by reference. Technical Field

[0004] The present disclosure relates generally to data processing, and more particularly to sparse data processing via a matrix accelerator of a general purpose graphics processing unit. Background Art

[0005] Current parallel graphics data processing includes systems and methods developed for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently, portions of graphics processors have become programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.

[0006] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency. A general overview of the software and hardware of the SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to understand the above-described features of the present embodiment in detail, the embodiments briefly summarized above may be described in more detail by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments and therefore should not be considered as limiting the scope thereof.

[0008] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0009] Figure 2A-2D illustrates parallel processor components;

[0010] Figure 3A-3C is a block diagram of a graphics multiprocessor and a multiprocessing-based GPU;

[0011] Figure 4A-4F illustrates an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0012] Figure 5 Diagram of the graphics processing pipeline;

[0013] Figure 6 Diagram of the machine learning software stack;

[0014] Figure 7 Illustration of a general purpose graphics processing unit;

[0015] Figure 8 Diagram of a multi-GPU computing system;

[0016] Figure 9A-9B illustrates the layers of an exemplary deep neural network;

[0017] Fig.10 illustrates an exemplary recurrent neural network;

[0018] Fig.11 Illustration of the training and deployment of deep neural networks;

[0019] Fig.12 is a block diagram illustrating distributed learning;

[0020] Fig.13 illustrates an exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model;

[0021] Fig.14 is a block diagram of the processing system;

[0022] Figure 15A-Figure 15C Graphics computing systems and graphics processors;

[0023] Figure 16A-16C A block diagram illustrating an additional graphics processor and computing accelerator architecture;

[0024] Fig.17 is a block diagram of a graphics processing engine of a graphics processor;

[0025] Figure 18A-18B The diagram includes thread execution logic for an array of processing elements employed in a graphics processor core;

[0026] Fig.19 Figure 1 shows additional execution units;

[0027] Fig. 20 is a block diagram illustrating a graphics processor instruction format;

[0028] Fig.21 is a block diagram of an additional graphics processor architecture;

[0029] Figure 22A-22B Illustrate the graphics processor command format and command sequence;

[0030] Fig.23 illustrates an exemplary graphical software architecture for a data processing system;

[0031] Fig.24A is a block diagram illustrating an IP core development system;

[0032] Fig. 24B illustrates a cross-sectional side view of an integrated circuit package assembly;

[0033] Fig.24C illustrates a package assembly including a hardware logic chiplet (e.g., base die) of multiple units connected to a substrate;

[0034] Fig.24D The illustration includes a package assembly including interchangeable chiplets;

[0035] Fig.25 is a block diagram illustrating an exemplary system-on-chip integrated circuit;

[0036] Figure 26A-26B is a block diagram illustrating an exemplary graphics processor for use within a SoC;

[0037] Fig. 27 illustrates additional execution units according to an embodiment;

[0038] Fig.28 illustrates matrix operations performed by an instruction pipeline according to an embodiment;

[0039] Figure 29A-29B illustrates details of a hardware-based systolic array according to some embodiments;

[0040] Fig.30 The diagram includes a systolic array of parts and loops and circuits for accelerating sparse matrix multiplication;

[0041] Figure 31A-Figure 31B The diagram includes matrix acceleration logic for implementing a codec that reads sparse data in a compressed format;

[0042] Figure 32A-32B illustrates zero-based SM encoding for sparse neural network data according to an embodiment;

[0043] Figure 33A-Figure 33B illustrates SM encoding of specified values ​​for sparse neural network data according to an embodiment;

[0044] Figure 34A-Figure 34B illustrates a comparison between unstructured sparsity and block sparsity in training data for a neural network;

[0045] Figure 35A-Figure 35B illustrates a four-element dot product instruction that can be performed by the dot product logic;

[0046] Figure 36A-36B Figure 2 shows a two-element dot product instruction that can be performed by the dot product logic;

[0047] Figure 37A-Figure 37D illustrates instructions and associated hardware logic for implementing a multiply-add vector operation with zero skipping for sparse inputs;

[0048] Figure 38A-Figure 38BCompare 3D convolution and depthwise convolution;

[0049] Figure 39A-Figure 39C A system including a systolic tensor array and an image-to-column adapter for use during a depthwise convolution is illustrated;

[0050] Fig.40 illustrates a method for performing depthwise convolution on a systolic array; and

[0051] Fig.41 is a block diagram of a computing device including a graphics processor according to an embodiment. DETAILED DESCRIPTION

[0052] A graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate, for example, graphics operations, machine learning operations, pattern analysis operations, and / or various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to a host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the method used to connect the GPU, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0053] Embodiments described herein include software, firmware, and hardware logic that provide techniques for performing arithmetic on sparse data via systolic processing units. One embodiment provides data-aware sparsity via a compressed bitstream. One embodiment provides block sparse dot product instructions (e.g., dp4a, dp2a). One embodiment provides a deep adapter for systolic arrays.

[0054] In the following description, numerous specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be implemented without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the current embodiments.

[0055] System Overview

[0056] Figure 11 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the exemplary embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104. The one or more processors 102 communicate with the system memory 104 via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 may enable a display controller that may be included in the one or more processors 102 to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0057] For example, the processing subsystem 101 includes one or more parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. The one or more parallel processors 112 can form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. For example, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) for enabling direct connection to one or more display devices 110B.

[0058] Within the I / O subsystem 111, a system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 120. (Multiple) plug-in devices 120 may also include, for example, one or more external graphics processor devices and / or computing accelerators. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0059] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or any other bus or point-to-point communication interface and / or protocol(s) such as the NV-Link high-speed interconnect or an interconnect protocol known in the art.

[0060] One or more parallel processors 112 may include circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). Alternatively or additionally, as described in more detail herein, one or more parallel processors 112 may include circuits optimized for general-purpose processing while retaining the underlying computing architecture. The components of the computing system 100 may be integrated on a single integrated circuit with one or more other system elements. For example, one or more parallel processors 112, a memory hub 105, a processor 102, and an I / O hub 107 may be integrated in a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least some of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0061] It will be appreciated that the computing system 100 shown herein is illustrative, and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (multiple) processors 102, and the number of (multiple) parallel processors 112, may be modified as desired. For example, the system memory 104 may be connected to the (multiple) processors 102 directly rather than through a bridge, while other devices communicate with the system memory 104 through the memory hub 105 and the (multiple) processors 102. In other alternative topologies, the (multiple) parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. It is also possible for two or more groups of (multiple) processors 102 to be attached via multiple slots, which may be coupled to two or more instances of (multiple) parallel processors 112.

[0062] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may be specific to devices such as Figure 1 Different terminology is used for components than those illustrated in For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0063] Figure 2A The figure shows a parallel processor 200. The parallel processor 200 may be a GPU, a GPGPU, or the like as described herein. The components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The illustrated parallel processor 200 may be Figure 1 The parallel processor(s) 112 shown in FIG. 1 or one of the parallel processor(s) 112 .

[0064] Parallel processor 200 includes parallel processing unit 202. Parallel processing unit includes I / O unit 204 to enable communication with other devices, including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. For example, I / O unit 204 is connected to other devices by using a hub or switch interface (such as memory hub 105). The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

[0065] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. The scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before distributing tasks to the processing clusters in the processing cluster array 212. The scheduler 210 can be implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 212. Preferably, the host software can confirm the workload for scheduling on the processing array 212 via one of a plurality of graphics processing doorbell mechanisms. The workload can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0066] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each cluster 214A-214N in the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may allocate work to the clusters 214A-214N in the processing cluster array 212 using various scheduling and / or work distribution algorithms that may vary depending on the workload that occurs for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during compilation of program logic that is configured to be executed by the processing cluster array 212. Optionally, different clusters 214A-214N in the processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

[0067] Processing cluster array 212 may be configured to perform various types of parallel processing operations. For example, cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0068] Processing cluster array 212 is configured to perform parallel graphics processing operations. In such embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing, and then the data may be written back to system memory.

[0069] In embodiments where parallel processing units 202 are used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some of these embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0070] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands that define how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to retrieve an index corresponding to the task, or may receive the index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0071] Each of the one or more instances of the parallel processing unit 202 can be coupled to a parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar switch 216, which can receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B to partition unit 220N), which can each be coupled to a portion (e.g., memory cells) of the parallel processor memory 222. The number of partition units 220A-220N can be configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and an Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0072] The memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A-224N, allowing the partition units 220A-220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be excluded to facilitate the use of a unified memory design of the system memory combined with the local cache memory.

[0073] Optionally, any of the clusters 214A-214N in the processing cluster array 212 has the ability to process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any of the partition units 220A-220N or to another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment of an embodiment having a memory crossbar switch 216, the memory crossbar switch 216 has connections to a memory interface 218 for communicating with the I / O unit 204, and has connections to a local instance of a parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In general, the memory crossbar switch 216 may be able to separate traffic streams between the clusters 214A-214N and the partition units 220A-220N using virtual channels, for example.

[0074] Although a single instance of parallel processing unit 202 is illustrated in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be arranged on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate, even if different instances have different number of processing cores, different local parallel processor memory amounts, and / or other configuration differences. Optionally, some instances of parallel processing unit 202 may include floating point units with higher precision relative to other instances. Systems comprising one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented with various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0075] Figure 2B is a block diagram of the partition unit 220. The partition unit 220 may be Figure 2A 220N, and a partition unit 220A-220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent writeback requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as Figure 2A Partition unit 220 may also additionally or alternatively interface with one of the memory units in the parallel processor memory via a memory controller (not shown).

[0076] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a tile-by-tile basis.

[0077] ROP 226 may be included in each processing cluster (e.g., Figure 2A 214A-214N) rather than being included in the partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar switch 216. The processed graphics data may be displayed on a display device (such as, Figure 1 100), may be routed for further processing by the processor(s) 102, or may be routed for Figure 2A The processing is further processed by one of the processing entities within the parallel processor 200.

[0078] Figure 2C is a block diagram of a processing cluster 214 within a parallel processing unit. For example, a processing cluster is Figure 2A An instance of a processing cluster in the processing clusters 214A-214N. Processing cluster 214 can be configured to execute multiple threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific input data set. Optionally, a single instruction multiple data (SIMD) instruction issuance technology can be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Alternatively, a single instruction multiple thread (SIMT) technology can be used to use a public instruction unit configured to issue instructions to a processing engine set within each processing cluster in the processing cluster to support the parallel execution of a large number of threads that are generally synchronized. Unlike the SIMD execution mechanism in which all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. Those skilled in the art will understand that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0079] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. The pipeline manager 232 Figure 2A The scheduler 210 receives instructions and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations, including other shader units. The pipeline manager 232 may facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0080] Each graphics multiprocessor 234 within a processing cluster 214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner in which a new instruction may be issued before a previous instruction is completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. The same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0081] The instructions transmitted to the processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. A thread group may also include more threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing may be performed on consecutive clock cycles. Optionally, multiple thread groups may be executed simultaneously on the graphics multiprocessor 234.

[0082] The graphics multiprocessor 234 may include internal cache memory to perform load and store operations. Alternatively, the graphics multiprocessor 234 may abandon the internal cache and use cache memory (e.g., L1 cache 248) within the processing cluster 214. Each graphics multiprocessor 234 also has a partition unit (e.g., Figure 2A220A-220N) that are shared between all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 248.

[0083] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 may reside in Figure 2A 218. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of the slice and optionally includes a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical address is processed to distribute surface data access locality, thereby allowing efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0084] In graphics and compute applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown), or in some embodiments, from an L1 cache within the graphics multiprocessor 234 and fetched from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to ROP units, which may communicate with partition units (e.g., as described herein) as described herein. Figure 2A The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0085] It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Further, although only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing cluster 214. Optionally, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0086] Figure 2D An example of a graphics multiprocessor 234 is shown, where the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268. The graphics multiprocessor 234 may additionally include tensor and / or ray tracing cores 263 that include hardware logic for accelerating matrix and / or ray tracing operations.

[0087] The instruction cache 252 may receive an instruction stream to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch the instructions as thread groups (e.g., warps), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 262. The instructions may access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 may be used to convert addresses in the unified address space to different memory addresses that may be accessed by the load / store unit 266.

[0088] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 234. The register file 258 provides temporary storage for operands for data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 234. The register file 258 may be divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. For example, the register file 258 may be divided between different warps executed by the graphics multiprocessor 234.

[0089] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 234. In some implementations, the GPGPU cores 262 may include hardware logic that may otherwise reside within the tensor and / or ray tracing cores 263. The GPGPU cores 262 may be similar in architecture, or may be architecturally distinct. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. Optionally, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or implement variable-precision floating-point arithmetic. The graphics multiprocessor 234 may additionally include one or more fixed-function units or specialized function units for performing specific functions (such as copying rectangles or pixel blending operations). One or more of the GPGPU cores may also include fixed or specialized function logic.

[0090] GPGPU core 262 may include SIMD logic capable of executing a single instruction to multiple data sets. Optionally, GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for GPGPU cores may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, and in one embodiment, eight SIMT threads may be executed in parallel via a single SIMD8 logic unit, and these eight SIMT threads perform the same or similar operations.

[0091] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. For example, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 are very low latency. The shared memory 270 can be used to implement communication between threads executed on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as a data cache, for example, for caching texture data transferred between the functional unit and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0092] Figure 3A-3C Additional graphics multiprocessors are illustrated according to embodiments. Figure 3A-3B Graphics multiprocessors 325, 350 are shown, which are connected to Figure 2C The graphics multiprocessor 234 of FIG. 234 is related to and can be used to replace one of the graphics multiprocessors 234. Therefore, the disclosure of any features in combination with the graphics multiprocessor 234 herein also discloses the corresponding combination with the graphics multiprocessor(s) 325, 350, but is not limited thereto. Figure 3C A graphics processing unit (GPU) 380 is illustrated that includes a dedicated collection of graphics processing resources arranged into multi-core groups 365A-365N that correspond to the graphics multiprocessors 325, 350. The illustrated graphics multiprocessors 325, 350 and multi-core groups 365A-365N may be streaming multiprocessors (SMs) that are capable of executing a large number of execution threads simultaneously.

[0093] Relative to Figure 2D Graphics multiprocessor 234, Figure 3AThe graphics multiprocessor 325 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and (multiple) texture units 344A-344B. The graphics multiprocessor 325 also includes multiple graphics or compute execution unit sets (e.g., GPGPU cores 336A-336B, tensor cores 337A-337B, ray tracing cores 338A-338B) and multiple load / store unit sets 340A-340B. The execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and a shared memory 346.

[0094] The components may communicate via an interconnect fabric 327. The interconnect fabric 327 may include one or more crossbar switches to enable communication between the components of the graphics multiprocessor 325. The interconnect fabric 327 may be a separate, high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect fabric 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with the shared memory 346 via the interconnect fabric 327. The interconnect fabric 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0095] Figure 3B The graphics multiprocessor 350 includes a plurality of execution resource sets 356A-356D, wherein, for example Figure 2D and Figure 3A As shown in FIG. 1 , each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units. Execution resources 356A-356D can work in conjunction with (multiple) texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 353. For example, execution resources 356A-356D can share multiple instances of instruction cache 354 and shared memory 353 as well as texture and / or data cache memory 358A-358B. Each component can be connected to the CPU via a processor similar to Figure 3A The interconnect structure 327 communicates with the interconnect structure 352.

[0096] Those skilled in the art will understand that Figure 1 , Figure 2A-2D as well as Figure 3A-3BThe architecture described in is illustrative and does not limit the scope of the present embodiments. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as, Figure 2A parallel processing unit 202), and one or more graphics processors or special processing units.

[0097] The parallel processor or GPGPU described herein may be communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the method used to connect the GPU, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0098] Figure 3C A graphics processing unit (GPU) 380 is shown that includes a collection of dedicated graphics processing resources arranged as multi-core groups 365A-365N. Although details of only a single multi-core group 365A are provided, it will be understood that other multi-core groups 365B-365N may be equipped with the same or similar collections of graphics processing resources. The details described with respect to multi-core groups 365A-365N may also be applied to any of the graphics multiprocessors 234, 325, 350 described herein.

[0099] As illustrated, multi-core group 365A may include a set 370 of graphics cores, a set 371 of tensor cores, and a set 372 of ray tracing cores. Scheduler / dispatcher 368 schedules and dispatches graphics threads for execution on the various cores 370, 371, 372. A set 369 of register files stores operand values ​​used by cores 370, 371, 372 when executing graphics threads. These register files may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and operand matrix registers for storing tensor / matrix values. Slice registers may be implemented as a set of combined vector registers.

[0100] One or more combined first level (L1) caches and shared memory units 373 store graphics data locally within each multi-core group 365A, such as texture data, vertex data, pixel data, light data, bounding volume data, etc. One or more texture units 374 may also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 375 shared by all multi-core groups 365A-365N or a subset of multi-core groups 365A-365N stores graphics data and / or instructions for multiple concurrent graphics threads. As shown, the L2 cache 375 may be shared across multiple multi-core groups 365A-365N. One or more memory controllers 367 couple the GPU 380 to a memory 366, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0101] Input / output (I / O) circuitry 363 couples GPU 380 to one or more I / O devices 362, such as digital signal processors (DSPs), network controllers, or user input devices. On-chip interconnects may be used to couple I / O devices 362 to GPU 380 and memory 366. One or more memory management units (IOMMUs) 364 of I / O circuitry 363 directly couple I / O devices 362 to system memory 366. Optionally, IOMMU 364 manages page tables for mapping virtual addresses to multiple sets of physical addresses in system memory 366. I / O devices 362, CPU(s) 361, and GPU(s) 380 may then share the same virtual address space.

[0102] In one implementation of IOMMU 364, IOMMU 364 supports virtualization. In this case, IOMMU 364 manages a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 366). The base address of each of the first set of page tables and the second set of page tables may be stored in a control register and swapped out upon context switch (e.g., so that the new context is provided with access to the associated set of page tables). Although not described in detail in the prior art, the first set of page tables and the second set of page tables may be stored in a control register and swapped out upon context switch (e.g., so that the new context is provided with access to the associated set of page tables). Figure 3C , but each of the cores 370, 371, 372 and / or multi-core groups 365A-365N may include a translation lookaside buffer (TLB) that is used to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0103] The CPU 361, GPU 380, and I / O device 362 may be integrated on a single semiconductor chip and / or chip package. The illustrated memory 366 may be integrated on the same chip, or may be coupled to a memory controller 367 via an off-chip interface. In one implementation, the memory 366 includes GDDR6 memory that shares the same virtual address space with other physical system-level memories, but the underlying principles described herein are not limited to this particular implementation.

[0104] Tensor core 371 may include multiple execution units specifically designed to perform matrix operations, which are basic computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations may be used for neural network training and inference. Tensor core 371 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). For example, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to build a high-quality final image.

[0105] In a deep learning implementation, parallel matrix multiplication work can be scheduled for execution on the Tensor Core 371. The training of neural networks in particular requires a large number of matrix dot product operations. To handle the inner product formulation of the N x N x N matrix multiplication, the Tensor Core 371 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the operand matrix register, and for each of the N loops, at least one column of the second matrix is ​​loaded. For each loop, there are N dot products that are processed.

[0106] Depending on the specific implementation, matrix elements can be stored in different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the tensor cores 371 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization to bytes and nibbles).

[0107] The ray tracing core 372 can accelerate ray tracing operations for both real-time ray tracing implementations and non-real-time ray tracing implementations. Specifically, the ray tracing core 372 may include a ray traversal / intersection circuit for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 372 may also include circuits for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing core 372 performs traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be performed on the tensor core 371. For example, the tensor core 371 may implement a deep learning neural network to perform denoising on frames generated by the ray tracing core 372. However, the CPU(s) 361, the graphics core 370, and / or the ray tracing core 372 may also implement all or part of the denoising and / or deep learning algorithms.

[0108] Furthermore, as described above, a distributed approach to noise reduction may be employed in which GPU 380 is in a computing device coupled to other computing devices via a network or high-speed interconnect. In this distributed approach, the interconnected computing devices may share neural network learning / training data to improve the speed at which the entire system learns to perform noise reduction for different types of image frames and / or different graphics applications.

[0109] The ray tracing core 372 can handle all BVH traversals and / or ray-primitive intersections, thereby saving the graphics core 370 from being overloaded with thousands of instructions for each ray. For example, each ray tracing core 372 includes a first set of specialized circuits for performing bounding box tests (e.g., for traversal operations) and / or a second set of specialized circuits for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, for example, the multi-core group 365A can simply initiate ray detection, and the ray tracing core 372 independently performs ray traversals and intersections and returns hit data (e.g., hits, no hits, multiple hits, etc.) to the thread context. While the ray tracing core 370 performs traversal and intersection operations, the other cores 371, 372 are freed up to perform other graphics or computational work.

[0110] Optionally, each ray tracing core 372 may include a traversal unit for performing BVH test operations and / or an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response, which it provides to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 370 and tensor core 371) are freed up to perform other forms of graphics work.

[0111] In an alternative embodiment described below, a hybrid rasterization / ray tracing approach is used in which the work is distributed between graphics core 370 and ray tracing core 372.

[0112] The ray tracing core 372 (and / or other cores 370, 371) may include hardware support for ray tracing instruction sets, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable the assignment of a unique set of shaders and textures to each object. Another ray tracing platform that may be supported by the ray tracing core 372, graphics core 370, and tensor core 371 is Vulkan 1.1.85. However, it is noted that the underlying principles described herein are not limited to any particular ray tracing instruction set architecture ISA.

[0113] In general, each core 372, 371, 370 may support a ray tracing instruction set including instructions / functions for one or more of the following: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, preferred embodiments include ray tracing instructions for performing one or more of the following functions:

[0114] Light Generation - Ray generation instructions can be executed per pixel, sample, or user-defined work distribution.

[0115] Recent Hits - A nearest hit command may be executed to locate the closest intersection of a ray with a primitive within the scene.

[0116] Any hit - Any hit instruction identifies multiple intersections of a ray with a primitive within the scene, thereby potentially identifying a new closest intersection point.

[0117] intersect ——The intersection instruction performs a ray-primitive intersection test and outputs the result.

[0118] Per-primitive bounding box construction - This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0119] miss - Indicates that the ray missed all geometry in the scene or a specified region of the scene.

[0120] visit ——Indicates the subvolume that the ray will traverse.

[0121] abnormal-- Includes various types of exception handlers (e.g., called for various error conditions).

[0122] Technologies for GPU to host processor interconnect

[0123] Figure 4A The figure shows that a plurality of GPUs 410-413 (e.g., such as Figure 2A 200) is communicatively coupled to a plurality of multi-core processors 405-406 via high-speed links 440A-440D (e.g., buses, point-to-point interconnects, etc.). Depending on the implementation, high-speed links 440A-440D may support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles described herein are not limited to any particular communication protocol or throughput.

[0124] Two or more of the GPUs 410-413 may be interconnected via high-speed links 442A-442B, which may be implemented using the same or different protocols / links as those used for high-speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 443, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). As mentioned, however, the basic principles described herein are not limited to any particular type of interconnect technology.

[0125] Each multi-core processor 405-406 may be communicatively coupled to a processor memory 401-402 via a memory interconnect 430A-430B, respectively, and each GPU 410-413 may be communicatively coupled to a GPU memory 420-423 via a GPU memory interconnect 450A-450D, respectively. The memory interconnects 430A-430B and 450A-450D may utilize the same or different memory access technologies. As an example and not by way of limitation, the processor memory 401-402 and the GPU memory 420-423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint / Optane or Nano-Ram. For example, a portion of these memories may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0126] As described below, although each processor 405-406 and GPU 410-413 may be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each include 64GB of system memory address space, and GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0127] Figure 4B The figure shows additional optional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0128] The illustrated processor 407 includes a plurality of cores 460A-460D, each having a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data, which are not illustrated to avoid obscuring the basic principles of the components described herein (e.g., instruction fetching unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.). Caches 462A-462D may include a level 1 (L1) cache and a level 2 (L2) cache. In addition, one or more shared caches 456 may be included in the cache hierarchy and shared by the core set 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. Processor 407 and graphics accelerator integrated module 446 are connected to system memory 441, which may include processor memories 401-402.

[0129] Coherence is maintained for data and instructions stored in each cache 462A-462D, 456 and system memory 441 via inter-core communications over coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles described herein.

[0130] A proxy circuit 425 may be provided that communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in a cache coherence protocol as a peer of the core. Specifically, an interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and an interface 437 connects the graphics acceleration module 446 to the high-speed link 440.

[0131] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be separate GPUs integrated on a common package, line card, or chip.

[0132] The accelerator integrated circuit 436 may include a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and a memory access protocol for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. The data stored in the cache 438 and the graphics memories 433-434, M may be kept consistent with the core caches 462A-462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, 456 (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A-462D, 456 and receiving updates from cache 438).

[0133] The register set 445 stores context data for threads executed by the graphics processing engines 431-432, N, and the context management circuit 448 manages these thread contexts. For example, the context management circuit 448 may perform save and restore operations for saving and restoring the contexts of each thread during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, the context management circuit 448 may store the current register values ​​to a specified area in memory (e.g., identified by a context pointer). When returning to that context, it may then restore the register values. For example, the interrupt management circuit 447 may receive and process interrupts received from system devices.

[0134] In one implementation, the virtual / effective address from the graphics processing engine 431 is converted to an actual / physical address in the system memory 411 by the MMU 439. Optionally, the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407, or may be shared between multiple applications. Optionally, a virtualized graphics execution environment is provided in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). These resources can be subdivided into "slices", which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0135] Thus, the accelerator integrated circuit 436 acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory cache services. In one embodiment, to facilitate the bridging function, the accelerator integrated circuit 436 may also include a shared I / O 497 (e.g., PCIe, USB) and hardware to implement system control for voltage, timing, performance, heat, and security. The shared I / O 497 may utilize a separate physical connection or may traverse the high-speed link 440. In addition, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0136] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the actual address space viewed by the host processor 407, any host processor can directly address these resources using effective address values. An optional function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0137] One or more graphics memories 433-434, M may be respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3DXPoint / Optane or Nano-Ram.

[0138] To reduce the amount of data traffic on the high-speed link 440, biasing techniques may be used to ensure that the data stored in the graphics memories 433-434, M is data that will be used most frequently by the graphics processing engines 431-432, N and preferably not used (at least not frequently) by the cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not the graphics processing engines 431-432, N) within the caches 462A-462D, 456 of these cores and the system memory 411.

[0139] according to Figure 4C In the illustrated variant, the accelerator integrated circuit 436 is integrated into the processor 407. The graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via the high-speed link 440 via the interface 437 and the interface 435 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 may perform the same operations as the reference. Figure 4B The operations are the same as those described, but given the close proximity of the accelerator integrated circuit 436 to the coherency bus 464 and caches 462A-462D, 456, it is potentially possible to perform the operations at a higher throughput.

[0140] The described embodiments may support different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0141] In an embodiment of a dedicated process model, graphics processing engines 431-432, N can be dedicated to a single application or process under a single operating system. The single application can aggregate other application requests to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0142] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires the system hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0143] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431-432, N use a process handle to select a process element. The process element may be stored in the system memory 411 and may be addressable using the effective address to real address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (i.e., calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0144] Figure 4D An exemplary accelerator integrated slice 490 is illustrated. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit 436. An application effective address space 482 within the system memory 411 stores process elements 483. Process elements 483 may be stored in response to a GPU call 481 from an application 480 executed on a processor 407. Process elements 483 contain the process state of the corresponding application 480. A work descriptor (WD) 484 contained in the process element 483 may be a single job requested by an application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0145] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N can be shared by all or a subset of processes in the system. For example, the techniques described herein may include infrastructure for establishing process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0146] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0147] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484 including an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. As illustrated, data from the WD 484 may be stored in registers 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 448. For example, the MMU 439 may include a segment / page walk circuit for accessing a segment table / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 may process an interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432, N is converted into an actual address by the MMU 439.

[0148] The same register set 445 may be replicated for each graphics processing engine 431-432, N and / or graphics acceleration module 446 and may be initialized by a hypervisor or operating system. Each of these replicated registers may be included in an accelerator integrated slice 490. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0149] Table 1 - Registers initialized by the hypervisor

[0150] 1 Slice Control Register 2 Real Address (RA) dispatched process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0151] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0152] Table 2 - Registers initialized by the operating system

[0153]

[0154]

[0155] Each WD 484 may be specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required by the graphics processing engine 431-432, N to do its work, or it may be a pointer to a memory location where a command queue where an application has set up work to be done is located.

[0156] Figure 4E The diagram shows additional optional details of the sharing model. It includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

[0157] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sharing and graphics-directed sharing.

[0158] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests are guaranteed to be completed within a specified amount of time by the graphics acceleration module 446, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt processing of jobs. 3) When operating under a directed sharing programming model, the graphics acceleration module 446 must be guaranteed fairness between processes.

[0159] For the shared model, the application 480 may be required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type may be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446, and the WD may be in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application of setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user authority mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current permission mask override register (AMOR) value before placing the AMR into the process element 483. The CSRP may be a register in the registers 445 that contains the effective address of an area in the application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area may be fixed system memory.

[0160] Upon receiving the system call, the operating system 495 may verify that the application 480 is registered and has been given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0161] Table 3 - OS call parameters to the hypervisor

[0162] 1 Work Descriptor (WD) 2 The authority mask register (AMR) value (potentially masked). 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0163] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 in the process element linked list for the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0164] Table 4 - Process element information

[0165]

[0166]

[0167] The hypervisor may initialize the plurality of accelerator integrated slice 490 registers 445 .

[0168] like Figure 4F As shown in , in an optional implementation, a unified memory addressable via a common virtual memory address space is employed, which is used to access physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402 and vice versa, thereby simplifying programmability. A first portion of the virtual / effective address space may be allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as an effective address space) can thus be distributed across each of processor memory 401-402 and GPU memory 420-423, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0169] Bias / coherency management circuitry 494A-494E within one or more of the MMUs 439A-439E may be provided that ensures cache coherency between the caches of the host processor (e.g., 405) and the caches of the GPUs 410-413 and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. Figure 4F Multiple instances of bias / coherency management circuits 494A- 494E are shown in FIG. 4 , but bias / coherency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0170] The GPU-attached memory 420-423 can be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but will not suffer from the typical performance defects associated with full system cache coherence. The ability of the GPU-attached memory 420-423 to be accessed as system memory and without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420-423 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large number of streaming write memory services, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU calculation all play a role in determining the effectiveness of GPU offloading.

[0171] The selection between GPU bias and host processor bias may be driven by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure (i.e., controlled at a memory page granularity) comprising 1 or 2 bits per GPU-attached memory page. The bias table may be implemented in a stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., for caching frequently / recently used bias table entries). Alternatively, the entire bias table may be maintained within the GPU.

[0172] In one implementation, the bias table entry associated with each access to the GPU-attached memory 420-423 is accessed prior to the actual access to the GPU memory, resulting in the following operations. First, local requests from the GPU 410-413 for pages that find them in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPU for pages that find them in the host bias are forwarded to the processor 405 (e.g., as discussed above, over a high-speed link). Optionally, requests from the processor 405 that find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests involving pages in the GPU bias may be forwarded to the GPU 410-413. If the GPU is not currently using the page, the GPU may then convert the page to the host processor bias.

[0173] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, by a purely hardware-based mechanism.

[0174] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU to instruct it to change the bias state and perform a cache flush operation in the host for some transitions. The cache flush operation is necessary for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0175] Cache coherency may be maintained by temporarily rendering GPU-biased pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between host processor 405 and GPU 410, it is beneficial to ensure that GPU-biased pages are those pages requested by the GPU rather than host processor 405, and vice versa.

[0176] Graphics processing pipeline

[0177] Figure 5 The figure shows a graphics processing pipeline 500. A graphics multiprocessor such as Figure 2D Graphics multiprocessor 234, Figure 3A Graphics multiprocessor 325, Figure 3B The graphics multiprocessor 350 of FIG. 5 may implement the illustrated graphics processing pipeline 500. The graphics multiprocessor may be included in a parallel processing subsystem as described herein, such as a graphics multiprocessor 350 of FIG. Figure 2A A parallel processor 200, which can be used with Figure 1 The parallel processors 112 are related to and can be used to replace one of the parallel processors 112. Various parallel processing systems can be implemented by parallel processing units (e.g., Figure 2A The graphics processing pipeline 500 may be implemented using one or more instances of a parallel processing unit 202 of the graphics processing unit. For example, a shader unit (e.g., Figure 2C The graphics multiprocessor 234 of the graphics multiprocessor 234 may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by a processing cluster (e.g., Figure 2A Other processing engines and corresponding partition units (e.g., Figure 2A The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. It is also possible that one or more portions of the graphics processing pipeline 500 are executed by parallel processing logic within a general-purpose processor (e.g., a CPU). Optionally, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as a CPU) via a memory interface 528. Figure 2A The parallel processor memory 222 in the memory interface 528 may be Figure 2A The graphics processor pipeline 500 may also be implemented via Figure 3C This is achieved using the multi-core group 365A.

[0178] The data assembler 502 is a processing unit that can collect vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes the vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in cache, local or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0179] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0180] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. The control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for use in a surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and to tessellate the patch into a plurality of geometric primitives (such as line, triangle, or quadrilateral primitives), which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0181] The second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and builds graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. Geometry processing unit 516 can be programmed to tessellate graphics primitives into one or more new graphics primitives and calculate parameters used to rasterize the new graphics primitives.

[0182] The geometry processing unit 516 may be able to add or remove elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometry data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0183] The rasterizer 522 may perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 may read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade with samples, pixels, slices, or other granularities depending on the sampling rate configured for the processing unit.

[0184] Raster operation unit 526 is a processing unit that performs raster operations and outputs pixel data to be stored in graphics memory (e.g., as Figure 2A The parallel processor memory 222 and / or Figure 1 The raster operation unit 526 may be configured to compress z or color data written to memory and decompress z or color data read from memory.

[0185] Machine Learning Overview

[0186] The architecture described above can be applied to perform training and inference operations using machine learning models. Machine learning has been successful in solving many types of tasks. The calculations generated when training and using machine learning algorithms (e.g., neural networks) are naturally suitable for efficient parallel implementation. Therefore, parallel processors such as general-purpose graphics processing units (GPGPUs) have played an important role in the actual implementation of deep neural networks. Parallel graphics processors with single instruction multiple threads (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency. The efficiency provided by the parallel machine learning algorithm implementation allows the use of high-capacity networks and enables those networks to be trained to larger data sets.

[0187] A machine learning algorithm is an algorithm that can learn based on a set of data. For example, a machine learning algorithm can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numeric value given an input; and a pattern recognition algorithm can be used to generate converted text or perform text-to-speech and / or speech recognition.

[0188] An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The network nodes are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each consecutive layer in the network based on coefficients ("weights") associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0189] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves: selecting a network topology; using a set of training data that represents the problem being modeled by the network; and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and as the error signal is propagated backward through the layers of the network, the weights associated with the connections are adjusted to minimize that error. The network is considered "trained" when the error for each of the outputs generated from the instances of the training data set is minimized.

[0190] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Therefore, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to exploit the parallel processing hardware within general-purpose graphics processing devices.

[0191] Figure 6 is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 may include training and inference functions for a neural network and / or specialized software that may be used to train a neural network prior to deployment. Machine learning applications 602 may implement any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0192] Hardware acceleration for machine learning applications 604 can be enabled via a machine learning framework 602. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations often performed by machine learning algorithms. Without the machine learning framework 604, the developer of the machine learning algorithm would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when developing a new parallel processor. Instead, the machine learning application can be configured to use the primitives provided by the machine learning framework 604 to perform the necessary calculations. Exemplary primitives include tensor convolutions, excitation activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning framework 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0193] The machine learning framework 604 can process input data received from the machine learning application 602 and generate appropriate inputs to the computation framework 606. The computation framework 606 can abstract the underlying instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to be intimately familiar with the architecture of the GPGPU hardware 610. In addition, the computation framework 606 can enable hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610.

[0194] GPGPU machine learning acceleration

[0195] Figure 7 The general-purpose graphics processing unit 700 is shown in FIG. Figure 2A Parallel processor 200 or Figure 1(multiple) parallel processors 112. The general purpose processing unit (GPGPU) 700 can be configured to be particularly efficient in processing the type of computational workload associated with training deep neural networks. In addition, the GPGPU 700 can be directly linked to other instances of the GPGPU to create a multi-GPU cluster, thereby improving the training speed of deep neural networks in particular.

[0196] GPGPU 700 includes a host interface 702 for enabling connection to a host processor. Host interface 702 may be a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and distributes execution threads associated with those commands to a collection of processing clusters 706A-706H using a global scheduler 704. Processing clusters 706A-706H share a cache memory 708. Cache memory 708 may act as a higher level cache for cache memory within processing clusters 706A-706H. The processing clusters 706A-706H shown may be connected to Figure 2A Corresponding to the processing clusters 214A-214N in.

[0197] GPGPU 700 includes memory 714A-714B coupled to processing clusters 706A-706H via a set of memory controllers 712A-712B. Memories 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Memories 714A-714B may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0198] Each of processing clusters 706A-706H may include a collection of graphics multiprocessors such as Figure 2D Graphics multiprocessor 234, Figure 3A Graphics multiprocessor 325, Figure 3B The graphics multiprocessor 350 may include Figure 3C The graphics multiprocessors of these computing clusters include multiple types of integer logic units and floating point logic units that can perform computational operations including those suitable for machine learning computations within a certain range of precision. For example, at least a subset of the floating point units in each of the processing clusters 706A-706H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

[0199] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies across embodiments. For example, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 708, which couples GPGPU 700 with a GPU link 710, which enables direct connection to other instances of GPGPU. GPU link 710 can be coupled to a dedicated GPU-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 700. Optionally, GPU link 710 is coupled to a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. Multiple instances of GPGPU 700 can be located in separate data processing systems and communicate via a network device, which can be accessed via a host interface 702. In addition to or instead of the host interface 702, GPU link 710 can be configured to enable connection to a host processor.

[0200] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, an alternative configuration of GPGPU 700 can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, relative to the training configuration, GPGPU 700 includes fewer processing clusters in the processing clusters 706A-706H. In addition, the memory technology associated with the memory 714A-714B can be different between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0201] Figure 8 A multi-GPU computing system 800 is shown. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. The host interface switch 804 may be a PCI Express switch device that couples the processor 802 to a PCI Express bus, through which the processor 802 may communicate with the set of GPGPUs 806A-806D. Each of the plurality of GPGPUs 806A-806D may be Figure 7806A-806D can be interconnected via a set of high-speed point-to-point GPU-GPU links 816. The high-speed GPU-GPU links can be connected to each of the GPGPUs 806A-806D via a dedicated GPU link, such as, for example, Figure 7 P2P GPU link 816 enables direct communication between each of GPGPUs 806A-806D without requiring communication over a host interface bus to which processor 802 is connected. With GPU-GPU traffic directed to the P2P GPU link, the host interface bus remains available for system memory access or for communicating with other instances of multi-GPU computing system 800, for example, via one or more network devices. Figure 8 8, GPGPUs 806A-806D are connected to processor 802 via host interface switch 804, however, processor 802 may alternatively include direct support for P2P GPU link 816 and connect directly to GPGPUs 806A-806D.

[0202] Machine Learning Neural Network Implementation

[0203] The computing architecture described herein can be configured to perform these types of parallel processing that are particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0204] The second exemplary type of neural network is a convolutional neural network (CNN). CNN is a specialized feedforward neural network for processing data (such as image data) with a known, grid-like topology. Therefore, CNNs are commonly used for computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized as a set of "filters" (feature detectors stimulated by the receptive fields found in the retina), and the output of each filter set is propagated to the nodes in the successive layers of the network. The calculation for CNN includes applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to the convolution layer can be a multidimensional data array defining the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted by the training process for the neural network.

[0205] A recurrent neural network (RNN) is a type of feedforward neural network that includes feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for RNNs includes loops. These loops represent the effect of the current value of a variable on its own value at future moments, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature of language data, which can be composed.

[0206] The figures described below present exemplary feedforward networks, CNN networks, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiments described herein, and that the concepts illustrated are generally applicable to deep neural networks and machine learning techniques.

[0207] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition that produces reduced output errors relative to shallow machine learning techniques.

[0208] The deep neural network used in deep learning typically includes a front-end network for performing feature recognition, which is coupled to a back-end network that represents a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering for the model. Instead, a deep neural network can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical model used by the network is typically dedicated to a specific task to be performed, and different models will be used to perform different tasks.

[0209] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each of the neurons in the output layer. The error values ​​are then propagated backward until each neuron has an associated error value that roughly represents the contribution of the neuron to the original output. The network can then learn through those errors using an algorithm (such as a stochastic gradient descent algorithm) to update the weights of the neural network.

[0210] Figure 9A-9B Illustration of an example convolutional neural network. Fig. 9A The diagram shows the various layers within a CNN. Fig. 9A As shown in , an exemplary CNN for modeling image processing may receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 may be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The outputs from the plurality of convolutional layers may optionally be processed by a collection 908 of fully connected layers. As previously described for feedforward networks, neurons in a fully connected layer have full connections to all activations in the previous layer. The outputs from the fully connected layer 908 may be used to generate output results from the network. Activations within the fully connected layer 908 may be calculated using matrix multiplication instead of convolution. Not all CNN implementations utilize the fully connected layer 908. For example, in some implementations, the convolutional layer 906 may generate the output of the CNN.

[0211] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, as illustrated, the convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is input to the nodes of the subsequent layer. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0212] Fig. 9B An exemplary computational stage within a convolutional layer of a CNN is shown. An input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolutional stage 916, a detector stage 918, and a pooling stage 920. Subsequently, the convolutional layer 914 may output data to a successive convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to the CNN.

[0213] In convolution stage 916, several convolutions are performed in parallel to produce a set of linear activations. Convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the weight of the region to which the neuron is connected in the local input. The output from convolution stage 916 defines a set of linear activations processed by the successive stages of convolution layer 914.

[0214] The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the threshold of the activation function is set to zero.

[0215] Pooling stage 920 uses a pooling function that replaces the output of convolutional layer 906 with summary statistics of nearby outputs. Pooling functions can be used to introduce translation invariance into neural networks so that small translations to the input do not change the pooled output. Local translation invariance can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during pooling stage 920, including maximum pooling, average pooling, and l2 norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations substitute additional convolution stages with increased strides relative to previous convolution stages.

[0216] Subsequently, the output from the convolutional layer 914 may be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or a layer in the fully connected layer 908. For example, Fig. 9A The first convolution layer 904 can output to the second convolution layer 906, and the second convolution layer can output to the first layer in the fully connected layer 908.

[0217] Fig.10 An exemplary recurrent neural network 1000 is illustrated. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. RNNs can be established in various ways using various functions. The use of RNNs generally revolves around the use of mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given previous word sequences. The illustrated RNN 1000 can be described as having the following: an input layer 1002, which receives an input vector; a hidden layer 1004, which is used to implement a recurrent function; a feedback mechanism 1005, which is used to enable "memory" of previous states; and an output layer 1006, which is used to output a result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. At the initial input (x 1 ) can be processed by the hidden layer 1004. The second input (x 2 ) can be used by the hidden layer 1004 to process the initial input (x 1 ) is processed by the state information determined during the period. A given state can be calculated as s t =f(Ux t +Ws (t-1)), where U and W are parameter matrices. The function f is generally nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or a modified function f(x)=max(0,x). However, the specific mathematical function used in the hidden layer 1004 may vary depending on the specific implementation details of the RNN 1000.

[0218] In addition to the basic CNN network and RNN network described, changes in those networks can also be implemented. An example RNN variant is a long short-term memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is a convolutional deep belief network, which has a structure similar to CNN and is trained in a manner similar to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. Greedy unsupervised learning can be used to train DBN layer by layer. Subsequently, the learned weights of the DBN can be used to provide a pre-trained neural network by determining the best initial weight set for the neural network.

[0219] Fig.11 The training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training dataset 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to the untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108.

[0220] To start the training process, initial weights can be chosen randomly or by pre-training using a deep belief network. Subsequently, a training cycle is performed in a supervised or unsupervised manner.

[0221] Supervised learning is a learning method in which training is performed as an intermediate operation, such as when the training data set 1102 includes an input paired with an expected output of the input, or when the training data set includes an input with a known output and the output of the neural network is manually graded. The network processes the input and compares the resulting output with the expected output or a set of expected outputs. Subsequently, the error is back-propagated through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 converges to a model suitable for generating the correct answer based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. Subsequently, the trained neural network 1108 can be deployed to implement any number of machine learning operations to generate inference results 1114 based on the input of new data 1112.

[0222] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn the groupings within the unlabeled inputs and can determine how the individual inputs are related to the entire data set. Unsupervised training can be used to generate a self-organizing map, which is a class of trained neural networks 1108 that can perform operations that help reduce the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal pattern of the data.

[0223] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which a mixture of labeled and unlabeled data having the same distribution is included in the training data set 1102. Incremental learning is a variation of supervised learning in which input data is used continuously to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge embedded in the network during initial training.

[0224] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than using a single computing node.

[0225] Fig.12is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes can each include one or more host processors and one or more general processing nodes in the general processing node, such as Figure 7 700 in a highly parallel general purpose graphics processing unit. As illustrated, distributed learning may be performed model parallelism 1202, data parallelism 1204, or a combination of model parallelism and data parallelism 1204.

[0226] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0227] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. Subsequently, the results from different nodes are combined. Although different methods for data parallelism are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data, and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, with the exception that updates to the model are transmitted instead of transmitting parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0228] Combined model and data parallelism 1206 can be implemented, for example, in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with multiple separate GPUs within each node used to train different parts of the model.

[0229] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-GPU data transfer and accelerated remote data synchronization.

[0230] Example Machine Learning Applications

[0231] Machine learning can be applied to solve various technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision is from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, computer vision applications can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than previously feasible training data sets to train computer vision applications, and enables the use of low-power parallel processors to deploy inference systems.

[0232] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described in this article enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0233] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has been implemented to replace the hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0234] Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can utilize statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0235] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 The general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0236] Fig.13 An exemplary inference system on chip (SOC) 1300 suitable for performing inference using a trained model is illustrated. The SOC 1300 may integrate multiple processing components, including a media processor 1302, a visual processor 1304, a GPGPU 1306, and a multi-core processor 1308. The GPGPU 1306 may be a GPGPU described herein, such as the GPGPU 700, and the multi-core processor 1308 may be a multi-core processor described herein, such as the multi-core processors 405-406. The SOC 1300 may additionally include an on-chip memory 1305 that may enable a shared on-chip data pool that may be accessed by each of the processing components. The processing components may be optimized for low-power operation to enable deployment to various machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of the SOC 1300 may be used as part of a master control system for an autonomous vehicle. Where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

[0237] During operation, the media processor 1302 and the visual processor 1304 can work in unison to accelerate computer vision operations. The media processor 1302 can enable low latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. Subsequently, the visual processor 1304 can parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using the trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for a CNN that is used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0238] The multi-core processor 1308 may include control logic to assist in sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor to execute software applications that may utilize the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or may issue computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0239] GPGPU 1306 may include a computing cluster, such as a low-power configuration of processing clusters 706A-706H within general purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions specifically optimized to perform inference calculations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision calculations, such as 8-bit and 4-bit integer vector operations.

[0240] Additional System Overview

[0241] Fig.14 is a block diagram of processing system 1400 . Fig.14 Elements with the same or similar names as elements of any other figures herein are described as the same elements in other figures, can operate or function in a manner similar to elements in other figures, can include the same components, and can be linked to other entities, such as those described elsewhere in this document, but not limited thereto. System 1400 can be used in the following: a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1402 or processor cores 1407. System 1400 can be a processing platform incorporated into a system on a chip (SoC) integrated circuit for use in a mobile device, a handheld device, or an embedded device, such as for use in an Internet of Things (IoT) device with wired or wireless connectivity to a local area network or a wide area network.

[0242] System 1400 may be a system having Figure 1 For example, in different configurations, (multiple) processors 1402 or (multiple) processor cores 1407 may be associated with Figure 1 The graphics processor(s) 1408 may correspond to the processor(s) 102. Figure 1 The external graphics processor 1418 may be Figure 1One of the (multiple) plug-in devices 120.

[0243] The system 1400 may include, be coupled with, or be incorporated into a server-based gaming platform, a gaming console including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. The system 1400 may be part of a mobile phone, a smart phone, a tablet computing device, or a mobile internet-connected device such as a notebook with low internal storage capacity. The processing system 1400 may also include, be coupled with, or be integrated into a wearable device such as a smart watch wearable device; smart glasses or clothing enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. The processing system 1400 may include, or may be part of, a television or set-top box device. System 1400 may include, be coupled to, or be integrated into an autonomous vehicle, such as a bus, a tractor trailer, an automobile, an electric or electrical cycle, an airplane, or a glider (or any combination thereof). An autonomous vehicle may use system 1400 to process the environment sensed around the vehicle.

[0244] The one or more processors 1402 may include one or more processor cores 1407 for processor instructions that, when executed, perform operations for system or user software. At least one of the one or more processor cores 1407 may be configured to process a specific instruction set 1409. The instruction set 1409 may facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). The one or more processor cores 1407 may process different instruction sets 1409, which may include instructions for facilitating emulation of other instruction sets. The processor core 1407 may also include other processing devices, such as a digital signal processor (DSP).

[0245] The processor 1402 may include a cache memory 1404. Depending on the architecture, the processor 1402 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 1402. In some embodiments, the processor 1402 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared between the processor cores 1407 using known cache coherence techniques. A register file 1406 may additionally be included in the processor 1402, and the register file 106 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1402.

[0246] One or more processors 1402 may be coupled to one or more interface buses 1410 to transmit communication signals, such as address, data, or control signals, between the processor 1402 and other components in the system 1400. In one of these embodiments, the interface bus 1410 may be a processor bus, such as a version of a direct media interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI express), a memory bus, or other types of interface buses. For example, the processor(s) 1402 may include an integrated memory controller 1416 and a platform controller hub 1430. The memory controller 1416 facilitates communication between memory devices and other components of the system 1400, while the platform controller hub (PCH) 1430 provides connections to I / O devices via a local I / O bus.

[0247] The memory device 1420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having appropriate performance to act as a process memory. For example, the memory device 1420 may operate as a system memory for the system 1400 to store data 1422 and instructions 1421 for use when one or more processors 1402 execute applications or processes. The memory controller 1416 is also coupled to an optional external graphics processor 1418, which may communicate with one or more graphics processors 1408 in the processor 1402 to perform graphics operations and media operations. In some embodiments, graphics operations, media operations, or computing operations may be assisted by an accelerator 1412, which is a coprocessor that may be configured to perform a collection of specialized graphics operations, media operations, or computing operations. For example, the accelerator 1412 may be a matrix multiplication accelerator for optimizing machine learning or computing operations. The accelerator 1412 may be a ray tracing accelerator that may be used to perform ray tracing operations in concert with the graphics processor 1408. In one embodiment, an external accelerator 1419 may be used in place of or in concert with the accelerator 1412.

[0248] A display device 1411 may be provided, which may be connected to the processor(s) 1402. The display device 1411 may be one or more of: an internal display device, such as in a mobile electronic device or laptop device; or an external display device attached via a display interface (e.g., a display port, etc.). The display device 1411 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0249] The platform controller hub 1430 can enable peripheral devices to be connected to the memory device 1420 and the processor 1402 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1446, a network controller 1434, a firmware interface 1428, a wireless transceiver 1426, a touch sensor 1425, a data storage device 1424 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D XPoint / Optane, etc.). The data storage device 1424 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI express). The touch sensor 1425 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 1426 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G or long term evolution (LTE) transceiver. The firmware interface 1428 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). The network controller 1434 can enable network connection to a wired network. In some embodiments, a high-performance network controller (not shown) is coupled to the interface bus 1410. The audio controller 1446 can be a multi-channel high-definition audio controller. In some of these embodiments, the system 1400 includes an optional traditional I / O controller 1440 for coupling a traditional (e.g., personal system 2 (PS / 2)) device to the system. The platform controller hub 1430 can also be connected to one or more universal serial bus (USB) controllers 1442 to connect input devices, such as a keyboard and mouse 1443 combination, a camera 1444, or other USB input devices.

[0250] It will be appreciated that the illustrated system 1400 is exemplary and not limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 1416 and the platform controller hub 1430 may be integrated into a discrete external graphics processor, such as the external graphics processor 1418. The platform controller hub 1430 and / or the memory controller 1416 may be external to the one or more processors 1402. For example, the system 1400 may include an external memory controller 1416 and a platform controller hub 1430 that may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 1402.

[0251] For example, a circuit board ("sled") may be used on which components (such as CPUs, memory, and other components) are placed, designed to achieve improved thermal performance. Processing components such as processors may be located on the top side of the sled, while nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the enhanced airflow provided by the design, the components can operate at higher frequencies and power levels than typical systems, thereby increasing performance. In addition, the sled is configured to blindly mate power and data communication cables in the rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and / or replaced. Similarly, the various components (such as processors, accelerators, memory, and data storage devices) located on the sled are configured to be easily upgraded due to their increased spacing relative to each other. In an illustrative embodiment, the components additionally include hardware authentication features for proving their authenticity.

[0252] The data center may utilize a single network fabric ("fabric") that supports multiple other network architectures, including Ethernet and omni-path. The sleds may be coupled to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center may, in use, concentrate physically disaggregated resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.) and data storage drives, and provide them to computing resources (e.g., processors) as needed, thereby enabling the computing resources to access these concentrated resources as if the concentrated resources were local.

[0253] A power supply or power source may provide voltage and / or current to the system 1400 or any component or system described herein. In one example, the power supply includes an AC-DC (alternating current-direct current) adapter for plugging into a wall socket. Such AC power may be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. The power source or power supply may also include wireless charging hardware for charging by approaching a charging field. The power source may include an internal battery, an AC supply, an action-based power supply, a solar power supply, or a fuel cell source.

[0254] Figure 15A-Figure 15C Illustration of a computing system and a graphics processor. Figure 15A-Figure 15CThose elements having the same or similar names as elements of any other figures herein describe the same elements in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto.

[0255] Fig.15A 1402. It is a block diagram of a processor 1500, which may be a variant of and may be used in place of one of the processors 1402. Therefore, the disclosure of any features herein in combination with the processor 1500 also discloses the corresponding combination with the processor(s) 1402, but is not limited thereto. The processor 1500 may have one or more processor cores 1502A-1502N, an integrated memory controller 1514, and an integrated graphics processor 1508. In the case where the integrated graphics processor 1508 is excluded, a system including the processor will include a graphics processor device within a system chipset or a graphics processor device coupled via a system bus. The processor 1500 may include additional cores, up to and including the additional core 1502N represented by the dashed box. Each of the processor cores 1502A-1502N includes one or more internal cache units 1504A-1504N. In some embodiments, each processor core 1502A-1502N also has access to one or more shared cache units 1506. The internal cache units 1504A-1504N and the shared cache units 1506 represent a cache memory hierarchy within the processor 1500. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherency between each cache unit 1506 and 1504A-1504N.

[0256] The processor 1500 may also include a set of one or more bus controller units 1516 and a system agent core 1510. The one or more bus controller units 1516 manage a set of peripheral buses, such as one or more PCI buses or PCI Express buses. The system agent core 1510 provides management functions for various processor components. The system agent core 1510 may include one or more integrated memory controllers 1514 for managing access to various external memory devices (not shown).

[0257] For example, one or more of the processor cores 1502A-1502N may include support for simultaneous multithreading. The system agent core 1510 includes components for coordinating and operating the cores 1502A-1502N during multithreaded processing. The system agent core 1510 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1502A-1502N and the graphics processor 1508.

[0258] The processor 1500 may additionally include a graphics processor 1508 for performing graphics processing operations. In some of these embodiments, the graphics processor 1508 is coupled to a set of shared cache units 1506 and to a system agent core 1510, which includes one or more integrated memory controllers 1514. The system agent core 1510 may also include a display controller 1511 for driving the graphics processor output to one or more coupled displays. The display controller 1511 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1508.

[0259] A ring-based interconnect unit 1512 may be used to couple internal components of the processor 1500. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some of these embodiments with a ring-based interconnect 1512, the graphics processor 1508 is coupled to the ring-based interconnect 1512 via an I / O link 1513.

[0260] Exemplary I / O link 1513 represents at least one of a plurality of various I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1518 (such as an eDRAM module). Optionally, each of the processor cores 1502A-1502N and the graphics processor 1508 can use the embedded memory module 1518 as a shared last-level cache.

[0261] For example, processor cores 1502A-1502N may be isomorphic cores that execute the same instruction set architecture. Alternatively, processor cores 1502A-1502N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1502A-1502N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. Processor cores 1502A-1502N may be heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. As another example, processor cores 1502A-1502N are heterogeneous in terms of computing power. In addition, processor 1500 may be implemented on one or more chips, or may be implemented as a SoC integrated circuit having the illustrated components in addition to other components.

[0262] Fig. 15B 1 is a block diagram of the hardware logic of a graphics processor core 1519 according to some embodiments described herein. A graphics processor core 1519 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. An example of a graphics processor core 1519 is a graphics core slice, and based on a target power envelope and a performance envelope, a graphics processor as described herein may include multiple graphics core slices. Each graphics processor core 1519 may include a fixed function block 1530 coupled to multiple sub-cores 1521A-1521F (also referred to as sub-slices), which include blocks of modular general purpose and fixed function logic.

[0263] Fixed function block 1530 may include a geometry / fixed function pipeline 1531, which may be shared by all sub-cores in graphics processor core 1519, for example, in a lower performance and / or lower power graphics processor implementation. Geometry / fixed function pipeline 1531 may include a 3D fixed function pipeline (e.g., as described below). Fig.16A ), a video front end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that unifies the return buffers (e.g., as described below in Fig.17 Unified return buffer 1718 in .

[0264] Fixed function blocks 1530 may also include graphics SoC interface 1532, graphics microcontroller 1533, and media pipeline 1534. Graphics SoC interface 1532 provides an interface between graphics processor core 1519 and other processor cores within the system on chip integrated circuit. Graphics microcontroller 1533 is a programmable subprocessor that can be configured to manage various functions of graphics processor core 1519, including thread dispatching, scheduling, and preemption. Media pipeline 1534 (e.g., Fig.16A and Fig.17 The media pipeline 1616 of the embodiment includes logic for facilitating decoding, encoding, pre-processing and / or post-processing of multimedia data including image data and video data. The media pipeline 1534 implements media operations via requests to computational or sampling logic within the sub-cores 1521A-1521F.

[0265] The SoC interface 1532 may enable the graphics processor core 1519 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 1532 may also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomicity, which may be shared between the graphics processor core 1519 and the CPU within the SoC. The SoC interface 1532 may also implement power management control for the graphics processor core 1519 and enable an interface between the clock domain of the graphics core 1519 and other clock domains within the SoC. Optionally, the SoC interface 1532 enables receiving a command buffer from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. These commands and instructions may be dispatched to media pipeline 1534 when media operations are to be performed, or to geometry and fixed function pipelines (eg, geometry and fixed function pipeline 1531, geometry and fixed function pipeline 1537) when graphics processing operations are to be performed.

[0266] The graphics microcontroller 1533 may be configured to perform various scheduling and management tasks for the graphics processor core 1519. In one configuration, for example, the graphics microcontroller 1533 may perform graphics and / or computational workload scheduling for each graphics parallel engine within the execution unit (EU) arrays 1533A-1522F, 1524A-1524F within the sub-cores 1521A-1521F. In this workload scheduling, host software executing on a CPU core of a SoC including the graphics processor core 1519 may submit a workload to one of a plurality of graphics processor doorbells, which invokes a scheduling operation to the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to a command stream converter, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. Optionally, graphics microcontroller 1533 may also facilitate a low power or idle state for graphics processor core 1519, thereby providing graphics processor core 1519 with the ability to save and restore registers within graphics processor core 1519 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0267] The graphics processor core 1519 may have more or fewer sub-cores 1521A-1521F than those shown, up to N modular sub-cores. For each group of N sub-cores, the graphics processor core 1519 may also include shared function logic 1535, shared and / or cache memory 1536, geometry / fixed function pipelines 1537, and additional fixed function logic 1538 for accelerating various graphics and compute processing operations. The shared function logic 1535 may include functions that are shared by each of the N sub-cores within the graphics processor core 1519, and functions that are shared by each of the N sub-cores within the graphics processor core 1519. Fig.17 The shared function logic 1720 (e.g., sampler logic, math logic, and / or inter-thread communication logic) of the graphics processor core 1519 may be associated with the shared function logic 1720 (e.g., sampler logic, math logic, and / or inter-thread communication logic). The shared and / or cache memory 1536 may be a last-level cache for the set 1521A-1521F of N sub-cores within the graphics processor core 1519, and may also serve as a shared memory accessible by multiple sub-cores. A geometry / fixed function pipeline 1537 may be included within the fixed function block 1530 instead of the geometry / fixed function pipeline 1531, and the geometry / fixed function pipeline 1537 may include the same or similar logic units.

[0268] The graphics processor core 1519 may include additional fixed function logic 1538, which may include various fixed function acceleration logic for use by the graphics processor core 1519. Optionally, the additional fixed function logic 1538 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline within the geometry / fixed function pipelines 1538, 1531; and a culling pipeline, which is an additional geometry pipeline that may be included in the additional fixed function logic 1538. For example, the culling pipeline may be a streamlined version of the full geometry pipeline. The full pipeline and the culling pipeline may execute different instances of the same application, each with a separate context. Position-only shading can hide long culling runs for discarded triangles, thereby enabling shading to be completed earlier in some instances. For example, the culling pipeline logic within the additional fixed function logic 1538 can execute the position shader in parallel with the main application and generally generate key results faster than the full pipeline because the culling pipeline only takes the position attributes of the vertices and shades them without performing rasterization and rendering of the pixels to the frame buffer. The culling pipeline can use the generated key results to calculate visibility information for all triangles, regardless of whether those triangles are culled. The full pipeline (which can be referred to as a replay pipeline in this example) can consume this visibility information to skip culled triangles, thereby only shading visible triangles that are ultimately passed to the rasterization stage.

[0269] Optionally, the additional fixed-function logic 1538 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, which is used to include an optimized implementation for machine learning training or inference.

[0270] Included within each graphics sub-core 1521A-1521F is a collection of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests made by a graphics pipeline, a media pipeline, or a shader program. Graphics sub-cores 1521A-1521F include: multiple EU arrays 1522A-1522F, 1524A-1524F; thread dispatch and inter-thread communication (TD / IC) logic 1523A-1523F; 3D (e.g., texture) samplers 1525A-15255F; media samplers 1506A-1506F; shader processors 1527A-1527F; and shared local memory (SLM) 1528A-1528F. EU arrays 1522A-1522F, 1524A-1524F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to serve graphics operations, media operations, or computing operations (including graphics programs, media programs, or computing shader programs). TD / IC logic 1523A-1523F performs local thread dispatch and thread control operations for execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. 3D samplers 1525A-1525F can read textures or other 3D graphics-related data into memory. 3D samplers can read texture data in different ways based on the configured sample state and the texture format associated with a given texture. Media samplers 1506A-1506F can perform similar read operations based on the type and format associated with media data. For example, each graphics sub-core 1521A-1521F can alternately include unified 3D and media samplers. Threads executing on execution units within each of the sub-cores 1521A-1521F may utilize shared local memory 1528A-1528F within each sub-core, such that threads executing within a thread group can execute using a common pool of on-chip memory.

[0271] Fig. 15C1 is a block diagram of a general purpose graphics processor unit (GPGPU) 1570, which may be configured as a graphics processor (e.g., graphics processor 1508) and / or a computing accelerator, according to embodiments described herein. GPGPU 1570 may be interconnected with a host processor (e.g., one or more CPUs 1546) and memories 1571, 1572 via one or more system and / or memory buses. Memory 1571 may be system memory that may be shared with one or more CPUs 1546, while memory 1572 is device memory dedicated to GPGPU 1570. For example, components within GPGPU 1570 and device memory 1572 may be mapped to memory addresses accessible by one or more CPUs 1546. Access to memories 1571 and 1572 may be facilitated via a memory controller 1568. Memory controller 1568 may include an internal direct memory access (DMA) controller 1569, or may include logic for performing operations that would otherwise be performed by a DMA controller.

[0272] GPGPU 1570 includes multiple cache memories, including L2 cache 1553, L1 cache 1554, instruction cache 1555, and shared memory 1556, at least part of which may also be partitioned as cache memories. GPGPU 1570 also includes multiple computing units 1560A-1560N. Each computing unit 1560A-1560N includes a set of vector registers 1561, a set of scalar registers 1562, a set of vector logic units 1563, and a set of scalar logic units 1564. Computing units 1560A-1560N may also include a local shared memory 1565 and a program counter 1566. Compute units 1560A-1560N may be coupled with a constant cache 1567, which may be used to store constant data, which is data that will not change during the execution of a kernel program or shader program executing on GPGPU 1570. Constant cache 1567 may be a scalar data cache, and cached data may be fetched directly into scalar registers 1562.

[0273] During operation, one or more CPUs 1546 may write commands to registers in GPGPU 1570, or to memory in GPGPU 1570 that has been mapped to an accessible address space. Command processor 1557 may read commands from registers or memory and determine how to process those commands within GPGPU 1570. Thread dispatcher 1558 may then be used to dispatch threads to computing units 1560A-1560N to execute those commands. Each computing unit 1560A-1560N may execute threads independently of other computing units. In addition, each computing unit 1560A-1560N may be independently configured for conditional computation and may conditionally output the results of the computation to memory. Command processor 1557 may interrupt one or more CPUs 1546 when the submitted commands are completed.

[0274] Figure 16A-16C A block diagram illustrating additional graphics processor and computing accelerator architectures provided by embodiments described herein, for example, according to Figure 15A-Figure 15C . Figure 16A-16C Those elements having the same or similar names as elements of any other figures herein describe the same elements in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto.

[0275] Fig.16A 1 is a block diagram of a graphics processor 1600, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores or other semiconductor devices, such as but not limited to memory devices or network interfaces. Graphics processor 1600 may be a variant of graphics processor 1508 and may be used in place of graphics processor 1508. Therefore, the disclosure of any feature in combination with graphics processor 1508 herein also discloses the corresponding combination with graphics processor 1600, but is not limited thereto. The graphics processor may communicate via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. Graphics processor 1600 may include a memory interface 1614 for accessing memory. Memory interface 1614 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0276] Optionally, the graphics processor 1600 also includes a display controller 1602 for driving display output data to a display device 1618. The display controller 1602 includes hardware for compositing one or more overlay planes of a display and multiple layers of video or user interface elements. The display device 1618 can be an internal or external display device. In one embodiment, the display device 1618 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. The graphics processor 1600 may include a video codec engine 1606 for encoding media to one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as, MPEG-2), Advanced Video Coding (AVC) formats (such as, H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as, JPEG, and Motion JPEG (MJPEG) formats).

[0277] Graphics processor 1600 may include a block image transfer (BLIT) engine 1604 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, alternatively, 2D graphics operations may be performed using one or more components of a graphics processing engine (GPE) 1610. In some embodiments, GPE 1610 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0278] GPE 1610 may include a 3D pipeline 1612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1612 includes programmable and fixed-function elements that perform various tasks within elements and / or generated execution threads of 3D / media subsystem 1615. While 3D pipeline 1612 may be used to perform media operations, embodiments of GPE 1610 also include a media pipeline 1616 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0279] The media pipeline 1616 may include fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of the video codec engine 1606. The media pipeline 1616 may additionally include a thread generation unit to generate threads for execution on the 3D / media subsystem 1615. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1615.

[0280] 3D / media subsystem 1615 may include logic for executing threads generated by 3D pipeline 1612 and media pipeline 1616. The pipelines may send thread execution requests to 3D / media subsystem 1615, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. Execution resources include an array of graphics execution units for processing 3D threads and media threads. 3D / media subsystem 1615 may include one or more internal caches for thread instructions and data. Additionally, 3D / media subsystem 1615 may also include shared memory for sharing data between threads and for storing output data, which includes registers and addressable memory.

[0281] Fig. 16B Graphics processor 1620 is shown, which is a variant of graphics processor 1600 and can be used in place of graphics processor 1600, or vice versa. Therefore, any feature disclosed herein in combination with graphics processor 1600 also discloses the corresponding combination with graphics processor 1620, but is not limited thereto. Graphics processor 1620 has a sliced ​​architecture according to the embodiments described herein. Graphics processor 1620 may include graphics processing engine cluster 1622, which has graphics engine slices 1610A-1610D. Fig.16A1624. The graphics engine slices 1610A-1610D may be interconnected via a set of slice interconnects 1623A-1623F. Each graphics engine slice 1610A-1610D may also be connected to a memory module or memory device 1626A-1626D via a memory interconnect 1625A-1625D. The memory devices 1626A-1626D may use any graphics memory technology. For example, the memory devices 1626A-1626D may be graphics double data rate (GDDR) memory. The memory devices 1626A-1626D may be high bandwidth memory (HBM) modules that may be on the die with their corresponding graphics engine slices 1610A-1610D. The memory devices 1626A-1626D may be stacked memory devices that may be stacked on top of their respective graphics engine slices 1610A-1610D. Each graphics engine slice 1610A-1610D and associated memory devices 1626A-1626D may reside on separate chiplets that are bonded to a base die or substrate, such as in Figure 24B-Figure 24D As described in further detail in .

[0282] Graphics processor 1620 may be configured with a non-uniform memory access (NUMA) system in which memory devices 1626A-1626D are coupled to associated graphics engine slices 1610A-1610D. A given memory device may be accessed by a slice different from the graphics engine slice to which the memory device is directly connected. However, when accessing the local slice, access latency to memory devices 1626A-1626D may be minimized. In one embodiment, a cache-consistent NUMA (ccNUMA) system is enabled that uses slice interconnects 1623A-1623F to enable communication between cache controllers within graphics engine slices 1610A-1610D to maintain consistent memory mirroring when more than one cache stores the same memory location.

[0283] The graphics processing engine cluster 1622 may be connected to an on-chip or on-package fabric interconnect 1624. The fabric interconnect 1624 may enable communication between the graphics engine slices 1610A-1610D and components such as the video codec 1606 and one or more replica engines 1604. The replica engines 1604 may be used to move data out of memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory), move data into memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory), and move data between memory devices 1626A-1626D and memory external to the graphics processor 1620 (e.g., system memory). The fabric interconnect 1624 may also be used to interconnect the graphics engine slices 1610A-1610D. The graphics processor 1620 may optionally include a display controller 1602 to enable connection to an external display device 1618. The graphics processor may also be configured as a graphics accelerator or a computing accelerator. In an accelerator configuration, the display controller 1602 and the display device 1618 may be omitted.

[0284] Graphics processor 1620 may be connected to a host system via host interface 1628. Host interface 1628 may enable communication between graphics processor 1620, system memory, and / or system components. Host interface 1628 may be, for example, a PCIexpress bus or another type of host system interface.

[0285] Fig. 16C FIG. 16 shows a computing accelerator 1630 according to an embodiment described herein. The computing accelerator 1630 may include Fig. 16BThe computing engine cluster 1632 may include a collection 1640A-1640D of computing engine slices, which include execution logic optimized for parallel or vector-based general-purpose computing operations. The computing engine slices 1640A-1640D may not include fixed-function graphics processing logic, but in some embodiments, one or more of the computing engine slices 1640A-1640D may include logic for performing media acceleration. The computing engine slices 1640A-1640D may be connected to memory devices 1626A-1626D via memory interconnects 1625A-1625D. The memory devices 1626A-1626D and the memory interconnects 1625A-1625D may be technologies similar to those in the graphics processor 1620, or may be different technologies. The graphics compute engine slices 1640A-1640D may also be interconnected via a set of slice interconnects 1623A-1623F and may be connected to and / or interconnected by a fabric interconnect 1624. In one embodiment, the compute accelerator 1630 includes a large L3 cache 1636 that may be configured as a device-wide cache. The compute accelerator 1630 may also be configured to communicate with Fig. 16B Graphics processor 1620 in FIG. 1 is connected to a host processor and memory via host interface 1628 in a similar manner.

[0286] Graphics processing engine

[0287] Fig.17 1 is a block diagram of a graphics processing engine 1710 of a graphics processor according to some embodiments. The graphics processing engine (GPE) 1710 may be Fig.16A A version of the GPE 1610 shown in FIG. 1610 and may also represent Fig. 16B Graphics engine slices 1610A-1610D in. Fig.17 Elements with the same or similar names as elements of any other figures herein describe the same elements as in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto. For example, Fig.17 Also shown Fig.16A 1710. The 3D pipeline 1612 and the media pipeline 1616 of the GPE 1710. The media pipeline 1616 is optional in some embodiments of the GPE 1710 and may not be explicitly included in the GPE 1710. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 1710.

[0288] The GPE 1710 may be coupled to or include a command stream converter 1703 that provides a command stream to the 3D pipeline 1612 and / or the media pipeline 1616. Alternatively or additionally, the command stream converter 1703 may be directly coupled to a unified return buffer 1718. The unified return buffer 1718 may be communicatively coupled to the graphics core array 1714. Optionally, the command stream converter 1703 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. The command stream converter 1703 may receive commands from the memory and send these commands to the 3D pipeline 1612 and / or the media pipeline 1616. These commands are instructions taken from a circular buffer that stores commands for the 3D pipeline 1612 and the media pipeline 1616. The circular buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 1612 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for the 3D pipeline 1612 and / or image data and memory objects for the media pipeline 1616. The 3D pipeline 1612 and the media pipeline 1616 process commands and data by executing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 1714. The graphics core array 1714 includes blocks of one or more graphics cores (e.g., (multiple) graphics cores 1715A, (multiple) graphics cores 1715B), each block including one or more graphics cores. Each graphics core includes a collection of graphics execution resources, including: general execution logic and graphics-specific execution logic for performing graphics operations and computational operations; and fixed-function texture processing logic and / or machine learning and artificial intelligence acceleration logic.

[0289] In various embodiments, the 3D pipeline may include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 1714. The graphics core array 1714 provides a unified execution resource block for use in processing these shader programs. The multifunctional execution logic (e.g., execution unit) within the (multiple) graphics cores 1715A-1714B of the graphics core array 1714 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0290] Graphics core array 1714 may include execution logic for performing media functions such as video and / or image processing. The execution units may include general purpose logic that may be programmed to perform parallel general purpose computing operations in addition to performing graphics processing operations. The general purpose logic may be coupled to Fig.14 (multiple) processor cores 1407 or Fig.15A The general logic within cores 1502A-1502N in the performs processing operations in parallel or in combination.

[0291] Output data generated by threads executing on graphics core array 1714 may output data to memory in unified return buffer (URB) 1718. URB 1718 may store data for multiple threads. URB 1718 may be used to send data between different threads executing on graphics core array 1714. URB 1718 may additionally be used for synchronization between threads on graphics core array 1714 and fixed function logic within shared function logic 1720.

[0292] Optionally, graphics core array 1714 may be scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 1710. Execution resources may be dynamically scalable such that execution resources may be enabled or disabled as needed.

[0293] The graphics core array 1714 is coupled to shared function logic 1720, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 1720 are hardware logic units that provide specialized supplementary functions to the graphics core array 1714. In various embodiments, the shared function logic 1720 includes, but is not limited to, sampler logic 1721, math logic 1722, and inter-thread communication (ITC) logic 1723. In addition, one or more caches 1725 may be implemented within the shared function logic 1720.

[0294] Shared functionality is implemented at least in cases where the demand for a given specialized functionality is insufficient to be included in the graphics core array 1714. Instead, a single instantiation of that specialized functionality is implemented as an independent entity in shared functionality logic 1720 and shared between execution resources within the graphics core array 1714. The exact set of functionality shared between and included within the graphics core array 1714 varies from embodiment to embodiment. Specific shared functionality within shared functionality logic 1720 that is widely used by the graphics core array 1714 may be included within shared functionality logic 1716 within the graphics core array 1714. Alternatively, shared functionality logic 1716 within the graphics core array 1714 may include some or all of the logic within shared functionality logic 1720. All logic elements within shared functionality logic 1720 may be replicated within shared functionality logic 1716 of the graphics core array 1714. Alternatively, shared functionality logic 1720 is excluded in favor of shared functionality logic 1716 within the graphics core array 1714.

[0295] Execution Unit

[0296] Figure 18A-18B Thread execution logic 1800 is illustrated including an array of processing elements employed in a graphics processor core, according to embodiments described herein. Figure 18A-18B Those elements having the same or similar names as elements of any other figures herein describe the same elements in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto. Figure 18A-Figure 18A An overview of thread execution logic 1800 is shown, which may represent a Fig. 15B Schematic diagram of the hardware logic of each sub-core 1521A-1521F. Fig.18A represents an execution unit within a general-purpose graphics processor, and Fig.18B Represents an execution unit that can be used within a computing accelerator.

[0297] As in Fig.18AAs shown in , thread execution logic 1800 may include a shader processor 1802, a thread dispatcher 1804, an instruction cache 1806, a scalable execution unit array including a plurality of execution units 1808A-1808N, a sampler 1810, a shared local memory 1811, a data cache 1812, and a data port 1814. Optionally, the scalable execution unit array may be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 1808A, 1808B, 1808C, 1808D, up to 1808N-1 and 1808N) based on the computational requirements of the workload. The included components may be interconnected via an interconnect structure that links to each of the components. Thread execution logic 1800 may include one or more connections to a memory (such as system memory or cache memory) through instruction cache 1806, data port 1814, sampler 1810, and one or more of execution units 1808A-1808N. Each execution unit (e.g., 1808A) may be a self-contained programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 1808A-1808N is scalable to include any number of separate execution units.

[0298] Execution units 1808A-1808N may be primarily used to execute shader programs. Shader processor 1802 may process various shader programs and may dispatch execution threads associated with the shader programs via thread dispatcher 1804. The thread dispatcher may include logic for arbitrating thread initiation requests from graphics pipelines and media pipelines and instantiating the requested threads on one or more execution units 1808A-1808N. For example, a geometry pipeline may dispatch a vertex shader, a tessellation shader, or a geometry shader to thread execution logic for processing. Optionally, thread dispatcher 1804 may also process runtime thread generation requests from executed shader programs.

[0299] Execution units 1808A-1808N can support instruction sets including native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each execution unit in execution units 1808A-1808N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations enable efficient execution environments in the face of high latency memory accesses. Each hardware thread in each execution unit has a dedicated high-bandwidth register stack and associated independent thread states. For pipelines capable of integer operations, single-precision floating-point operations, and double-precision floating-point operations, capable of SIMD branching capabilities, capable of logical operations, capable of transcendental operations, and capable of other miscellaneous operations, execution is multi-issued for each clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 1808A-1808N causes the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during the delay associated with vertex shader operations, the execution unit can execute code for a pixel shader, a fragment shader, or a different vertex shader such as Fig.21 The operations of another type of shader program (vertex shader 2107 shown in FIG. 2 ) are described herein. Embodiments may be applied to use execution utilizing single instruction multiple threads (SIMT) as an alternative to the SIMD use case, or in addition to the SIMD use case. References to SIMD cores or operations may also apply to SIMT, or to SIMD in conjunction with SIMT.

[0300] Each execution unit in execution units 1808A-1808N operates on arrays of data elements. The number of data elements is the "execution size," or number of lanes for an instruction. An execution lane is a logical unit used for execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs), floating point units (FPUs), or other logic units (e.g., tensor cores, ray tracing cores, etc.) used for a particular graphics processor. Additionally, execution units 1808A-1808N may support integer and floating point data types.

[0301] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process each element based on the data size of the element. For example, when a 256-bit wide vector is operated, 256 bits of the vector are stored in registers, and the execution unit operates the vector as four independent 184-bit compact data elements (quad-word (QW) size data elements), eight independent 32-bit compact data elements (double-word (DW) size data elements), sixteen independent 16-bit compact data elements (data elements of word (W) size), or thirty-two independent 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0302] Optionally, one or more execution units can be combined into a fused execution unit 1809A-1809N, which has a common thread control logic (1807A-1807N) for the fused EU. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group can vary according to the embodiment. In addition, various SIMD widths can be executed EU by EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 1809A-1809N includes at least two execution units. For example, the fused execution unit 1809A includes a first EU 1808A, a second EU 1808B, and a common thread control logic 1807A for the first EU 1808A and the second EU 1808B. Thread control logic 1807A controls threads executing on fused graphics execution unit 1809A, allowing each EU within fused execution units 1809A-1809N to execute using a common instruction pointer register.

[0303] One or more internal instruction caches (e.g., 1806) are included in the thread execution logic 1800 to cache thread instructions for the execution unit. One or more data caches (e.g., 1812) may be included in the thread execution logic 1800 to cache thread data during thread execution. Threads executing on the execution logic 1800 may also store explicitly managed data in the shared local memory 1811. Samplers 1810 may be included to provide texture sampling for 3D operations and media sampling for media operations. Samplers 1810 may include specialized texture or media sampling functions to process texture data or media data during the sampling process before providing the sampled data to the execution unit.

[0304] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 1800 via thread generation and dispatch logic. Once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 1802 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). The pixel shader or fragment shader can calculate the value of each vertex attribute, and the value of each vertex attribute will be interpolated across the rasterized object. The pixel processor logic within the shader processor 1802 can then execute the pixel shader program or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 1802 dispatches the thread to the execution unit (e.g., 1808A) via the thread dispatcher 1804. The shader processor 1802 can use the texture sampling logic in the sampler 1810 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0305] In addition, the data port 1814 may provide a memory access mechanism for the thread execution logic 1800 to output processed data to memory for further processing in the graphics processor output pipeline. The data port 1814 may include or be coupled to one or more cache memories (e.g., data cache 1812) to cache data for memory access via the data port 1814.

[0306] Optionally, the execution logic 1800 may further include a ray tracer 1805 that can provide ray tracing acceleration functionality. The ray tracer 1805 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be used with Figure 3C The ray tracing instruction set supported by the ray tracing core 372 in may be similar or different.

[0307] Fig.18B1826, and a set of dedicated integer SIMDALUs. The GRF 1824 and ARF 1826 include a set of general register files and architectural register files associated with each simultaneous hardware thread that can be active in the graphics execution unit 1808. Per-thread architectural state can be maintained in the ARF 1826, while data used during thread execution is stored in the GRF 1824. The execution state of each thread, including the instruction pointer for each thread, can be maintained in thread-specific registers in the ARF 1826.

[0308] Graphics execution unit 1808 may have an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture may have a modular configuration that may be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are divided across logic for executing multiple simultaneous threads. The number of logical threads that may be executed by graphics execution unit 1808 is not limited to the number of hardware threads, and multiple logical threads may be assigned to each hardware thread.

[0309] Optionally, the graphics execution unit 1808 may issue multiple instructions in coordination, each of which may be a different instruction. The thread arbiter 1822 of the graphics execution unit thread 1808 may dispatch the instruction to one of the following for execution: the send unit 1830, the branch unit 1832, or (multiple) SIMD FPUs 1834. Each execution thread can access 128 general registers within the GRF 1824, wherein each register can store 32 bytes accessible as a SIMD 8 element vector with 32-bit data elements. Each execution unit thread may have access to 4 kilobytes within the GRF 1824, but the embodiment is not limited thereto, and more or less register resources may be provided in other embodiments. The graphics execution unit 1808 may be partitioned into seven hardware threads that can independently perform computing operations, but the number of threads of each execution unit may also vary according to the embodiment, for example, up to 16 hardware threads may be supported. In an exemplary embodiment in which seven threads can access 4 kilobytes, the GRF 1824 may store a total of 28 kilobytes. In another exemplary embodiment where 16 threads can access 4 kilobytes, GRF 1824 can store a total of 64 kilobytes. However, the number of threads per execution unit is not limited to those examples and can be greater or less than the given number. Flexible addressing modes can permit multiple registers to be addressed together, thereby creating effectively wider registers or representing strided rectangular block data structures.

[0310] Additionally or alternatively, memory operations, sampler operations, and other longer latency system communications may be dispatched via "send" instructions executed by message passing send unit 1830. Branch instructions may be dispatched to a dedicated branch unit 1832 to facilitate SIMD divergence and eventual convergence.

[0311] The graphics execution unit 1808 may include one or more SIMD floating point units (FPUs) 1834 for performing floating point operations. (Multiple) FPUs 1834 may also support integer calculations. In some instances, (multiple) FPUs 1834 may SIMD perform up to a number M of 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. Optionally, at least one of the (multiple) FPUs provides extended math capabilities that support high throughput transcendental math functions and double precision 184-bit floating points. A set 1835 of 8-bit integer SIMD ALUs may also be present and may be specifically optimized to perform operations associated with machine learning calculations.

[0312] Optionally, an array of multiple instances of graphics execution unit 1808 may be instantiated in graphics sub-core groupings (e.g., sub-slices). For scalability, product architects may choose the exact number of execution units per sub-core grouping. Execution unit 1808 may execute instructions across multiple execution lanes. Furthermore, each thread executing on graphics execution unit 1808 may be executed on a different lane.

[0313] Fig.19 A further exemplary execution unit 1900 is illustrated. Fig.19 Those elements having the same or similar names as elements of any other figures herein describe the same elements as in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere in this document, but are not limited thereto. Execution unit 1900 can be a device for, for example, Fig. 16C The execution unit 1900 may be a computationally optimized execution unit used in the computing engine slices 1640A-1640D in the embodiment of the present invention, but is not limited thereto. The execution unit 1900 may also be a computationally optimized execution unit used in the computing engine slices 1640A-1640D in the embodiment of the present invention, but is not limited thereto. Fig. 16B The execution unit 1900 may include a thread control unit 1901, a thread state unit 1902, an instruction fetch / prefetch unit 1903, and an instruction decode unit 1904. The execution unit 1900 may additionally include a register file 1906, which stores registers that can be assigned to hardware threads within the execution unit. The execution unit 1900 may additionally include a dispatch unit 1907 and a branch unit 1908. The dispatch unit 1907 and the branch unit 1908 can be used in conjunction with Fig.18B The sending unit 1830 and the branching unit 1832 of the graphics execution unit 1808 in FIG. 1 operate in a similar manner.

[0314] The execution unit 1900 may also include a computing unit 1910, which includes a plurality of functional units of different types. The computing unit 1910 may also include an ALU unit 1911, which includes an array of arithmetic logic units. The ALU unit 1911 may be configured to perform 64-bit, 32-bit, and 16-bit integer and floating-point operations. Integer and floating-point operations may be performed simultaneously. The computing unit 1910 may also include a systolic array 1912 and a mathematical unit 1913. The systolic array 1912 includes a network of width W and depth D of a data processing unit, which may be used to perform vector or other data parallel operations in a systolic manner. The systolic array 1912 may be configured to perform matrix operations, such as matrix dot product operations. The systolic array 1912 may support 16-bit floating-point operations as well as 8-bit and 4-bit integer operations. The systolic array 1912 may be configured to accelerate machine learning operations. The systolic array 1912 may be configured with support for bfloat16 (16-bit floating-point format). Math unit 1913 may be included to perform a specific subset of math operations in an efficient and lower power manner than ALU unit 1911. Math unit 1913 may include math logic found in the shared functional logic of the graphics processing engine provided by other described embodiments, for example, Fig.17 The math logic 1722 of the shared function logic 1720 in the math unit 1913 can be configured to perform 32-bit and 64-bit floating point operations.

[0315] Thread control unit 1901 includes logic for controlling the execution of threads within execution units. Thread control unit 1901 may include thread arbitration logic for starting, stopping, and preempting the execution of threads within execution unit 1900. Thread state unit 1902 may be used to store thread states for threads assigned to execute on execution unit 1900. Storing thread states in execution unit 1900 enables fast preemption of threads when they become locked or idle. Instruction fetch / prefetch unit 1903 may fetch instructions from an instruction cache of higher level execution logic (e.g., Fig.18A The instruction fetch / prefetch unit 1903 also issues prefetch requests for instructions to be loaded into the execution cache based on analysis of the current execution thread. The instruction decode unit 1904 may be used to decode instructions to be executed by the computational unit. The instruction decode unit 1904 may be used as a secondary decoder to decode complex instructions into constituent micro-operations.

[0316] Execution unit 1900 additionally includes a register file 1906 that can be used by hardware threads executing on execution unit 1900. Registers in register file 1906 can be divided across logic used to execute multiple simultaneous threads within compute unit 1910 of execution unit 1900. The number of logical threads that can be executed by graphics execution unit 1900 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 1906 can vary from embodiment to embodiment based on the number of hardware threads supported. Register renaming can be used to dynamically assign registers to hardware threads.

[0317] Fig. 20 is a block diagram illustrating a graphics processor instruction format 2000. The graphics processor execution unit supports an instruction set having instructions in a variety of formats. Solid line boxes illustrate components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. The instruction format 2000 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to microinstructions that result from instruction decoding that occurs once the instructions are processed.

[0318] As described herein, the graphics processor execution unit may natively support instructions in the 128-bit instruction format 2010. Based on the selected instructions, instruction options, and number of operands, a 64-bit compact instruction format 2030 may be used for some instructions. The native 128-bit instruction format 2010 provides access to all instruction options, while some options and operations are limited in the 64-bit format 2030. The native instructions available in the 64-bit format 2030 vary from embodiment to embodiment. The instructions are partially compressed using a set of index values ​​in the index field 2013. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions of the 128-bit instruction format 2010. Other sizes and formats of instructions may be used.

[0319] For each format, the instruction opcode 2012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. The instruction control field 2014 can enable control of certain execution options, such as channel selection (e.g., assertion) and data channel order (e.g., mixing). For instructions in the 128-bit instruction format 2010, the execution size field 2016 limits the number of data channels that will be executed in parallel. The execution size field 2016 may not be available for the 64-bit compact instruction format 2030.

[0320] Some execution unit instructions have up to three operands, including two source operands src0 2020, src1 2022, and one destination operand 2018. The execution unit may support dual destination instructions, where one of the dual destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2024), where the instruction opcode 2012 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0321] The 128-bit instruction format 2010 may include an access / addressing mode field 2026 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0322] The 128-bit instruction format 2010 may also include an access / addressing mode field 2026, which specifies the addressing mode and / or access mode of the instruction. The access mode may be used to define the data access alignment for the instruction. Access modes including 16-byte aligned access modes and 1-byte aligned access modes may be supported, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in the first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0323] The addressing mode portion of the access / addressing mode field 2026 may determine whether the instruction uses direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be calculated based on the address register value and the address immediate field in the instruction.

[0324] Instructions can be grouped based on the opcode 2012 bit fields to simplify opcode decoding 2040. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. Move and logic opcode group 2042 may include data movement and logic instructions (e.g., move (mov), compare (cmp)). Move and logic group 2042 may share five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. Flow control instruction group 2044 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). Miscellaneous instruction group 2046 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2048 includes component-by-component arithmetic instructions (e.g., add, multiply (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math group 2048 performs arithmetic operations in parallel across data channels. The vector math group 2050 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In one embodiment, the illustrated opcode decode 2040 can be used to determine which portion of the execution unit will be used to execute the decoded instructions. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown) may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0325] Graphics Pipeline

[0326] Fig.21 is a block diagram of a graphics processor 2100 according to another embodiment. Fig.21 Those elements having the same or similar names as elements of any other figures herein describe the same elements in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto.

[0327] The graphics processor 2100 may include different types of graphics processing pipelines, such as a graphics pipeline 2120, a media pipeline 2130, a display engine 2140, a thread execution logic 2150, and a rendering output pipeline 2170. The graphics processor 2100 may be a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor may be controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2100 through a ring interconnect 2102. The ring interconnect 2102 may couple the graphics processor 2100 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2102 are interpreted by a command stream converter 2103, which supplies instructions to various components of the geometry pipeline 2120 or the media pipeline 2130.

[0328] The command stream converter 2103 may direct the operation of the vertex fetcher 2105, which reads vertex data from the memory and executes the vertex processing commands provided by the command stream converter 2103. The vertex fetcher 2105 may provide the vertex data to the vertex shader 2107, which performs coordinate space transformation and lighting operations on each vertex. The vertex fetcher 2105 and the vertex shader 2107 may execute the vertex processing instructions by dispatching execution threads to the execution units 2152A-2152B via the thread dispatcher 2131.

[0329] The execution units 2152A-2152B may be arrays of vector processors with instruction sets for performing graphics operations and media operations. The execution units 2152A-2152B may have an attached L1 cache 2151 that is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0330] The geometry pipeline 2120 may include a tessellation component for performing hardware accelerated tessellation of 3D objects. The programmable shell shader 2111 may configure the tessellation operation. The programmable domain shader 2117 may provide back-end evaluation of the tessellation output. The tessellation 2113 may operate under the direction of the shell shader 2111 and include dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the geometry pipeline 2120. In addition, if tessellation is not used, the tessellation components (e.g., the shell shader 2111, the tessellation 2113, and the domain shader 2117) may be bypassed.

[0331] The complete geometric object may be processed by the geometry shader 2119 via one or more threads dispatched to the execution units 2152A-2152B, or may proceed directly to the clipper 2129. The geometry shader may operate on the entire geometric object rather than on vertices or vertex patches as in the previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 2119 receives input from the vertex shader 2107. The geometry shader 2119 may be programmable by a geometry shader program to perform geometry tessellation if the tessellation unit is disabled.

[0332] Before rasterization, the clipper 2129 processes the vertex data. The clipper 2129 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. The rasterizer and depth test component 2173 in the rendering output pipeline 2170 can dispatch a pixel shader to convert the geometric object into a pixel-by-pixel representation. The pixel shader logic can be included in the thread execution logic 2150. Optionally, the application can bypass the rasterizer and depth test component 2173 and access the unrasterized vertex data via the outflow unit 2123.

[0333] The graphics processor 2100 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the processor. In some embodiments, the execution units 2152A-2152B and associated logic units (e.g., L1 cache 2151, sampler 2154, texture cache 2158, etc.) are interconnected via data ports 2156 to perform memory accesses and communicate with the rendering output pipeline components of the processor. The sampler 2154, caches 2151, 2158, and execution units 2152A-2152B may each have a separate memory access path. Optionally, the texture cache 2158 may also be configured as a sampler cache.

[0334] The rendering output pipeline 2170 may include a rasterizer and depth test component 2173, which converts vertex-based objects into associated pixel-based representations. The rasterizer logic may include a windower / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 2178 and depth cache 2179 are also available in some embodiments. The pixel operation component 2177 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 2141, or replaced by the display controller 2143 using an overlay display plane when displayed. A shared L3 cache 2175 may be available for all graphics components, allowing data to be shared without using main system memory.

[0335] The graphics processor media pipeline 2130 may include a media engine 2137 and a video front end 2134. The video front end 2134 may receive pipeline commands from the command stream converter 2103. The media pipeline 2130 may include a separate command stream converter. The video front end 2134 may process the media commands before sending them to the media engine 2137. The media engine 2137 may include a thread generation function for generating threads for dispatching to the thread execution logic 2150 via the thread dispatcher 2131.

[0336] The graphics processor 2100 may include a display engine 2140. The display engine 2140 may be external to the processor 2100 and may be coupled to the graphics processor via a ring interconnect 2102, or some other interconnect bus or structure. The display engine 2140 may include a 2D engine 2141 and a display controller 2143. The display engine 2140 may contain dedicated logic that can operate independently of the 3D pipeline. The display controller 2143 may be coupled to a display device (not shown), which may be a system integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0337] The geometry pipeline 2120 and the media pipeline 2130 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not dedicated to any one application programming interface (API). The driver software of the graphics processor can convert API calls dedicated to a specific graphics or media library into commands that can be processed by the graphics processor. Support can be provided for the Open Graphics Library (OpenGL), the Open Computing Language (OpenCL) and / or the Vulkan graphics and computing APIs all from the Khronos Group. Support can also be provided for the Direct3D library from Microsoft. A combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If a mapping from the pipeline of a future API to the pipeline of a graphics processor can be performed, future APIs with compatible 3D pipelines will also be supported.

[0338] Graphics Pipeline Programming

[0339] Fig.22A is a diagram for a graphics processing pipeline (such as, for example, Fig.16A , Fig.17 , Fig.21 A block diagram of a graphics processor command format 2200 for programming a graphics processor pipeline (described in detail in the accompanying drawings). Fig. 22B is a block diagram illustrating a graphics processor command sequence 2210 according to an embodiment. Fig.22AThe solid-line boxes in illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.22A An exemplary graphics processor command format 2200 includes data fields for identifying the client 2202 of the command, a command operation code (opcode) 2204, and data 2206. A subopcode 2205 and a command size 2208 are also included in some commands.

[0340] Client 2202 may specify a client unit of a graphics device that processes command data. A graphics processor command parser may examine the client field of each command to adjust further processing of the command and route the command data to the appropriate client unit. A graphics processor client unit may include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit may have a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads an opcode 2204 and a subopcode 2205 (if present) to determine the operation to be performed. The client unit uses the information in data field 2206 to execute the command. For some commands, an explicit command size 2208 is expected to specify the size of the command. The command parser may automatically determine the size of at least some of the commands in the command based on the command opcode. Commands may be aligned via multiples of double words. Other command formats may also be used.

[0341] Fig. 22B 2210. The flowchart in 22220 illustrates an exemplary graphics processor command sequence. Software or firmware of a data processing system featuring an exemplary graphics processor may use a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only and is not limited to these particular commands or command sequences. Moreover, the commands may be issued as batches of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0342] The graphics processor command sequence 2210 may begin with a pipeline flush command 2212 to cause any active graphics pipeline to complete the currently pending commands for the pipeline. Optionally, the 3D pipeline 2222 and the media pipeline 2224 may not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will suspend command processing until the active drawing engine completes pending operations and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the render cache may be flushed to memory. The pipeline flush command 2212 may be used for pipeline synchronization, or before placing the graphics processor in a low power state.

[0343] When a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 2213 may be used. A pipeline select command 2213 may be required only once in an execution context before issuing pipeline commands unless the context will issue commands for both pipelines. A pipeline flush command 2212 may be required immediately before a pipeline switch via a pipeline select command 2213.

[0344] Pipeline control commands 2214 may configure the graphics pipeline for operation and may be used to program the 3D pipeline 2222 and the media pipeline 2224. Pipeline control commands 2214 may configure the pipeline state of the active pipeline. Pipeline control commands 2214 may be used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

[0345] Return buffer state commands 2216 may be used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers into which the operation writes intermediate data during processing. A graphics processor may also use one or more return buffers to store output data and perform cross-thread communication. Return buffer state 2216 may include selecting the size and number of return buffers to be used for a set of pipeline operations.

[0346] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 2220 , the command sequence is tailored for either 3D pipeline 2222 starting at 3D pipeline state 2230 , or media pipeline 2224 starting at media pipeline state 2240 .

[0347] The commands for configuring the 3D pipeline state 2230 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. If certain pipeline elements will not be used, the 3D pipeline state 2230 commands may also be able to selectively disable or bypass those elements.

[0348] 3D primitive 2232 commands can be used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2232 commands are forwarded to the vertex fetching function in the graphics pipeline. The vertex fetching function uses the 3D primitive 2232 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. The 3D primitive 2232 commands can be used to perform vertex operations on 3D primitives via vertex shaders. In order to process the vertex shader, the 3D pipeline 2222 dispatches the shader execution thread to the graphics processor execution unit.

[0349] The 3D pipeline 2222 may be triggered via an execution 2234 command or event. A register may be written to trigger command execution. Execution may be triggered via a "go" or "kick" command in a command sequence. Pipeline synchronization commands may be used to trigger command execution so that a command sequence is flushed through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is complete, the resulting geometry is rasterized and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0350] When performing media operations, the graphics processor command sequence 2210 may follow the media pipeline 2224 path. Generally, the specific purpose and manner of programming the media pipeline 2224 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be transferred to the media pipeline. The media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. The media pipeline can also include elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0351] The media pipeline 2224 can be configured in a similar manner to the 3D pipeline 2222. A set of commands for configuring the media pipeline state 2240 is dispatched or placed into the command queue, before the media object commands 2242. The commands for the media pipeline state 2240 may include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. The commands for the media pipeline state 2240 may also support the use of one or more pointers to "indirect" state elements that contain batches of state settings.

[0352] The media object command 2242 may supply a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. Optionally, all media pipeline states must be valid before issuing the media object command 2242. Once the pipeline state is configured and the media object command 2242 is queued, the media pipeline 2224 is triggered via an execute command 2244 or an equivalent execute event (e.g., a register write). The output from the media pipeline 2224 may then be post-processed by operations provided by the 3D pipeline 2222 or the media pipeline 2224. GPGPU operations may be configured and executed in a manner similar to media operations.

[0353] Graphics software architecture

[0354] Fig.23 An exemplary graphics software architecture for data processing system 2300 is illustrated. Such a software architecture may include a 3D graphics application 2310, an operating system 2320, and at least one processor 2330. Processor 2330 may include a graphics processor 2332 and one or more general-purpose processor cores 2334. Processor 2330 may be a variant of processor 1402, or any other processor in the processors described herein. Processor 2330 may be used in place of processor 1402 or any other processor in the processors described herein. Therefore, the disclosure of any features in combination with processor 1402 or any other processor in the processors described herein also discloses the corresponding combination with graphics processor 2330, but is not limited to this. In addition, Fig.23 Those elements having the same or similar names as elements of any other figures herein describe the same elements in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto. Graphics application 2310 and operating system 2320 are each executed in system memory 2350 of the data processing system.

[0355] The 3D graphics application 2310 may include one or more shader programs that include shader instructions 2312. The shader language instructions may be in a high-level shader language, such as DirectD's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application may also include executable instructions 2314 in a machine language suitable for execution by the general purpose processor core 2334. The application may also include graphics objects 2316 defined by vertex data.

[0356] The operating system 2320 may be a system from Microsoft Corporation. The operating system 2320 may be a graphics API 2322, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 2320 uses a front-end shader compiler 2324 to compile any shader instructions 2312 using HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation, or an application executable shader pre-compilation. During the compilation of the 3D graphics application 2310, a high-level shader may be compiled into a low-level shader. The shader instructions 2312 may be provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by the Vulkan API.

[0357] The user mode graphics driver 2326 may include a backend shader compiler 2327 for converting shader instructions 2312 into hardware specific representations. When the OpenGL API is in use, shader instructions 2312 in the GLSL high level language are passed to the user mode graphics driver 2326 for compilation. The user mode graphics driver 2326 may communicate with the kernel mode graphics driver 2329 using the operating system kernel mode functions 2328. The kernel mode graphics driver 2329 may communicate with the graphics processor 2332 to dispatch commands and instructions.

[0358] IP Core Implementation

[0359] One or more aspects may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0360] Fig.24A2400 can be used to manufacture integrated circuits to perform operations. The IP core development system 2400 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). The design facility 2430 can generate software simulation 2410 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 2410 can be used to design, test and verify the behavior of the IP core using a simulation model 2412. The simulation model 2412 can include functional simulation, behavioral simulation and / or timing simulation. A register transfer level (RTL) design 2415 can then be created or synthesized from the simulation model 2412. The RTL design 2415 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2415, a lower level design at the logic level or transistor level can also be created, designed or synthesized. Thus, the specific details of the initial design and simulation can be different.

[0361] The RTL design 2415 or equivalent can be further synthesized into a hardware model 2420 by the design facility, which can adopt a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored using a non-volatile memory 2440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2465. Alternatively, the IP core design can be transmitted via a wired connection 2450 or a wireless connection 2460 (e.g., via the Internet). The manufacturing facility 2465 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0362] Fig. 24BA cross-sectional side view of an integrated circuit package assembly 22470 is illustrated. The integrated circuit package assembly 2470 illustrates an implementation of one or more processors or accelerator devices as described herein. The package assembly 2470 includes a plurality of hardware logic units 2472, 2474 connected to a substrate 2480. The logic 2472, 2474 may be implemented at least in part in configurable logic or fixed-function logic hardware, and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein (multiple) processor cores, (multiple) graphics processors, or other accelerator devices. Each logic unit 2472, 2474 may be implemented within a semiconductor die and coupled to the substrate 2480 via an interconnect structure 2473. The interconnect structure 2473 may be configured to route electrical signals between the logic 2472, 2474 and the substrate 2480, and may include interconnects such as, but not limited to, bumps or pillars. The interconnect structure 2473 can be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 2472, 2474. Optionally, the substrate 2480 can be a laminate substrate based on epoxy resin. The package substrate 2480 can also include other suitable types of substrates. The package assembly 2470 can be connected to other electrical devices via the package interconnect 2483. The package interconnect 2483 can be coupled to the surface of the substrate 2480 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0363] The logic units 2472, 2474 may be electrically coupled to a bridge 2482 configured to route electrical signals between the logic 2472 and the logic 2474. The bridge 2482 may be a dense interconnect structure that provides routing for electrical signals. The bridge 2482 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic 2472 and the logic 2474.

[0364] Although two logic units 2472, 2474 and bridge 2482 are illustrated, the embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 2482 may be excluded when logic is included on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

[0365] Fig.24CThe illustrated package assembly 2490 includes a hardware logic chiplet (e.g., a base die) of multiple units connected to a substrate 2480. A graphics processing unit, parallel processor, and / or computing accelerator as described herein may be composed of various silicon chiplets manufactured separately. In this context, a chiplet is an integrated circuit that is at least partially packaged and includes different logic units that can be assembled into a larger package with other chiplets. Various collections of chiplets with different IP core logic can be assembled into a single device. In addition, active inserter technology can be used to integrate chiplets into a base die or base chiplet. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and assembled during manufacturing, which avoids the complexity of aggregating multiple IPs into the same manufacturing process, especially for large SoCs with several styles of IP. Allowing the use of multiple process technologies improves time to market and provides a cost-effective method to create multiple product SKUs. Additionally, disaggregated IP is more amenable to being independently power-gated, shutting down components that are not used on a given workload, thereby reducing overall power consumption.

[0366] The hardware logic chiplets may include dedicated hardware logic chiplets 2472, logic or I / O chiplets 2474, and / or memory chiplets 2475. The hardware logic chiplets 2472 and logic or I / O chiplets 2474 may be implemented at least in part in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplet 2475 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0367] Each chiplet may be fabricated as a separate semiconductor die and coupled to substrate 2480 via interconnect structure 2743. Interconnect structure 2473 may be configured to route electrical signals between various chiplets and logic within substrate 2480. Interconnect structure 2473 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structure 2473 may be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of logic chiplets, I / O chiplets, and memory chiplets.

[0368] Substrate 2480 may be an epoxy-based laminate substrate, however, substrate 2480 is not limited to epoxy-based laminate substrates and substrate 2480 may also include other suitable types of substrates. Package assembly 2490 may be connected to other electrical devices via package interconnect 2483. Package interconnect 2483 may be coupled to the surface of substrate 2480 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0369] The logic or I / O chiplet 2474 and the memory chiplet 2475 may be electrically coupled via a bridge 2487 configured to route electrical signals between the logic or I / O chiplet 2474 and the memory chiplet 2475. The bridge 2487 may be a dense interconnect structure that provides routing for electrical signals. The bridge 2487 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I / O chiplet 2474 and the memory chiplet 2475. The bridge 2487 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 2487 is an embedded multi-die interconnect bridge (EMIB). Alternatively, the bridge 2487 may be simply a direct connection from one chiplet to another chiplet.

[0370] The substrate 2480 may include hardware components for I / O 2491, cache memory 2492, and other hardware logic 2493. Fabric 2485 may be embedded in the substrate 2480 to enable communication between various logic chiplets within the substrate 2480 and the logic 2491, 2493. Alternatively, the I / O 2491, fabric 2485, cache, bridge, and other hardware logic 2493 may be integrated in a base die stacked on top of the substrate 2480.

[0371] In addition, the package assembly 2490 may also include a fewer or greater number of components and bridges interconnected by the structure 2485 or one or more bridges 2487. The chiplets within the package assembly 2490 can be arranged in a 3D arrangement or a 2.5D arrangement. In general, the bridge structure 2487 can be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. The structure 2485 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 2472, 2474, 2491, 2493) with other logic and / or I / O chiplets. The cache memory 2492 within the substrate can act as a global cache for the package assembly 2490, as part of a distributed global cache, or as a dedicated cache for the structure 2485.

[0372] Fig.24DA package assembly 2494 including an interchangeable chiplet 2495 is illustrated according to an embodiment. The interchangeable chiplet 2495 can be assembled into standardized sockets on one or more base chiplets 2496, 2498. The base chiplets 2496, 2498 can be coupled via a bridge interconnect 2497, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. The I / O and logic chiplets can communicate via an interconnect structure. The base chiplets can each support one or more sockets in a standardized format for logic or I / O or memory / cache.

[0373] The SRAM and power delivery circuits may be fabricated into one or more of the base chiplets 2496, 2498, which may be fabricated using a different process technology relative to the interchangeable chiplets 2495, which are stacked on top of the base chiplets. For example, the base chiplets 2496, 2498 may be fabricated using a larger process technology while the interchangeable chiplets may be fabricated using a smaller process technology. One or more of the interchangeable chiplets 2495 may be memory (e.g., DRAM) chiplets. Different memory densities may be selected for the package assembly 2494 based on power and / or performance for the product using the package assembly 2494. In addition, logic chiplets with different numbers of types of functional units may be selected at assembly time based on power and / or performance for the product. In addition, chiplets containing IP logic cores of different types may be inserted into interchangeable chiplet sockets, thereby enabling hybrid memory designs that can mix and match IP blocks of different technologies.

[0374] Exemplary System-on-Chip Integrated Circuit

[0375] Figure 25-26B An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores are shown. Other logic and circuits may be included in addition to what is shown, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores. Figure 25-26B Those elements having the same or similar names as elements of any other figures herein describe the same elements as those in the other figures, can operate or function in a manner similar to the elements in the other figures, can include the same components, and can be linked to other entities, such as those described elsewhere herein, but not limited thereto.

[0376] Fig.252 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2500 that can be manufactured using one or more IP cores. The exemplary integrated circuit 2500 includes one or more application processors 2505 (e.g., CPUs), at least one graphics processor 2510, which can be a variant of the graphics processors 1408, 1508, 2510 or any of the graphics processors described herein, and can be used to replace any of the graphics processors described. Therefore, the disclosure of any feature combined with the graphics processor herein also discloses the corresponding combination with the graphics processor 2510, but is not limited to this. The integrated circuit 2500 may additionally include an image processor 2515 and / or a video processor 2520, any of which can be a modular IP core from the same design facility or multiple different design facilities. The integrated circuit 2500 may include peripheral or bus logic, including a USB controller 2525, a UART controller 2530, a SPI / SDIO controller 2535, and an I2S / I2C controller 2540. In addition, the integrated circuit may include a display device 2545, which is coupled to one or more of a high-definition multimedia interface (HDMI) controller 2550 and a mobile industry processor interface (MIPI) display interface 2555. Storage may be provided by a flash memory subsystem 2560 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2565 to obtain access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2570.

[0377] Figure 26A-26B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. The graphics processor may be a variation of graphics processor 1408, 1508, 2510, or any other graphics processor described herein. The graphics processor may be used in place of graphics processor 1408, 1508, 2510, or any other of the graphics processors described herein. Therefore, the disclosure of any features in combination with graphics processor 1408, 1508, 2510, or any other of the graphics processors described herein also discloses features in combination with graphics processor 1408, 1508, 2510, or any other of the graphics processors described herein. Figure 26A-26B Corresponding combinations of graphics processors, but not limited to these. Fig.26A An exemplary graphics processor 2610 of a system on chip integrated circuit is illustrated that may be fabricated using one or more IP cores in accordance with an embodiment. Fig.26B An additional exemplary graphics processor 2640 is illustrated that may be fabricated using one or more IP cores of a system on a chip integrated circuit in accordance with an embodiment. Fig.26A Graphics processor 2610 is an example of a low-power graphics processor core. Fig.26BThe graphics processor 2640 of FIG. 2610 is an example of a higher performance graphics processor core. For example, as mentioned at the beginning of this paragraph, each of the graphics processors 2610 and 2640 can be Fig.25 A variant of the graphics processor 2610.

[0378] like Fig.26A As shown in , the graphics processor 2610 includes a vertex processor 2605 and one or more fragment processors 2615A-2615N (e.g., 2615A, 2615B, 2615C, 2615D, all the way to 2615N-1 and 2615N). The graphics processor 2610 can execute different shader programs via separate logic, so that the vertex processor 2605 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2615A-2615N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 2605 performs the vertex processing stage of the 3D graphics pipeline and generates primitive data and vertex data. (Multiple) fragment processors 2615A-2615N use the primitive data and vertex data generated by the vertex processor 2605 to generate a frame buffer that is displayed on the display device. The fragment processor(s) 2615A-2615N may be optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0379] The graphics processor 2610 additionally includes one or more memory management units (MMUs) 2620A-2620B, cache(s) 2625A-2625B, and circuit interconnect(s) 2630A-2630B. The one or more MMUs 2620A-2620B provide virtual to physical address mappings for the graphics processor 2610 (including for the vertex processor 2605 and / or fragment processor(s) 2615A-2615N), which may reference vertex data or image / texture data stored in memory in addition to vertex data or image / texture data stored in the one or more caches 2625A-2625B. The one or more MMUs 2620A-2620B may be synchronized with other MMUs within the system, including with other MMUs within the system, so that each processor 2505-2520 may participate in a shared or unified virtual memory system. Fig.25 One or more MMUs associated with one or more application processors 2505, image processors 2515, and / or video processors 2520. The components of graphics processor 2610 may correspond to the components of other graphics processors described herein. One or more MMUs 2620A-2620B may be associated with Figure 2C The vertex processor 2605 and the fragment processor(s) 2615A-2615N may correspond to the graphics multiprocessor 234. According to an embodiment, one or more circuit interconnects 2630A-2630B enable the graphics processor 2610 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection. The one or more circuit interconnects 2630A-2630B may be connected to the graphics multiprocessor 234. Figure 2C Further correspondence may be found between graphics processor 2610 described herein and similar components of various graphics processor architectures.

[0380] like Fig.26B As shown in FIG. , the graphics processor 2640 includes Fig.26A One or more MMUs 2620A-2620B, caches 2625A-2625B, and circuit interconnects 2630A-2630B of a graphics processor 2610. Graphics processor 2640 includes one or more shader cores 2655A-2655N (e.g., 2655A, 2655B, 2655C, 2655D, 2655E, 2655F, all the way to 2655N-1 and 2655N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary depending on the embodiment and implementation. In addition, the graphics processor 2640 includes an inter-core task manager 2645 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2655A-2655N and a tiling unit 2658 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches. The shader cores 2655A-2655N may, for example, communicate with Figure 2D The graphics multiprocessor 234 in the embodiment corresponds to, or respectively corresponds to Figure 3A and Figure 3B The graphics multiprocessors 325, 350 in the embodiment of the present invention correspond to or are Figure 3C Corresponding to the multi-core group 365A.

[0381] Embodiments described herein include software, firmware, and hardware logic that provide techniques for performing arithmetic on sparse data via systolic processing units. Embodiments described herein provide techniques for skipping computation operations for zero-filled matrices and sub-matrices. Embodiments additionally provide techniques for maintaining data compression up to the processing unit. Embodiments additionally provide an architecture for a sparsely aware logic unit.

[0382] GPGPU with tensor acceleration logic and unified memory

[0383] Fig. 27 27 is a block diagram of a data processing system 2700 according to an embodiment. The data processing system 2700 is a heterogeneous processing system having a processor 2702, a unified memory 2710, and a GPGPU 2720 including machine learning acceleration logic. The processor 2702 and the GPGPU 2720 may be any of a processor and a GPGPU / parallel processor as described herein. The processor 2702 may execute instructions for a compiler 2715 stored in a system memory 2712. The compiler 2715 is executed on the processor 2702 to compile a source code 2714A into a compiled code 2714B. The compiled code 2714B may include instructions executable by the processor 2702 and / or instructions executable by the GPGPU 2720. During compilation, the compiler 2715 may perform operations to insert metadata including hints about the level of data parallelism present in the compiled code 2714B and / or hints about data locality associated with threads to be dispatched based on the compiled code 2714B. Compiler 2715 may include the information necessary to perform such operations, or may perform these operations with the assistance of runtime library 2716. Runtime library 2716 may also assist compiler 2715 in compiling source code 2714A, and may also include instructions that are linked together with compiled code 2714B at runtime for facilitating execution of compiled instructions on GPGPU 2720.

[0384] Unified memory 2710 represents a unified address space accessible by processor 2702 and GPGPU 2720. Unified memory may include system memory 2712 and GPGPU memory 2718. GPGPU memory 2718 is memory within the address space of GPGPU 2720 and may include some or all of system memory 2712. In one embodiment, GPGPU memory 2718 may also include at least a portion of any memory dedicated to exclusive use by GPGPU 2720. In one embodiment, compiled code 2714B stored in system memory 2712 may be mapped into GPGPU memory 2718 for access by GPGPU 2720.

[0385] GPGPU 2720 includes multiple computing blocks 2724A-2724N, which may include one or more of the various computing resources described herein. The processing resources may be or include various different computing resources, such as, for example, execution units, computing units, streaming multiprocessors, graphics multiprocessors, or multi-core groups. In one embodiment, GPGPU 2720 additionally includes a tensor (e.g., matrix) accelerator 2723, which may include one or more dedicated function computing units designed to accelerate a subset of matrix operations (e.g., dot products, etc.). Tensor accelerator 2723 may also be referred to as a tensor accelerator or tensor core. In one embodiment, the logical components within tensor accelerator 2723 may be distributed across the processing resources of multiple computing blocks 2724A-2724N.

[0386] GPGPU 2720 may also include a collection of resources that may be shared by computing blocks 2724A-2724N and tensor accelerator 2723, including, but not limited to, a set of registers 2725, a power and performance module 2726, and a cache 2727. In one embodiment, registers 2725 include directly accessible and indirectly accessible registers, wherein the indirectly accessible registers are optimized for use by tensor accelerator 2723. Power and performance module 2726 may be configured to adjust power delivery and clock frequency for computing blocks 2724A-2724N so as to power gate idle components within computing blocks 2724A-2724N. In various embodiments, cache 2727 may include an instruction cache and / or a low-level data cache.

[0387] The GPGPU 2720 may additionally include an L3 data cache 2730, which may be used to cache data accessed from the unified memory 2710 by the tensor accelerator 2723 and / or computing elements within the computational blocks 2724A-2724N. In one embodiment, the L3 data cache 2730 includes a shared local memory 2732, which may be shared by the computing elements within the computational blocks 2724A-2724N and the tensor accelerator 2723.

[0388] In one embodiment, the GPGPU 2720 includes instruction handling logic, such as a fetch and decode unit 2721 and a scheduler controller 2722. The fetch and decode unit 2721 includes a fetch unit and a decode unit for fetching instructions and decoding the instructions for execution by one or more of the computational blocks 2724A-2724N or by the tensor accelerator 2723. The instructions can be dispatched to the appropriate functional units within the computational blocks 2724A-2724N or the tensor accelerator via the scheduler controller 2722. In one embodiment, the scheduler controller 2722 is an ASIC that can be configured to perform advanced scheduling operations. In one embodiment, the scheduler controller 2722 is a microcontroller or a processing core with low per-instruction energy that can execute scheduler instructions loaded from a firmware module.

[0389] In one embodiment, some functions for being performed by computing blocks 2724A-2724N can be directly scheduled or offloaded to tensor accelerator 2723. In various embodiments, tensor accelerator 2723 includes processing element logic configured to efficiently perform matrix calculation operations, such as multiplication and addition operations and dot product operations used by 3D graphics or computing shader programs. In one embodiment, tensor accelerator 2723 can be configured to accelerate operations used by machine learning frameworks. In one embodiment, tensor accelerator 2723 is an application-specific integrated circuit explicitly configured to perform a specific set of parallel matrix multiplication and / or addition operations. In one embodiment, tensor accelerator 2723 is a field programmable gate array (FPGA) that provides fixed-function logic that can be updated between workloads. The set of matrix operations that can be performed by tensor accelerator 2723 may be limited relative to the operations that can be performed by computing blocks 2724A-2724N. However, the tensor accelerator 2723 is able to perform those operations at a significantly higher throughput relative to the compute blocks 2724A-2724N.

[0390] Fig.28 Matrix operations 2805 performed by the instruction pipeline 2800 according to an embodiment are illustrated. The instruction pipeline 2800 can be configured to perform matrix operations 2805, such as but not limited to dot product operations. The dot product of two vectors is a scalar value equal to the sum of the products of the corresponding components of the vectors. The dot product can be calculated as shown in the following equation (1).

[0391]

[0392] Dot product can be used in the convolution operation of convolutional neural network (CNN). Fig.28A two-dimensional (2D) convolution using a matrix operation 2805 including a dot product operation is illustrated. Although a 2D convolution is illustrated, an N-dimensional convolution may be performed on an N-dimensional volume using an N-dimensional filter. A receptive field slice 2802 highlights a portion of an input volume in an input volume buffer 2804. The input volume buffer may be stored in a memory 2830. A dot product matrix operation 2805 may be performed between the data in the receptive field slice 2802 and the convolution filter to generate data points in an output buffer 2806, which may also be stored in the memory 2830. The memory 2830 may be any of the memories described herein, including, for example, Fig. 27 The system memory 2712, GPGPU memory 2718 or one or more cache memories 2727, 2730.

[0393] The combination of data points within the output buffer 2806 represents an activation map generated by the convolution operation. Each point within the activation map is generated by sliding a receptive field slice across the input volume buffer 2804. The activation map data may be input to an activation function to determine an output activation value. In one embodiment, the convolution of the input volume buffer 2804 may be defined within the framework as a high-level matrix operation 2905. The high-level matrix operation may be performed via primitive operations, such as basic linear algebra subroutines (BLAS) operations. Primitive operations may be accelerated via hardware instructions executed via the instruction pipeline 2800.

[0394] The instruction pipeline 2800 for accelerating hardware instructions may include: an instruction fetch and decode unit 2721, which can fetch and decode hardware instructions; and a scheduler controller 2722, which can schedule decoded instructions to one or more processing resources within the computing blocks 2724A-2724N and / or the tensor accelerator 2723. In one embodiment, the hardware instructions can be scheduled to the computing blocks 2724A-2724N and can be transferred to the tensor accelerator 2723. One or more hardware instructions and associated data for performing the matrix operation 2805 can be stored in the memory 2830. The output of the hardware instructions can also be stored in the memory 2830.

[0395] In one embodiment, the tensor accelerator 2723 may use an integrated systolic array 2808 (DP logic) to execute one or more hardware instructions to perform matrix operations 2805. The systolic array 2808 may include a combination of programmable function hardware and fixed function hardware that can be configured to perform dot product operations. Although the functional units within the computational blocks 2724A-2724N may also be configured to perform dot product operations, the systolic array 2808 may be configured to perform a limited subset of dot product operations at a significantly higher throughput relative to the computational blocks 2724A-2724N.

[0396] Figure 29A-29B Illustrated is detail of a hardware based systolic array 2808 in accordance with some embodiments. Fig.29A Illustration of a grid of multiple functional units that can be configured to perform multiple dot product operations in a single clock cycle. Fig.29B A single exemplary functional unit is shown during a systolic matrix calculation.

[0397] like Fig.29A As shown, in one embodiment, the systolic array 2808 may be configured to perform a collection of parallel dot product operations using various functional units. The dot product may be performed in a 'systolic' manner, where SIMD data is pumped across multiple layers of functional units. Fig.29A As shown, in one embodiment, the systolic array 2808 may be configured to perform a collection of parallel dot product operations using various functional units. The dot products may be performed in a 'systolic' manner, where SIMD data is pumped across multiple layers of functional units. The systolic array 2808 is a collection of functional units arranged in a grid. The grid of functional units operates in lockstep and is optimized to perform multiply-accumulate operations. The matrix to be operated on by the systolic array 2808 is divided into sub-matrices, which are pumped across the grid of functional units.

[0398] In one embodiment, the systolic array 2808 can use a configurable systolic depth to process data for a configurable number of SIMD lanes. For a given instruction, the SIMD width and systolic depth can be selected to process a set of source data. The systolic depth defines the number of systolic layers of hardware logic that will be used to process the instruction. A systolic layer is a group of multiplier and adder logic units with variable SIMD width, where a systolic layer can receive an initial accumulator value as input and generate a dot product value to output to a consecutive systolic layer or to an output register.

[0399] In some embodiments, three sources may be processed, each of which may be a vector register or an immediate value. In one embodiment, source 2900 (SRC0) may be one or more initial accumulator values, which may be a single value or a vector of accumulator values. The initial accumulator values ​​are added to a first set of dot products calculated by each functional unit within the first systolic layer. The dot products calculated by the functional units may be provided to the next systolic layer of a given SIMD channel. The dot products may be calculated based on source 2901 (SRC1) and source 2902 (SRC2), which are vector registers that may contain packed data for one or more channels, each channel containing a four-element vector. In one embodiment, each channel is 32 bits wide and provides four 8-bit vector elements. Some embodiments may be configured to calculate dot products based on input vectors having 8-bit elements, 4-bit elements, and / or 2-bit elements. In one embodiment, any combination of supported element sizes (e.g., 8-bit x2-bit, 8-bit x4-bit, 4-bit x4-bit, etc.) may be used to perform mixed precision operations. In one embodiment, the systolic array 2808 is configured for integer calculations, but in some embodiments, automatic fixed-point operations are configurable. Although the instructions described herein are four-element dot products, in some embodiments, the systolic array 2808 can also be configured to support floating-point dot product calculations for different numbers of elements per vector.

[0400] In one embodiment, a plurality of lanes of four-element vectors may be packed into a single vector register of various widths (e.g., 64 bits, 128 bits, 256 bits, 512 bits, etc.). Dot products may be computed simultaneously for vector elements of a plurality of lanes via systolic array 2808, with the vector elements of the plurality of lanes provided via source 2901 and source 2902. The number of lanes of vector elements to be processed may be configured based on the execution size and systolic depth selected for the dot product calculation. In one embodiment, multiple cycles of systolic array 2808 may be used to compute source vectors wider than the specified execution size and / or systolic depth.

[0401] The number of calculations that can be performed in a given clock cycle can vary based on the number of SIMD channels and systolic layers. As shown, the systolic array 2808 can perform a throughput of sixteen dot products per SIMD channel using a systolic depth of four. If configured for eight SIMD channels, the logic can perform 128 eight-bit integer (INT8) dot products in a given cycle. If configured for eight SIMD channels and a systolic depth of eight, each channel can perform 32 eight-bit integer (INT8) dot products, and a total of 256 dot products are performed. These specific numbers of operations are exemplary for one embodiment, and the throughput of other embodiments may vary. In addition, if the data type is different, the number of operations will be scaled based on the different data types.

[0402] At each functional unit, the dot product is calculated via multiplier and adder logic and added to an accumulator value. The resulting data may be output to a destination register or provided to an accumulator of the next systolic layer. Details of functional unit 2912 are given in Fig.29B Shown in.

[0403] like Fig.29B As shown, functional unit 2912 may include a set of input data buffers 2904, 2906 and accumulators 2922, which may each receive input data. In one embodiment, input data buffer 2906 may receive source 2902 (SRC2), which may be a compact vector of input data. Input data buffer 2904 may receive source 2901 (SRC1), which may also be a compact vector of input data. Accumulator 2922 may receive source 2900 (SRC0), which provides an initial accumulator value for functional unit 2912. The initial accumulator value is added to the dot product calculated according to the elements of source 2901 and source 2902. The dot product is calculated using a set 2923A-2923D of multipliers and adder 2924 via element-wise multiplication of source vectors. Multipliers 2923A-2923D are used to calculate a set of products. The sum of the set of products is calculated by adder 2924. The sum may be accumulated (e.g., added) with any initial value provided via source 2900. In one embodiment, the accumulated value may be provided as input value 2926 to the next accumulator, which may reside in a subsequent systolic layer. In one embodiment, source 2901 may include input data for multiple channels. Additional channels of source 2901 may be relayed as SRC1 inputs to additional SIMD channels 2928. In one embodiment, source 2902 may include input data for multiple channels. Additional channels of source 2902 may be used as SRC2 input data to logic units within additional systolic depths. In one embodiment, source 2900 may optionally include multiple channels, wherein additional channels are provided as inputs to accumulators within additional functional units. In one embodiment, source 2900 may be a single value that is added to each accumulator in each functional unit of the initial systolic layer.

[0404] Fig.30The systolic array 3000 is illustrated including a partial sum loopback and circuitry for accelerating sparse matrix multiplication. In the systolic array 2808 described above, operands including weight data may be fixed within the array, and the partial sums are propagated throughout the array structure. Although other details regarding the systolic array 2808 may be applicable, in the systolic array 3000, the partial sums are recycled rather than propagated to the next systolic layer. In one embodiment, the systolic array 3000 may be configured with M rows and N columns of processing elements (PE 3012AA-PE 3012MN). The processing elements may access registers that store input data in the form of row and column data for an input matrix. The registers may be stored in a register file local to the systolic array 3000, or in a register file of a processing resource coupled to or including the systolic array 3000. The registers may store row elements of matrix A 3002A-3002M, which are used to multiply column elements of matrix B 3001A-3002N.

[0405] In one embodiment, a fused multiply-add (FMA) may be performed at each processing element PE3012AA-PE3012MN per clock cycle. The elements of matrix A are multiplied by the corresponding elements of matrix B and then added to the accumulator value, or to an optional initial input value (e.g., SRC0) for the first cycle. Partial and loops may be configured at each processing element. After each cycle, the accumulator value may be sent back within the processing element and used as input for the next cycle. Once the operation has been performed on the entire row, the result may be stored in the register file. After a set of computation cycles, the data movement between processing elements PE3012AA-PE3012MN may vary based on the instructions or macro operations executed.

[0406] Using Compressed Data to Aware Sparsity

[0407] Embodiments described herein provide encoding arrangements that enable sample blocks of sparse neural network data to be encoded in a reduced bit form that reduces the amount of data required to be transmitted or stored when processing a neural network associated with the data. The number of non-zero values ​​in the sample block is indicated in a header, followed by an importance map indicating a map of non-zero values ​​within the block. The non-zero values ​​of the samples are encoded in the order in which they appear within the stream. In one embodiment, compression can be based on values ​​other than zero. For example, specified values ​​within a data set can be encoded and excluded from the compressed data stream, thereby achieving compression based on one, two, or other specified values. In one embodiment, compression is achieved based on proximity values. Values ​​within a data set that are within a threshold of zero, or within a threshold of a specified value, can be compressed as if those values ​​are zero or within a threshold of a specified value. Data-aware sparsity with compression can be achieved via codec logic coupled to or within matrix accelerator logic.

[0408] Figure 31A-Figure 31B The diagram includes matrix acceleration logic for implementing a codec that reads sparse data in a compressed format. Fig.31A The diagram shows a computation block 3100 including decomposed systolic logic to enable a codec. Fig.31B Illustrated are processing elements within a systolic array coupled to a codec to decompress input data.

[0409] like Fig.31A As shown, instead of Fig.28 In the example of FIG. 20 , a systolic array 2808 is included in a separate tensor accelerator 2723, or as in Fig.19 In each execution unit 1900, a systolic array 1912 is included, and a decomposed set 3112A-3112B of the systolic array can be included in a computation block 3100, and the computation block 3100 is connected to Fig. 27 The computing block 3100 may also include Fig.18A Components of the execution logic 1800 include a plurality of interconnected processing resources (PRs 3108A-3108O) that may be similar to EUs 1808A-1808N or any other processing resources described herein. In one embodiment, the systolic arrays 3112A-3112B include codecs 3124A-3124B that implement encoding and decoding of input and output data that is received for processing.

[0410] The systolic arrays 3112A-3112B include a network of data processing elements that are wide W and deep D, which can be used to perform vector or other data parallel operations in a systolic manner, similar to other systolic arrays described herein. In one embodiment, the systolic arrays 3112A-3112B can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, the systolic arrays 3112A-3112B support 16-bit floating point operations as well as 8-bit and 4-bit integer operations. In one embodiment, the systolic arrays 3112 can be configured to accelerate machine learning operations. In such embodiments, the systolic arrays 3112 can be configured with support for the bfloat 16-bit floating point format. By including the systolic arrays 3112A-3112B within the computational block 3100 but outside the PRs 3108A-3108O, the size and number of the systolic arrays 3112A-3112B can be scaled independently of the number of PRs 3108A-3108O. Furthermore, communication bandwidth within the PR that would otherwise be consumed by systolic array activity may be preserved.In addition, the systolic arrays 3112A-3112B may be clock / power gated when matrix workloads are not being executed.

[0411] Communication between the systolic arrays 3112A-3112 and the PRs 3108A-3108O may be performed via a cache or shared local memory (cache / SLM 3110) and / or a shared register file 3114. In one embodiment, instead of a separate shared register file 3114, the cache / SLM 3110 may be partitioned to serve as a shared register file. The shared register file 3114 may be constructed similarly to other GPGPU register files, such as Fig.19 The shared register file may also include a set of special registers used to configure the interaction between the systolic arrays 3112A-3112B and the PRs 3108A-3108O. The cache / SLM 3110 may be an L1 cache, an L2 cache, and / or a block of explicitly addressable on-die memory.

[0412] Matrix data for processing by the systolic arrays 3112A-3112B may be stored in the cache / SLM 3110. Processing commands or instructions may be provided to the systolic arrays 3112A-3112B via the shared register file 3114. Processing results may be read from the cache / SLM 3110 by the PRs 3108A-3108O, or may be read from destination / output registers within the shared register file. During operation, instead of consuming bus / fabric bandwidth within the PRs 3108A-3108O, communication traffic may be local to the systolic arrays 3112A-3112B, the cache / SLM 3110, and / or the shared register file 3114. Any of the PRs 3108A-3108O within the compute block 3100 may offload the matrix workload to one or both of the systolic arrays 3112A-3112B. A message with a command may be sent from the PR to the systolic array, the command specifying the operation to be performed and the operands for the operation. The systolic arrays 3112A-3112B may perform the requested operation (multiplication / addition, fused multiplication / addition, multiplication / accumulation, dot product, etc.) and output the result to the shared register file 3114. The input data, intermediate data, and / or output data of the requested operation may be stored in the cache / SLM 3110, and multiple dependent operations may be linked. In one embodiment, when processing operations for training or inference of a neural network are performed, the systolic arrays 3128A-3128B may also execute activation functions, including but not limited to sigmoid, ReLU, and hyperbolic tangent (TanH) activations. In such embodiments, operations for the neural network may be transferred to the systolic arrays 3112A-3112B at a coarse granularity.

[0413] PR 3108A-3108O can provide input data to systolic array 3112A-3112B in a compressed format, and codec 3124A-3124B can be used to decompress the data. When output data is ready to be provided to PR 3108A-3108O, if PR will perform operations on the data and does not support direct reading of compressed data, the data can remain decompressed. If PR 3108A-3108O supports reading of compressed data or will not perform additional operations on the data, the output data can be re-encoded. Zero-based encoding can be used, and compression can be enabled or disabled based on the degree of data sparsity. Alternatively, other forms of encoding can be used based on the data set to be processed or the distribution of the output. For example, codec 3124A-3124B can be configured to decode sparse data, which is encoded according to zero-based compression or using another form of compression described herein (e.g., one-based, two-based, near zero, near one, near two, etc.).

[0414] like Fig.31B As shown, system 3150 illustrates processing elements of a systolic array 3000, wherein the systolic array is configured to decode compressed sparse data. Fig.30 As described, each PE 3012AA-3013MN includes hardware logic for performing calculations for matrix operations. M ) and B(B0, B1 to B N ) is an element of an input matrix associated with a dot product, matrix multiplication, multiplication / addition, or multiply-accumulate operation. In one embodiment, each PE 3012AA-3013MN is associated with a codec (3151a, 3151b, ..., 3151m; 3152a, 3152b, ..., 3152n) to decode compressed input operands associated with the operation to be performed. The codec may be configured to decode sparse data that is encoded according to zero-based compression or using another form of compression described herein.

[0415] Sparse neural network data can be encoded (e.g., compressed) using various encoding techniques, such as, but not limited to, unique absolute value (UAV) table encoding, significance map (SM) encoding, table encoding (TE), unique value coordinate (UVC) encoding, and mean encoding (ME). Metadata for the encoded data indicates the type of encoding format used for the data. In one embodiment, a specific encoding format can be selected for a specific type of data, such as kernel data or feature data. In one embodiment, a statistical analysis is performed on the data before encoding to enable selection of an appropriate encoder for each data block. The encoding can be zero-based encoding, near-zero encoding, or based on other values ​​(one, two, etc.).

[0416] In one embodiment, data generated during SM encoding may be used to facilitate providing compressed data to a systolic tensor array. In zero-based SM encoding mode, only non-zero values ​​in a block are encoded. The number of non-zero values ​​in a block of samples is indicated in a header, followed by a significance map indicating a map of non-zero values ​​within the block. The non-zero values ​​of the samples are then encoded in the order they appear within the stream.

[0417] Figure 32A-32B Illustrated is zero-based SM encoding for sparse neural network data, according to an embodiment. Fig.32A A coding layout 3220 for zero-based SM coding is illustrated. Fig.32B Decoding of an exemplary SM-encoded bitstream is illustrated.

[0418] like Fig.32AAs shown, the coding layout 3220 enables a sample block of sparse neural network data to be encoded in a reduced bit form that reduces the amount of data required to be transmitted or stored when processing a neural network associated with the data. In the illustrated coding layout 3220, the number of non-zero values ​​in the sample block is indicated in a header 3222, followed by an importance map 3224 indicating a map of non-zero values ​​within the block. The non-zero values ​​3226 of the samples are encoded in the order in which they appear within the stream.

[0419] like Fig.32B As shown, the encoded bitstream data can be decoded based on the importance map data. In one embodiment, the SM coding mode data is presented as starting with a two-byte header followed by a third byte, where the presence of SM coding is indicated by the first bit of the bitstream header (not shown) at the beginning of the encoded data stream. The number of non-zero values ​​in the sample block is indicated in the header 3222. In one embodiment, the encoding format can be changed from sample block to sample block, so the header 3222 can also include metadata that indicates that SM coding is enabled for the upcoming sample block. The importance map 3224 indicates a map of non-zero values ​​within the sample block, where an entry of one bit is associated with each value. The non-zero values ​​3226 of the samples are then encoded in the order in which they appear within the stream. In order to decode the importance map data into an exemplary decoded bitstream 3230, the decoder logic can initialize at least a portion of the output data buffer 3210 to zero. The decoder logic can then reference the importance map 3224 to determine which values ​​in the bitstream are non-zero. The non-zero values ​​can be sequentially unpacked and written to the position indicated by the importance map in the output data buffer 3210. For example, a value of zero (0b0) in the significance map 3224 indicates that the corresponding decoded value is zero. A value of one (0b1) in the significance map 3224 indicates that the corresponding decoded value corresponds to the next consecutive entry in the non-zero values ​​3226 in the encoded bitstream.

[0420] In one embodiment, lossy near-zero encoding can be enabled, which encodes values ​​near zero as if those values ​​were zero. Although some precision is lost, this loss of precision may be acceptable in some cases for inferring data. Lossy near-zero encoding can be used as an alternative to explicit weight pruning operations, which can be used to induce sparsity within post-training data.

[0421] Figure 33A-Figure 33B Illustrated is SM encoding of specified values ​​for sparse neural network data according to an embodiment. Fig.33A Illustrated is a coding layout 3320 for SM encoding of a specified value. Fig.33B Decoding of an exemplary SM-encoded bitstream of specified values ​​is illustrated.

[0422] like Fig.33AAs shown, an encoding layout 3320 similar to encoding layout 3220 may be used, with a different header 3322 indicating that significance map encoding of the specified value is enabled, and a specified value 3323 specifying values ​​to be skipped when encoding the bitstream. Significance map 3324 identifies the location within the output buffer where the data within residual value 3326 should be unpacked.

[0423] like Fig.33B As shown, you can press Fig.32B 3324. The encoded bitstream data is decoded based on the significance map data in a similar manner as in . The header 3322 includes a bit field that specifies that the significance map of the specified value is enabled. The specified value 3323 identifies the value that will be skipped by the significance map 3324. The number of residual values ​​3326 in the sample block is indicated in the header 3322. In one embodiment, the encoding format can change from sample block to sample block, so the header 3322 can also include metadata that indicates that SM encoding of the specified value is enabled for the upcoming sample block and specifies the specified value 3323 to be used. The significance map 3324 indicates a map of residual values ​​within the sample block, where an entry of one bit is associated with each residual value. The residual values ​​3326 of the samples are then encoded in the order in which they appear within the stream. In order to decode the significance map data of the specified value into the exemplary decoded bitstream 3330, the decoder logic can initialize at least a portion of the output data buffer 3310 to the specified value 3323. The decoder logic can then reference the significance map 3324 to determine which values ​​in the bitstream are residuals. The residual values ​​may be sequentially unpacked and written to the locations indicated by the significance map in the output data buffer 3310. For example, a value of zero (0b0) in the significance map 3324 indicates that the corresponding decoded value is the specified value 3323. A value of one (0b1) in the significance map 3324 indicates that the corresponding decoded value corresponds to the next consecutive entry in the residual values ​​3226 in the encoded bitstream.

[0424] In one embodiment, lossy specified value encoding can be enabled, which encodes values ​​close to the specified value as if those values ​​are equal to the specified value. Although some precision is lost, this loss of precision may be acceptable in some cases for inferring data.

[0425] By using the above techniques, a person skilled in the art can implement, for example, a general-purpose graphics processing unit including a matrix accelerator configured to accelerate sparse matrix operations. The matrix accelerator may include a hardware decoder for decoding input data including a plurality of matrix elements. The input data may be received in a compressed format, and the input data may be decoded by the hardware decoder before being processed by the matrix accelerator. In one embodiment, the matrix accelerator includes a plurality of processing elements, which in one embodiment are configured as a systolic array. The plurality of processing elements of the systolic array may include a decoder for decoding the input data processing element by processing element, or for decoding the input data for a group of processing elements less than the entire systolic array.

[0426] In one embodiment, data is received in a compressed format, the data being encoded according to zero-based compression. In one embodiment, the compressed data is encoded in a near-zero format, values ​​within a threshold of zero are set to a zero value according to the near-zero format. In one embodiment, data is received in a compressed format, the data being encoded based on a specified value compression. In one embodiment, the compressed data is encoded in a near-specified value format, values ​​within a threshold specified value are set to a specified value according to the near-specified value format.

[0427] Block sparse dot product operation

[0428] Various techniques are applied in the field of deep neural networks (DNNs) to improve computational speed and / or efficiency while maintaining acceptable accuracy results. It has been determined that for some types of DNN models, the computational precision of operations can be reduced without significantly reducing the accuracy of the model. In addition to reducing computational precision, for example, by using 16-bit floating point values ​​instead of 36-bit floating point values ​​for training or using integer values ​​to perform inference operations, training techniques can also be adapted to introduce sparsity into weight values ​​associated with DNN models. Sparsity refers to the proportion of weights with zero values ​​of a DNN. Higher sparsity corresponds to fewer weights, which results in smaller computational and storage requirements. For zero-valued weights, any multiplication performed using those weights can be bypassed, and a sparse matrix format can be used to compactly store and transmit the model. Empirical results show that DNNs can tolerate high levels of sparsity and minimal or acceptable reductions in accuracy. In view of this trend, it would be beneficial to adjust GPGPU and parallel processor hardware for performing training and inference operations of DNN models.

[0429] Figure 34A-Figure 34B Illustration of a comparison between unstructured sparsity and block sparsity within training data for a neural network. Fig.34A Figure 3. Comparison between unstructured sparsity and block sparsity. Fig.34B Illustration of block pruning of weights for a neural network.

[0430] like Fig.34A As shown, sparsity in a DNN model can take the form of irregular sparsity as in matrix 3402, or in the form of block sparsity as in matrix 3404. Irregular sparsity as in matrix 3402 can occur naturally during training, or pruning techniques can be applied to zero weight values ​​below a minimum threshold. Block sparsity as in matrix 3404 can be generated by pruning block by block. Block sizes can be defined, and blocks below a minimum absolute size can be pruned.

[0431] like Fig.34B As shown, weight pruning can be performed after the DNN model is trained by summing the weight values ​​within the block and setting all weights in the block to zero if the absolute size of the weight is below a threshold. The matrix 3412 can be pruned into a block sparse matrix 3414 by using, for example, a weight threshold of 0.4 and a 4x4 block. For each 4x4 block, the weights in the block can be summed, and any block with an absolute size below the threshold can have its weights set to zero. Matrix multiplication operations involving those blocks can be bypassed during inference.

[0432] In one embodiment, block sparse operations on a systolic array can be optimized by enabling block sparse macroinstructions to perform dot product operations on block sparse data. In response to receiving a block sparse macroinstruction (dpXaV), a sequence of dot product instructions (dp4a, dp2a) can be generated inside the GPGPU. In one embodiment, a bit field is generated that indicates the degree of sparsity of the rows of matrix A to be provided as input to the block sparse macroinstruction. The macroinstruction can use the bit field to automatically generate a set of instructions and operands to perform continuous dot product operations on the elements of the matrix. The dot product instruction can be used to generate a scalar product of the row elements of matrix A and the column elements of matrix B. In the case where all input values ​​of matrix A for the instruction will be zero, the dot product instruction for the row can be skipped. Because the result will be zero. When one or more matrix A elements to be processed but not all elements are zero, the predicate mask can be used to disable multiplication of specific zero-valued elements.

[0433] Figure 35A-Figure 35B A dot product instruction 3500 is shown that may be performed by the dot product logic. Fig.35A Illustrated are fields of a four-element dot product with accumulate instruction that may be executed by systolic matrix logic provided by an embodiment. Fig.35B Illustration of element-wise computations performed during the computation of a four-element dot product with accumulation using systolic matrix logic.

[0434] like Fig.35AAs shown, a four-element dot product with accumulation instruction 3500 may be used to cause a systolic matrix accelerator to perform a four-element dot product with accumulation. In one embodiment, instruction 3500 includes a predicate field 3502, an opcode field 3504, a conditional modifier field 3506, an execution size field 3508, and an operand field for specifying a destination 3510, a zeroth source 3512 (src0), a first source 3514 (src1), a second source 3516 (src2), and a systolic depth 3518 (sdepth). Predicate field 3502 may specify, for example, Fig.35B Assertion mask 3562 in . Turn to Fig.35B , the assertion mask can be used to enable or disable the execution channel of the instruction so that the output generation for a particular element is disabled. In various embodiments, the disabled channel can bypass execution, or can be executed while preventing the execution logic from modifying the architectural state associated with the disabled channel. In one embodiment, the output of the execution can be discarded without being committed. When all elements of the assertion mask 3562 are zero, all operations of the instruction can be bypassed. When the dp4aV vector instruction is being used to generate multiple dp4as instructions, the generation of the dp4as instruction can be bypassed when the assertion mask 3562 is zero.

[0435] Back to Fig.35A , the opcode field 3504 may specify an opcode that identifies the instruction 3500 to the execution logic. In one embodiment, the opcode field 3504 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., tensor accelerator 2723) as described herein. In one embodiment, the opcode field 3504 may also include one or more bits that specify that the instruction 3500 is to be executed by dedicated dot product logic, such as dot product logic within the matrix accelerator (e.g., dot product logic 1608).

[0436] The condition modifier field 3506 may be used to set a flag register based on an internal condition signal output from the execution pipeline, such as a sign, zero, overflow, non-number (NaN), etc. If this field is set to 0000, no flag register is updated. In one embodiment, the supported conditions include, but are not limited to, the following: zero or equal, non-zero or not equal, greater than, greater than or equal to, less than, less than or equal to, overflow, and unordered and calculated NaN. In addition, in some configurations, the source modifier field may be enabled.

[0437] Execution size 3508 (exec_size) specifies the number of execution lanes for instruction 3500. In the case of a four-element dot product instruction, in one embodiment, the number of execution lanes may be used to specify the number of pairs of four-element vectors on which the calculation is to be performed.

[0438] The destination 3510, the zeroth source 3512 (src0), the first source 3514 (src1), and the second source 3516 (src2) may be used to specify a destination to which computations are written and a location from which source data may be retrieved. In one embodiment, the destination 3510 may specify a register to which data is to be written. In one embodiment, the destination 3510 may be a scalar register, but in some embodiments, the destination may also be a vector register that stores outputs from multiple channels. For example, where a single four-element channel is specified, a single dot product may be written to a single output channel at the destination. Where multiple four-element channels are specified, multiple dot products may be written to vector destination registers. The zeroth source 3512, the first source 3514, and the second source 3516 may be registers or immediate values ​​comprising source data for one or more channels, each channel having four elements to be processed by the dot product logic, such as Figure 29A-29B In one embodiment, the four elements of each source can be provided to the source 2900, source 2901 and source 2902. Fig.30 3518. The systolic depth 3518 (sdepth) may be used to specify the number of systolic layers used to process the input data. In one embodiment, the systolic depth 3518 may be provided as an immediate value.

[0439] In some embodiments, there may be additional fields different from those shown. For example, in one embodiment, there is a source modifier field that specifies the value modification of the source operand. Before being passed to the execution pipeline, the value of each data element of the source operand can optionally have its absolute value taken and / or its sign reversed. The absolute value modifier can be applied before the negation modifier so that a necessary negative value can be generated. In one embodiment, there is a saturation field that can be used to control the destination saturation. When saturation is enabled, the output data going to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is the operation of converting any data outside the saturation target range of the data type to the closest representation value within the target range.

[0440] exist Fig.35B 3500. In one embodiment, a hardware buffer, temporary register, or internal register of a functional unit within the dot product logic of a systolic matrix accelerator may store elements A3-A0 of lane 3524 of a first source 3514. An additional hardware buffer or temporary register may store elements B3-B0 of lane 3526 of a second source 3516. Elements may be loaded into a functional unit (e.g., Fig.29A The functional unit 2912). A collection of multipliers (e.g., Fig.29BThe multipliers 2923A-2923D) can generate a set of products 3534. The set of products can be loaded into an adder (e.g., Fig.29B in adder 2924).

[0441] The adder may generate a sum of the set of products 3535, which may be accumulated with an existing accumulator value 3522 (e.g., C0). The existing accumulator value 3522 may be an initial accumulator value provided via instruction 3500, or may be an accumulator value provided by a previous systolic layer. The accumulated sum of the set of products 3535 may then be output to a destination 3538, which may be the destination 3510 specified by instruction 3500, or the accumulated sum 3535 may be loaded as an initial accumulator value 3536 for the next systolic layer. The destination for the accumulated sum output by a systolic layer may be determined based on whether the given systolic layer is the last layer in a chain, where the number of layers is specified by the systolic depth.

[0442] Figure 36A-36B Illustrated are instructions 3600 that may be executed by dot product logic according to embodiments described herein. Fig.36A Illustrated are fields of a two-element dot product instruction with accumulate that may be executed by systolic matrix logic provided by an embodiment. Fig.36B Illustration of element-wise computations performed during the computation of a two-element dot product with accumulation using systolic matrix logic.

[0443] Fig.36A The fields of a two-element dot product with accumulation instruction 3600 are illustrated, which, when executed, causes the systolic matrix accelerator to perform a two-element dot product with accumulation. In one embodiment, instruction 3600 includes a predicate field 3602, an opcode field 3604, a conditional modifier field 3606, an execution size field 3608, and operand fields for specifying a destination 3610, a zeroth source 3612 (src0), a first source 3614 (src1), a second source 3616 (src2), and a systolic depth 3618 (sdepth). Each of the fields shown may be similar to those of instruction 3500, except that opcode field 3604 specifies a two-element dot product, and each operand specifies a vector having two packed elements instead of four packed elements.

[0444] Assertion field 3602 can specify Fig.36B Assertion mask 3662. Turn to Fig.36B, the assertion mask 3662 may be used to enable or disable the execution path of the instruction so that output generation for a particular element is disabled, as with the assertion field 3502 and the assertion mask 3562. The assertion mask 3662 shown indicates that element A0 is non-zero, while element A1 is zero. For this set of matrix A inputs, instructions may be generated to perform a dot product operation and multiply A0 of input channel 3624 by B0 of channel 3626. A set 3634 of products including only A0*B0 may be generated, which may then be multiplied with the existing accumulator value 3622 (e.g., C0). The accumulated sum 3635 of the set of products may then be output to a destination 3638, which may be the destination 3610 specified by the instruction 3600, or the accumulated sum 3635 may be loaded as the initial accumulator value 3636 for the next systolic layer. The destination for the accumulated sum output by a systolic layer may be determined based on whether the given systolic layer is the last layer in a chain, where the layer number is specified by the systolic depth.

[0445] Figure 37A-Figure 37D Illustrated are instructions and associated hardware logic for implementing a sparse dot product operation with zero skipping for...

Claims

1. A general-purpose graphics processor, comprising: A computing cluster comprising a plurality of processing resources coupled to a cache memory, at least one of the processing resources comprising a matrix accelerator, the matrix accelerator configured to perform a dot product operation on a plurality of elements of a first sparse matrix and a second matrix in response to a sparse dot product instruction, wherein the first sparse matrix has a structured sparsity in which elements are pruned, the elements of the first sparse matrix are compacted to a compressed representation comprising a set of elements based on the structured sparsity, the set of elements comprising at least one non-zero valued element and an indication of the at least one non-zero valued element; wherein the compressed representation is to be stored in the cache memory in a compressed format; and Wherein, the at least one processing resource is configured as: loading the compressed representation from the cache memory into a memory within the at least one processing resource; loading the second matrix from the cache memory into the memory within the at least one processing resource; performing the dot product operation on elements from the compressed representation and corresponding elements of the second matrix and skipping computations associated with zero-valued elements of the first sparse matrix, wherein the corresponding elements of the second matrix correspond to non-zero values ​​of the first sparse matrix stored in the compressed representation, wherein the memory within the at least one processing resource comprises a register file; and An output of the dot product operation is written to the memory within the at least one processing resource.

2. The general purpose graphics processor according to claim 1, wherein: The cache memory is a second level L2 cache memory.

3. The general purpose graphics processor according to claim 1, wherein: The memory within the at least one processing resource includes a first level L1 cache memory.

4. The general purpose graphics processor according to claim 1, wherein: The memory within the at least one processing resource comprises shared memory.

5. The general purpose graphics processor according to claim 1, wherein: The memory within the at least one processing resource includes memory within the matrix accelerator.

6. The general purpose graphics processor according to claim 1, wherein: The first sparse matrix includes weight data associated with a neural network.

7. The general purpose graphics processor according to claim 6, wherein: The second matrix includes input activation data associated with the neural network.

8. The general purpose graphics processor according to claim 7, wherein: The output of the dot product operation includes output activation data associated with the neural network.

9. The general purpose graphics processor according to claim 8, wherein: The output of the dot product operation is a dense matrix.

10. The general purpose graphics processor according to claim 1, wherein: The matrix accelerator includes a systolic array of processing elements.

11. The general purpose graphics processor according to claim 1, wherein: The dot product operation is an 8-bit integer dot product operation.

12. The general purpose graphics processor according to claim 11, wherein: The first sparse matrix includes 8-bit integer elements.

13. A data processing system comprising: Memory devices; as well as A general purpose graphics processor as claimed in any one of claims 1 to 12.

14. A method for data processing, comprising: performing a dot product operation on a plurality of elements of a first sparse matrix and a second matrix in response to a sparse dot product instruction, the dot product operation being performed via a computing cluster, the computing cluster comprising a plurality of processing resources coupled to a cache memory, at least one processing resource comprising a matrix accelerator, wherein the first sparse matrix has a structured sparsity in which elements are pruned, the elements of the first sparse matrix are compacted to a compressed representation comprising a set of elements based on the structured sparsity, the set of elements comprising at least one non-zero valued element and an indication of the at least one non-zero valued element; storing the compressed representation in a compressed format in the cache memory; and via the at least one processing resource: loading the compressed representation from the cache memory into a memory within the at least one processing resource; loading the second matrix from the cache memory into the memory within the at least one processing resource; performing the dot product operation on elements from the compressed representation and corresponding elements of the second matrix and skipping computations associated with zero-valued elements of the first sparse matrix, wherein the corresponding elements of the second matrix correspond to non-zero values ​​of the first sparse matrix stored in the compressed representation, wherein the memory within the at least one processing resource comprises a register file; and An output of the dot product operation is written to the memory within the at least one processing resource.

15. The method of claim 14, wherein: The method further includes packing elements of the first sparse matrix into the compressed representation within a memory of the at least one processing resource.

16. The method of claim 14, wherein: Performing a dot product operation includes performing an 8-bit integer dot product operation.

17. The method of claim 16, wherein: The first sparse matrix includes 8-bit integer elements.

18. A machine-readable medium storing code which, when executed, causes a machine to perform the method of any one of claims 14 to 17.

19. An apparatus for data processing, comprising means for executing the method as claimed in any one of claims 14 to 17.

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