Self-correcting SoC

Abstract

The present invention provides a self-correcting system-on-a-chip, comprising a semiconductor substrate, at least one silicon intellectual property circuit including a plurality of dynamic random access memories, a correction circuit and a functional circuit, a cyclic oscillator and a control circuit. Each dynamic random access memory has a coarse adjustment capacitance value and a coarse adjustment resistance value, and the correction circuit has a fine adjustment capacitance value and a fine adjustment resistance value. The cyclic oscillator transmits an oscillation clock signal to the control circuit to select the coarse adjustment capacitance value, the coarse adjustment resistance value, the fine adjustment capacitance value and the fine adjustment resistance value, and provides the same to the functional circuit to adjust the functional parameters. The present invention utilizes the larger capacitance value and resistance value of the dynamic random access memory in combination with the smaller capacitance value and resistance value to increase the circuit operation range and reduce the required chip area.

Description

Technical Field

[0001] The invention relates to a system on a chip, in particular to a self-correcting system on a chip. Background Art

[0002] When making chips, each chip will often have a process drift effect due to different wafers or wafer positions. Therefore, analog circuit design and RF circuit design often include a large number of resistors, capacitors and inductors. In order to avoid process variation, various correction mechanisms are added to each Silicon Intellectual Property (SIP) design. The most common is to use resistors and capacitors to increase the circuit operating range. When the circuit characteristics drift, they can still be adjusted back to the original characteristics through the calibration mechanism.

[0003] For example, in a radio frequency identification (RFID) system, a reader uses its own antenna to send out a modulated signal, and a signal receiver uses an antenna with the same resonant frequency as the reader's antenna to receive and demodulate the modulated signal. However, due to the errors in the inductance and capacitance values ​​of the signal receiver, there is usually an error between the resonant frequency of the signal receiver's antenna and the resonant frequency of the reader's antenna, resulting in a shorter operating distance of the RFID system. Therefore, it is difficult for the designer of the signal receiver to design a signal receiver that works well when faced with process drift of the integrated circuit. However, the design of resistors and capacitors will use a lot of chip area and increase the manufacturing cost, so how to reduce costs while maintaining the proper circuit performance will become an important issue. Summary of the invention

[0004] The main purpose of the present invention is to provide a self-correcting system single chip that utilizes the larger and smaller area capacitor and resistor values ​​of a dynamic random access memory in combination with smaller capacitor and resistor values ​​to avoid process drift problems, increase the circuit operating range, and reduce the required chip area.

[0005] To achieve the above-mentioned purpose, the present invention provides a self-correcting system-on-chip, comprising a semiconductor substrate, at least one silicon intellectual property (SIP) circuit including a plurality of dynamic random access memories, a correction circuit and a functional circuit, a cyclic oscillator and a control circuit. All dynamic random access memories are arranged on the semiconductor substrate, and each dynamic random access memory has a coarse adjustment capacitance value and a coarse adjustment resistance value. The correction circuit is arranged on the semiconductor substrate, and the correction circuit has a plurality of fine adjustment capacitance values ​​and a plurality of fine adjustment resistance values. The functional circuit is arranged on the semiconductor substrate and electrically connects all dynamic random access memories and the correction circuit, and the functional circuit has a functional parameter. The cyclic oscillator is arranged on the semiconductor substrate, and the cyclic oscillator generates an oscillation clock signal within a preset time period. The control circuit is arranged on the semiconductor substrate, and electrically connects the cyclic oscillator, all dynamic random access memories and the correction circuit, and the control circuit receives the oscillation clock signal and calculates the number of pulses of the oscillation clock signal. When the number of pulses is greater than or less than a preset value, the control circuit controls all dynamic random access memories and correction circuits to select coarse adjustment capacitance value, coarse adjustment resistance value, fine adjustment capacitance value and fine adjustment resistance value according to the number of pulses and the preset value, and provides them to the functional circuit. The functional circuit adjusts the functional parameters according to the selected coarse adjustment capacitance value, coarse adjustment resistance value, fine adjustment capacitance value and fine adjustment resistance value.

[0006] In one embodiment of the present invention, each dynamic random access memory further includes a vertical resistor, a first transistor switch and a vertical capacitor. The vertical resistor is arranged on the semiconductor substrate, and the vertical resistor has a coarse adjustment resistance value. The first transistor switch is arranged on the semiconductor substrate, and the first transistor switch has a first control electrode, a first connection electrode and a second connection electrode, the first connection electrode is electrically connected to the functional circuit through the vertical resistor, and the first control electrode is electrically connected to the control circuit. The vertical capacitor is arranged on the semiconductor substrate and electrically connected to the second connection electrode and a voltage terminal, and the vertical capacitor has a coarse adjustment capacitance value. When the control circuit turns on the first transistor switch, the functional circuit adjusts the functional parameters according to the coarse adjustment resistance value of the vertical resistor and the coarse adjustment capacitance value of the vertical capacitor.

[0007] In one embodiment of the present invention, the correction circuit further includes a plurality of correctors, which are disposed on a semiconductor substrate, all correctors respectively have all fine-tuning capacitance values, and respectively have all fine-tuning resistance values, and all correctors are electrically connected to the control circuit and the functional circuit. When the number of pulses is greater than or less than a preset value, the control circuit controls all correctors to select fine-tuning capacitance values ​​and fine-tuning resistance values ​​according to the number of pulses and the preset value.

[0008] In one embodiment of the present invention, each corrector further includes a second transistor switch, a horizontal resistor and a horizontal capacitor. The second transistor switch is arranged on the semiconductor substrate, and the second transistor switch has a second control electrode, a third connection electrode and a fourth connection electrode. The second control electrode is electrically connected to the control circuit, and the third connection electrode is electrically connected to the functional circuit. The horizontal resistor and the horizontal capacitor are arranged on the semiconductor substrate, the horizontal resistor has a fine-tuning resistance value, the horizontal capacitor has a fine-tuning capacitance value, the horizontal resistor is connected to a voltage terminal, and is electrically connected in series with the horizontal capacitor, and the horizontal capacitor is electrically connected to the fourth connection electrode of the second transistor switch. When the control circuit turns on the second transistor switch, the functional circuit adjusts the functional parameters according to the fine-tuning resistance value of the horizontal resistor and the fine-tuning capacitance value of the horizontal capacitor.

[0009] In one embodiment of the present invention, the control circuit further includes a counter and a decoder. The counter is disposed on the semiconductor substrate, the counter is electrically connected to the cyclic oscillator, the counter receives the oscillation clock signal, and within a preset period, the counter counts the number of pulses according to the rising edge or the falling edge of the pulse to generate a set of digital values. The decoder is disposed on the semiconductor substrate, the decoder is electrically connected to the counter, all dynamic random access memories and the correction circuit, the decoder receives the set of digital values, and controls all dynamic random access memories and the correction circuit to select the coarse adjustment capacitor value, the coarse adjustment resistor value, the fine adjustment capacitor value and the fine adjustment resistor value according to the preset value, and provides the same to the functional circuit.

[0010] In one embodiment of the present invention, the counter is a shift register. In one embodiment of the present invention, the cyclic oscillator further receives a reference clock signal, the preset period is the period of the reference clock signal, and the oscillation frequency is greater than the reference frequency of the reference clock signal.

[0011] In one embodiment of the present invention, the cyclic oscillator is further electrically connected to a quartz crystal oscillator, and the quartz crystal oscillator generates a reference clock signal.

[0012] In one embodiment of the present invention, when the number of pulses is less than a preset value, the control circuit and the functional circuit reduce the functional parameters, and when the number of pulses is greater than the preset value, the control circuit and the functional circuit increase the functional parameters.

[0013] In one embodiment of the present invention, the coarse adjustment capacitance value and the coarse adjustment resistance value form a first time constant, the fine adjustment capacitance value and the fine adjustment resistance value form a second time constant, and the value of the first time constant divided by the second time constant is greater than or equal to 10.

[0014] In one embodiment of the present invention, the functional circuit is an analog circuit, a radio frequency circuit, a digital circuit, a processor, a static random access memory or a flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 A structural cross-sectional view of an embodiment of a self-correcting system-on-a-chip of the present invention;

[0017] Figure 2 A circuit diagram of an embodiment of a self-correcting system-on-a-chip of the present invention;

[0018] Figure 3 A waveform diagram of the oscillation clock signal and the reference clock signal of the present invention;

[0019] Explanation of symbols:

[0020] 10. semiconductor substrate, 12. dynamic random access memory, 13. correction circuit, 14. functional circuit, 15. silicon intellectual property circuit, 16. cyclic oscillator, 18. control circuit, 22. quartz crystal oscillator, 24. first transistor switch, 26. vertical resistor, 28. vertical capacitor, 30. insulating layer, 32. first conductive through hole, 34. second conductive through hole, 36. third conductive through hole, 37. corrector, 38. second transistor switch, 40. horizontal resistor, 42. horizontal capacitor, 44. counter, 46. decoder. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] When an element is referred to as being "on...", it can generally refer to the element being directly on other elements, or there being other elements between the two. Conversely, when an element is referred to as being "directly on" another element, there cannot be other elements between the two. As used herein, the term "and / or" includes any combination of one or more of the listed associated items.

[0024] The description of "one embodiment" or "an embodiment" below refers to a setting element, structure or feature associated with at least one embodiment. Therefore, multiple descriptions of "one embodiment" or "an embodiment" appearing in multiple places below do not refer to the same embodiment. Furthermore, the setting components, structures and features in one or more embodiments can be combined in an appropriate manner.

[0025] Please see below Figure 1 , Figure 2 and Figure 3 , and introduces an embodiment of the self-correcting system on a chip (System on a Chip, Soc) of the present invention. In this embodiment, the self-correcting system on a chip includes a semiconductor substrate 10, at least one Silicon Intellectual Property (SIP) circuit 15 including a plurality of dynamic random access memories 12, a correction circuit 13 and a functional circuit 14, a cyclic oscillator 16 and a control circuit 18. The number of the Silicon Intellectual Property circuits 15 can be multiple, and each Silicon Intellectual Property circuit 15 includes a plurality of dynamic random access memories 12, a correction circuit 13 and a functional circuit 14. In this embodiment, the number of the Silicon Intellectual Property circuit 15 is taken as one, which can be an analog circuit, a radio frequency circuit, a digital circuit, a processor, a static random access memory or a flash memory, and the cyclic oscillator 16 can be a ring oscillator, but the present invention is not limited thereto. Specifically, the input / output ports (I / O ports), the silicon intellectual property circuit 15 including all dynamic random access memories 12, the correction circuit 13 and the functional circuit 14, the cyclic oscillator 16 and the control circuit 18 are all located on the same semiconductor substrate 10. In the system-level package (SiP), the dies with different functions are mainly packaged in the same package to increase the unavoidable parasitic spurious effects and reduce the performance, and the manufacturing cost is also higher. In addition, in the system-level package, each silicon intellectual property (Silicon Intellectual Property, SIP) circuit has tens of thousands of internal signal lines, but due to the limitation of the size of the die, the number of input / output ports (I / O ports) is often not large, so when data is transmitted from one die to another, the data transmission speed is low and the power consumption is high. Different from the system-level package, the present invention integrates all silicon intellectual property circuits in the same die, which can avoid spurious effects, is not limited by the number of input / output ports, and the number of buses in the die is not limited. Compared to system-level packaging, system-on-chips only need to use the system bus to communicate with each other. The data transmission speed of the system-on-chip is higher, the power consumption is lower, and the transmission bandwidth can be directly designed according to demand, thereby improving overall efficiency.

[0026] Each dynamic random access memory 12 has a coarse tuning capacitance value and a coarse tuning resistance value. The correction circuit 13 has a plurality of fine tuning capacitance values ​​and a plurality of fine tuning resistance values, wherein the coarse tuning capacitance value is greater than the fine tuning capacitance value, and the coarse tuning resistance value is greater than the fine tuning resistance value. For example, the coarse tuning capacitance value and the coarse tuning resistance value form a first time constant, and the fine tuning capacitance value and the fine tuning resistance value form a second time constant, and the value of the first time constant divided by the second time constant is greater than or equal to 10. The functional circuit 14 electrically connects all dynamic random access memories 12 and the correction circuit 13, and the functional circuit 14 has a functional parameter. The cyclic oscillator 16 generates an oscillation clock signal Co within a preset time period, wherein the oscillation frequency of the oscillation clock signal Co will change due to the process drift of the single chip. The control circuit 18 is electrically connected to the cyclic oscillator 16, all dynamic random access memories 12 and the correction circuit 13. The control circuit 18 receives the oscillation clock signal Co and calculates the number of pulses of the oscillation clock signal Co. When the number of pulses is greater than or less than a preset value, the control circuit 18 controls all dynamic random access memories 12 and the correction circuit 13 to select a coarse adjustment capacitor value, a coarse adjustment resistor value, a fine adjustment capacitor value and a fine adjustment resistor value according to the number of pulses and the preset value, and provides this to the functional circuit 14. The functional circuit 14 adjusts the functional parameters according to the selected coarse adjustment capacitor value, coarse adjustment resistor value, fine adjustment capacitor value and fine adjustment resistor value. Specifically, when the number of pulses is less than the preset value, the control circuit 18 and the functional circuit 14 reduce the functional parameters. When the number of pulses is greater than the preset value, the control circuit 18 and the functional circuit 14 increase the functional parameters. The preset value can be used as a standard for judging whether a single wafer has process drift. As long as the number of pulses is different from the preset value, it means that the problem of process drift exists, and the number of pulses is used to quantify the degree of process drift. The preset value can be written externally into the control circuit 18 as a backup mechanism to prevent the self-correction amount from being insufficient and still be adjusted to the optimal state at any time. The present invention adjusts the functional parameters according to the preset value to avoid the problem of inaccurate signals generated by the functional circuit 14 due to process drift.

[0027] The preset time period can be built into the cyclic oscillator 16, or provided by a reference clock signal Cr. If the preset time period is provided by the reference clock signal Cr, the cyclic oscillator 16 is also electrically connected to a quartz crystal oscillator 22, and the quartz crystal oscillator 22 generates the reference clock signal Cr. Because the quartz crystal is less affected by temperature changes, the frequency characteristics it produces are very stable, and it is often used as an external clock source. The oscillation frequency of the oscillation clock signal Co is greater than the reference frequency of the reference clock signal Cr. For example, the reference frequency of the oscillation clock signal Co divided by the oscillation frequency of the reference clock signal Cr is N, and N is a natural number greater than 1. The preset time period is set to the period T of the reference clock signal Cr, such as Figure 3As shown, in the cycle T, the number of pulses is eight. If the preset value is seven, the control circuit 18 and the functional circuit 14 increase the resistance, capacitance and functional parameters. If the preset value is nine, the control circuit 18 and the functional circuit 14 reduce the resistance, capacitance and functional parameters. Because the calibration process only needs to refer to one cycle T of the clock signal Cr, it will not increase the boot time of the overall system too much. Such a self-calibration mechanism allows the single chip to perform self-calibration every time it is turned on in different usage environments, so that the single chip maintains consistent performance.

[0028] In some embodiments of the present invention, each dynamic random access memory 12 further includes a first transistor switch 24, a vertical resistor 26 and a vertical capacitor 28. The vertical capacitor 28 is disposed on the semiconductor substrate 10, and the vertical resistor 28 has a coarse adjustment resistance value. The first transistor switch 24 is a metal oxide semiconductor field effect transistor or a bipolar junction transistor, but the present invention is not limited thereto. In this embodiment, the first transistor switch 24 is an N-channel metal oxide semiconductor field effect transistor as an example. The first transistor switch 24 is disposed on the semiconductor substrate 10, and the first transistor switch 24 has a first control electrode, a first connection electrode and a second connection electrode. The first control electrode, the first connection electrode and the second connection electrode are respectively implemented as a drain, a gate and a source. An insulating layer 30 is formed on the semiconductor substrate 10, and the insulating layer 30 covers the first transistor switch 24. A first conductive through hole 32, a second conductive through hole 34 and a third conductive through hole 36 are formed in the insulating layer 30. The first conductive through hole 32 serves as a vertical resistor 26, and the first connection electrode is electrically connected to the functional circuit 14 through the vertical resistor 26. The first control electrode is electrically connected to the control circuit 18 through the second conductive through hole 34. The vertical capacitor 28 is arranged on the semiconductor substrate 10 and is located in the insulating layer 30. One end of the vertical capacitor 28 is electrically connected to the second connection electrode through the third conductive through hole 36, and the other end is electrically connected to a voltage terminal, such as a ground terminal. The vertical capacitor 28 has a coarse adjustment capacitance value. When the control circuit 18 turns on the first transistor switch 24, the functional circuit 14 adjusts the functional parameters according to the coarse adjustment resistance value of the vertical resistor 26 and the coarse adjustment capacitance value of the vertical capacitor 28. The first transistor switch 24, the vertical resistor 26 and the vertical capacitor 28 can also change their positions as long as they are connected in series with each other. In some embodiments of the present invention, the correction circuit 13, the functional circuit 14, the cyclic oscillator 16 and the control circuit 18 are located on the semiconductor substrate 10, but the present invention is not limited to this.

[0029] In some embodiments of the present invention, the correction circuit 13 further includes a plurality of correctors 37, which are disposed on the semiconductor substrate 10. All correctors 37 respectively have all fine-tuning capacitance values ​​and all fine-tuning resistance values, and all correctors 37 are electrically connected to the control circuit 18 and the functional circuit 14. When the number of pulses is greater than or less than a preset value, the control circuit 18 controls all correctors 37 to select fine-tuning capacitance values ​​and fine-tuning resistance values ​​according to the number of pulses and the preset value.

[0030] In some embodiments of the present invention, each corrector 37 further includes a second transistor switch 38, a horizontal resistor 40 and a horizontal capacitor 42. The second transistor switch 38 is a metal oxide semiconductor field effect transistor or a bipolar junction transistor, but the present invention is not limited thereto. In this embodiment, the second transistor switch 38 is an N-channel metal oxide semiconductor field effect transistor. The second transistor switch 38 is disposed on the semiconductor substrate 10. The second transistor switch 38 has a second control electrode, a third connection electrode and a fourth connection electrode. The second control electrode, the third connection electrode and the fourth connection electrode are respectively implemented as a gate, a drain and a source. The second control electrode is electrically connected to the control circuit 18, and the third connection electrode is electrically connected to the functional circuit 14. The horizontal resistor 40 and the horizontal capacitor 42 are disposed on the semiconductor substrate 10. The horizontal resistor 40 has a fine-tuning resistance value, and the horizontal capacitor 42 has a fine-tuning capacitance value. The horizontal resistor 40 is connected to a voltage terminal, such as a ground terminal, and is electrically connected in series with the horizontal capacitor 42. The horizontal capacitor 42 is electrically connected to the fourth connection electrode of the second transistor switch 38. When the control circuit 18 turns on the second transistor switch 38, the functional circuit 14 adjusts the functional parameters according to the fine-tuning resistance value of the horizontal resistor 40 and the fine-tuning capacitance value of the horizontal capacitor 42. The second transistor switch 38, the horizontal resistor 40 and the horizontal capacitor 42 can also change their positions as long as they are connected in series. In the conventional technology, the process drift phenomenon is improved by the horizontal resistor and the horizontal capacitor, but because the horizontal resistor and the horizontal capacitor occupy too much chip area, the manufacturing cost is increased. Therefore, the present invention uses the vertical resistor 26 and the vertical capacitor 28 in the dynamic random access memory 12 to replace part of the horizontal resistor and the horizontal capacitor. Compared with the horizontal resistor 40 and the horizontal capacitor 42, the vertical resistor 26 and the vertical capacitor 28 have a higher height and a smaller area, so the required chip area can be reduced. Usually, in order to minimize the suppression of process drift, more precise resistance and capacitance values ​​are often required, and if a larger control range is required, more resistance area and capacitance area are required to achieve a larger control range, which means that the circuit can have a higher adjustment range, and there is still a chance to suppress the process drift and adjust it back to the original required characteristics. Based on the above idea, since the present invention uses the dynamic random access memory 12, it is equivalent to having an additional capacitor element with a large capacitance but not very accurate. Although the vertical resistor 26 and the vertical capacitor 28 have a higher error value than the horizontal resistor 40 and the horizontal capacitor 42, because the coarse adjustment capacitance value and the coarse adjustment resistance value of the vertical resistor 26 and the vertical capacitor 28 are very high, the characteristics of the coarse adjustment capacitance value and the coarse adjustment resistance value can be used to increase the circuit operation range with a smaller fine adjustment capacitance value and fine adjustment resistance value. For example, the coarse adjustment capacitance value and the coarse adjustment resistance value form a first time constant, and the fine adjustment capacitance value and the fine adjustment resistance value form a second time constant.For the delay line of the delay locked loop (DLL) as the functional circuit 14, since the process drift will also change the delay time of the delay line in the functional parameters, in order to maintain the original delay time of the delay line, all dynamic random access memories 12 and the correction circuit 13 are adjusted. Assume that the first time constant is 100 nanoseconds (ns), the second time constant is 10 nanoseconds, and the first time constant is controlled by 10 first transistor switches 24, and the second time constant is controlled by 15 second transistor switches 38. Therefore, the total delay of fine adjustment is 150 nanoseconds, which is greater than the single delay time of coarse adjustment, that is, 100 nanoseconds. The delay time of coarse adjustment and fine adjustment can overlap to ensure that linear switching will not cause problems. The present invention can coordinate the delay time of coarse adjustment and fine adjustment to obtain the required delay time. Assuming that the required delay time is 240 nanoseconds, only two first transistor switches 24 and four second transistor switches 38 need to be turned on, and the remaining first transistor switches 24 and second transistor switches 38 need to be turned off. If the coarse adjustment has an error of ±30% due to process inaccuracy, the present invention can accurately compensate to the required delay time through fine adjustment control.

[0031] In some embodiments of the present invention, the control circuit 18 further includes a counter 44 and a decoder 46, wherein the counter 44 may also be a shift register. The counter 44 is disposed on the semiconductor substrate 10, and is electrically connected to the cyclic oscillator 16. The counter 44 receives the oscillation clock signal Co. Within a preset period, the counter 44 counts the number of pulses according to the rising edge or the falling edge of the pulse, and generates a set of digital values ​​D according to the number of pulses. The rising edge of the pulse represents a rise from a low voltage level to a high voltage level, and the falling edge represents a fall from a high voltage level to a low voltage level. The decoder 46 is disposed on the semiconductor substrate 10, and is electrically connected to the counter 44, the first control electrodes of the first transistor switches 24 of all dynamic random access memories 12, and the second control electrodes of the second transistor switches 38 of the correction circuit 13. The decoder 46 receives this set of digital values ​​D, and controls all dynamic random access memories 12 and correction circuits 13 to select coarse adjustment capacitor values, coarse adjustment resistor values, fine adjustment capacitor values ​​and fine adjustment resistor values ​​according to this set of digital values ​​D and preset values, and provides them to the functional circuit 14.

[0032] The operation process of the self-correcting system-on-a-chip of the present invention is described below. First, all first transistor switches 24 are partially closed and partially turned on, and all second transistor switches 38 are in the closed state, wherein the number of closed first transistor switches 24 is equal to or greater than the number of turned-on first transistor switches 24, and this condition is determined according to the requirements. Next, the quartz crystal oscillator 22 generates a reference clock signal Cr, and the cyclic oscillator 16 is used to generate an oscillation clock signal Co, so that the counter 44 receives the oscillation clock signal Co, and within a preset period of time, the number of pulses is calculated according to the rising edge or the falling edge of the pulse, and a set of digital values ​​D is generated according to the number of pulses. Then, the decoder 46 receives this set of digital values ​​D, and according to this and the preset value, turns on the required first transistor switches 24 and second transistor switches 38, or turns off the required first transistor switches 24, so as to select the coarse adjustment capacitance value, coarse adjustment resistance value, fine adjustment capacitance value and fine adjustment resistance value corresponding to the turned-on first transistor switches 24 and second transistor switches 38. Therefore, the functional circuit 14 and the selected coarse adjustment capacitance value, coarse adjustment resistance value, fine adjustment capacitance value and fine adjustment resistance value adjust the functional parameters to achieve the purpose of calibration.

[0033] For example, if the functional circuit 14 is a radio frequency circuit, the functional parameter is its operating frequency. Specifically, the radio frequency circuit has a transmission (TX) circuit and a reception (RX) circuit, and its operating frequency is regulated, so a circuit such as a phase-locked loop must be used to generate the frequency. For example, Bluetooth and wireless fax (Wi-Fi) operate at 2.4×10 9Hertz (Hz). Since high-frequency circuits are easily affected by process drift, a set of correction circuits composed of resistors and capacitors for process drift is usually designed and added to the resonant node of its oscillator. The oscillator of the phase-locked loop usually uses an oscillator composed of an inductor and a capacitor. The oscillation method is through an amplifier, and the inductor and the capacitor are designed at the resonant frequency, and the circuit will self-oscillate. The present invention places all dynamic random access memories 12 and correction circuits 13 on two mutually oscillating nodes. Because the chip will have process drift, each oscillator will change the oscillation frequency due to the process drift of components such as resistors, inductors, capacitors and transistor switches. In the case where the transistor switches and inductors cannot be changed, the present invention uses all the added dynamic random access memories 12 and correction circuits 13 to adjust the load of the oscillation node, change the oscillation frequency, and prevent the influence caused by process drift. In other words, the process drifts in which direction, and the load of the node will be modified in the opposite direction to maintain the original functional parameters. If the above-mentioned functional circuit 14 is an amplifier circuit, the functional parameters include gain and phase. The amplifier circuit has an input current source, and the size of the current source directly affects the characteristics of the amplifier circuit, namely, the gain and phase. If the current source is connected to all dynamic random access memories 12 and the correction circuit 13, the size of the current source can be changed to change the gain and phase. If the functional circuit 14 is a loop filter, the functional parameter can be its loop bandwidth. The loop filter is mainly composed of an amplifier, a resistor and a capacitor. If the loop filter is connected to all dynamic random access memories 12 and the correction circuit 13, the loop bandwidth of the loop filter can be compensated.

[0034] In summary, the present invention utilizes the larger capacitance and resistance values ​​of the dynamic random access memory that occupy a small area, combined with smaller capacitance and resistance values, to avoid the problem of process drift, increase the circuit operation range, and reduce the required chip area.

[0035] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A self-correcting system-on-a-chip, characterized in that: Include: a semiconductor substrate; At least one silicon intellectual property circuit is disposed on the semiconductor substrate, and the at least one silicon intellectual property circuit comprises: A plurality of dynamic random access memories are disposed on the semiconductor substrate, each of the dynamic random access memories having a coarse adjustment capacitance value and a coarse adjustment resistance value; a correction circuit disposed on the semiconductor substrate, the correction circuit having a plurality of fine-tuning capacitance values ​​and a plurality of fine-tuning resistance values; a functional circuit disposed on the semiconductor substrate and electrically connected to the dynamic random access memories and the calibration circuit, the functional circuit having a functional parameter; A cyclic oscillator is disposed on the semiconductor substrate, and the cyclic oscillator generates an oscillation clock signal within a preset period of time; as well as A control circuit is arranged on the semiconductor substrate. The control circuit is electrically connected to the cyclic oscillator, the dynamic random access memories and the correction circuit. The control circuit receives the oscillation clock signal and calculates the number of pulses of the oscillation clock signal. When the number of pulses is greater than or less than a preset value, the control circuit controls the dynamic random access memories and the correction circuit to select the coarse adjustment capacitor value, the coarse adjustment resistor value, the fine adjustment capacitor value and the fine adjustment resistor value according to the number of pulses and the preset value, and provides this to the functional circuit. The functional circuit adjusts the functional parameter according to the selected coarse adjustment capacitor value, the coarse adjustment resistor value, the fine adjustment capacitor value and the fine adjustment resistor value.

2. The self-correcting system-on-a-chip as claimed in claim 1, wherein: Each of the dynamic random access memories further comprises: a vertical resistor disposed on the semiconductor substrate, the vertical resistor having the coarse adjustment resistance value; a first transistor switch disposed on the semiconductor substrate, the first transistor switch having a first control electrode, a first connecting electrode and a second connecting electrode, the first connecting electrode being electrically connected to the functional circuit via the vertical resistor, and the first control electrode being electrically connected to the control circuit; and A vertical capacitor is arranged on the semiconductor substrate and electrically connected to the second connecting electrode and a voltage end. The vertical capacitor has the coarse adjustment capacitance value. When the control circuit turns on the first transistor switch, the functional circuit adjusts the functional parameter according to the coarse adjustment resistance value of the vertical resistor and the coarse adjustment capacitance value of the vertical capacitor.

3. The self-correcting system-on-a-chip of claim 1, wherein: The correction circuit also includes a plurality of correctors, which are arranged on the semiconductor substrate. The correctors respectively have the fine-tuning capacitance values ​​and the fine-tuning resistance values. The correctors are electrically connected to the control circuit and the functional circuit. When the number of the pulses is greater than or less than the preset value, the control circuit controls the correctors to select the fine-tuning capacitance value and the fine-tuning resistance value according to the number of the pulses and the preset value.

4. The self-correcting system-on-a-chip as claimed in claim 3, wherein: Each of the correctors also comprises: a second transistor switch disposed on the semiconductor substrate, the second transistor switch having a second control electrode, a third connection electrode and a fourth connection electrode, the second control electrode being electrically connected to the control circuit, and the third connection electrode being electrically connected to the functional circuit; as well as A horizontal resistor and a horizontal capacitor are arranged on the semiconductor substrate, the horizontal resistor has the fine-tuning resistance value, the horizontal capacitor has the fine-tuning capacitance value, the horizontal resistor is connected to a voltage end and is electrically connected in series with the horizontal capacitor, the horizontal capacitor is electrically connected to the fourth connection electrode of the second transistor switch, and when the control circuit turns on the second transistor switch, the functional circuit adjusts the functional parameter according to the fine-tuning resistance value of the horizontal resistor and the fine-tuning capacitance value of the horizontal capacitor.

5. The self-correcting system-on-a-chip of claim 1, wherein: The control circuit also includes: a counter, disposed on the semiconductor substrate, the counter being electrically connected to the cyclic oscillator, the counter receiving the oscillation clock signal, and within the preset time period, the counter counting the number of the pulses according to the rising edge or the falling edge of the pulse to generate a set of digital values; A decoder is disposed on the semiconductor substrate. The decoder is electrically connected to the counter, the dynamic random access memories and the correction circuit. The decoder receives the set of digital values ​​and controls the dynamic random access memories and the correction circuit to select the coarse adjustment capacitor value, the coarse adjustment resistor value, the fine adjustment capacitor value and the fine adjustment resistor value based on the digital values ​​and the preset value, and provides the digital values ​​to the functional circuit.

6. The self-correcting system-on-a-chip of claim 5, wherein: The counter is a shift register.

7. The self-correcting system-on-a-chip of claim 1, wherein: The cyclic oscillator also receives a reference clock signal. The preset period is the cycle of the reference clock signal, and the oscillation frequency of the oscillation clock signal is greater than the reference frequency of the reference clock signal.

8. The self-correcting system-on-a-chip of claim 7, wherein: The circulating oscillator is also electrically connected to a quartz crystal oscillator, and the quartz crystal oscillator generates the reference clock signal.

9. The self-correcting system-on-a-chip of claim 1, wherein: When the number of the pulses is less than the preset value, the control circuit and the functional circuit reduce the functional parameter, and when the number of the pulses is greater than the preset value, the control circuit and the functional circuit increase the functional parameter.

10. The self-correcting system-on-a-chip of claim 1, wherein: The coarse adjustment capacitance value and the coarse adjustment resistance value form a first time constant, the fine adjustment capacitance value and the fine adjustment resistance value form a second time constant, and a value of the first time constant divided by the second time constant is greater than or equal to 10.

11. The self-correcting system-on-a-chip of claim 1, wherein: The functional circuit is an analog circuit, a radio frequency circuit, a digital circuit, a processor, a static random access memory or a flash memory.

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