Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure, comprising: a substrate; a fan-out structure disposed on the substrate, and comprising: a first fan-out layer attached to the substrate by a first adhesive layer, the first fan-out layer comprising a first via hole passing through the first adhesive layer, the first via hole being electrically connected to the substrate; and a second fan-out layer electrically connected to the first fan-out layer in a flip-chip manner. In embodiments, a method for forming a semiconductor structure is also provided. The purpose of the present application is to at least improve the value of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] The process capability of semiconductor wafer has reached 7 nanometers, even 5 nanometer process, and the pitch of the chip pads is less than 50 μm, but the minimum pitch of the existing semiconductor substrate is 130 μm, which does not meet the use.

[0003] The fan-out substrate is to paste the fan-out layer to the end of the substrate, and then to electrically connect the fan-out layer and the substrate by laser drilling, but when the number of fan-out layers is large, the aperture of the laser drilling will be large, which causes the process and electrical properties to be not up to the requirements. SUMMARY

[0004] In view of the problems in the related art, the purpose of the present application is to provide a semiconductor structure and a forming method thereof, so as to at least improve the use value of the semiconductor structure.

[0005] To achieve the above-mentioned purpose, the present application provides a semiconductor structure, comprising: a substrate; a fan-out structure disposed on the substrate, and comprising: a first fan-out layer attached to the substrate through a first adhesive layer, the first fan-out layer comprising a first via hole passing through the first adhesive layer, the first via hole being electrically connected to the substrate; a second fan-out layer electrically connected to the first fan-out layer in a flip-chip manner.

[0006] In an embodiment, the first via hole in the first fan-out layer gradually narrows along a first direction, and the second via hole in the second fan-out layer electrically connected to the first via hole gradually narrows along a second direction, the first direction being opposite to the second direction.

[0007] In an embodiment, the second via hole in the second fan-out layer is electrically connected to the first via hole through a conductive material.

[0008] In an embodiment, the first fan-out layer further comprises a first dielectric layer, and the first via hole further passes through the first dielectric layer, the thickness of the first fan-out layer and the adhesive layer being less than 100 μm.

[0009] In an embodiment, the thickness of the first fan-out layer and the adhesive layer is less than 20 μm.

[0010] In an embodiment, further comprising a second adhesive layer between the first fan-out layer and the second fan-out layer, the thickness of the first adhesive layer being less than 20 μm, and the thickness of the second adhesive layer being less than 10 μm.

[0011] In an embodiment, a method of forming a semiconductor structure is also provided, comprising: providing a substrate; forming a first adhesive layer on the substrate; attaching a first fan-out layer to the substrate through the first adhesive layer; forming a first via in the first fan-out layer through the first adhesive layer and electrically connected to the substrate; flip-chipping a second fan-out layer on the first fan-out layer, the second fan-out layer electrically connected to the first fan-out layer.

[0012] In an embodiment, forming the first via comprises: forming an opening through the first dielectric layer and the adhesive layer of the first fan-out layer by laser drilling, the opening exposing a pad of the substrate; filling a metal material in the opening.

[0013] In an embodiment, electrically connecting the second fan-out layer to the first fan-out layer comprises: forming a conductive material on a second via of the second fan-out layer, flip-chipping the second fan-out layer on the first fan-out layer in a manner that the first via is aligned with the second via, such that the conductive material is located between the first via and the second via.

[0014] In an embodiment, after forming the first via, and before flip-chipping the second fan-out layer on the first fan-out layer, a second adhesive layer is formed on the first fan-out layer, such that after flip-chipping the second fan-out layer on the first fan-out layer, the second adhesive layer surrounds the first via and the second via of the second fan-out layer that are electrically connected to each other. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figures 1 to 15 A process diagram of forming a second fan-out layer is shown according to some embodiments of the present application

[0016] Figures 16 to 25 A process diagram of forming a first fan-out layer is shown according to some embodiments of the present application.

[0017] Figures 26 to 41 A process diagram of forming a semiconductor structure is shown according to some embodiments of the present application.

[0018] Figures 42 to 46 A structure diagram of a semiconductor structure is shown according to some embodiments of the present application. DETAILED DESCRIPTION

[0019] For better understanding of the spirit of the embodiments of the present application, the following further describes the embodiments of the present application in combination with some preferred embodiments of the present application.

[0020] Embodiments of the present application will be described in detail herein after. In the entire description of the present application, the same or similar components and components having the same or similar functions are denoted by similar reference numerals. The embodiments described herein with respect to the accompanying drawings are of illustrative nature, diagrammatic nature and for providing a basic understanding of the present application. The embodiments of the present application should not be interpreted as a limitation of the present application.

[0021] As used herein, the terms "substantially," "generally," "essentially," and "about" are used to describe and account for small variations in, e.g., measurements, temperatures, etc. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs exactly as well as instances where the event or circumstance occurs with minor deviations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be considered "generally" the same if the difference between the two values is less than or equal to ±10% of the average of the values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0022] In this specification, unless expressly specified or limited, relative terms such as "central," "longitudinal," "lateral," "forward," "rearward," "rightward," "leftward," "internal," "external," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description only and do not require that the application be practiced with any particular orientation.

[0023] In addition, quantities, ratios and other numerical values are sometimes presented in a range format. It is to be understood that such range format is used for convenience and brevity and should be construed as having been followed had each numerical value within the range been individually listed. To the extent that any numerical range is stated herein to include endpoints, the range format is also meant to include the endpoint values themselves.

[0024] Further, for the sake of brevity, the terms "first," "second," "third," etc. can be used herein to describe various components. The skilled person will appreciate that these terminologies are not intended to limit the scope of the corresponding components.

[0025] The organic substrate is expensive because the yield of the substrate meeting high specifications is low at present, especially in high-order packaging products such as 2.5-dimensional (2.5D) / three-dimensional (3D) (accounting for at least 50% of the whole), mainly because the process error of the substrate is large, so that the stability of the structure geometry is low (compared with the pad yellow light process). At the same time, in order to have enough input / output (I / O) to meet the needs at the chip end, the structure stability must be handled with a multilayer (Multilayer) redistribution layer (RDL) structure due to the low structure stability. In fact, the more layers of the structure can provide more I / O, but the cost and yield loss are relatively high.

[0026] The best process capability of the substrate at present is only in the middle-order (for example, line width / spacing-L / S>10μm / 10μm and the diameter of the via>50μm) line density capability, but it has the advantages of lower single-layer manufacturing cost and shorter time; the pad technology process capability has the advantages of higher-order (for example, L / S<2μm / 2μm and the diameter of the via<5μm) line density capability and structure thinning, which is extremely helpful for fewer RDL layers, but it has the disadvantages of higher single-layer manufacturing cost and longer time.

[0027] In the existing semiconductor structure, layers are accumulated to form a fan-out layer, and a via is formed through all the layers. The diameter of the via formed in this way is large, so the overall I / O number is limited. The via through all the layers connects all the patterns and contacts inside, so only one function can be realized (for example, only ground is realized), and if different functions are needed, the wire must be cut off. In order to realize the required I / O number, the existing semiconductor structure needs a larger package size (larger fan-out structure, larger substrate and higher cost), and is not conducive to miniaturization requirements.

[0028] In this way, if a substrate structure forming a high-density line can be found, not only can the cost be reduced due to fewer RDL layers, but also the packaging structure can increase many I / O numbers and be more useful.

[0029] The semiconductor structure and the forming method thereof according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0030] Reference Figure 1 A carrier 10 is provided, and a first seed layer 12 is formed on the carrier 10. In the embodiment, the thickness of the first seed layer 12 is 0.1μm to 0.3μm.

[0031] Reference Figure 2 A first mask layer 20 is formed on the first seed layer 12, the first mask layer 20 includes a photoresist (PR) material, and an exposure process 21 is performed on the first mask layer 20 to solidify.

[0032] Referring to Figure 3 The first mask layer 20 is patterned and a first metal material 30 is deposited in the patterned first mask layer 20.

[0033] Referring to Figure 4 The patterned first mask layer 20 is removed and the first metal material 30 is used as a mask to pattern the first seed layer 12. In embodiments, the first metal material 30 is about 1 μιη to about 2 μιη higher than the first seed layer 12. In this context, the thickness of the seed layer and the metal material / conductive material removed therefrom is in the numerical range of the first seed layer 12 and the first metal material 30 described above.

[0034] Referring to Figure 5 A second dielectric layer 50 is deposited, which can include a polyamide (PA) material, and an exposure process 51 is performed on the second dielectric layer 50 to cure it.

[0035] Referring to Figure 6 A circuit layer 60 is formed in the second dielectric layer, which contacts the first metal material 30. In embodiments, the circuit layer 60 has a line width / space of less than 2 μιη / 2 μιη. The circuit layer 60 includes functional vias through the second dielectric layer 50, which have a diameter in the range of 5 μιη to 20 μιη.

[0036] Referring to Figure 7 A third dielectric layer 70 is formed over the circuit layer 60, which can include a polyamide (PA) material, and an exposure process 71 is performed on the third dielectric layer 70 to cure it. The third dielectric layer 70 is a dielectric for fan-out structures and can also include organic materials such as polyimide (PI), epoxy, polybenzoxazole (PBO), flame retardant 4th class material (e.g., FR4), prepreg (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT), or / and inorganic materials such as silicon, glass, ceramic, oxide (e.g., SiOx, TaOx), nitride (e.g., SiNx), etc. In embodiments, the third dielectric layer 70 is formed using processes such as printing, lamination, potting, coating, etc.

[0037] Referring to Figure 8 A portion of the third dielectric layer 70 is removed to form an opening 80 exposing the circuit layer 60, and a second seed layer 82 is formed in the opening 80 and on the third dielectric layer 70.

[0038] Referring to Figure 9A second mask layer 90 is formed over the second seed layer 82, the second mask layer 90 comprising a photoresist (PR) material. An exposure process 91 is performed on the second mask layer 90 to solidify.

[0039] Referring to Figure 10 A patterning process is performed on the second mask layer 90 to form a patterned second mask layer 90. A second metal material 92 is formed in the patterned second mask layer 90.

[0040] Referring to Figure 11 The patterned second mask layer 90 is removed, leaving the second metal material 92 to form a trace. In an embodiment, the trace has a line / space (L / S) of greater than 2 μm / 2 μm.

[0041] Referring to Figure 12 A third mask layer 120 is formed over the trace, the third mask layer 120 comprising a photoresist (PR) material. An exposure process 121 is performed on the third mask layer 120 to solidify.

[0042] Referring to Figure 13 The third mask layer 120 is patterned to expose the second seed layer 82, and a conductive material 131 is formed on the exposed second seed layer 82 to form a second via 130. In an embodiment, the second via 130 comprises the second seed layer 82, the conductive material 131 on the second seed layer 82. The second via 130 further comprises an interconnect layer 132, 133 on the conductive material 131, and a solder layer 142 on the interconnect layer 132, 133. In an embodiment, the second via 130 and the layers in the interconnect layer 132, 133 comprise, from bottom to top, copper, nickel, and copper. In an embodiment, the second seed layer 82 comprises titanium, tungsten, nickel, etc., and the conductive material 131 comprises copper, silver, gold, nickel, platinum, etc. In an embodiment, the interconnect layer 132, 133 comprises adaptively coupled plasma (ACP), anisotropic conductive film (ACF), solder, direct metal (e.g., copper, silver, gold, nickel, platinum, etc.), etc. In an embodiment, the second seed layer, the conductive material 131, and the interconnect layer 132, 133 can be formed using sputtering, electroplating, electroless (E'less), and / or printing, lamination, and / or potting processes. In an embodiment, the second via 130 has a diameter in a range of 5 μm to 20 μm.

[0043] Referring to Figure 14The patterned third mask layer 120 is removed and a heating process 140 is performed. The second seed layer 82 and the conductive material 131 also form an inner pattern 143. In an embodiment, the line width / space of the inner pattern 143 is greater than 2 pm / 2 pm. The second seed layer 82 and the conductive material 131 can be formed using sputtering, electroplating, electroless (E’less), and / or printing, lamination, and / or potting processes.

[0044] Referring to Figure 15 The heating process 140 causes the uppermost layer of solder 142 of the second via 130 to melt to form a second fan-out layer 150 on the first carrier 10. The thickness of the solder layer 142 is thin, in one embodiment, 1 pm - 2 pm.

[0045] Referring to Figure 16 A third seed layer 162 is formed on the second carrier 160. In an embodiment, the third seed layer 162 is formed on the second carrier 160 using a physical vapor deposition (PVD) process.

[0046] Referring to Figure 17 A fourth mask layer 170 is formed on the third seed layer 162, the fourth mask layer 170 includes a photoresist (PR) material, and an exposure process 171 is performed to cure the fourth mask layer 170.

[0047] Referring to Figure 18 The fourth mask layer 170 is patterned and a third metal material 180 is formed in the patterned fourth mask layer 170.

[0048] Referring to Figure 19 The patterned fourth mask layer 170 is removed and the third seed layer 162 is etched using the third metal material 180 as a mask to form a patterned third seed layer 162.

[0049] Referring to Figure 20A first dielectric layer 200 is formed on the second carrier 160 and the third metal material 180. The first dielectric layer 200 can include a polyamide (PA) material, and an exposure process 201 is performed on the first dielectric layer 200 to solidify the first dielectric layer 200. The first dielectric layer 200 is a dielectric of the fan-out structure, and can further include an organic material, such as polyimide (PI), epoxy, polybenzoxazole (PBO), flame-retardant 4-level material (e.g., FR4), prepreg (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT), or / and an inorganic material, such as silicon, glass, ceramic, oxide (e.g., SiOx, TaOx), nitride (e.g., SiNx), etc. In an embodiment, the first dielectric layer 200 is formed using a printing, lamination, potting, coating, etc. process. In an embodiment, the thickness of the first dielectric layer 200 is less than 20 pm.

[0050] Referring to Figure 21 The first dielectric layer 200 is etched to expose the third metal material 180, and a fourth seed layer 210 is formed on the exposed third metal material 180 and the first dielectric layer 200.

[0051] Referring to Figure 22 A fifth mask layer 220 is formed on the fourth seed layer 210. The fifth mask layer 220 includes a photoresist (PR) material, and an exposure process 211 is performed to solidify the fifth mask layer 220.

[0052] Referring to Figure 23 The fifth mask layer 220 is patterned, and a fourth metal material 230 is formed in the patterned fifth mask layer 220.

[0053] Referring to Figure 24 The patterned fifth mask layer 220 is removed, and the fourth seed layer 210 is etched using the fourth metal material 230 as a mask to form a patterned fourth seed layer 210.

[0054] Referring to Figure 25 The second carrier 160 and the structure on the second carrier 160 are cut to form a singulated first fan-out layer 250 on the second carrier 160.

[0055] Referring to Figure 26, a substrate 260 is provided, the substrate 260 has a substrate via 262 through a substrate dielectric layer 261 of the substrate 260, and a first pad 264 electrically connected with the substrate via 262. The substrate dielectric layer 261 includes organic polyimide (PI), epoxy, polybenzoxazole (PBO), flame retardant 4 (FR4), prepreg (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT), etc. In embodiments, the substrate dielectric layer 261 is formed using printing, lamination, potting, coating, etc. The substrate seed layer 265 between the first pad 264 and the substrate 260 includes titanium, tungsten, nickel, etc., and the first pad 264 includes copper, silver, gold, nickel, platinum, etc. The first pad 264 and the substrate seed layer 265 constitute a substrate trace. In embodiments, the first pad 264 and the substrate seed layer 265 can be formed using sputtering, electroplating, electroless (E’less), and / or printing, lamination, and / or potting processes. In embodiments where the substrate dielectric layer 261 includes organic material, the substrate via 262 can be a through organic via (TOV). In embodiments where the substrate dielectric layer 261 includes inorganic material, the substrate via 262 can be a through inorganic via, such as a through silicon via (TSV), a through glass via (TGV). In embodiments, the L / S of the first pad 264 is > 20 μm / 20 μm

[0056] Referring to Figure 27 A first adhesive layer 270 is formed on the substrate 260. The first adhesive layer 270 includes organic polyimide (PI), epoxy, polybenzoxazole (PBO), flame retardant 4 (FR4), prepreg (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT), etc.

[0057] Referring to Figure 28 The second carrier 160 and the second fan-out layer 150 on the second carrier 160 are placed upside down on the substrate 260. The first adhesive layer 270 is used to bond the second fan-out layer 150 and the substrate 260. The adhesion of the first adhesive layer 270 overcomes the bonding problem between the substrate 260 and the second fan-out layer 150.

[0058] Referring to Figure 29 The second carrier 160 is removed, and a second opening 290 is formed through the second fan-out layer 150 and the first adhesive layer 270, the second opening 290 exposes the first pad 264 of the substrate 260.

[0059] refer to Figure 30 Continue laser processing on the second fan-shaped layer 250 to form... Figure 31 The diagram shows multiple second openings 290. The top surface of the first pad 264 of the substrate 260 has a different height, therefore the multiple openings 290 also extend to different heights. A fifth seed layer 310 is formed on the second openings 290 and the second fan-out layer 150.

[0060] refer to Figure 32 A sixth mask layer 320 is formed on the fifth seed layer 310. The sixth mask layer 320 includes a photoresist (PR) material, and an exposure process 321 is performed on the sixth mask layer 320 to cure it.

[0061] refer to Figure 33 A sixth mask layer 320 is patterned to expose a fifth seed layer 310 located in a second opening 290, and a second conductive material 332 is formed on the fifth seed layer 310 to form a first via 330. The first via 330 is a through-hole. In an embodiment, the fifth seed layer 310 includes titanium, tungsten, nickel, etc., and the second conductive material 332 includes copper, silver, gold, nickel, platinum, etc. In an embodiment, the fifth seed layer 310 and the second conductive material 332 can be formed using sputtering, electroplating, electroless plating (E'less), and / or printing, lamination, and / or potting processes. In an embodiment, the diameter of the first via 330 is less than 30 μm. In an embodiment, the diameter of the first via 330 has a range between 10 μm and 30 μm. In existing structures, the diameter of the via connecting the substrate and the fan-out layer is at least greater than 70 μm.

[0062] refer to Figure 34 Remove the patterned sixth mask layer 320 and retain the first through hole 330.

[0063] refer to Figure 35A second adhesive layer 350 is formed on the first fan-out layer 250 to mount the first carrier 10 and the second fan-out layer 150 on the first fan-out layer 250 in an inverted manner. The solder layer 142 is bonded to the first via 330. The second adhesive layer 350 includes polyimide (PI), epoxy, polybenzoxazole (PBO), flame retardant 4 (FR4), prepreg (PP), Ajinomoto build-up film (ABF), bismaleimide triazine (BT), etc. In embodiments, the second adhesive layer 350 is formed using printing, lamination, potting, coating, etc. The second adhesive layer 350 provides good connection between single and multi-layer fan-out layers. Compared to conventional structures, the present solution forms a perfect fan-out substrate structure with high I / O, thinner package, and lower cost. In embodiments, the thickness of the second adhesive layer 350 is less than 10 pm.

[0064] Referring to Figure 36 The first carrier 10 is removed, and the solder layer 142 connects the first fan-out layer 250 and the first fan-out layer 150.

[0065] Referring to Figure 37 An etching process 371 is performed on the back side of the second fan-out layer 150 to remove the first seed layer 12, exposing the first metal material 30, as shown. Figure 38

[0066] Referring to Figure 39 A chip 390 is formed on the second fan-out layer 150 and electrically connected to the first metal material 30. The chip 390 is electrically connected to the first metal material 30 through a bottom connection 392 and a top pad 396 on the first metal material 30 through a wire 394.

[0067] Referring to Figure 40 The chip 390 is encapsulated using an encapsulation layer 400.

[0068] Referring to Figure 41 A solder ball 410 is formed on the second pad 266 under the substrate via 262 of the substrate 260 to form a semiconductor structure 4100.

[0069] Referring to Figure 42 Compared to Figure 41 The first fan-out layer 250 of the semiconductor structure 4200 includes multiple layers of circuit layers.

[0070] Referring to Figure 43 Compared to Figure 41 ​The first fan-out layer 250 and the second fan-out layer 150 of the semiconductor structure 4300 are formed on both sides of the substrate 260. That is, the other side of the substrate 260 is also formed with a first fan-out layer 250' and a second fan-out layer 150'.

[0071] Referring to Figure 44 In comparison with Figure 41 The first dielectric layer 200 of the first fan-out layer 250 and the third dielectric layer 70 of the second fan-out layer 150 of the semiconductor structure 4400 are also formed with fillers 440, respectively.

[0072] Referring to Figure 45 In comparison with Figure 41 The third metal material 180 and the fourth metal material 230 of the semiconductor structure 4500 are also connected with a lead 450.

[0073] Referring to Figure 46 In comparison with Figure 45 The third metal material 180 and the fourth metal material 230 of the semiconductor structure 4500 are also connected with a connector 460. In an embodiment, the lead 450 and the connector 460 can also be / include active devices, such as chips and / or passive (e.g., embedded) components.

[0074] In an embodiment, the first fan-out layer 250 of the present application is an interposer fan-out layer, and the second fan-out layer 150 is a functional fan-out layer. The functional fan-out layer and the substrate are separated to facilitate testing of the circuit. Moreover, the manufacturing of the substrate and the functional fan-out layer do not interfere with each other.

[0075] The present application divides the fan-out structure into two parts (the first and second fan-out layers), the first part of the fan-out layer is still attached to the substrate through the adhesive layer, by controlling the thickness value of this part (e.g., only two layers of fan-out), a smaller via hole can be formed, and the second part of the fan-out layer is connected to the first part of the fan-out layer through soldering by flip-chip method, thus forming a complete substrate fan-out circuit structure. The internal functional via hole and the RDL of the present application have a small pitch.

[0076] An embodiment of the present application provides a semiconductor structure 4100, comprising: a substrate 260; a fan-out structure disposed on the substrate and comprising: a first fan-out layer 250 attached to the substrate 260 through a first adhesive layer 270, the first fan-out layer 250 comprising a first via hole 330 passing through the first adhesive layer 270, the first via hole 330 being electrically connected to the substrate 2500; and a second fan-out layer 150 electrically connected to the first fan-out layer 250 in a flip-chip manner.

[0077] In an embodiment, the first via 330 in the first fan-out layer 250 tapers in a first direction, and the second via 130 in the second fan-out layer 150 electrically connected to the first via 330 tapers in a second direction, the first direction opposite to the second direction.

[0078] In an embodiment, the second via 130 in the second fan-out layer 150 is electrically connected to the first via by a conductive material (in one embodiment, including interconnect layers 132, 133 and a solder layer 142; in one embodiment, can only include the solder layer 142).

[0079] In an embodiment, the first fan-out layer 250 further includes a first dielectric layer 200, and the first via 330 further passes through the first dielectric layer 250, and the thickness of the first fan-out layer 250 and the first adhesive layer 270 is less than 100 μm.

[0080] In an embodiment, the thickness of the first fan-out layer 250 and the first adhesive layer 270 is less than 20 μm.

[0081] In an embodiment, a second adhesive layer is further included between the first fan-out layer 250 and the second fan-out layer 150, the thickness of the first adhesive layer 270 is less than 20 μm, and the thickness of the second adhesive layer 350 is less than 10 μm.

[0082] In an embodiment, a method of forming a semiconductor structure is further provided, including: providing a substrate 260; forming a first adhesive layer 270 on the substrate 260; attaching a first fan-out layer 150 to the substrate 260 through the first adhesive layer 270; forming a first via 330 in the first fan-out layer 250 that passes through the first adhesive layer 270 and is electrically connected to the substrate; flip-chipping a second fan-out layer 150 on the first fan-out layer 250, the second fan-out layer 150 electrically connected to the first fan-out layer 250.

[0083] In an embodiment, forming the first via 330 includes: forming an opening (second opening 290) through a first dielectric layer 200 and the first adhesive layer 270 of the first fan-out layer 250 by laser drilling, the opening exposing a pad (first pad 264) of the substrate 260; filling a metal material (fifth seed layer 310 and second conductive material 332) in the opening.

[0084] In an embodiment, electrically connecting the second fan-out layer 150 to the first fan-out layer 250 includes: forming a conductive material (in one embodiment, including interconnect layers 132, 133 and a solder layer 142; in one embodiment, can only include the solder layer 142) on the second via 130 of the second fan-out layer 150, flip-chipping the second fan-out layer 150 on the first fan-out layer 250 in a manner that the first via 330 is aligned with the second via 130, so that the conductive material is located between the first via 330 and the second via 130.

[0085] In an embodiment, after forming the first through holes 330, and before flip-chipping the second fan-out layer 150 to the first fan-out layer 250, a second adhesive layer 350 is formed on the first fan-out layer 250, such that after flip-chipping the second fan-out layer 150 to the first fan-out layer 250, the second adhesive layer 350 encloses the first through holes 330 and the second through holes 130 of the second fan-out layer 150 that are electrically connected to each other.

[0086] The above descriptions are only the preferred embodiments of the present application and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A fan-out structure is disposed on the substrate and includes: A first fan-out layer is attached to the substrate via a first adhesive layer, the first fan-out layer including a first through-hole through the first adhesive layer, the first through-hole being electrically connected to the substrate; The second fan-out layer is electrically connected to the first fan-out layer via an inverted connection. The second fan-out layer has an interconnect layer formed on a second through-hole and a solder layer on the interconnect layer, the solder layer being bonded to the first through-hole. The interconnect layer and the solder layer together with the first through hole and the second through hole form a connection portion, which is wide in the middle and gradually narrows at both ends away from the middle.

2. The semiconductor structure according to claim 1, characterized in that, The first through hole in the first fan-out layer gradually narrows along a first direction, and the second through hole in the second fan-out layer that is electrically connected to the first through hole gradually narrows along a second direction, wherein the first direction is opposite to the second direction.

3. The semiconductor structure according to claim 1, characterized in that, The first fan-out layer includes a third metal material, which is connected to a third seed layer on the upper surface of the first fan-out layer opposite to the substrate, and the first via penetrates the third metal material and the third seed layer. The first fan-out layer further includes a fourth metal material, which is connected to a fourth seed layer on the lower surface of the first fan-out layer, and the first through hole penetrates the fourth metal material and the fourth seed layer.

4. The semiconductor structure according to claim 1, characterized in that, The first fan-out layer further includes a first dielectric layer, and the first via also passes through the first dielectric layer. The thickness of the first fan-out layer and the first adhesive layer is less than 100 μm.

5. The semiconductor structure according to claim 4, characterized in that, The thickness of the first fan-out layer and the first adhesive layer is less than 20 μm.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: A second adhesive layer is located between the first fan-out layer and the second fan-out layer. The thickness of the first adhesive layer is less than 20 μm, and the thickness of the second adhesive layer is less than 10 μm.

7. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first adhesive layer is formed on the substrate; The first fan-out layer is attached to the substrate via the first adhesive layer; A first via is formed in the first fan-out layer, passing through the first adhesive layer and electrically connected to the substrate; The second fan-out layer is flip-mounted onto the first fan-out layer, and the second fan-out layer is electrically connected to the first fan-out layer. The second fan-out layer has a second through hole, an interconnect layer and a solder layer are formed on the second through hole, the solder layer is bonded to the first through hole, wherein the interconnect layer and the solder layer together with the first through hole and the second through hole form a connection portion, the connection portion having a shape that is wide in the middle and gradually narrows at both ends away from the middle.

8. The method according to claim 7, characterized in that, Forming the first through hole includes: An opening is formed by laser drilling through the first dielectric layer and the first adhesive layer of the first fan-out layer, the opening exposing the pads of the substrate; The opening is filled with metallic material.

9. The method according to claim 7, characterized in that, Electrically connecting the second fan-out layer to the first fan-out layer includes: The interconnect layer and the solder layer constitute a conductive material. The second fan-out layer is flip-chipped onto the first fan-out layer with the first via aligned with the second via, such that the conductive material is located between the first via and the second via.

10. The method according to claim 7, characterized in that, After the first through-hole is formed and before the second fan-out layer is flipped onto the first fan-out layer, a second adhesive layer is formed on the first fan-out layer such that after the second fan-out layer is flipped onto the first fan-out layer, the second adhesive layer surrounds the first through-hole and the second through-hole of the second fan-out layer that are electrically connected to each other.

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