semiconductor devices

Abstract

A semiconductor device is provided. The semiconductor device includes a plurality of first-direction wirings extending in a first direction and a plurality of second-direction wirings extending in a second direction intersecting the first direction. The plurality of first-direction wirings extending in the first direction include: gate wirings spaced apart from each other in the second direction at a gate pitch; first wirings spaced apart from each other in the second direction at a first pitch above the gate wirings; second wirings spaced apart from each other in the second direction at a second pitch above the first wirings; and third wirings spaced apart from each other in the second direction at a third pitch above the second wirings. The ratio between the gate pitch and the second pitch is 6:5.

Description

Technical Field

[0001] Example embodiments generally relate to semiconductor devices. Background Art

[0002] Semiconductor devices have attracted attention as an important factor in the electronics industry due to their features such as miniaturization, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store (logic) data, semiconductor logic devices that perform arithmetic processing on logic data, hybrid semiconductor devices including memory elements and logic elements, and / or the like.

[0003] As the electronics industry rapidly develops, demands and / or expectations for improved performance of semiconductor devices are increasing. For example, demands for high reliability, high speed, and / or multifunctionality are increasing. To meet these desired performance requirements, the structures within semiconductor devices are becoming increasingly complex and highly integrated.

[0004] Since the structure is complicated, the layout of the wiring in the semiconductor device becomes important. One reason may be that when the wiring is efficiently arranged, many wirings can be arranged in a limited area. Summary of the Invention

[0005] Aspects of example embodiments provide a semiconductor device having improved wiring density.

[0006] However, aspects of the exemplary embodiments are not limited to those described herein. The above and other aspects of the exemplary embodiments will become more apparent to those skilled in the art to which the exemplary embodiments pertain by referring to the detailed description of the exemplary embodiments given below.

[0007] According to some example embodiments, a semiconductor device is provided, comprising a plurality of first-direction wirings extending in a first direction and a plurality of second-direction wirings extending in a second direction intersecting the first direction. The plurality of first-direction wirings extending in the first direction include: gate wirings spaced apart from each other in the second direction at a gate pitch; first wirings spaced apart from each other in the second direction at a first pitch above the gate wirings; second wirings spaced apart from each other in the second direction at a second pitch above the first wirings; and third wirings spaced apart from each other in the second direction at a third pitch above the second wirings. The ratio between the gate pitch and the second pitch is 6:5.

[0008] According to some example embodiments, a semiconductor device is provided, the semiconductor device including a plurality of first-direction wirings extending in a first direction and a plurality of second-direction wirings extending in a second direction intersecting the first direction. The plurality of second-direction wirings extending in the second direction include: a fourth wiring spaced apart from one another at a fourth pitch in the first direction; a fifth wiring spaced apart from one another at a fifth pitch in the first direction above the fourth wiring; a sixth wiring spaced apart from one another at a sixth pitch in the first direction above the fifth wiring; and a seventh wiring spaced apart from one another at a seventh pitch in the first direction above the sixth wiring. The ratio between the fourth pitch and the fifth pitch is 5:4.

[0009] According to some example embodiments, a semiconductor device is provided, comprising a plurality of first-direction wirings extending in a first direction and a plurality of second-direction wirings extending in a second direction intersecting the first direction. The plurality of first-direction wirings include: gate wirings spaced apart from each other at a gate pitch in the second direction; and first wirings spaced apart from each other at a first pitch in the second direction above the gate wirings. The plurality of second-direction wirings include: fourth wirings spaced apart from each other at a fourth pitch in the first direction above the gate wirings and below the first wirings; and fifth wirings spaced apart from each other at a fifth pitch in the first direction above the first wirings. The ratio between the gate pitch and the first pitch is 6:4, and the ratio between the fourth pitch and the fifth pitch is 5:4. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0011] Figure 1 is a wiring layout of a semiconductor device according to some example embodiments;

[0012] Figure 2 Is shown separately Figure 1 A layout of wiring extending in the Y direction among the wirings;

[0013] Figure 3 It is along Figure 1 A cross-sectional view taken along line PP';

[0014] Figure 4 Is shown separately Figure 2 Layout of gate wiring;

[0015] Figure 5 Is shown separately Figure 2 The layout of the M2 wiring;

[0016] Figure 6 Is shown separately Figure 2The layout of the M4 wiring;

[0017] Figure 7 Is shown separately Figure 2 The layout of D6 wiring;

[0018] Figure 8 Is shown separately Figure 1 A layout of wiring extending in the X direction among the wirings;

[0019] Figure 9 It is along Figure 8 A cross-sectional view taken along line Q-Q';

[0020] Figure 10 Is shown separately Figure 8 The layout of the M1 wiring;

[0021] Figure 11 Is shown separately Figure 8 The layout of the M3 wiring;

[0022] Figure 12 Is shown separately Figure 8 The layout of the M5 wiring;

[0023] Figure 13 Is shown separately Figure 8 The layout of D7 wiring;

[0024] Figure 14 and Figure 15 is a diagram illustrating a process of determining a wiring pitch of a semiconductor device according to some example embodiments;

[0025] Figure 16 is a layout diagram for illustrating a semiconductor device according to some example embodiments;

[0026] Figure 17 It is along Figure 16 A cross-sectional view taken along line AA of FIG.

[0027] Figure 18 It is along Figure 16 A cross-sectional view taken along line BB;

[0028] Figure 19 It is along Figure 16 A cross-sectional view taken along line CC of ;

[0029] Figure 20 It is along Figure 16 A cross-sectional view taken along line DD;

[0030] Figure 21 It is along Figure 16 A cross-sectional view taken along line EE of FIG.

[0031] Figure 22 and Figure 23 is a cross-sectional view illustrating a semiconductor device according to some example embodiments;

[0032] Figure 24 is a block diagram of a computer system for performing layout design of a semiconductor device according to some example embodiments; and

[0033] Figure 25 is a flowchart for explaining a layout design method and a manufacturing method of a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0034] Some example embodiments will be described below with reference to the accompanying drawings.

[0035] Figure 1 is a wiring layout of a semiconductor device according to some embodiments.

[0036] Reference Figure 1 , the semiconductor device 1 may include a plurality of wirings PC, M2, M4, and D6 each extending in a first direction (e.g., Y direction, hereinafter referred to as Y) and a plurality of wirings M1, M3, M5, and D7 each extending in a second direction (e.g., X direction, hereinafter referred to as X). The first direction Y and the second direction X may intersect each other. For example, the first direction Y may be perpendicular to the second direction X.

[0037] Although not in Figure 1 Although not specifically shown in FIG, such a plurality of wirings PC, M2, M4, D6, M1, M3, M5, and D7 can be used to provide, for example, voltages and / or signals to functional components such as bipolar and / or MOSFET N-type and / or P-type transistors and / or capacitors arranged in the semiconductor device 1. Therefore, the plurality of wirings PC, M2, M4, D6, M1, M3, M5, and D7 can be arranged between the plurality of functional components and the plurality of conductive contacts and / or paths associated with the transistors / capacitors / etc.

[0038] In the semiconductor device 1 according to some example embodiments, the wirings PC, M2, M4, and D6 extending in the first direction Y may be arranged so that the pitch of each of the wirings PC, M2, M4, and D6 has a constant relationship with each other. In addition, the plurality of wirings M1, M3, M5, and D7 extending in the second direction X may be arranged so that the pitch of each of the wirings M1, M3, M5, and D7 has a constant relationship with each other. Here, the pitch may refer to the center-to-center distance between adjacent wirings.

[0039] In the following, reference will be made to Figures 2 to 7 First, the relationship between the wirings PC, M2, M4, and D6 extending in the first direction Y will be described.

[0040] Figure 2 Is shown separately Figure 1 Layout of wiring extending in the Y direction among the wirings. Figure 3 It is along Figure 2 A cross-sectional view taken along line PP'. Figure 4 Is shown separately Figure 2 The gate wiring layout. Figure 5 Is shown separately Figure 2 The layout of the M2 wiring. Figure 6 Is shown separately Figure 2 The layout of the M4 wiring. Figure 7 Is shown separately Figure 2 The layout of the D6 wiring.

[0041] Reference Figures 2 to 7 , the wirings PC, M2, M4, and D6 extending in the first direction Y may include a gate wiring PC, a first wiring M2, a second wiring M4, and a third wiring D6.

[0042] The gate wiring PC may be arranged below the first wiring M2. The gate wiring PC may be arranged on / over the substrate 100, and the first wiring M2 may be arranged on the gate wiring PC. Figures 2 to 7 , although other components arranged in the semiconductor device (e.g., transistors, vias, conductive contacts, and / or the like) are not shown to more easily illustrate the relationship between wiring PC, M2, M4, and D6, for example, the gate wiring PC can be electrically connected to the gate electrode of the transistor and / or serve as the gate electrode of the transistor. Each of wiring PC, M2, M4, and D6 may include a conductive material. For example, the gate wiring PC may include a conductive material such as doped and / or undoped polysilicon and / or a metal such as tungsten. Wiring M2, M4, and D6 may include a material such as aluminum and / or copper.

[0043] The width of the first wiring M2 arranged over the gate wiring PC may be greater than the width of the gate wiring PC.

[0044] The second wiring M4 may be arranged on the first wiring M2. In some example embodiments, although the width of the second wiring M4 may be substantially the same as the width of the first wiring M2, example embodiments are not limited thereto, and the width of the first wiring M2 may be greater than and / or less than the width of the second wiring M4.

[0045] The third wiring D6 may be disposed on the second wiring M4. In some example embodiments, although the width of the third wiring D6 may be wider than the widths of the gate wiring PC, the first wiring M2, and the second wiring M4, example embodiments are not limited thereto.

[0046] The gate wiring PC, the first wiring M2, the second wiring M4, and the third wiring D6 may be insulated from one another by the interlayer insulating film 10. The interlayer insulating film 10 may include a plurality of layers and may include an insulator such as silicon oxide insulator; however, example embodiments are not limited thereto.

[0047] Reference Figure 4 , the gate wirings PC may be spaced apart from each other by a gate pitch GP and extend in the first direction Y. The gate wirings PC may be spaced apart from each other by a gate pitch GP in the second direction X and extend side by side in the first direction Y. For example, the centers of each gate wiring PC may be spaced apart from each other by the gate pitch GP in the second direction X. Alternatively or additionally, the left edge (respectively, the right edge) of each gate wiring PC may be spaced apart from the left edge (respectively, the right edge) of an adjacent gate wiring PC by the gate pitch GP.

[0048] Reference Figure 5 , the first wirings M2 may be spaced apart from each other at a first pitch P2 and extend in the first direction Y. The first wirings M2 may be spaced apart from each other at the first pitch P2 in the second direction X and extend side by side in the first direction Y. For example, the centers of each of the first wirings M2 may be spaced apart from each other at the first pitch P2 in the second direction X. Alternatively or additionally, the left edge (respectively, the right edge) of each first wiring M2 may be spaced apart from the left edge (respectively, the right edge) of an adjacent first wiring M2 at the first pitch P2.

[0049] Reference Figure 6 , the second wirings M4 may be spaced apart from each other at a second pitch P4 and extend in the first direction Y. The second wirings M4 may be spaced apart from each other at a second pitch P4 in the second direction X and extend side by side in the first direction Y. For example, the centers of each second wiring M4 may be spaced apart from each other at the second pitch P4 in the second direction X. Alternatively or additionally, the left edge (respectively, the right edge) of each second wiring M4 may be spaced apart from the left edge (respectively, the right edge) of an adjacent second wiring M4 at the second pitch P4.

[0050] Reference Figure 7 , the third wirings D6 may be spaced apart from each other at a third pitch P6 and may extend in the first direction Y. The third wirings D6 may be spaced apart from each other at a third pitch P6 in the second direction X and extend side by side in the first direction Y. For example, the centers of each of the third wirings D6 may be spaced apart from each other at the third pitch P6 in the second direction X. Alternatively or additionally, the left edge (respectively, the right edge) of each third wiring D6 may be spaced apart from the left edge (respectively, the right edge) of an adjacent third wiring D6 at the third pitch P6.

[0051] In some example embodiments, the ratio (e.g., gear ratio) between the gate pitch GP of the gate wiring PC and the first pitch P2 of the first wiring M2 satisfies 6:4. For example, the gate pitch GP is greater than the first pitch P2. Here, the ratio of 6:4 does not include process errors generated in the production / manufacturing process of the gate wiring PC and the first wiring M2. Therefore, although this ratio may vary slightly to 6.01:4, 6:3.99, etc. depending on the actual manufacturing process of the gate wiring PC and the first wiring M2, such a value can be considered as the ratio being designed and manufactured to 6:4 according to the technical concept of the example embodiments.

[0052] All ratios described below should be understood as numerical values ​​that may not necessarily reflect slight differences in manufacturing / process conditions that may occur in actual manufacturing / fabrication processes.

[0053] In addition, in some example embodiments, the ratio (e.g., gear ratio) between the gate pitch GP of the gate wiring PC, the first pitch P2 of the first wiring M2, and the second pitch P4 of the second wiring M4 is / satisfies 6:4:5. The second pitch P4 may be larger than the first pitch P2 and may be smaller than the gate pitch GP.

[0054] Furthermore, in some example embodiments, a ratio (e.g., a gear ratio) among the gate pitch GP of the gate wiring PC, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6 is / satisfies 6:4:5:9. The third pitch P6 may be greater than the gate pitch GP, the first pitch P2, and the second pitch P4.

[0055] In some example embodiments, a ratio (eg, a gear ratio) between the gate pitch GP of the gate wiring PC and the second pitch P4 of the second wiring M4 satisfies 6:5.

[0056] In some example embodiments, a ratio (eg, a gear ratio) among the gate pitch GP of the gate wire PC, the second pitch P4 of the second wire M4 , and the third pitch P6 of the third wire D6 is / satisfies 6:5:9.

[0057] In some example embodiments, a ratio (eg, a gear ratio) between the gate pitch GP of the gate wiring PC and the third pitch P6 of the third wiring D6 satisfies 6:9.

[0058] In some example embodiments, a ratio (eg, a gear ratio) between the first pitch P2 of the first wiring M2 and the second pitch P4 of the second wiring M4 satisfies 4:5.

[0059] In some example embodiments, a ratio (eg, a gear ratio) among the first pitch P2 of the first wire M2 , the second pitch P4 of the second wire M4 , and the third pitch P6 of the third wire D6 satisfies 4:5:9.

[0060] In some example embodiments, a ratio (eg, a gear ratio) between the second pitch P4 of the second wire M4 and the third pitch P6 of the third wire D6 satisfies 5:9.

[0061] On the other hand, any combination of ratios not described above may also be achieved according to example embodiments, wherein the ratios among the gate pitch GP of the gate wiring PC, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6 satisfy 6:4:5:9.

[0062] The following will refer to Figures 8 to 13 The relationship among the wirings M1 , M3 , M5 , and D7 extending in the second direction X is described.

[0063] Figure 8 Is shown separately Figure 1 Layout of wiring extending in the X direction among the wirings. Figure 9 It is along Figure 8 A cross-sectional view taken along line Q-Q'. Figure 10 Is shown separately Figure 8 The layout of the M1 wiring. Figure 11 Is shown separately Figure 8 The layout of the M3 wiring. Figure 12 Is shown separately Figure 8 The layout of the M5 wiring. Figure 13 Is shown separately Figure 8 The layout of the D7 wiring.

[0064] Reference Figures 8 to 13 The wirings M1 , M3 , M5 , and D7 extending in the second direction X may include a fourth wiring M1 , a fifth wiring M3 , a sixth wiring M5 , and a seventh wiring D7 .

[0065] Although the fourth wiring M1 is different from the gate wiring PC in the extension direction, the fourth wiring M1 can be provided on / above the gate wiring PC. There may be a contact and / or via (not shown) connecting at least one of the fourth wirings M1 to at least one of the gate wirings PC; however, example embodiments are not limited thereto. Figure 9 The wirings PC, M2, M4 and D6 extending in the first direction Y are also conceptually shown to illustrate the height relationship between the wirings M1, M3, M5 and D7 extending in the second direction X and the wirings PC, M2, M4 and D6 extending in the first direction Y.

[0066] Similarly, although Figures 8 to 13 Other components provided in the semiconductor device (such as transistors, paths, conductive contacts, etc.) are not shown to more easily illustrate the relationship between the wirings M1, M3, M5 and D7, but, for example, the fourth wiring M1 can be used as a wiring that electrically connects the drain of the first transistor and the source of the second transistor to each other.

[0067] The fifth wiring M3 may be disposed on the fourth wiring M1. Furthermore, although the fifth wiring M3 extends in a different direction than the first wiring M2, the fifth wiring M3 may be disposed on the first wiring M2. Contacts and / or vias (not shown) may be present connecting at least one of the fifth wirings M3 to at least one of the first wirings M2; however, example embodiments are not limited thereto. In some example embodiments, the width of the fifth wiring M3 may be narrower than that of the fourth wiring M1, but example embodiments are not limited thereto.

[0068] The sixth wiring M5 may be disposed on the fifth wiring M3. Furthermore, the sixth wiring M5 extends in a direction different from the second wiring M4 and may be disposed on the second wiring M4. Contacts and / or vias (not shown) may be present connecting at least one of the sixth wiring M5 to at least one of the second wiring M4; however, example embodiments are not limited thereto. In some example embodiments, the width of the sixth wiring M5 may be wider than the width of the fourth wiring M1 and the width of the fifth wiring M3, but example embodiments are not limited thereto.

[0069] The seventh wiring D7 may be disposed on the sixth wiring M5. Furthermore, although the seventh wiring D7 extends in a different direction than the third wiring D6, the seventh wiring D7 may be disposed on the third wiring D6. Contacts and / or vias (not shown) may be present connecting at least one of the seventh wiring D7 to at least one of the third wiring D6; however, example embodiments are not limited thereto. In some embodiments, the width of the seventh wiring D7 may be wider than the width of the fourth wiring M1, the width of the fifth wiring M3, and the width of the sixth wiring M5, but embodiments are not limited thereto.

[0070] The fourth wiring M1, the fifth wiring M3, the sixth wiring M5, and the seventh wiring D7 may be insulated from one another by the interlayer insulating film 10. In addition, the fourth wiring M1, the fifth wiring M3, the sixth wiring M5, and the seventh wiring D7 may be insulated from the gate wiring PC, the first wiring M2, the second wiring M4, and the third wiring D6 by the interlayer insulating film 10. In some example embodiments, there may be vias / contacts (not shown) connecting each of the wirings PC, M1, M2, M3, M4, M5, D6, and D7 to one another.

[0071] Reference Figure 10, the fourth wirings M1 may be spaced apart from each other at a fourth pitch P1 and may extend in the second direction X. The fourth wirings M1 may be spaced apart from each other at a fourth pitch P1 in the first direction Y and may extend side by side in the second direction X. For example, the center of each of the fourth wirings M1 may be spaced apart from each other at the fourth pitch P1 in the first direction Y. Alternatively or additionally, the top edge (respectively, the bottom edge) of each of the fourth wirings M1 may be spaced apart from the top edge (respectively, the bottom edge) of an adjacent fourth wiring M1 at the fourth pitch P1.

[0072] Reference Figure 11 , the fifth wirings M3 may be spaced apart from each other at a fifth pitch P3 and may extend in the second direction X. The fifth wirings M3 may be spaced apart from each other at a fifth pitch P3 in the first direction Y and may extend side by side in the second direction X. For example, the centers of each of the fifth wirings M3 may be spaced apart from each other at the fifth pitch P3 in the first direction Y. Alternatively or additionally, the top edge (respectively, the bottom edge) of each of the fifth wirings M3 may be spaced apart from the top edge (respectively, the bottom edge) of an adjacent fifth wiring M3 at the fifth pitch P3.

[0073] Reference Figure 12 , the sixth wirings M5 may be spaced apart from each other at a sixth pitch P5 and may extend in the second direction X. The sixth wirings M5 may be spaced apart from each other at a sixth pitch P5 in the first direction Y and may extend side by side in the second direction X. For example, the centers of each of the sixth wirings M5 may be spaced apart from each other at the sixth pitch P5 in the first direction Y. Alternatively or additionally, the top edge (respectively, the bottom edge) of each of the sixth wirings M5 may be spaced apart from the top edge (respectively, the bottom edge) of an adjacent sixth wiring M5 at the sixth pitch P5.

[0074] Reference Figure 13 , the seventh wiring lines D7 may be spaced apart from each other at a seventh pitch P7 and may extend in the second direction X. The seventh wiring lines D7 may be spaced apart from each other at a seventh pitch P7 in the first direction Y and may extend side by side in the second direction X. For example, the center of each of the seventh wiring lines D7 may be spaced apart from each other at the seventh pitch P7 in the first direction Y. Alternatively or additionally, the top edge (respectively, the bottom edge) of each of the seventh wiring lines D7 may be spaced apart from the top edge (respectively, the bottom edge) of an adjacent seventh wiring line D7 at the seventh pitch P7.

[0075] In some example embodiments, a ratio between a fourth pitch P1 of the fourth wiring M1 and a fifth pitch P3 of the fifth wiring M3 satisfies 5: 4. The fourth pitch P1 may be greater than the fifth pitch P3.

[0076] Furthermore, in some example embodiments, a ratio of the fourth pitch P1 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3, and the sixth pitch P5 of the sixth wiring M5 is / satisfies 5:4:6. The sixth pitch P5 may be greater than the fourth pitch P1 and the fifth pitch P3.

[0077] Furthermore, in some example embodiments, a ratio among the fourth pitch P1 of the fourth wiring M1 , the fifth pitch P3 of the fifth wiring M3 , the sixth pitch P5 of the sixth wiring M5 , and the seventh pitch P7 of the seventh wiring D7 is / satisfies 5:4:6:10.

[0078] In some example embodiments, a ratio between the fourth pitch P1 of the fourth wiring M1 and the sixth pitch P5 of the sixth wiring M5 is / satisfies 5:6.

[0079] In some example embodiments, a ratio among the fourth pitch P1 of the fourth wiring M1 , the sixth pitch P5 of the sixth wiring M5 , and the seventh pitch P7 of the seventh wiring D7 is / satisfies 5:6:10.

[0080] In some example embodiments, a ratio between the fourth pitch P1 of the fourth wiring M1 and the seventh pitch P7 of the seventh wiring D7 is / satisfies 5:10.

[0081] In some example embodiments, a ratio between the fifth pitch P3 of the fifth wiring M3 and the sixth pitch P5 of the sixth wiring M5 is / satisfies 4:6.

[0082] Furthermore, in some example embodiments, a ratio among the fifth pitch P3 of the fifth wiring M3 , the sixth pitch P5 of the sixth wiring M5 , and the seventh pitch P7 of the seventh wiring D7 is / satisfies 4:6:10.

[0083] In some example embodiments, a ratio between the sixth pitch P5 of the sixth wiring M5 and the seventh pitch P7 of the seventh wiring D7 is / satisfies 6:10.

[0084] On the other hand, in an example embodiment, any combination of ratios not described above may also be achieved, wherein the ratios among the fourth pitch P1 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7 satisfy 5:4:6:10.

[0085] Figure 14 and Figure 15 is a diagram illustrating a process of determining a wiring pitch of a semiconductor device according to some example embodiments.

[0086] Reference Figure 14In order to determine a good (e.g., preferred) ratio between the gate pitch GP of the gate wiring PC extending in the first direction Y, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6, n simulations can be performed while changing the first to third pitches P2, P4, and P6 (n is a very large natural number).

[0087] Specifically, while changing the first pitch P2 of the first wiring M2 from a1 to an, the second pitch P4 of the second wiring M4 from b1 to bn, and the third pitch P6 of the third wiring D6 from c1 to cn, the least common multiples (LCM) M1 to Mn can be obtained for each case.

[0088] The case with the smallest least common multiple among the least common multiples (LCM) M1 to Mn calculated for each case corresponds to a case in which a large number (e.g., the maximum number) of wirings can be arranged within a predetermined (or alternatively, variably determined) limited area. In this case, the ratios of the gate pitch GP of the gate wiring PC, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6 satisfy 6:4:5:9.

[0089] Similarly, refer to Figure 15 In order to obtain an improved (e.g., preferred) ratio between the fourth pitch P1 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7 extending in the second direction X, n simulations may be performed while changing the fifth to seventh pitches P3, P5, and P7.

[0090] Specifically, while changing the fifth pitch P3 of the fifth wiring M3 from d1 to dn, the sixth pitch P5 of the sixth wiring M5 from e1 to en, and the seventh pitch P7 of the seventh wiring D7 from f1 to fn, the least common multiples (LCM) L1 to Ln are obtained for each case.

[0091] The case with the smallest least common multiple among the least common multiples (LCM) L1 to Ln calculated for each case is the case in which the most wirings can be arranged within a limited area. In this case, the ratios of the fourth pitch P1 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7 satisfy 5:4:6:10.

[0092] For example, when the wirings PC, M2, M4, and D6 extending in the first direction Y are arranged in the semiconductor device so that the ratios of the gate pitch GP of the gate wiring PC, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6 satisfy 6:4:5:9, the wiring density of the semiconductor device can be improved because as many wirings as possible can be provided in a limited area. Even in a case where the ratio between the pitch of the lower wiring (such as the gate pitch GP) and the pitch of the upper wiring (such as the first pitch P2) does not change monotonically, the wiring density of the semiconductor device can be improved.

[0093] In addition, when the wirings M1, M3, M5 and D7 extending in the second direction X are arranged in the semiconductor device so that the ratio between the fourth pitch P1 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth wiring M5 and the seventh pitch P7 of the seventh wiring D7 satisfies 5:4:6:10, since as many wirings as possible can be arranged in a limited area, the wiring density of the semiconductor device can be improved.

[0094] Although other components provided in the semiconductor device are not shown and described to focus on describing the relationship between the above wirings, a practical implementation example of the gate wiring PC and the fourth wiring M1 described above will be described below. However, example embodiments are not limited thereto.

[0095] On the other hand, in the following figures, although a fin transistor FinFET including a channel region having a fin pattern shape is shown as an example of a semiconductor device, example embodiments are not limited thereto. According to some embodiments, the semiconductor device may include a tunneling field effect transistor (TFET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. In addition, according to some embodiments, the semiconductor device may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), and / or the like.

[0096] Figure 16 is a layout diagram for illustrating a semiconductor device according to some embodiments. Figure 17 It is along Figure 16 Cross-sectional view taken along line AA. Figure 18 It is along Figure 16 A cross-sectional view taken along line BB. Figure 19 It is along Figure 16 Cross-sectional view taken along line CC. Figure 20 It is along Figure 16 A cross-sectional view taken along line DD. Figure 21 It is along Figure 16 Cross-sectional view taken along line EE.

[0097] Reference Figures 16 to 21 , a semiconductor device according to some example embodiments may be formed on a substrate 100 .

[0098] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI), or include bulk silicon or silicon-on-insulator (SOI). Alternatively or additionally, the substrate 100 may be a silicon substrate or include a silicon substrate, or may include, but is not limited to, other materials such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide.

[0099] The substrate 100 may include a first active region AR1 and a second active region AR2. For ease of description, hereinafter, the first active region AR1 will be described as a PFET region and the second active region AR2 will be described as an NFET region; however, example embodiments are not limited thereto.

[0100] In some example embodiments, the first active region AR1 and the second active region AR2 may be separated by an element separation film I2. Figures 19 to 21 As shown, the element separation film I2 extends in the second direction X and can separate the first active region AR1 from the second active region AR2.

[0101] A plurality of active patterns F1 to F4 may be formed on the substrate 100. For example, the first active pattern F1 and the second active pattern F2 may be formed on the first active region AR1, and the third active pattern F3 and the fourth active pattern F4 may be formed on the second active region AR2. In some example embodiments, each of the active patterns F1 to F4 may include a fin pattern protruding from the upper surface of the substrate 100.

[0102] The first to fourth active patterns F1 to F4 may be spaced apart from each other and may extend side by side. For example, each of the first to fourth active patterns F1 to F4 may extend in the second direction X. In addition, the first to fourth active patterns F1 to F4 may be sequentially arranged along the first direction Y. In some example embodiments, the first to fourth active patterns F1 to F4 may each be formed over the first to third cell regions CR1 to CR3.

[0103] In some example embodiments, the first cell separation film I1a and the second cell separation film I1b may intersect the first to fourth active patterns F1 to F4. The first cell separation film I1a and the second cell separation film I1b may define the first to third cell regions CR1 to CR3 through the first to fourth active patterns F1 to F4. For example, Figure 17 and Figure 18As shown, the first cell separation film I1a may define the first cell region CR1 and the second cell region CR2 through the first active pattern F1. In addition, the second cell separation film I1b may define the first cell region CR1 and the third cell region CR3 through the first active pattern F1.

[0104] The field insulating film 105 may be formed on the substrate 100. In some example embodiments, the field insulating film 105 may surround some of the side surfaces of the first to fourth active patterns F1 to F4. Figure 19 As shown, some of the first to fourth active patterns F1 to F4 may protrude upward from the field insulating film 105 .

[0105] The field insulating film 105 may include, for example, but is not limited to, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), and combinations thereof.

[0106] The gate electrodes G1 to G3 may each intersect the first to fourth active patterns F1 to F4. In some example embodiments, the gate electrodes G1 to G3 may correspond to the gate wiring ( Figure 4 PC). In addition, in some example embodiments, although not specifically shown, the gate wiring ( Figure 4 PC) may correspond to wiring electrically connected to the gate electrodes G1 to G3.

[0107] The gate electrodes G1 to G3 may each include a gate conductive film 130. The gate conductive film 130 may include, for example, but not limited to, at least one of Ti, Ta, W, Al, Co, and combinations thereof. In addition to metal, the gate conductive film 130 may include, for example, doped or undoped single crystal or polycrystalline silicon, or doped or undoped single crystal or polycrystalline silicon germanium.

[0108] Although the gate conductive film 130 is shown as a single film in the drawings, example embodiments are not limited thereto. Unlike the illustrated example, the gate conductive film 130 may be formed by stacking a plurality of conductive materials. For example, the gate conductive film 130 may include a work function adjustment film for adjusting the work function and / or a filling conductive film for filling a space formed by the work function adjustment film. The work function adjustment film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W and / or Al.

[0109] The gate conductive film 130 may be formed by, for example, a replacement process, but is not limited to the replacement process.

[0110] In some example embodiments, first and second dummy gate electrodes DG1 and DG2 may be formed to intersect the first to fourth active patterns F1 to F4. The first dummy gate electrode DG1 may extend in the first direction Y between the first and second cell regions CR1 and CR2, and the second dummy gate electrode DG2 may extend in the first direction Y between the first and third cell regions CR1 and CR3.

[0111] In some example embodiments, the first dummy gate electrode DG1 may be formed on the first cell separation film I1a, and the second dummy gate electrode DG2 may be formed on the second cell separation film I1b. In some example embodiments, the first dummy gate electrode DG1 and the second dummy gate electrode DG2 may be omitted. For example, the first cell separation film I1a and the second cell separation film I1b may be formed to fill the regions occupied by the first dummy gate electrode DG1 and the second dummy gate electrode DG2, respectively.

[0112] The gate dielectric film 120 may be interposed between the first to fourth active patterns F1 to F4 and the gate conductive film 130. For example, the gate dielectric film 120 may extend along the sidewalls and bottom surface of the gate conductive film 130. However, example embodiments are not limited thereto, and the gate dielectric film 120 may extend only along the bottom surface of the gate conductive film 130.

[0113] In some example embodiments, a portion of the gate dielectric film 120 may be interposed between the field dielectric film 105 and the gate conductive film 130. For example, Figure 19 As shown, the gate dielectric film 120 may extend along the upper surface of the field insulating film 105 .

[0114] The gate dielectric film 120 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include, for example, but is not limited to, hafnium oxide.

[0115] The gate spacer 140 may be formed on the substrate 100 and the field insulating film 105. In addition, the gate spacer 140 may extend along both sides of the gate conductive film 130. Therefore, the gate spacer 140 may intersect the first to fourth active patterns F1 to F4. For example, the gate spacer 140 may extend in the first direction Y.

[0116] The gate spacer 140 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0117] The gate capping pattern 150 may cover the upper surface of the gate conductive film 130. For example, the gate capping pattern 150 may extend along the upper surface of the gate conductive film 130. In addition, the gate capping pattern 150 may extend in the first direction Y.

[0118] The first source / drain region 160 may be formed on the first active region AR1. For example, the first source / drain region 160 may be formed in the first active pattern F1 and the second active pattern F2 on both sides of the gate conductive film 130. However, the first source / drain region 160 may be insulated from the gate conductive film 130. For example, the first source / drain region 160 may be separated from the gate conductive film 130 by a gate spacer 140.

[0119] The second source / drain region 260 may be formed on the second active region AR2. For example, the second source / drain region 260 may be formed in the third active pattern F3 and the fourth active pattern F4 on both sides of the gate conductive film 130. However, the second source / drain region 260 may be insulated from the gate conductive film 130. For example, the second source / drain region 260 may be separated from the gate conductive film 130 by the gate spacer 140.

[0120] Each of the first and second source / drain regions 160 and 260 may include an epitaxial layer, eg, a doped or undoped hetero- or homo-epitaxial layer, formed in a corresponding active pattern among the first to fourth active patterns F1 to F4 .

[0121] When the semiconductor device formed in the first active region AR1 is a PFET, the first source / drain region 160 may include p-type impurities and / or impurities for preventing or reducing the amount of diffusion of p-type impurities. For example, the first source / drain region 160 may include at least one of a Group III element such as B, In, Ga, and Al, and a combination thereof, and may include a Group IV element such as C, Ge, and / or Sn, however, example embodiments are not limited thereto.

[0122] When the semiconductor device formed in the second active region AR2 is an NFET, the second source / drain region 260 may include n-type impurities and / or impurities for preventing or reducing the amount of diffusion of n-type impurities. For example, the second source / drain region 260 may include at least one of a Group V element such as P, Sb, As, and a combination thereof, and may include a Group IV element such as C, Ge, and / or Sn; however, example embodiments are not limited thereto.

[0123] Although each of the first source / drain region 160 and the second source / drain region 260 is shown as a single film, example embodiments are not limited thereto. For example, the first source / drain region 160 and the second source / drain region 260 may be formed of a plurality of films each containing a different impurity concentration.

[0124] A plurality of interlayer insulating films 110, 210, 310, and 410 may be formed on the substrate 100. For example, first to fourth interlayer insulating films 110, 210, 310, and 410 sequentially stacked may be formed on the substrate 100.

[0125] In some example embodiments, the first interlayer insulating film 110 and the second interlayer insulating film 210 may be formed to cover the field insulating film 105, the first source / drain region 160, the second source / drain region 260, the gate spacer 140, and the gate capping pattern 150. For example, the first interlayer insulating film 110 may cover the upper surface of the field insulating film 105, the upper surface of the first source / drain region 160, the upper surface of the second source / drain region 260, and the side surfaces of the gate spacer 140. Furthermore, for example, the second interlayer insulating film 210 may cover the upper surface of the gate capping pattern 150 and the upper surface of the first interlayer insulating film 110.

[0126] The first to fourth interlayer insulating films 110 , 210 , 310 , and 410 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than silicon oxide.

[0127] Furthermore, in some example embodiments, a plurality of source / drain contacts CA11 to CA33 may pass through the first interlayer insulating film 110 and the second interlayer insulating film 210 and may be connected to the first source / drain region 160 and / or the second source / drain region 260. For example, the second source / drain contact CA12, the fourth source / drain contact CA22, and the eighth source / drain contact CA32 may be connected to the first source / drain region 160. Furthermore, for example, the third source / drain contact CA13, the sixth source / drain contact CA23, and the ninth source / drain contact CA33 may be connected to the second source / drain region 260. In some example embodiments, the first source / drain contact CA11, the fourth source / drain contact CA21, and the seventh source / drain contact CA31 may be connected to both the first source / drain region 160 and the second source / drain region 260. The plurality of source / drain contacts CA11 to CA33 may be or include doped polysilicon and / or a metal such as tungsten; however, example embodiments are not limited thereto.

[0128] In some example embodiments, a plurality of source / drain vias VA11 to VA33 may pass through the third interlayer insulating film 310 and may be connected to the source / drain contacts CA11 to CA33. The source / drain vias VA11 to VA33 may include a metal such as tungsten; however, example embodiments are not limited thereto.

[0129] In some example embodiments, a plurality of gate vias VB1 to VB3 may pass through the gate capping pattern 150, the second interlayer insulating film 210, and the third interlayer insulating film 310 and may be connected to the gate electrodes G1 to G3. The gate vias VB1 to VB3 may include doped polysilicon and / or a metal such as tungsten; however, example embodiments are not limited thereto.

[0130] In some example embodiments, the plurality of wiring patterns M1 may be disposed at the same level as one another. As used herein, the expression "disposed at the same level" means being formed at the same height based on the upper surface of the substrate 100. Furthermore, as used herein, the term "same" includes not only completely identical things but also slight differences that may occur due to process margins, etc.

[0131] In some example embodiments, the plurality of wiring patterns M1 may correspond to the fourth wiring pattern ( Figure 10 of M1).

[0132] For example, Figure 16 and Figure 17 As shown, the first connection wiring CW1 is formed in the fourth interlayer insulating film 410 and can be connected to the fourth source / drain via VA21 and the first gate via VB1. In addition, the second wiring OW is formed in the fourth interlayer insulating film 410 and can be connected to the seventh source / drain via VA31.

[0133] For example, Figure 16 and Figure 18 As shown, the first wiring IW is formed in the fourth interlayer insulating film 410 and can be connected to the second gate via VB2. In addition, the second connection wiring CW2 is formed in the fourth interlayer insulating film 410 and can be connected to the first source / drain via VA11 and the third gate via VB3.

[0134] Furthermore, in some example embodiments, the plurality of wiring patterns M1 may be formed by the same fabrication / manufacturing process.

[0135] In some example embodiments, the plurality of wiring patterns M1 may be disposed at the same level as the first power wiring VDD and / or the second power wiring VSS.

[0136] For example, Figure 16 and Figure 21As shown, the first power supply wiring VDD is formed in the fourth interlayer insulating film 410 and can be connected to the second source / drain path VA12, the fifth source / drain path VA22, and the eighth source / drain path VA32. In addition, the second power supply wiring VSS is formed in the fourth interlayer insulating film 410 and can be connected to the third source / drain path VA13, the sixth source / drain path VA23, and the ninth source / drain path VA33.

[0137] Furthermore, in some example embodiments, the plurality of wiring patterns M1 may be formed at the same level as the first power wiring VDD and / or the second power wiring VSS.

[0138] Therefore, a semiconductor device can be provided in which power loss and PnR resource loss are reduced (for example, by reducing the use of auxiliary upper wiring).

[0139] In some example embodiments, the source / drain contacts CA11 to CA33 may each include a first barrier film 190 and a first filling film 192. The first barrier film 190 may extend along an upper surface of the first source / drain region 160, an upper surface of the second source / drain region 260, a side surface of the first interlayer insulating film 110, and a side surface of the second interlayer insulating film 210. The first filling film 192 may fill a space formed by the first barrier film 190.

[0140] In some example embodiments, the source / drain vias VA11 to VA33 may each include a second barrier film 290 and a second filling film 292. The second barrier film 290 may extend along upper surfaces of the source / drain contacts CA11 to CA33 and side surfaces of the third interlayer insulating film 310. The second filling film 292 may fill a space formed by the second barrier film 290.

[0141] In some example embodiments, the gate vias VB1 to VB3 may each include a third barrier film 390 and a third filling film 392. The third barrier film 390 may extend along an upper surface of the gate conductive film 130, side surfaces of the gate capping pattern 150, side surfaces of the second interlayer insulating film 210, and side surfaces of the third interlayer insulating film 310. The third filling film 392 may fill a space formed by the third barrier film 390.

[0142] In some example embodiments, the first power wiring VDD, the second power wiring VSS, and the plurality of wiring patterns M1 may each include a fourth barrier film 490 and a fourth filling film 492. The fourth barrier film 490 may extend along upper surfaces of the source / drain vias VA11 to VA33, upper surfaces of the gate vias VB1 to VB3, an upper surface of the third interlayer insulating film 310, and side surfaces of the fourth interlayer insulating film 410. The fourth filling film 492 may fill a space formed by the fourth barrier film 490.

[0143] The first to fourth barrier films 190 to 490 may include a metal or a metal nitride for preventing or reducing the diffusion amount of the first to fourth filling films 192 to 492. For example, the first to fourth barrier films 190 to 490 may include, but are not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof.

[0144] The first to fourth filling films 192 to 492 may include, but are not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and alloys thereof.

[0145] The source / drain paths VA11 to VA33, the gate paths VB1 to VB3, the first power supply wiring VDD, the second power supply wiring VSS, and the wiring pattern M1 can be formed by, for example, (but not limited to), a single damascene process. For example, the source / drain paths VA11 to VA33, the gate paths VB1 to VB3, the first power supply wiring VDD, the second power supply wiring VSS, and the wiring pattern M1 can be formed by, for example, a dual damascene process or another wiring process.

[0146] The following will refer to Figure 22 and Figure 23 Another exemplary embodiment of the gate wiring PC and the fourth wiring M1 described above will be described. First, the above reference will be briefly described or omitted. Figures 16 to 21 The repeated portion of the content described.

[0147] Figure 22 and Figure 23 is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0148] Figure 22 It is along Figure 16 The cross-sectional view taken along line AA, Figure 23 It is along Figure 16 Cross-sectional view taken along line CC.

[0149] Reference Figure 22 and Figure 23In the semiconductor device according to some embodiments, each of the first to fourth active patterns F1 to F4 includes a plurality of line patterns 114 , 116 , and 118 .

[0150] For example, each of the first to fourth active patterns F1 to F4 may include first to third line patterns 114, 116, and 118 sequentially stacked on the substrate 100 and spaced apart from each other. For example, the first line pattern 114 may be spaced apart from the substrate 100 in the third direction Z, the second line pattern 116 may be spaced apart from the first line pattern 114 in the third direction Z, and the third line pattern 118 may be spaced apart from the second line pattern 116 in the third direction Z.

[0151] Each of the first to third line patterns 114, 116, and 118 may extend in the second direction X. In addition, the first to third line patterns 114, 116, and 118 may pass through each of the first to third gate electrodes G1 to G3. Figure 22 As shown, the first to third gate electrodes G1 to G3 may each surround outer surfaces of the first to third line patterns 114 , 116 , and 118 .

[0152] Although the cross sections of the first to third line patterns 114, 116, and 118 are Figure 23 1 and 2. For example, the cross-sections of the first to third line patterns 114, 116, and 118 may be other polygonal shapes or circular shapes, respectively.

[0153] In some example embodiments, each of the first to fourth active patterns F1 to F4 may further include a fin pattern 112 protruding from the upper surface of the substrate 100 and extending in the second direction X. The fin pattern 112 may be, for example, disposed under the first line pattern 114 .

[0154] Figure 24 is a block diagram of a computer system for performing layout design of a semiconductor device according to some embodiments.

[0155] Reference Figure 24 The computer system may include a CPU 11, a working memory 30, an I / O device 50, and an auxiliary memory 70. Here, the computer system shown may be provided as a dedicated device for layout design of semiconductor devices according to some example embodiments. In some example embodiments, the computer system may include various design and verification simulation programs.

[0156] The CPU 11 can execute computer-readable instructions, such as software (applications, operating systems, device drivers, and / or the like) to be executed on the computer system. When executed by the CPU 11, the computer-readable instructions can cause the CPU to perform various functions. The CPU 11 can then execute the operating system loaded into the working memory 30. The CPU 11 can execute various applications (applications) driven by the operating system. For example, the CPU 11 can execute the layout design tool 32, the placement and routing tool 34, and / or the OPC tool 36 loaded into the working memory 30.

[0157] An operating system and / or application programs may be loaded into the working memory 30. An operating system image (not shown) stored in the secondary memory 70 may be loaded into the working memory 30 based on a startup sequence when the computer system boots up. The operating system may support all I / O operations of the computer system.

[0158] A layout design tool 32 for layout design of a semiconductor device according to some embodiments may be loaded from the auxiliary memory 70 into the working memory 30. Subsequently, a place and route tool 34 may be loaded from the auxiliary memory 70 into the working memory 30 for placing the designed standard cells, rearranging internal wiring patterns in the placed standard cells, and routing the placed standard cells.

[0159] When the internal wiring patterns in the standard cells thus laid out are laid out and / or rearranged, the ratio between the pitches of the wiring patterns described above may be applied.

[0160] Specifically, the wiring pattern may be laid out or rearranged in the standard cell so that the ratios of the gate pitch GP of the gate wiring PC extending in the first direction Y, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6 satisfy 6:4:5:9. Furthermore, the wiring pattern may be laid out or rearranged in the standard cell so that the ratios of the fourth pitch P1 of the fourth wiring M1 extending in the second direction X, the fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7 satisfy 5:4:6:10.

[0161] Subsequently, an optical proximity correction (OPC) tool 36 for performing OPC on the designed layout data may be loaded from the auxiliary memory 70 to the working memory 30 .

[0162] I / O device 50 can control user input and output from the user interface device. For example, I / O device 50 includes a keyboard and a monitor and can receive information input from the user. The user can use I / O device 50 to receive information input regarding a semiconductor region or data channel whose operating characteristics require adjustment. In addition, the processing progress or processing results of OPC tool 36 can be displayed via I / O device 50.

[0163] The auxiliary memory 70 may be provided as a storage medium of the computer system and may store application programs, operating system images, and various data.

[0164] The system interconnector 90 may be or include a system bus for providing a network within the computer system. The CPU 11, the working memory 30, the I / O device 50, and the auxiliary memory 70 are electrically connected through the system interconnector 90 and can exchange data with each other.

[0165] Figure 25 is a flowchart for explaining a layout design method and a manufacturing method of a semiconductor device according to some embodiments.

[0166] Reference Figure 25 , the advanced design of semiconductor integrated circuits can be based on Figure 24 The computer system described executes (S10). The high-level design can represent a description of the designed integrated circuit in the native language of a computer language. For example, a native language such as C language can be used for the high-level design. The circuit designed by the high-level design can be more specifically represented by memory transfer level (RTL) coding or simulation. Subsequently, the code generated by the memory transfer level coding is converted into a netlist and can be synthesized by the entire semiconductor component. The synthesized principle circuit is verified by a simulation tool, and an adjustment process is given based on the verification results.

[0167] Subsequently, a layout design for implementing the logically prepared semiconductor integrated circuit on the silicon substrate may be performed (S20). For example, the layout design may be performed with reference to a schematic circuit synthesized from a high-level design or a netlist corresponding thereto. The layout design may include a wiring process for placing and connecting various standard cells provided from a cell library according to specified design rules.

[0168] Layout may be or include the process of actually defining the form or size of the patterns used to form transistors and metal wiring to be formed on a silicon substrate. For example, to actually form an inverter circuit on a silicon substrate, layout patterns such as PFETs, NFETs, P-wells, N-wells, gate electrodes, and wiring patterns to be laid out thereon may be appropriately laid out, such as by designing a layout for a photomask used in the manufacture of semiconductor devices.

[0169] When the layout pattern is laid out in this manner, the ratio between the pitches of the wiring patterns described above can be applied.

[0170] Specifically, the layout pattern may be arranged so that a ratio of 6:4:5:9 is satisfied among the gate pitch GP of the gate wiring PC extending in the first direction Y, the first pitch P2 of the first wiring M2, the second pitch P4 of the second wiring M4, and the third pitch P6 of the third wiring D6. Furthermore, the layout pattern may be arranged so that a ratio of 5:4:6:10 is satisfied among the fourth pitch P1 of the fourth wiring M1, the fifth pitch P3 of the fifth wiring M3, the sixth pitch P5 of the sixth wiring M5, and the seventh pitch P7 of the seventh wiring D7 extending in the second direction X.

[0171] Subsequently, wiring of the selected and laid-out standard cells may be performed. Specifically, upper wiring (wiring pattern) may be laid out on the laid-out standard cells. By performing wiring, the laid-out standard cells may be interconnected according to the design.

[0172] After routing, the layout may be verified for any design rule violations. Items to be verified may include DRC (Design Rule Check), ERC (Electrical Rule Check), LVS (Layout Versus Schematic), and / or similar items.

[0173] Subsequently, an optical proximity correction (OPC) process (S30) may be performed. The layout pattern provided by the layout design may be implemented on the silicon substrate using a photolithography process. At this time, optical proximity correction may be a technique for correcting deformation phenomena that may occur in the photolithography process.

[0174] Subsequently, a photomask may be manufactured based on the layout changed by the optical proximity correction (S40).The photomask may be manufactured, for example, using a chrome film applied on a glass substrate in such a manner that a layout pattern is drawn.

[0175] Subsequently, the semiconductor element can be manufactured using the generated photomask (S50). In the production / manufacturing process of the semiconductor element using the photomask, various types of exposure and etching processes can be repeated. The form of the pattern formed during the layout design can be continuously formed on the silicon substrate through such a process.

[0176] Summarizing the detailed description, those skilled in the art will recognize that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the exemplary embodiments. Therefore, the disclosed exemplary embodiments are used in a generic and descriptive sense only and not for purposes of limitation.

[0177] This application claims the benefit of Korean Patent Application No. 10-2019-0159496 filed on December 4, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: A plurality of wiring lines in a first direction extending in a first direction; and A plurality of wiring lines in a second direction extending in a second direction intersecting the first direction, The plurality of first-direction wirings extending in the first direction include: gate wirings spaced apart from each other at a gate pitch in the second direction, first wirings above the gate wiring and above the VDD power supply wiring, the first wirings being spaced apart from each other at a first pitch in the second direction, second wirings spaced apart from each other at a second pitch in the second direction over the first wirings, and third wirings, above the second wirings, spaced apart from each other at a third pitch in the second direction, a ratio between the gate pitch, the first pitch, the second pitch, and the third pitch is 6:4:5:9, the ratio being based on a least common multiple of the gate pitch, the first pitch, the second pitch, and the third pitch, The plurality of wirings in the second direction include: The VDD power supply wiring is in the interlayer insulating layer. a connection wiring in the interlayer insulating layer and directly connected to a gate via directly connected to one of the gate wirings, and VSS power supply wiring, in the interlayer insulating layer, The VDD power supply wiring, the VSS power supply wiring, and the connection wiring are located at the same level in the semiconductor device.

2. The semiconductor device according to claim 1, wherein the plurality of second-direction wirings include: fourth wirings spaced apart from each other at a fourth pitch in the first direction, and fifth wirings, above the fourth wirings, spaced apart from each other at a fifth pitch in the first direction, The fourth wiring is above the gate wiring and below the first wiring, The fifth wiring is above the first wiring and below the second wiring, and A ratio between the fourth pitch and the fifth pitch is 5:

4.

3. The semiconductor device according to claim 2, wherein the plurality of second-direction wirings further comprises: sixth wirings, above the fifth wirings, spaced apart from each other at a sixth pitch in the first direction, The sixth wiring is above the second wiring and below the third wiring, and A ratio among the fourth pitch, the fifth pitch, and the sixth pitch is 5:4:

6.

4. The semiconductor device according to claim 3, wherein the plurality of second-direction wirings further comprises: seventh wirings, above the sixth wirings, spaced apart from each other at a seventh pitch in the first direction, The seventh wiring is above the third wiring, and A ratio among the fourth pitch, the fifth pitch, the sixth pitch, and the seventh pitch is 5:4:6:

10.

5. The semiconductor device according to claim 1 , wherein the plurality of second-direction wirings include: fourth wirings spaced apart from each other at a fourth pitch in the first direction, fifth wirings spaced apart from each other at a fifth pitch in the first direction on the fourth wirings, and sixth wirings, above the fifth wirings, spaced apart from each other at a sixth pitch in the first direction, The fourth wiring is above the gate wiring and below the first wiring, The fifth wiring is above the first wiring and below the second wiring, The sixth wiring is above the second wiring and below the third wiring, and A ratio between the fifth pitch and the sixth pitch is 4:

6.

6. The semiconductor device according to claim 5, wherein the second direction plurality of wirings comprises: seventh wirings, above the sixth wirings, spaced apart from each other at a seventh pitch in the first direction, The seventh wiring is above the third wiring, and A ratio among the fifth pitch, the sixth pitch, and the seventh pitch is 4:6:

10.

7. The semiconductor device according to claim 1, wherein the second direction plurality of wirings comprises: fourth wirings arranged to be spaced apart from each other at a fourth pitch in the first direction, fifth wirings, above the fourth wirings, spaced apart from each other at a fifth pitch in the first direction, sixth wirings, above the fifth wirings, spaced apart from each other in the first direction at a sixth pitch in the first direction, seventh wirings, above the sixth wirings, spaced apart from each other at a seventh pitch in the first direction, The fourth wiring is above the gate wiring and below the first wiring, The fifth wiring is above the first wiring and below the second wiring, The sixth wiring is above the second wiring and below the third wiring, The seventh wiring is above the third wiring, and A ratio between the sixth pitch and the seventh pitch is 6:

10. 8 . The semiconductor device according to claim 1 , wherein each of the VDD power supply wiring, the VSS power supply wiring, and the connection wiring includes a barrier film on a bottom surface and a side wall surface thereof. 9 . The semiconductor device according to claim 1 , wherein a width of the VDD power supply wiring in the first direction is larger than a width of the connection wiring in the first direction.

10. The semiconductor device according to claim 1, further comprising: a plurality of active patterns extending in the second direction; a plurality of source / drain contacts extending in the first direction, at least one of the plurality of source / drain contacts directly contacting at least one of the plurality of active patterns; as well as a plurality of source / drain paths, at least one of the plurality of source / drain paths directly contacting the at least one of the plurality of source / drain contacts, wherein The VDD power supply wiring directly contacts the at least one of the plurality of source / drain paths.

11. The semiconductor device according to claim 10, wherein at least another one of the plurality of source / drain contacts directly contacts at least another one of the plurality of active patterns, At least one other of the plurality of source / drain vias directly contacts at least one other of the plurality of source / drain contacts, and The VSS power supply wiring directly contacts the at least another one of the plurality of source / drain paths.

12. A semiconductor device comprising: a plurality of first-directional wirings extending in the first direction and including gate wirings; and A plurality of wiring lines in a second direction extending in a second direction intersecting the first direction, The plurality of second-direction wirings extending in the second direction include: fourth wirings spaced apart from each other at a fourth pitch in the first direction and in the interlayer insulating layer, at least one of the fourth wirings being directly connected to a gate via directly connected to one of the gate wirings, VDD power supply wiring, in the interlayer insulating layer, VSS power supply wiring, in the interlayer insulating layer, fifth wirings, above the fourth wirings, spaced apart from each other at a fifth pitch in the first direction, sixth wirings, above the fifth wirings, spaced apart from each other at a sixth pitch in the first direction, and Seventh wirings are spaced apart from each other at a seventh pitch in the first direction above the sixth wiring, wherein A ratio between the fourth pitch, the fifth pitch, the sixth pitch, and the seventh pitch is 5:4:6:10, the ratio being based on a least common multiple of the fourth pitch, the fifth pitch, the sixth pitch, and the seventh pitch, and The at least one of the VDD power supply wiring, the VSS power supply wiring, and the fourth wiring is located at the same level in the semiconductor device, the same level being between the gate wiring and the next lowermost level among levels of the first-direction wirings.

13. The semiconductor device according to claim 12, wherein the plurality of first-direction wirings include: gate wirings spaced apart from each other at a gate pitch in the second direction, and first wirings, above the gate wirings, spaced apart from each other at a first pitch in the second direction, The gate wiring is below the fourth wiring, The first wiring is above the fourth wiring and below the fifth wiring, and A ratio between the gate pitch and the first pitch is 6:

4.

14. The semiconductor device according to claim 13, wherein the plurality of first-direction wirings further comprise: second wirings, above the first wirings, spaced apart from each other at a second pitch in the second direction, The second wiring is above the fifth wiring and below the sixth wiring, and A ratio among the gate pitch, the first pitch, and the second pitch is 6:4:

5.

15. The semiconductor device according to claim 14, wherein the plurality of first-direction wirings further comprise: third wirings, above the second wirings, spaced apart from each other at a third pitch in the second direction, The third wiring is above the sixth wiring and below the seventh wiring, and A ratio among the gate pitch, the first pitch, the second pitch, and the third pitch is 6:4:5:

9.

16. The semiconductor device according to claim 12, wherein the plurality of first-direction wirings include: gate wirings spaced apart from each other at a gate pitch in the second direction, first wirings spaced apart from each other at a first pitch in the second direction over the gate wiring, and second wirings, on the first wirings, spaced apart from each other at a second pitch in the second direction, The gate wiring is below the fourth wiring, The first wiring is above the fourth wiring and below the fifth wiring, The second wiring is above the fifth wiring and below the sixth wiring, and A ratio between the first pitch and the second pitch is 4:

5.

17. The semiconductor device according to claim 16, wherein the plurality of first-direction wirings further comprises: third wirings, above the second wirings, spaced apart from each other at a third pitch in the second direction, The third wiring is above the sixth wiring and below the seventh wiring, and A ratio among the first pitch, the second pitch, and the third pitch is 4:5:

9.

18. A semiconductor device comprising: A plurality of wiring lines in a first direction extending in a first direction; and A plurality of wiring lines in a second direction extending in a second direction intersecting the first direction, The plurality of wirings in the first direction include: gate wirings spaced apart from each other at a gate pitch in the second direction, first wirings, above the gate wirings, spaced apart from each other at a first pitch in the second direction, second wirings spaced apart from each other at a second pitch in the second direction over the first wirings, and third wirings, above the second wirings, spaced apart from each other at a third pitch in the second direction, The plurality of wirings in the second direction include: fourth wirings above the gate wirings and below the first wirings and spaced apart from each other at a fourth pitch in the first direction and in the interlayer insulating layer, at least one of the fourth wirings being directly connected to a gate via directly connected to one of the gate wirings, VDD power supply wiring, in the interlayer insulating layer, VSS power supply wiring, in the interlayer insulating layer, fifth wirings, above the first wirings and spaced apart from each other at a fifth pitch in the first direction, sixth wirings above the fifth wirings and spaced apart from each other at a sixth pitch in the first direction, and seventh wirings, above the sixth wirings and spaced apart from each other at a seventh pitch in the first direction, wherein a first ratio between the gate pitch and the first pitch is 6:4, the first ratio being based on a least common multiple of the gate pitch, the first pitch, the second pitch, and the third pitch, A second ratio between the fourth pitch and the fifth pitch is 5:4, the second ratio being based on a least common multiple of the fourth pitch, the fifth pitch, the sixth pitch, and the seventh pitch, and The VDD power supply wiring, the VSS power supply wiring, and the fourth wiring are located at the same level in the semiconductor device, and the same level is between the gate wiring and the first wiring.

Images