Display panel and electronic device including the same

Abstract

A display panel and an electronic device including the display panel are provided. The display panel having at least one hole in a display area includes: a substrate; a plurality of display elements arranged in a plane around the at least one hole; and a plurality of signal lines extending in a first direction. Wherein, the at least one hole includes a first hole, the first hole has a first width in a second direction and has two sides, and the two sides have an asymmetric shape with respect to a first center line passing through the center of the first width. Wherein, each of adjacent first and second signal lines among the plurality of signal lines extends in the first direction, the first signal line winds around the first side of the first hole, and the second signal line winds around the second side of the first hole opposite to the first side. Wherein, the first signal line and the second signal line are asymmetric with respect to a first virtual line therebetween.

Description

[0001] This application claims priority and benefit of Korean Patent Application No. 10-2019-0159368, filed on Dec. 3, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display panel and an electronic device including the display panel. Background Art

[0003] Recently, the purposes of display devices have been diversified. In addition, since display devices have become thinner and lighter in weight, their range of use has gradually expanded.

[0004] Since display devices are used in various suitable ways, their shapes can be designed in various suitable ways. In addition, the functions that can be combined with or associated with display devices are increasing. Summary of the Invention

[0005] Aspects and features of the present disclosure relate to a display device capable of increasing functions that can be combined with or associated with a display device. One or more embodiments of the present disclosure provide a display panel and an electronic device, the display panel including a plurality of regions within a display area, in which a camera, a sensor, etc. may be disposed. However, in this case, it is difficult to design the arrangement of wirings around the plurality of regions.

[0006] One or more embodiments of the present disclosure provide a structure that can prevent or reduce deterioration of display quality by appropriately arranging wirings around a plurality of regions. However, it should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display panel having at least one hole in a display area includes: a substrate; a plurality of display elements arranged on the substrate, the plurality of display elements being arranged in a plane around the at least one hole and defining the display area; and a plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, wherein the at least one hole includes a first hole having a first width in a second direction different from the first direction, and the first hole has two sides with an asymmetric shape with respect to a first center line passing through the center of the first width, wherein each of a first signal line among the plurality of signal lines and a second signal line adjacent to the first signal line among the plurality of signal lines extends in the first direction, the first signal line winds around a first side of the first hole, and the second signal line winds around a second side of the first hole opposite to the first side, wherein the first signal line and the second signal line are asymmetric with respect to a first virtual line between the first signal line and the second signal line.

[0009] The first virtual line may be spaced apart from the first center line in the second direction.

[0010] The display panel may further include an intermediate area between the first hole and the display area, the first signal line may include a first winding portion located in the intermediate area and winding around the first side of the first hole, and the second signal line may include a second winding portion located in the intermediate area and winding around the second side of the first hole.

[0011] The first winding portion and the second winding portion may have an asymmetric shape with respect to the first virtual line.

[0012] A first distance interval between the first signal line and the second signal line located in the display area may be greater than a second distance interval between the first signal line and the second signal line located in the intermediate area.

[0013] One of the first signal line and the second signal line may include a first conductive layer and a second conductive layer, the second conductive layer is located on the first conductive layer, and an insulating layer is located between the second conductive layer and the first conductive layer, and the second conductive layer is connected to the first conductive layer through a contact hole located in the insulating layer.

[0014] The plurality of signal lines may further include a third signal line and a fourth signal line, the third signal line is located on one side of the second signal line, and the first signal line is located between the third signal line and the second signal line; the fourth signal line is located on one side of the first signal line, and the second signal line is located between the fourth signal line and the first signal line, and the third signal line and the fourth signal line may be asymmetric with respect to the first virtual line.

[0015] Each of the first signal line and the third signal line may include: an extending portion extending in a first direction; and a detouring portion connected to the extending portion and disposed around a first side of the first hole, a first connection point between the extending portion and the detouring portion of the first signal line and a second connection point between the extending portion and the detouring portion of the third signal line may be disposed on a first virtual diagonal line inclined with respect to the first direction and a second direction.

[0016] The plurality of signal lines may include data lines or scan lines.

[0017] Each of the plurality of display elements may include an organic light emitting diode.

[0018] According to one or more embodiments, a display panel having a first hole includes: a plurality of display elements disposed in a plane around the first hole; and a plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, wherein each of a first signal line among the plurality of signal lines and a second signal line adjacent to the first signal line among the plurality of signal lines extends in the first direction, the first signal line detours around a first side of the first hole, and the second signal line detours around a second side of the first hole opposite to the first side, wherein the first signal line and the second signal line are asymmetric with respect to a first virtual line between the first signal line and the second signal line.

[0019] Each of the first signal line and the second signal line may include: extending portions both extending in the first direction and spaced apart from each other; and detouring portions connected to each of the extending portions, wherein the detouring portion of the first signal line detours around the first side of the first hole, and the detouring portion of the second signal line detours around the second side of the first hole, the detouring portion of the first signal line and the detouring portion of the second signal line may be asymmetric with respect to the first virtual line.

[0020] The plurality of signal lines may further include: a third signal line located on one side of the second signal line and having the first signal line located between the third signal line and the second signal line; and a fourth signal line located on one side of the first signal line and having the second signal line located between the fourth signal line and the first signal line, the third signal line and the fourth signal line may be asymmetric with respect to the first virtual line.

[0021] The third signal line may include: an extending portion extending in the first direction; and a detouring portion connected to the extending portion and disposed around the first side of the first hole, a first connection point between one of the extending portions of the first signal line and the detouring portion and a second connection point between the extending portion of the third signal line and the detouring portion may be disposed along a first virtual diagonal line inclined with respect to the first direction.

[0022] The fourth signal line may include: an extending portion extending in a first direction; and a detouring portion connected to the extending portion and disposed around a second side of the first hole, and a third connection point between one of the extending portions of the second signal line and the detouring portion and a fourth connection point between the extending portion of the fourth signal line and the detouring portion may be disposed along a second virtual oblique line inclined with respect to the first direction.

[0023] Each of the first signal line and the fourth signal line may include a first conductive layer and a second conductive layer, the second conductive layer being located on the first conductive layer, with an insulating layer being located between the second conductive layer and the first conductive layer, and the second conductive layer is connected to the first conductive layer through a contact hole located in the insulating layer.

[0024] The detouring portion of the first signal line may be spaced apart from a first side of the first hole by a constant distance, and the detouring portion of the second signal line may be spaced apart from a second side of the first hole by a constant distance.

[0025] The first hole may have a first width in a second direction different from the first direction, and both sides of the first hole may have an asymmetrical shape with respect to a first center line passing through the center of the first width in the first direction.

[0026] The first virtual line may be spaced apart from the first center line in the second direction.

[0027] The first virtual line and the first center line may be the same line, and the width or thickness of one of the detouring portions of the first signal line and the detouring portion of the second signal line may be greater than the width or thickness of the other of the detouring portions of the first signal line and the detouring portion of the second signal line.

[0028] The display panel may include: a substrate; a display layer located on the substrate and including the plurality of display elements; and a packaging layer located on the display layer, and the first hole may pass through a stacked structure including the substrate, the display layer, and the packaging layer.

[0029] According to one or more embodiments, an electronic device includes: a display panel having a first hole; and at least one component corresponding to the first hole of the display panel, wherein the display panel includes: a plurality of display elements disposed around the first hole; and a plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, wherein each of a first signal line among the plurality of signal lines and a second signal line adjacent to the first signal line among the plurality of signal lines extends in the first direction, the first signal line includes a first detouring portion detouring around a first side of the first hole, the second signal line includes a second detouring portion detouring around a second side of the first hole opposite to the first side, and wherein the first detouring portion of the first signal line and the second detouring portion of the second signal line are asymmetrical with respect to a first virtual line between the first signal line and the second signal line.

[0030] The plurality of signal lines may further include: a third signal line located on one side of the second signal line, with the first signal line located between the third signal line and the second signal line, and the third signal line including a third detour portion that detours around the first side of the first hole; and a fourth signal line located on one side of the first signal line, with the second signal line located between the fourth signal line and the first signal line, and the fourth signal line including a fourth detour portion that detours around the second side of the first hole, wherein the third detour portion of the third signal line and the fourth detour portion of the fourth signal line may be asymmetric with respect to the first virtual line.

[0031] The first signal line may include an extension portion extending in a first direction and a first detour portion connected to the extension portion, the third signal line may include an extension portion extending in the first direction and a third detour portion connected to the extension portion, and a first connection point between the extension portion and the first detour portion of the first signal line and a second connection point between the extension portion and the third detour portion of the third signal line may be arranged along a first virtual oblique line inclined with respect to the first direction.

[0032] The first hole may have a first width in a second direction different from the first direction, and both sides of the first hole may have an asymmetric shape with respect to a first center line passing through the center of the first width.

[0033] The first virtual line may be spaced apart from the first center line in the second direction.

[0034] The first virtual line and the first center line may be the same line, and the width or thickness of one of the first detour portion and the second detour portion may be greater than the width or thickness of the other of the first detour portion and the second detour portion.

[0035] The at least one component may include an electronic component that emits or receives light through the first hole.

[0036] The electronic component may include a camera, a sensor for recognizing a part of the human body, or a lamp.

[0037] The display panel may further have a second hole spaced apart from the first hole, and the display panel may further include an additional component corresponding to the second hole.

[0038] These and other aspects and features will become more apparent and will be more easily understood in light of the description of the embodiments, the drawings, and the claims and their equivalents. Description of the Drawings

[0039] In light of the following description taken in conjunction with the accompanying drawings, the above and other aspects and features of the present disclosure will become more apparent, in which:

[0040] Figure 1A andFigure 1B Perspective views of an electronic device according to an embodiment, respectively;

[0041] Figures 2A to 2C Cross-sectional views of an electronic device according to an embodiment, respectively;

[0042] Figure 3A and Figure 3B Cross-sectional views of a display panel according to an embodiment, respectively;

[0043] Figure 4A and Figure 4B Cross-sectional views of a display panel according to an embodiment, respectively;

[0044] Figure 5A and Figure 5B Plan views of a display panel according to an embodiment, respectively;

[0045] Figure 6 Equivalent circuit diagram of a pixel circuit of an organic light-emitting diode electrically connected to a display panel according to an embodiment;

[0046] Figure 7 Plan view of a part of a display panel according to an embodiment;

[0047] Figure 8 Plan view of signal lines arranged around a first region according to an embodiment;

[0048] Figure 9A is Figure 8 Plan view of four signal lines adjacent to each other among the signal lines of;

[0049] Figure 9B and Figure 9C are each Figure 9A Cross-sectional view of one of the signal lines of;

[0050] Figure 10 is along Figure 8 Cross-sectional view of a signal line taken along lines Xa-Xa' and Xb-Xb' of;

[0051] Figure 11 Plan view of a part of a display panel according to an embodiment;

[0052] Figure 12A Plan view of signal lines arranged around a first region according to an embodiment;

[0053] Figure 12B is Figure 12A Extracted plan view of some of the signal lines of;

[0054] Figure 13 Plan view of a part of a display panel according to an embodiment;

[0055] Figure 14A is a plan view of a part of a display panel according to an embodiment;

[0056] Figure 14B is a cross-sectional view of the display panel taken along line XIV-XIV’; and Figure 14A is a plan view of a part of a display panel according to an embodiment.

[0057] Figure 15 DETAILED DESCRIPTION DETAILED DESCRIPTION

[0058] Embodiments will now be described with reference to the accompanying drawings, in which examples of the embodiments are shown, and like reference numerals always denote like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments will only be described below with reference to the accompanying drawings to explain aspects and features of the present disclosure. As used herein, when describing embodiments of the present invention, the use of the term "may" means "one or more embodiments of the present invention". As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0059] Since the present disclosure allows for various suitable changes and many embodiments, example embodiments will be shown in the drawings and described in the written description. When referring to the embodiments described below in conjunction with the accompanying drawings, aspects and features of the present disclosure and methods for implementing the present disclosure will be apparent. However, the present disclosure is not limited to the embodiments described below and can be implemented in various forms.

[0060] Hereinafter, the disclosed embodiments will be described with reference to the accompanying drawings. In the drawings, the same reference numerals are assigned to the same or corresponding elements, and a repeated description thereof may not be provided.

[0061] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0062] As used herein, unless the context clearly indicates otherwise, the singular form "a" is also intended to include the plural form.

[0063] It will also be understood that the terms "comprises" and "comprising" as used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0064] It will be understood that when a layer, region or component is referred to as being "on" another layer, region or component, the layer, region or component can be directly or indirectly on the other layer, region or component. For example, there can be one or more intermediate layers, regions or components. In contrast, when an element or layer is referred to as being "directly on" another layer, region or component, there are no intermediate layers, regions or components.

[0065] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. For example, for ease of explanation, the size and thickness of the components in the drawings may be exaggerated, and the following embodiments are not limited thereto. As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0066] When the disclosed embodiments can be implemented differently, the disclosed process sequences can be performed differently from the described sequences. For example, two consecutively described processes can be performed simultaneously or substantially simultaneously, or can be performed in an order opposite to the described order.

[0067] It will be understood that when a layer, region or component is referred to as being "connected" to another layer, region or component, the layer, region or component can be "directly connected" to the other layer, region or component, or the layer, region or component can be "indirectly connected" to the other layer, region or component with one or more other layers, regions or components disposed therebetween. For example, it will be understood that when a layer, region or component is referred to as being "electrically connected" to another layer, region or component, the layer, region or component can be "directly electrically connected" to the other layer, region or component, or the layer, region or component can be "indirectly electrically connected" to the other layer, region or component through one or more other layers, regions and / or components, with one or more other layers, regions and / or components being electrically disposed therebetween. Further, as used herein, when a layer, region or component is referred to as being "connected" or "coupled" to another layer, region or component, the one layer, region or component can be, for example, electrically connected or electrically coupled to the other layer, region or component for operation.

[0068] Figure 1A and Figure 1B are perspective views of an electronic device 1 according to an embodiment, respectively.

[0069] The electronic device 1 can include at least one component region disposed within a display area DA. For example, as Figure 1A shown, two component regions (e.g., a first region RA1 and a second region RA2) can be disposed within the display area DA. In some embodiments, as Figure 1BAs shown, a component region (e.g., the first region RA1) may be disposed within the display region DA. The first region RA1 and the second region RA2 are regions in which the components described with reference to Figures 2A to 2C are disposed. By utilizing such components, the electronic device 1 may have various suitable functions.

[0070] In the case where the electronic device 1 includes a plurality of component regions, the first region RA1 and the second region RA2 may have different sizes (e.g., areas) and / or different shapes. The first region RA1 may have an asymmetric and atypical shape with respect to the horizontal direction (e.g., the x-direction) and / or the longitudinal direction (e.g., the y-direction). For example, as Figure 1A and Figure 1B shown, the first region RA1 may have an asymmetric shape with respect to a line along the longitudinal direction (e.g., the y-direction). The second region RA2 may have a symmetric shape with respect to the horizontal direction (e.g., the x-direction) and / or the longitudinal direction (e.g., the y-direction). For example, as Figure 1A shown, the second region RA2 may have a shape such as a circle, a quasi-elliptical shape (ellipse), or a quadrilateral.

[0071] The display region DA may display a predetermined color or a set image by utilizing light emitted from a plurality of pixels disposed in the display region DA. Each pixel may include a display element for emitting light of a predetermined color or a set color. For example, display elements for emitting red light, green light, or blue light may be two-dimensionally disposed in the x-direction and the y-direction (e.g., disposed in a plane parallel to both the x-direction and the y-direction), and the display region DA for displaying an image may be defined (e.g., may be defined by a region including the display elements).

[0072] An intermediate region MA may be disposed between at least one component region and the display region DA. In some embodiments, the intermediate region MA may be adjacent to the component region, e.g., closely surrounding at least a part or all of the component region. The display region DA may be surrounded by a peripheral region PA. The intermediate region MA and the peripheral region PA may be a type of non-display region in which no pixels are disposed. The intermediate region MA may be entirely surrounded by the display region DA, and the display region DA may be surrounded by the peripheral region PA.

[0073] The electronic device 1 may include various suitable types of devices that can provide images, such as a tablet personal computer (PC), a notebook computer, a mobile phone, and a smart band or a smart watch that can be worn on the wrist.

[0074] Figures 2A to 2C Each is a cross-sectional view of the electronic device 1 according to an embodiment taken along the line II-II’ of Figure 1A ​

[0075] Reference Figures 2A to 2C , the electronic device 1 has a space therein and includes a housing HS having an open side. The open side of the housing HS may be coupled to a window 60 (e.g., covered by the window 60). A stacked structure may be disposed (e.g., disposed in the housing HS), the stacked structure including a display panel 10, an input sensing layer 40, and an optical function layer 50. At least one component may be disposed below the back side (e.g., the lower surface) of the display panel 10. Although Figures 2A to 2C the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 are shown, the number and type of components may be variably and appropriately changed.

[0076] The first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may be disposed within the housing HS and located between the display panel 10 and the bottom surface or bottom of the housing HS. Some of the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may be disposed in a first region RA1, and the remaining components of the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may be disposed in a second region RA2. In an embodiment, the first component 21, the second component 22, the third component 23, and the fourth component 24 may be disposed in the first region RA1, and the fifth component 25 may be disposed in the second region RA2.

[0077] The first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may include electronic components that utilize light and / or sound. The electronic components may include (e.g., may be) sensors for measuring distance (such as proximity sensors), sensors for identifying a part of a user's body (e.g., fingerprint, iris, face, etc.), small lights for outputting light, and / or image sensors for capturing images (e.g., cameras). The electronic components that utilize light may utilize light in various suitable wavelength bands including visible light, infrared light, and / or ultraviolet light. The electronic components that utilize sound may utilize ultrasonic waves and / or sound in other frequency bands.

[0078] The light and / or sound utilized by the electronic components may travel to the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 (e.g., may be received by the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25), and / or may be emitted from the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 through the first region RA1 and the second region RA2. Accordingly, the first region RA1 and the second region RA2 may be a type of transmissive region that can transmit light and / or sound.

[0079] The first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may include the same type of electronic components or may include different types of electronic components. In an embodiment, the first component 21 and the fifth component 25 may include image sensors (e.g., cameras), and the second component 22, the third component 23, and the fourth component 24 may include at least one infrared sensor.

[0080] The infrared sensor may include a light emitter and a light receiver. The light emitter and the light receiver may be formed as an integral body, or may be separately formed as individual elements. In an embodiment, the second component 22, the third component 23, and the fourth component 24 may each include a part of an infrared sensor. For example, some of the second component 22, the third component 23, and the fourth component 24 may include light emitters that emit light, and the remaining components of the second component 22, the third component 23, and the fourth component 24 may include light receivers that receive light.

[0081] The display panel 10 may display an image. The display panel 10 may display an image by using display elements (e.g., organic light-emitting diodes disposed in the display area DA). In an embodiment, the display elements may include inorganic light-emitting diodes or quantum dot light-emitting diodes.

[0082] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 includes sensing electrodes (e.g., touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may sense an external input by using a mutual capacitance method and / or a self-capacitance method.

[0083] As Figures 2A to 2C shown, the input sensing layer 40 may be directly formed on the display panel 10. For example, the input sensing layer 40 may be sequentially formed after the process of forming the display panel 10. In some embodiments, an adhesive layer may not be disposed between the input sensing layer 40 and the display panel 10. In some embodiments, the input sensing layer 40 may be separately formed and then bonded to the display panel 10 by using an adhesive layer. The adhesive layer may include (e.g., may be) an optically clear adhesive (OCA) (see Figures 2A to 2C the reference numeral OCA in the drawings).

[0084] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectance of light (external light) incident on the display panel 10 from the outside through the window 60. In some embodiments, the anti-reflection layer may reduce the amount of light (e.g., external light) incident on the display panel 10. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder (e.g., a film-based retarder) or a liquid crystal-type retarder (e.g., a liquid crystal-based retarder). The retarder may include a λ / 2 retarder (e.g., a half-wave plate retarder) and / or a λ / 4 retarder (e.g., a quarter-wave plate retarder). The polarizer may include a film-type polarizer (e.g., a film-based polarizer) or a liquid crystal-type polarizer (e.g., a liquid crystal-based polarizer). The film-type polarizer (e.g., a film-based polarizer) may include a stretchable synthetic resin film, and the liquid crystal-type polarizer (e.g., a liquid crystal-based polarizer) may include liquid crystals arranged in a predetermined arrangement or a set arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective films of the retarder and the polarizer may be defined as the base layer of the anti-reflection layer.

[0085] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged by considering the color of each beam of light (e.g., based on the color of the light) emitted from the pixels of the display panel 10 respectively. For example, a red color filter that filters red light may be arranged to overlap with the pixels that emit red light. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged on different layers respectively. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer respectively may undergo destructive interference, so the reflectance of external light may be reduced.

[0086] The optical functional layer 50 may include a lens layer. The lens layer may improve the emission efficiency of the light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or include multiple layers having different refractive indices. The optical functional layer 50 may include an anti-reflection layer and / or a lens layer.

[0087] The optical functional layer 50 may be bonded to the window 60 through an adhesive layer such as OCA.

[0088] The display panel 10, the input sensing layer 40, and / or the optical functional layer 50 may respectively have holes in the first region RA1 and the second region RA2. In an embodiment, as Figure 2AAs shown, the display panel 10, the input sensing layer 40, and the optical functional layer 50 respectively have a first hole 10H, a second hole 40H, and a third hole 50H that are stacked on one another. The first hole 10H may be formed to penetrate from the top surface of the display panel 10 to the bottom surface of the display panel 10. The second hole 40H may be formed to penetrate from the top surface of the input sensing layer 40 to the bottom surface of the input sensing layer 40. The third hole 50H may be formed to penetrate from the top surface of the optical functional layer 50 to the bottom surface of the optical functional layer 50. Each of the first hole 10H, the second hole 40H, and the third hole 50H may be positioned to correspond to (e.g., to overlap with) the first region RA1 and the second region RA2. The first region RA1 and the second region RA2 may each be a type of hole region (e.g., a region corresponding to (a plurality of) holes (e.g., corresponding to the first hole 10H, the second hole 40H, and / or the third hole 50H)). The sizes (e.g., diameters, widths, or areas) of the first hole 10H, the second hole 40H, and the third hole 50H may be equal to or different from one another. Although Figure 2A it is shown that the OCA may be integrally formed on the back side (e.g., the bottom side) of the window 60, in an embodiment, the OCA may include holes in the first region RA1 and / or the second region RA2.

[0089] In some embodiments, the display panel 10, the input sensing layer 40, and / or the optical functional layer 50 do not include holes. For example, in some embodiments, as Figure 2B shown, the display panel 10 may include the first hole 10H corresponding to the first region RA1 and the second region RA2, but the input sensing layer 40 and the optical functional layer 50 do not include holes. In some embodiments, when light and / or sound sufficiently pass through the first region RA1 and the second region RA2, each of the display panel 10, the input sensing layer 40, and the optical functional layer 50 does not include holes corresponding to the first region RA1 and the second region RA2, e.g., as Figure 2C shown.

[0090] Figure 3A and Figure 3B are cross-sectional views of the display panel 10 according to embodiments, respectively.

[0091] Referring to Figure 3A , the display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include (e.g., may be) a glass material and / or a polymer resin. The substrate 100 may include a multi-layer structure. For example, as Figure 3A shown in the enlarged view of the substrate 100 in, the substrate 100 may include a first matrix layer 101, a first barrier layer 102, a second matrix layer 103, and a second barrier layer 104.

[0092] Each of the first substrate layer 101 and the second substrate layer 103 may include (e.g., may be) a polymer resin. For example, the first substrate layer 101 and the second substrate layer 103 may include (e.g., may be) a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate, triacetyl cellulose (TAC), and / or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0093] The first barrier layer 102 and the second barrier layer 104 are barrier layers for preventing or blocking the penetration of external foreign substances, and may include a single-layer structure or a multi-layer structure containing (e.g., being) an inorganic material such as silicon nitride, silicon oxynitride, and / or silicon oxide.

[0094] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A, a pixel circuit layer 200B, and an insulating layer. The display element layer 200A may include display elements arranged for each pixel, and the pixel circuit layer 200B may include pixel circuits electrically connected to each display element. Each pixel circuit may include a thin-film transistor and a storage capacitor, and each display element may include an organic light-emitting diode.

[0095] The display elements of the display layer 200 may be covered by a thin-film encapsulation layer 300. The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin-film encapsulation layer 300 may have a structure in which a first inorganic encapsulation layer and a second inorganic encapsulation layer are sequentially stacked. In some embodiments, the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may be sequentially stacked in this order. The first inorganic encapsulation layer and the second inorganic encapsulation layer may include (e.g., may be) at least one of, for example, silicon nitride, silicon oxide, and silicon oxynitride. The organic encapsulation layer may include (e.g., may be) a polymer-based material. The polymer-based material may include (e.g., may be) an acrylate resin, an epoxy resin, a polyimide, and / or polyethylene.

[0096] In the case where the display panel 10 includes a substrate 100 that may be a multi-layer structure and a thin-film encapsulation layer 300, the flexibility of the display panel 10 can be improved. The display panel 10 may include a first hole 10H passing through the display panel 10. The first hole 10H may be located in the first region RA1 and the second region RA2, respectively. In Figure 3A It is shown that the substrate 100, the display layer 200, and the encapsulation member as the thin-film encapsulation layer 300 respectively include through holes 100H, 200H, and 300H that all correspond to the first hole 10H of the display panel 10.

[0097] In another embodiment, as Figure 3B shown, the substrate 100 and the thin film encapsulation layer 300 do not include through holes. Since the components are arranged in the first region RA1 and the second region RA2 as described above, the display layer 200 may include through holes 200H in the first region RA1 and the second region RA2, and it can be ensured that light can pass through the through holes 200H at its transmittance. For example, in some embodiments, even if the substrate 100 and the thin film encapsulation layer 300 do not include through holes, the through holes 200H in the display layer 200 can allow light to pass through the display panel 10.

[0098] Figure 4A and Figure 4B are each a cross-sectional view of the display panel 10 according to an embodiment.

[0099] Referring to Figure 4A and Figure 4B , the encapsulation member 300' includes an encapsulation substrate 340. The encapsulation substrate 340 faces the substrate 100. The display layer 200 is disposed between the encapsulation substrate 340 and the substrate 100. A sealing material 350 is disposed between the encapsulation substrate 340 and the substrate 100. The sealing material 350 may surround the outer surface (e.g., the edge or side surface) of the display layer 200. For example, in a plan view, the sealing material 350 may surround the display layer 200 (e.g., the display element layer 200A) in the peripheral region PA and the intermediate region MA.

[0100] Although in Figure 4A which is a cross-sectional view, the sealing material 350 in the intermediate region MA is shown to be separated (e.g., spaced apart) from each other on both sides of the first hole 10H, the sealing material 350 in the intermediate region MA may have an annular shape surrounding each of the first holes 10H in a plan view. The sealing material 350 disposed in the peripheral region PA may be separated (e.g., spaced apart) from the sealing material 350 disposed in the intermediate region MA. As Figure 4A shown, the first holes 10H may be respectively formed in the first region RA1 and the second region RA2, and each first hole 10H may be surrounded by the sealing material 350. As Figure 4A shown, the substrate 100, the display layer 200, and the encapsulation substrate 340 respectively include through holes 100H, 200H, and 340H that all correspond to the first hole 10H of the display panel 10.

[0101] In another embodiment, as Figure 4BAs shown, the base 100 and the encapsulation base 340 may not include vias. The display layer 200 may include vias 200H in the first region RA1 and the second region RA2, respectively, and ensure that light can pass through the vias 200H with a transmittance. For example, the vias 200H of the display layer 200 may allow light to pass through the display panel 10. In the case where the first holes 10H are not formed in the first region RA1 and the second region RA2 of the base 100 and the encapsulation base 340, the sealing material 350 may be only in the peripheral region PA.

[0102] Figure 5A and Figure 5B are respectively the plan views of the display panel 10 according to the embodiments.

[0103] Referring to Figure 5A and Figure 5B , the display panel 10 may include at least one region in which components may be arranged. For example, as Figure 5A shown, the display panel 10 may include a first region RA1, a second region RA2, and a display region DA, or as Figure 5B shown, the display panel 10 may include a first region RA1.

[0104] In an embodiment, as referred to Figure 2A above, the display panel 10 may include a first hole 10H corresponding to the first region RA1 and the second region RA2. In this case, Figure 5A and Figure 5B the first region RA1 or the second region RA2 shown in may correspond to the planar shape of the first hole 10H of the display panel 10 (see Figure 2A ). In another embodiment, as referred to above Figure 2C above, the display panel 10 does not include a first hole 10H corresponding to the first region RA1 and the second region RA2, respectively.

[0105] Referring to Figure 5A , the display panel 10 may include a first region RA1, a second region RA2, a display region DA, an intermediate region MA, and a peripheral region PA. Figure 5A The outer shape of the base 100 of the display panel 10 may be shown. For example, the base 100 may include a plurality of regions corresponding to the first region RA1, the second region RA2, the display region DA, the intermediate region MA, and the peripheral region PA. Referring to Figure 5B , the display panel 10 may include a first region RA1, a display region DA, an intermediate region MA, and a peripheral region PA. The base 100 may include regions corresponding to the first region RA1, the display region DA, the intermediate region MA, and the peripheral region PA, respectively.

[0106] Each of a plurality of pixels P arranged in a display area DA may include a display element such as an organic light-emitting diode. Each pixel P may emit, for example, red light, green light, or blue light from the organic light-emitting diode. A first area RA1 and a second area RA2 may be arranged within the display area DA( Figure 5A ), or the first area RA1 may be arranged within the display area DA( Figure 5B ). An intermediate area MA may be arranged between the first area RA1 and the second area RA2 and the display area DA, or between the first area RA1 and the display area DA.

[0107] The intermediate area MA is a type of non-display area. Signal lines may be arranged in the intermediate area MA, and the signal lines may supply signals to the pixels P arranged around the intermediate area MA.

[0108] A first external driving circuit 110, a second external driving circuit 120, a terminal 140, a first power supply line 160, and a second power supply line 170 may be arranged in a peripheral area PA.

[0109] The first external driving circuit 110 may include a scan driving circuit and a control driving circuit. The first external driving circuit 110 may supply a scan signal and an emission control signal to each pixel P through a scan line SWL and an emission control line EL, respectively. The second external driving circuit 120 may include a scan driving circuit and a control driving circuit. The second external driving circuit 120 may be arranged parallel (e.g., substantially parallel) to the first external driving circuit 110, and the display area DA may be located between the second external driving circuit 120 and the first external driving circuit 110. Like the first external driving circuit 110, the second external driving circuit 120 may supply a scan signal and an emission control signal to each pixel P through a scan line SWL and an emission control line EL, respectively.

[0110] The terminal 140 may be arranged at one side of the peripheral area PA (e.g., a side of the peripheral area PA different from the sides of the first external driving circuit 110 and the second external driving circuit 120) (e.g., arranged on one side of the peripheral area PA). The terminal 140 may be exposed without being covered by an insulating layer and electrically connected to a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB is configured to transmit power and / or signals of a controller to the display panel 10. Control signals generated by the controller may be transmitted to the first external driving circuit 110 and the second external driving circuit 120 through the printed circuit board PCB, respectively. The controller may supply a first power voltage ELVDD and a second power voltage ELVSS to the first power supply line 160 and the second power supply line 170 through a first connection line 161 and a second connection line 171, respectively (see Figure 6, as described below). The first power voltage ELVDD can be supplied to each pixel P through a driving voltage line PL connected to a first power supply line 160, and the second power voltage ELVSS can be supplied to a counter electrode of the pixel P connected to a second power supply line 170.

[0111] The data driving circuit 150 can be electrically connected to a data line DL. The data signal of the data driving circuit 150 can be supplied to each pixel P through a connection line 151 and the data line DL. The connection line 151 is connected to a terminal 140, and the data line DL is connected to the connection line 151. Although in Figure 5A and Figure 5B it is shown that the data driving circuit 150 is arranged on a printed circuit board PCB, in another embodiment, the data driving circuit 150 can be arranged on the substrate 100. For example, the data driving circuit 150 can be arranged between the terminal 140 and the first power supply line 160.

[0112] The first power supply line 160 can include a first sub-line 162 and a second sub-line 163 that are parallel to each other (e.g., substantially parallel to each other) and extend in the x direction, and the display area DA is located between the first sub-line 162 and the second sub-line 163. The second power supply line 170 can have an annular shape that has an open side and partially surrounds the display area DA. For example, the second power supply line 170 can surround the display area DA on three sides of a rectangular shape or a square shape.

[0113] Figure 6 is an equivalent circuit diagram of a pixel circuit PC of an organic light-emitting diode OLED electrically connected to a display panel 10 according to an embodiment.

[0114] Referring to Figure 6 , the organic light-emitting diode OLED can be connected to the pixel circuit PC, and the pixel circuit PC can include a plurality of thin film transistors and storage capacitors. The thin film transistors and storage capacitors can be connected to signal lines SL, SL-1, SL+1, EL, and DL, a first initialization voltage line VL1, a second initialization voltage line VL2, and a driving voltage line PL.

[0115] The plurality of thin film transistors can include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7.

[0116] The signal lines include a scan line SL, a previous scan line SL-1, a next scan line SL+1, an emission control line EL, and a data line DL. The scan line SL is configured to transmit a scan signal Sn (e.g., transmitted to the switching thin film transistor T2 and / or transmitted to the compensation thin film transistor T3). The previous scan line SL-1 is configured to transmit a previous scan signal Sn-1 to the first initialization thin film transistor T4. The next scan line SL+1 is configured to transmit the scan signal Sn to the second initialization thin film transistor T7. The emission control line EL is configured to transmit an emission control signal En to the operation control thin film transistor T5 and transmit it to the emission control thin film transistor T6. The data line DL intersects or crosses the scan line SL in the display panel 10 and is configured to transmit a data signal Dm. The driving voltage line PL can be configured to transmit a first power voltage ELVDD to the driving thin film transistor T1. The first initialization voltage line VL1 can be configured to transmit an initialization voltage Vint to the first initialization thin film transistor T4. The second initialization voltage line VL2 can be configured to transmit the initialization voltage Vint to the second initialization thin film transistor T7.

[0117] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5. The driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 is configured to receive the data signal Dm according to (e.g., based on) the switching operation of the switching thin film transistor T2, and supply a driving current I OLED to the organic light emitting diode OLED.

[0118] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL. The switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL. The switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and is also connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and is configured to perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0119] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin film transistor T3 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and is also connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the drive gate electrode G1 of the drive thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and is configured to diode-connect the drive thin film transistor T1 by electrically connecting the drive gate electrode G1 of the drive thin film transistor T1 to the drive drain electrode D1 of the drive thin film transistor T1.

[0120] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the first initialization voltage line VL1. The first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the drive gate electrode G1 of the drive thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and is configured to perform an initialization operation to initialize the voltage of the drive gate electrode G1 of the drive thin film transistor T1 by transmitting the initialization voltage Vint to the drive gate electrode G1 of the drive thin film transistor T1.

[0121] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control thin film transistor T5 is connected to the drive voltage line PL. The operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the drive source electrode S1 of the drive thin film transistor T1 and is connected to the switch drain electrode D2 of the switch thin film transistor T2.

[0122] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and is connected to the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and is connected to the pixel electrode of the organic light emitting diode OLED.

[0123] The operation control thin film transistor T5 and the emission control thin film transistor T6 turn on concurrently or simultaneously in response to an emission control signal En transmitted through an emission control line EL, allowing a first power voltage ELVDD to be transmitted to the organic light emitting diode OLED, thus allowing a driving current I OLED to flow through the organic light emitting diode OLED.

[0124] A second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to a next scan line SL+1, a second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to an emission control drain electrode D6 of the emission control thin film transistor T6 and is connected to a pixel electrode of the organic light emitting diode OLED, and a second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to a first initialization source electrode S4 of the first initialization thin film transistor T4 and is connected to a second initialization voltage line VL2.

[0125] Since the scan line SL is electrically connected to the next scan line SL+1, the same scan signal Sn can be applied to the scan line SL and the next scan line SL+1. Accordingly, the second initialization thin film transistor T7 can initialize the pixel electrode of the organic light emitting diode OLED by turning on in response to the scan signal Sn transmitted through the next scan line SL+1.

[0126] A second storage capacitor plate Cst2 of the storage capacitor Cst is connected to a driving voltage line PL, and a counter electrode of the organic light emitting diode OLED is connected to a second power voltage ELVSS. Accordingly, the organic light emitting diode OLED can be configured to receive the driving current I OLED from the driving thin film transistor T1 and emit light to thereby display an image.

[0127] Although it is shown in Figure 6 that both the compensation thin film transistor T3 and the first initialization thin film transistor T4 have dual gate electrodes, both the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0128] Although it is shown in Figure 6 that the pixel circuit PC includes seven thin film transistors and one storage capacitor, embodiments of the present disclosure are not limited thereto. The number of thin film transistors may be six or less, or eight or more, the number of storage capacitors may be two or more, or may be omitted, and the number of thin film transistors and storage capacitors may be variously and appropriately changed (e.g., set) according to the design of the pixel circuit PC.

[0129] Figure 7 is a plan view of a part of a display panel 10 according to an embodiment.

[0130] Refer toFigure 7 , the display panel 10 may include a first region RA1 disposed within a display region DA in which pixels P are disposed. In an embodiment, as referred to Figure 2A above, the display panel 10 may include a first hole 10H disposed in the first region RA1 (see Figure 2A ). In this case, Figure 7 the first region RA1 shown in

[0131] may have a planar shape of the first hole 10H (e.g., corresponding to the first hole 10H). The first region RA1 may have a first width W1 in the x direction, and both sides of the first region RA1 may have an asymmetrical shape with respect to a first center line CL1 passing through a first center C1 and dividing the first width W1 into two halves. The first center line CL1 may be a virtual line. In some embodiments, the first center line CL1 may extend in the y direction to pass through the first center C1. In an embodiment, the right side of the first center line CL1 (e.g., the right side of the first region RA1 on the right side of the first center line CL1) may have an approximately (or substantially) quadrilateral shape, and the left side of the first center line CL1 (e.g., the left side of the first region RA1 on the left side of the first center line CL1) may have an approximately (or substantially) semi-elliptical shape.

[0132] The middle region MA may have a shape substantially the same as that of the first region RA1. For example, the middle region MA may have a shape in which both of its sides are asymmetrical with respect to the first center line CL1. In an embodiment, the middle region MA may have a planar shape different from the planar shape of the first region RA1. For example, the middle region MA may have a shape in which both of its sides are symmetric (e.g., substantially symmetric) with respect to the first center line CL1. As disclosed herein, when two components or regions are referred to as symmetric or asymmetric, the two components or regions may have, for example, reflection symmetry or reflection asymmetry, respectively.

[0133] Figure 8 is a plan view of signal lines disposed around the first region RA1 according to an embodiment, Figure 9A is Figure 8 a plan view of four signal lines adjacent to each other among the signal lines of Figure 9B and Figure 9C each is Figure 9A a cross-sectional view of one of the signal lines of Figure 10 is Figure 8 a cross-sectional view of the signal lines taken along lines Xa-Xa' and Xb-Xb' of Figures 8 to 9C shows an embodiment in which the signal lines extending in one direction include data lines DL.

[0134] Referring to Figure 8, the data line DL can extend in one direction (e.g., the y direction). When the data line DL is said to extend in one direction (e.g., the y direction), the data line DL extends as a whole (e.g., generally, substantially, etc.) in one direction (e.g., the y direction). For example, the data line DL can extend in one direction (e.g., the y direction), and a part of each data line DL can detour around the first region RA1. For example, each data line DL can follow a curved path around the first region RA1.

[0135] In Figure 8 the plan view, each data line DL extends in the y direction to provide signals to pixels arranged above and below the first region RA1 and can detour in the middle region MA. For example, each data line DL can include an extending portion DL-L and a detouring portion DL-C. The extending portion DL-L is arranged on two opposite sides of the first region RA1, with the first region RA1 located between the extending portions DL-L. The detouring portion DL-C connects the extending portions DL-L. Most of the extending portion DL-L can be located in the display region DA, and some parts (e.g., the remaining parts) of the extending portion DL-L can be located in the middle region MA. The detouring portion DL-C can be located in the middle region MA.

[0136] A first pitch Δd1 (or first interval, e.g., distance interval) between parts of the data line DL located in the display region DA can be greater than a second pitch Δd2 (or second interval, e.g., distance interval) between parts of the data line DL in the middle region MA. For example, the first pitch Δd1 between the extending portions DL-L of the data line DL can be greater than the second pitch Δd2 between the detouring portions DL-C of the data line DL. Since the pitch between the data lines DL in the middle region MA is relatively small, the area of the middle region MA (e.g., the area of the non-effective region) can be reduced.

[0137] The data line DL can include a first group DLa and a second group DLb. The first group DLa includes data lines that detour around one side of the first region RA1 (e.g., Figure 8 the left side of the first region RA1 in Figure 8 ), and the second group DLb includes data lines that detour around the other side of the first region RA1 (e.g.,

[0138] The data lines DL of the first group DLa and the data lines DL of the second group DLb can extend from the first division point DP1 in different directions respectively. The data lines DL of the first group DLa can extend along the left side of the first region RA1 from the first division point DP1 (e.g., away from the first division point DP1), and the data lines DL of the second group DLb can extend along the right side of the first region RA1 from the first division point DP1 (e.g., away from the first division point DP1).

[0139] The data lines DL of the first group DLa can extend along the edge of the first region RA1 and maintain a first distance ds1 from the edge of the first region RA1. In an embodiment, the first distance ds1 can have a constant value, and the bypass portion DL-C of the data lines DL of the first group DLa can be separated (e.g., spaced apart) from the edge of the first region RA1 by a constant interval (e.g., a constant distance interval). In some embodiments, the portion of the innermost data line from the first group DLa that extends along the edge of the first region RA1 can be spaced apart from the edge of the first region RA1 by the first distance ds1, and the portion of each of the other data lines of the first group DLa that extends along the edge of the first region RA1 can be spaced apart from the edge of the first region RA1 by a distance greater than the first distance ds1.

[0140] Similarly, the data lines DL of the second group DLb can extend along the edge of the first region RA1 and maintain a second distance ds2 from the edge of the first region RA1. In an embodiment, the second distance ds2 can have a constant value, and the bypass portion of the data lines DL of the second group DLb can be separated (e.g., spaced apart) from the edge of the first region RA1 by a constant interval (e.g., a constant distance interval). The second distance ds2 can have the same value as the value of the first distance ds1. In some embodiments, the portion of the innermost data line from the second group DLb that extends along the edge of the first region RA1 can be spaced apart from the edge of the first region RA1 by the second distance ds2, and the portion of each of the other data lines of the second group DLb that extends along the edge of the first region RA1 can be spaced apart from the edge of the first region RA1 by a distance greater than the second distance ds2.

[0141] In some embodiments, the first division point DP1 is not located on the same line as the first center line CL1. For example, as Figure 8 shown, the first division point DP1 can be located on a first virtual line DPL1 that is separated (e.g., spaced apart) from the first center line CL1 by a predetermined interval or set interval (e.g., a distance interval) in a direction (e.g., the x direction) that intersects or crosses the extension direction of the data line DL (e.g., the y direction).

[0142] In a plan view, the data lines DL of the first group DLa and the data lines DL of the second group DLb may have asymmetrical shapes with respect to each other. For example, the bypass portions DL-C of each of the data lines DL in the first group DLa and the bypass portions DL-C of each of the data lines DL in the second group DLb may have asymmetrical shapes. In an embodiment, in the plan view, the bypass portion DL-C of each of the data lines DL in the first group DLa may have a shape similar to that of a part of the edge of the first region RA1, for example, an overall semi-elliptical shape (e.g., a substantially semi-elliptical shape). In the plan view, the bypass portion DL-C of each of the data lines DL in the second group DLb may have a shape similar to that of a part of the edge of the first region RA1, for example, an overall quadrilateral shape (e.g., a substantially quadrilateral shape).

[0143] The connection points between the extension portions DL-L and the bypass portions DL-C of each of the data lines DL in the first group DLa may be arranged along an inclined direction inclined with respect to the x-direction and the y-direction. The connection points between the extension portions DL-L and the bypass portions DL-C of each of the data lines DL in the first group DLa may be placed on a first virtual inclined line VOL1 inclined with respect to the x-direction and the y-direction. Similarly, the connection points between the extension portions DL-L and the bypass portions DL-C of each of the data lines DL in the second group DLb may be arranged along an inclined direction inclined with respect to the x-direction and the y-direction. The connection points between the extension portions DL-L and the bypass portions DL-C of each of the data lines DL in the second group DLb may be placed on a second virtual inclined line VOL2 inclined with respect to the x-direction and the y-direction. The connection points between the extension portions DL-L and the bypass portions DL-C of each data line DL may correspond to the ends of the bypass portion DL-C.

[0144] Referring to Figure 9A , the first data line DL1 and the second data line DL2 may extend in opposite directions from a first division point DP1 (e.g., away from the first division point DP1). The bypass portion DL1-C of the first data line DL1 may be located on one side of the first region RA1 (e.g., on one side of the first region RA1), for example, on the left side of the first region RA1 (e.g., on the left side of the first region RA1), and may extend along a part of the first region RA1. The bypass portion DL2-C of the second data line DL2 may be located on the other side of the first region RA1 (e.g., on the other side of the first region RA1), for example, on the right side of the first region RA1 (e.g., on the right side of the first region RA1), and may extend along another part of the first region RA1.

[0145] The first data line DL1 may include an extending portion DL1-L and a detouring portion DL1-C. The extending portion DL1-L passes through the display area DA, and the detouring portion DL1-C is connected to the extending portion DL1-L and is located in the middle area MA. The detouring portion DL1-C of the first data line DL1 may have a shape substantially the same as that of a part (e.g., the left part) of the first area RA1. For example, in a plan view, the detouring portion DL1-C of the first data line DL1 may have a substantially semi-elliptical shape.

[0146] The detouring portion DL1-C of the first data line DL1 may include a first detouring portion DL1-C1, a third detouring portion DL1-C3, and a second detouring portion DL1-C2 located between the first detouring portion DL1-C1 and the third detouring portion DL1-C3. Each of the first detouring portion DL1-C1 and the third detouring portion DL1-C3 may be connected to the extending portion DL1-L (e.g., each of the first detouring portion DL1-C1 and the third detouring portion DL1-C3 may be connected to a corresponding extending portion in the extending portion DL1-L), and extends in a direction different from (e.g., perpendicular or substantially perpendicular to) the direction of the extending portion DL1-L (e.g., the x direction).

[0147] The first detouring portion DL1-C1 and the third detouring portion DL1-C3 may be substantially straight lines, and the second detouring portion DL1-C2 may include a curved line. For example, the second detouring portion DL1-C2 may have a substantially semi-circular shape with a radius R1 in a plan view.

[0148] The second data line DL2 may include an extending portion DL2-L and a detouring portion DL2-C. The extending portion DL2-L passes through the display area DA, and the detouring portion DL2-C is connected to the extending portion DL2-L and is located in the middle area MA. The detouring portion DL2-C of the second data line DL2 may have a shape substantially the same as that of a part (e.g., the right part) of the first area RA1. For example, in a plan view, the detouring portion DL2-C of the second data line DL2 may have a substantially quadrilateral shape, e.g., a quadrilateral shape with rounded corners.

[0149] The detour portion DL2-C of the second data line DL2 may include a first detour portion DL2-C1, a third detour portion DL2-C3, and a second detour portion DL2-C2 located between the first detour portion DL2-C1 and the third detour portion DL2-C3. Each of the first detour portion DL2-C1 and the third detour portion DL2-C3 may be connected to the extension portion DL2-L (for example, each of the first detour portion DL2-C1 and the third detour portion DL2-C3 may be connected to a corresponding extension portion in the extension portion DL2-L), and extend in a direction different from the direction of the extension portion DL2-L (for example, perpendicular or substantially perpendicular), such as the x-direction.

[0150] The first detour portion DL2-C1, the second detour portion DL2-C2, and the third detour portion DL2-C3 of the second data line DL2 may be substantially straight lines. The connection portion of the second data line DL2 located between the first detour portion DL2-C1 and the second detour portion DL2-C2 may include a curved line, and the connection portion of the second data line DL2 located between the third detour portion DL2-C3 and the second detour portion DL2-C2 may include a curved line. For example, in a plan view, the connection portion of the second data line DL2 located between the first detour portion DL2-C1 and the second detour portion DL2-C2 may have an arc shape with a radius R2 in the plan view, and the connection portion of the second data line DL2 located between the third detour portion DL2-C3 and the second detour portion DL2-C2 may have an arc shape with a radius R3 in the plan view. The radius R2 and the radius R3 may be equal to or different from each other.

[0151] The first division point DP1 may be located in a first virtual line DPL1 separated (for example, spaced apart) from the first center line CL1 in the x-direction. Therefore, the central angle α1 of the detour portion DL1-C of the first data line DL1 may be different from the central angle β1 of the detour portion DL2-C of the second data line DL2. The central angle represents the angle formed by a virtual circular arc connecting the first center C1 and two opposite ends of the detour portion DL-C of the first detour region RA1 of each data line DL. In an embodiment, the central angle α1 of the detour portion DL1-C of the first data line DL1 may be greater than the central angle β1 of the detour portion DL2-C of the second data line DL2.

[0152] The length of the detour portion DL1-C of the first data line DL1 may be the same as or substantially the same as the length of the detour portion DL2-C of the second data line DL2. When the length of the detour portion DL1-C of the first data line DL1 is said to be the same as or substantially the same as the length of the detour portion DL2-C of the second data line DL2, the length deviation between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be within a few μm. For example, the difference between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be 80 μm or less, or 70 μm or less. In an embodiment, the difference between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be in the range of about 0.1 μm to about 70 μm.

[0153] As a comparative example, in the case where the first division point DP1 is located on the first center line CL1, the length of the detour portion DL1-C of the first data line DL1 may be different from the length of the detour portion DL2-C of the second data line DL2. For example, the difference between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be about one thousand μm to tens of thousands of μm or more. Such a length deviation causes a resistance deviation, and since a brightness difference and / or a color deviation are caused by the resistance deviation, the image quality of the display panel deteriorates.

[0154] In contrast, according to an embodiment, as described with reference to Figure 8 and Figure 9A the first division point DP1 located between the first group DLa and the second group DLb may be located on a first virtual line DPL1 separated (e.g., spaced apart) from the first center line CL1. Accordingly, the length of the detour portion DL1-C of the data lines of the first group DLa (e.g., the first data line DL1) and the length of the detour portion DL2-C of the data lines of the second group DLb (e.g., the second data line DL2) may be the same or substantially the same, and thus a brightness difference and / or a color deviation may be prevented, minimized, or reduced. For example, the distance between the first virtual line DPL1 and the first center line CL1 may be predetermined or set such that the length of the detour portion DL1-C of the data lines of the first group DLa is the same as or substantially the same as the length of the detour portion DL2-C of the data lines of the second group DLb.

[0155] The third data line DL3 and the fourth data line DL4 can be separated from each other (e.g., spaced apart), and the first data line DL1 and the second data line DL2 can be positioned between the third data line DL3 and the fourth data line DL4. The third data line DL3 can be on the opposite side of the second data line DL2, and the first data line DL1 can be between the third data line DL3 and the second data line DL2. The fourth data line DL4 can be on the opposite side of the first data line DL1, and the second data line DL2 can be between the fourth data line DL4 and the first data line DL1. For example, the third data line DL3, the first data line DL1, the second data line DL2, and the fourth data line DL4 can be arranged in this order from left to right in one direction (e.g., the x direction).

[0156] The third data line DL3 and the fourth data line DL4 can extend in opposite directions from the first division point DP1 respectively. The detour portion of the third data line DL3 can be on one side of the first region RA1, e.g., on the left side of the first region RA1 and can extend along a part of the first region RA1. The detour portion of the fourth data line DL4 can be on the other side of the first region RA1, e.g., on the right side of the first region RA1 and can extend along a part of the first region RA1.

[0157] The third data line DL3 can have characteristics (e.g., shape, length, etc.) substantially the same as those of the first data line DL1, and the fourth data line DL4 can have characteristics (e.g., shape, length, etc.) substantially the same as those of the second data line DL2. For example, the third data line DL3 and the fourth data line DL4 can have an asymmetric shape and / or can have different central angles of the detour portions. The third data line DL3 and the fourth data line DL4 can respectively include all the characteristics of the first data line DL1 and the second data line DL2.

[0158] The connection point between the extension portion and the detour portion of the third data line DL3 and the connection point between the extension portion and the detour portion of the first data line DL1 can be placed (e.g., located) on the first virtual diagonal line VOL1 as described with reference to Figure 8 Similarly, the connection point between the extension portion and the detour portion of the fourth data line DL4 and the connection point between the extension portion and the detour portion of the second data line DL2 can be placed (e.g., located) on the second virtual diagonal line VOL2 as described with reference to Figure 8 as described.

[0159] Some of the data lines DL in the first group DLa and the second group DLb can include an integral conductive layer, and others of the data lines DL can include conductive wires located on different layers.

[0160] As Figure 9BAs shown in [reference], the first data line DL1 may include a first conductive layer 2155 on the fourth insulating layer 2150. The extending portion DL1-L and the detouring portion DL1-C of the first data line DL1 may be formed integrally. In Figure 9B it is shown that a first insulating layer 2111, a second insulating layer 2141, and a third insulating layer 2143 are disposed between the substrate 100 and the fourth insulating layer 2150, and a fifth insulating layer 2160 and a sixth insulating layer 2180 are formed on the first data line DL1.

[0161] In contrast, as Figure 9C shown in [reference], the second data line DL2 may include a connection structure in which the first conductive layer 2155 on the fourth insulating layer 2150 is connected to the second conductive layer 2165 on the fifth insulating layer 2160. Most of the extending portion of the second data line DL2 may include the first conductive layer 2155, and the detouring portion DL2-C may include the second conductive layer 2165. The first conductive layer 2155 may be connected to the second conductive layer 2165 through a contact hole CNT (e.g., in the fifth insulating layer 2160) in the fifth insulating layer 2160 between the first conductive layer 2155 and the second conductive layer 2165.

[0162] The first conductive layer 2155 and the second conductive layer 2165 may include (e.g., may be) a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include (e.g., may be) a single-layer structure or a multi-layer structure including the above materials. In an embodiment, the first conductive layer 2155 and / or the second conductive layer 2165 may include (e.g., may be) three sub-layers of Ti / Al / Ti. The first conductive layer 2155 and the second conductive layer 2165 may include (e.g., may be) the same material. In some embodiments, the first conductive layer 2155 and the second conductive layer 2165 may include (e.g., may be) different materials.

[0163] Referring to Figure 8 and Figures 9A to 9C , one of the adjacent data lines DL may have the structure shown in Figure 9B , and the other of the adjacent data lines DL may have the structure shown in Figure 9C . In some embodiments, one of the adjacent data lines DL and the other adjacent data line DL may be adjacent data lines DL. For example, one of the adjacent data lines DL may have a monomer of the first conductive layer 2155 (e.g., as shown in Figure 9B ), and the other of the adjacent data lines DL may have a connection structure of the first conductive layer 2155 and the second conductive layer 2165 disposed on different layers (e.g., as shown in Figure 9C ). Therefore, as Figure 8 and Figure 9AAs shown, contact holes CNT may be alternately arranged among data lines DL in the x direction. In addition, as Figure 10 shown, the bypass portions of data lines DL may be alternately arranged up and down, with an insulating layer therebetween. As disclosed herein, when a line, component, or region is referred to as "adjacent" to another line, component, or region, the former may be, for example, a line, component, or region adjacent to, close to, or nearest to the latter.

[0164] Referring to Figure 8 and Figure 10 , the extended portion DL-L of data line DL may be arranged on the fourth insulating layer 2150 in the display area DA, but the bypass portions DL-C of data line DL may be alternately arranged up and down in the middle area MA, with the fifth insulating layer 2160 therebetween. For example, as Figure 10 shown, one bypass portion DL-C of a data line may be on the fourth insulating layer 2150, while another bypass portion DL-C of another data line adjacent to the said one data line may be on the fifth insulating layer 2160, and the fifth insulating layer 2160 may be between the one bypass portion DL-C and the another bypass portion DL-C. Since the bypass portions DL-C adjacent to each other among the bypass portions DL-C of data line DL are arranged on different layers in the middle area MA, the second pitch Δd2 described above with reference to Figure 8 may be smaller than the first pitch Δd1.

[0165] Figure 11 is a plan view of a part of the display panel 10 according to an embodiment.

[0166] Referring to Figure 11 , the display panel 10 may include a first area RA1 and a second area RA2 arranged in the display area DA where pixels P are arranged. In an embodiment, as referred to Figure 2A above, the display panel 10 may include a first hole 10H arranged in the first area RA1 and the second area RA2 (see Figure 2A ). In this case, Figure 11 the first area RA1 and the second area RA2 shown in

[0167] may respectively have the planar shape of the first hole 10H corresponding to the first area RA1 and the second area RA2. The first area RA1 and the second area RA2 may be separated (e.g., spaced apart) from each other in one direction (e.g., the x direction). In an embodiment, although in Figure 11The first region RA1 and the second region RA2 are shown arranged in the x direction, but the first region RA1 and the second region RA2 may be arranged in the y direction or may be arranged in a direction inclined with respect to the x direction and the y direction. Various appropriate modifications can be made.

[0168] The first region RA1 and the second region RA2 may be surrounded by an intermediate region MA. Portions of the intermediate region MA may be respectively arranged between the first region RA1 and the display region DA, between the second region RA2 and the display region DA, and / or between the first region RA1 and the second region RA2.

[0169] As referred to above Figure 7 as described, the first region RA1 may have a first width W1 in the x direction and have a shape in which its two opposite sides (e.g., the left side and the right side) are asymmetric with respect to a first center line CL1 passing through the first center C1 of the first width W1.

[0170] The second region RA2 may have a second width W2 in the x direction and have a shape in which its two opposite sides (e.g., the left side and the right side) are symmetric with respect to a second center line CL2 passing through the second center C2 of the second width W2. For example, the second region RA2 may have a circular shape in which its two opposite sides are symmetric with respect to the second center line CL2 passing through the second center C2. In some embodiments, the second region RA2 may have a shape such as a quadrilateral shape or an elliptical shape in which its two opposite sides are symmetric with respect to the second center line CL2 passing through the second center C2. In another embodiment, like the first region RA1, the second region RA2 may have a shape in which its two opposite sides are asymmetric with respect to the second center line CL2 passing through the second center C2.

[0171] Figure 12A is a plan view of signal lines arranged around the first region RA1 according to an embodiment, Figure 12B is Figure 12A an extraction plan view of some of the signal lines of Figure 12A and Figure 12B show a case where the signal lines include data lines DL.

[0172] Referring to Figure 12A , the data lines DL may extend in the y direction, some of the data lines DL may detour around the first region RA1 in the intermediate region MA, and some of the data lines DL may detour around the second region RA2 in the intermediate region MA.

[0173] Because the characteristics (e.g., shape, length, etc.) of the data lines DL (e.g., the data lines DL of the first group DLa and the data lines DL of the second group DLb) arranged around the first region RA1 are the same as those referred to above Figures 8 to 10Since the characteristics of the described data line DL are the same, a repeated description thereof will not be provided.

[0174] The data line DL may include a third group DLc and a fourth group DLd. The third group DLc includes data lines DL that wind around one side of the second region RA2 (e.g., the left side of the second region RA2 in Figure 12A ), and the fourth group DLd includes data lines DL that wind around the other side of the second region RA2 (e.g., Figure 12A the right side of the second region RA2 in

[0175] In a plan view, the data lines DL of the third group DLc and the data lines DL of the fourth group DLd may have symmetric shapes with respect to each other. For example, the winding portions DL-C of each of the data lines DL of the third group DLc and the winding portions DL-C of each of the data lines DL of the fourth group DLd may have symmetric shapes with respect to each other.

[0176] The data lines DL of the third group DLc and the data lines DL of the fourth group DLd may extend in different directions from the second division point DP2 (e.g., away from the second division point DP2). The data lines DL of the third group DLc may extend around the left edge of the second region RA2 from the second division point DP2 (e.g., away from the second division point DP2), and the data lines DL of the fourth group DLd may extend around the right edge of the second region RA2 from the second division point DP2 (e.g., away from the second division point DP2).

[0177] The second division point DP2 may be located on the same line as the second center line CL2. For example, the second division point DP2 may be located on the second virtual line DPL2, and the second virtual line DPL2 may be the second center line CL2.

[0178] Referring to Figure 12B , a fifth data line DL5 and a sixth data line DL6 may extend in opposite directions from the second division point DP2 (e.g., away from the second division point DP2). The winding portion DL5-C of the fifth data line DL5 may be located on one side of the second region RA2 (e.g., the left side of the second region RA2) and may extend around a part of the second region RA2. The winding portion DL6-C of the sixth data line DL6 may be located on the other side of the second region RA2 (e.g., the right side of the second region RA2) and may extend around a part of the second region RA2.

[0179] The fifth data line DL5 may include an extension portion DL5-L and a detour portion DL5-C. The extension portion DL5-L passes through the display area DA, and the detour portion DL5-C connects the extension portion DL5-L and is located in the middle area MA. The detour portion DL5-C of the fifth data line DL5 may have a shape substantially the same as that of a part of the second region RA2. For example, in a plan view, the detour portion DL5-C of the fifth data line DL5 may have a substantially semi-circular shape.

[0180] The sixth data line DL6 may include an extension portion DL6-L and a detour portion DL6-C. The extension portion DL6-L passes through the display area DA, and the detour portion DL6-C connects the extension portion DL6-L and is located in the middle area MA. The detour portion DL6-C of the sixth data line DL6 may have a shape substantially the same as that of a part of the second region RA2. For example, in a plan view, the detour portion DL6-C of the sixth data line DL6 may have a substantially semi-circular shape.

[0181] The detour portion DL5-C of the fifth data line DL5 and the detour portion DL6-C of the sixth data line DL6 may have substantially the same length. The central angle α2 of the detour portion DL5-C of the fifth data line DL5 may be equal to the central angle β2 of the detour portion DL6-C of the sixth data line DL6. The central angle (e.g., the central angle α2 or β2) represents an angle formed by a virtual arc connecting two opposite ends (e.g., two opposite ends of the detour portion DL5-C or DL6-C) of the detour portion DL-C that bypasses around the second region RA2 by the second center C2 and each data line DL (e.g., the fifth data line DL5 or the sixth data line DL6).

[0182] Although according to the embodiments described with reference to Figures 7 to 12B the signal lines extending in the y direction (e.g., extending in the y direction or passing through in the y direction) include data lines DL, and the data lines DL have an asymmetric shape with respect to the first virtual line DPL1, the embodiments of the present disclosure are not limited thereto. In another embodiment, the above structure may be applied to signal lines extending in the x direction (e.g., extending in the x direction or passing through in the x direction). For example, referring to Figure 6 the scan lines SL, the previous scan line SL-1, the next scan line SL+1, and / or the emission control line EL described may extend in the x direction.

[0183] Figure 13 is a plan view of a part of the display panel 10 according to an embodiment. In the embodiment, Figure 13 it is shown that the signal lines bypassing around the first region RA1 and the second region RA2 include scan lines SL.

[0184] Referring to Figure 13, the scan line SL can extend in one direction (e.g., the x direction). When the scan line SL extends in one direction (e.g., the x direction), the scan line SL can extend as a whole in one direction (e.g., the x direction) (e.g., can extend generally or substantially in the x direction). For example, the scan line SL can extend in one direction (e.g., the x direction) and locally detour around the first region RA1.

[0185] Each scan line SL can include an extending portion SL-L and a detouring portion SL-C. The extending portion SL-L passes through the display area DA, and the detouring portion SL-C is located in the intermediate area MA and connects the extending portion SL-L. The detouring portion SL-C can extend around a part of the first region RA1 in the intermediate area MA.

[0186] The scan line SL can include a first group SLa of scan lines and a second group SLb of scan lines. The first group SLa and the second group SLb are respectively arranged on two opposite sides (e.g., the top side and the bottom side) of the first virtual line DPL1'. The scan lines SL of the first group SLa and the scan lines SL of the second group SLb can be arranged asymmetrically with respect to the first virtual line DPL1'. For example, with respect to the first virtual line DPL1', the planar shape of the detouring portion SL-C of each of the scan lines SL in the first group SLa can be different from the planar shape of the detouring portion SL-C of each of the scan lines SL in the second group SLb.

[0187] The first scan line SL1, which is one of the scan lines SL in the first group SLa, and the second scan line SL2, which is one of the scan lines SL in the second group SLb, can extend in opposite directions respectively from the first dividing point DP1' (e.g., away from the first dividing point DP1'). The detouring portion of the first scan line SL1 can extend around one side of the first region RA1 (e.g., Figure 13 the top side of the first region RA1 in Figure 13 ), and the detouring portion of the second scan line SL2 can extend around the other side of the first region RA1 (e.g.,

[0188] In a plan view, the first region RA1 may have a first width W1' in the y direction and may have an asymmetric shape with respect to a first center line CL1' passing through the first width W1' and extending in the x direction. One side of the first region RA1 may have an approximately (or substantially) semi-elliptical shape with respect to the first center line CL1', and the other side of the first region RA1 may have an approximately (or substantially) quadrilateral shape (e.g., a quadrilateral shape with rounded corners) with respect to the first center line CL1'. In an embodiment, as referred to Figure 2A as described, the display panel 10 may include a first hole 10H disposed in the first region RA1 (see Figure 2A ). In this case, Figure 13 the first region RA1 shown in

[0189] The scan lines SL of the first group SLa may extend around the edge of the first region RA1 and maintain a first distance ds1' from the edge of the first region RA1. The first distance ds1' may have a constant value. For example, the bypass portion of the first scan line SL1 may be separated (e.g., spaced apart) from the edge of the first region RA1 by a constant interval. In some embodiments, the bypass portion of the innermost scan line among the scan lines of the first group SLa may be spaced apart from the edge of the first region RA1 by the first distance ds1' as the bypass portion extends around the first region RA1, and the bypass portions of the other scan lines of the first group SLa may be spaced apart from the edge of the first region RA1 by at least the first distance ds1' as the bypass portions extend around the first region RA1.

[0190] Similarly, the scan lines SL of the second group SLb may extend around the edge of the first region RA1 and maintain a second distance ds2' from the edge of the first region RA1. The second distance ds2' may have a constant value. For example, the bypass portion of the second scan line SL2 may be separated (e.g., spaced apart) from the edge of the first region RA1 by a constant interval. The second distance ds2' may have the same value as the first distance ds1'. For example, in some embodiments, the bypass portion of the innermost scan line among the scan lines of the second group SLb may be spaced apart from the edge of the first region RA1 by the second distance ds2' as the bypass portion extends around the first region RA1, and the bypass portions of the other scan lines of the second group SLb may be spaced apart from the edge of the first region RA1 by at least the second distance ds2' as the bypass portions extend around the first region RA1.

[0191] The first division point DP1' may be located on the first virtual line DPL1', and the first virtual line DPL1' may be separated (e.g., spaced apart) from the first center line CL1' in the y direction. The bypass portions of the first scan line SL1 and the second scan line SL2 may have substantially the same length. Thus, as described above, the resistance difference between the scan lines can be reduced or minimized, and the corresponding deterioration of the display quality can be reduced or minimized.

[0192] The display panel 10 may include a second region RA2 adjacent to the first region RA1. As Figure 13 shown, the second region RA2 may have a symmetric shape with respect to a second center line CL2' passing through the second region RA2 and extending in the x direction.

[0193] The scan line SL may include a third group SLc including scan lines and a fourth group SLd including scan lines. The third group SLc bypasses around one side of the second region RA2 (e.g., Figure 13 the top side of the second region RA2 in Figure 13 ), and the fourth group SLd bypasses around the other side of the second region RA2 (e.g.,

[0194] the bottom side of the second region RA2 in

[0195] In a plan view, the scan lines SL of the third group SLc and the scan lines SL of the fourth group SLd may have a symmetric shape. For example, each bypass portion SL-C of the scan lines SL of the third group SLc may have a shape symmetric to the bypass portion SL-C of each (or a corresponding one) of the scan lines SL of the fourth group SLd.

[0196] The second division point DP2' may be located on the same line as the second center line CL2'. For example, the second division point DP2' may be located on the second virtual line DPL2', and the second virtual line DPL2' may be the second center line CL2'.

[0197] Figure 14A is a plan view of a part of the display panel 10 according to an embodiment, Figure 14B is the display panel 10 along Figure 14AA cross-sectional view taken along line XIV-XIV'. Figure 14A It shows a case where the signal line that detours around the first region RA1 is the data line DL.

[0198] Referring to Figure 14A , the data line DL may include a first group DLa and a second group DLb. The first group DLa includes data lines DL arranged on the left side of the first virtual line DPL1, and the second group DLb includes data lines DL arranged on the right side of the first virtual line DPL1. The data lines DL of the first group DLa and the data lines DL of the second group DLb may be arranged asymmetrically with respect to the first virtual line DPL1. For example, in a plan view, the detour portion DL-C of the data lines DL of the first group DLa and the detour portion DL-C of the data lines DL of the second group DLb may have an asymmetric shape with respect to the first virtual line DPL1.

[0199] As described above (e.g., referring to Figure 7 etc.), the first region RA1 may have an asymmetric shape with respect to the first center line CL1. The detour portion DL-C of the data lines DL of the first group DLa may maintain a constant interval (e.g., the first distance ds1) from the edge of the first region RA1. Similarly, the detour portion DL-C of the data lines DL of the second group DLb may maintain a constant interval (e.g., the second distance ds2) from the edge of the first region RA1.

[0200] The first center line CL1 may be the same as the first virtual line DPL1. In this case, the detour portion DL-C of the data lines DL of the first group DLa and the detour portion DL-C of the data lines DL of the second group DLb may have different lengths. In this case, it may cause a reduction in brightness and / or color deviation, but at least a part of the width or thickness of each data line DL of the first group DLa may be different from at least a part of the width or thickness of each data line DL of the second group DLb. For example, the width or thickness of one of the detour portion DL-C of the data lines DL of the first group DLa and the detour portion DL-C of the data lines DL of the second group DLb may be greater than the width or thickness of the other of the detour portion DL-C of the data lines DL of the first group DLa and the detour portion DL-C of the data lines DL of the second group DLb. In an embodiment, as shown in Figure 14A and Figure 14B , at least a part of the width of each data line DL of the first group DLa may be smaller than at least a part of the width of each data line DL of the second group DLb.

[0201] Referring to Figure 14B, the width dw1 of at least a part of the first data line DL1 of the first group DLa can be smaller than the width dw2 of at least a part of the second data line DL2 of the second group DLb. In an embodiment, the width dw2 of the part of the second data line DL2 among the data lines DL of the second group DLb located in the middle region MA can be greater than the width dw1 of the part of the first data line DL1 among the data lines DL of the first group DLa located in the middle region MA. In an embodiment, the length of the detour part of the second data line DL2 can be greater than the length of the detour part of the first data line DL1, and the width dw2 of the detour part of the second data line DL2 can be greater than the width dw1 of the detour part of the first data line DL1.

[0202] With this structure, the resistance deviation between the first data line DL1 and the second data line DL2 can be reduced, so that luminance reduction and / or color deviation can be prevented, minimized or reduced.

[0203] Figure 15 is a plan view of a part of the display panel 10 according to an embodiment. Figure 15 It shows the case where the signal line that detours around the first region RA1 is the data line DL.

[0204] Refer to Figure 15 , the data line DL can detour around the first region RA1. The data line DL can be symmetrically arranged with respect to the first virtual line DPL1 on which the first division point DP1 is located. The data line DL can include a first group DLa and a second group DLb. The first group DLa includes the data lines DL arranged on one side (e.g., the left side) of the first virtual line DPL1, and the second group DLb includes the data lines DL arranged on the other side (e.g., the right side) of the first virtual line DPL1. The data lines DL of the first group DLa and the data lines DL of the second group DLb can be symmetrically arranged with respect to the first virtual line DPL1. For example, in the plan view, the detour part DL-C of the data line DL of the first group DLa and the detour part DL-C of the data line DL of the second group DLb can have a symmetrical shape with respect to the first virtual line DPL1.

[0205] As described above (e.g., refer to Figure 7)As described above, the first region RA1 may have an asymmetric shape with respect to the first center line CL1. In a plan view, the shape of the first region RA1 may be different from the shape of the bypass portion DL-C of the data lines DL of the first group DLa and / or the shape of the bypass portion DL-C of the data lines DL of the second group DLb. For example, in some embodiments, the shape of the bypass portion DL-C of the data lines DL of the first group DLa may have substantially the same shape as the portion of the first region RA1 around which they extend, and the shape of the bypass portion DL-C of the data lines DL of the second group DLb may have substantially the same shape as the portion of the first region RA1 around which they extend. Thus, the bypass portion DL-C of the data lines DL of the first group DLa may have a first distance ds1" from the edge of the first region RA1 (e.g., may be spaced apart from the first region RA1 by the first distance ds1"), and the first distance ds1" may have a variable value depending on the measurement point. For example, the first distance ds1" may vary as the bypass portion DL-C of the data lines DL of the first group DLa extends around a portion of the first region RA1. In contrast, the bypass portion DL-C of the data lines DL of the second group DLb may have a second distance ds2" from the edge of the first region RA1 (e.g., may be spaced apart from the first region RA1 by the second distance ds2"), and the second distance ds2" may have a constant value.

[0206] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment is generally to be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display panel, the display panel having at least one hole in a display area, and the display panel comprising: a substrate; a plurality of display elements located on the substrate, the plurality of display elements being two-dimensionally arranged around the at least one hole and defining the display area; and a plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, wherein the at least one hole includes a first hole, the first hole having a first width in a second direction different from the first direction, and the first hole having two sides, the two sides having an asymmetrical shape with respect to a first center line passing through the center of the first width, wherein the plurality of signal lines includes a first signal line and a second signal line adjacent to each other and divided by a first virtual line extending in the first direction, the first signal line winding around a first side of the first hole, and the second signal line winding around a second side of the first hole opposite to the first side, and wherein the first signal line and the second signal line are asymmetrical with respect to the first virtual line between the first signal line and the second signal line.

2. The display panel according to claim 1, wherein, The first virtual line is spaced apart from the first center line in the second direction.

3. The display panel according to claim 1, the display panel further comprising an intermediate area located between the first hole and the display area, Among them, the first signal line including a first winding portion located in the intermediate area and winding around the first side of the first hole, and the second signal line including a second winding portion located in the intermediate area and winding around the second side of the first hole.

4. The display panel according to claim 3, wherein, The first winding portion and the second winding portion have an asymmetrical shape with respect to the first virtual line.

5. The display panel according to claim 3, wherein, A first distance interval between the first signal line and the second signal line located in the display area is greater than a second distance interval between the first signal line and the second signal line located in the intermediate area.

6. The display panel according to claim 1, wherein, One of the first signal line and the second signal line includes: a first conductive layer; and a second conductive layer located on the first conductive layer, with an insulating layer located between the second conductive layer and the first conductive layer, the second conductive layer being connected to the first conductive layer through a contact hole located in the insulating layer.

7. The display panel according to claim 1, Among them, the plurality of signal lines further including: a third signal line located on one side of the second signal line, with the first signal line located between the third signal line and the second signal line; and a fourth signal line located on one side of the first signal line, with the second signal line located between the fourth signal line and the first signal line, and wherein the third signal line and the fourth signal line are asymmetrical with respect to the first virtual line.

8. The display panel according to claim 7, Among them, each of the first signal line and the third signal line including: an extending portion extending in the first direction; and a winding portion connected to the extending portion and arranged around the first side of the first hole, and Among them, a first connection point between the extension portion and the bypass portion of the first signal line and a second connection point between the extension portion and the bypass portion of the third signal line are arranged on a first virtual diagonal line inclined with respect to the first direction and the second direction.

9. The display panel according to claim 1, wherein, The plurality of signal lines include data lines or scan lines.

10. The display panel according to claim 1, wherein, Each of the plurality of display elements includes an organic light-emitting diode.

11. A display panel having a first hole and comprising: A plurality of display elements two-dimensionally arranged around the first hole; And A plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, Wherein the first hole has a first width in a second direction different from the first direction, and both sides of the first hole have an asymmetric shape with respect to a first center line passing through the center of the first width in the first direction, Wherein the plurality of signal lines include a first signal line and a second signal line adjacent to each other and divided by a first virtual line extending in the first direction, the first signal line bypasses around a first side of the first hole, and the second signal line bypasses around a second side of the first hole opposite to the first side, and Wherein the first signal line and the second signal line are asymmetric with respect to the first virtual line between the first signal line and the second signal line.

12. The display panel according to claim 11, Among them, Each of the first signal line and the second signal line includes: an extension portion, both extending in the first direction and spaced apart from each other; and a bypass portion connected to each of the extension portions, Wherein the bypass portion of the first signal line bypasses around the first side of the first hole, and the bypass portion of the second signal line bypasses around the second side of the first hole, and Wherein the bypass portion of the first signal line and the bypass portion of the second signal line are asymmetric with respect to the first virtual line.

13. The display panel according to claim 12, wherein, The plurality of signal lines further include: A third signal line located on one side of the second signal line and making the first signal line located between the third signal line and the second signal line; and A fourth signal line located on one side of the first signal line and making the second signal line located between the fourth signal line and the first signal line, and The third signal line and the fourth signal line are asymmetric with respect to the first virtual line.

14. The display panel according to claim 13, Among them, The third signal line includes: an extension portion extending in the first direction; and a bypass portion connected to the extension portion and arranged around the first side of the first hole, and Wherein a first connection point between one of the extension portions of the first signal line and the bypass portion and a second connection point between the extension portion and the bypass portion of the third signal line are arranged along a first virtual diagonal line inclined with respect to the first direction.

15. The display panel according to claim 13, Among them, The fourth signal line includes: an extending portion extending along the first direction; and a bypassing portion connected to the extending portion and disposed around the second side of the first hole, and wherein, a third connection point between one of the extending portions of the second signal line and the bypassing portion and a fourth connection point between the extending portion and the bypassing portion of the fourth signal line are arranged along a second virtual oblique line inclined with respect to the first direction.

16. The display panel according to claim 13, wherein, Each of the first signal line and the fourth signal line includes: a first conductive layer; and a second conductive layer located on the first conductive layer, with an insulating layer located between the second conductive layer and the first conductive layer, and the second conductive layer is connected to the first conductive layer through a contact hole located in the insulating layer.

17. The display panel according to claim 12, Among them, the bypassing portion of the first signal line is spaced apart from the first side of the first hole by a constant distance, and the bypassing portion of the second signal line is spaced apart from the second side of the first hole by a constant distance.

18. The display panel according to claim 11, wherein, The first virtual line is spaced apart from the first center line along the second direction.

19. The display panel according to claim 12, Among them, the first virtual line and the first center line are the same line, and wherein, the width of one of the bypassing portions of the first signal line and the second signal line is greater than the width of the other of the bypassing portions of the first signal line and the second signal line, or the thickness of one of the bypassing portions of the first signal line and the second signal line is greater than the thickness of the other of the bypassing portions of the first signal line and the second signal line.

20. The display panel according to claim 11, Among them, the display panel includes: a substrate; a display layer located on the substrate and including the plurality of display elements; and a packaging layer located on the display layer, and wherein, the first hole penetrates a stacked structure including the substrate, the display layer, and the packaging layer.

21. An electronic device, the electronic device includes: a display panel having a first hole; and at least one component corresponding to the first hole of the display panel, wherein, the display panel includes: a plurality of display elements two-dimensionally arranged around the first hole; and a plurality of signal lines electrically connected to the plurality of display elements and extending along a first direction, wherein, the first hole has a first width along a second direction different from the first direction, and both sides of the first hole have an asymmetric shape with respect to a first center line passing through the center of the first width, wherein, the plurality of signal lines includes a first signal line and a second signal line adjacent to each other and divided by a first virtual line extending along the first direction, the first signal line includes a first bypassing portion bypassing around the first side of the first hole, the second signal line includes a second bypassing portion bypassing around the second side opposite to the first side of the first hole, and Among them, the first detour portion of the first signal line and the second detour portion of the second signal line are asymmetric with respect to the first virtual line between the first signal line and the second signal line.

22. The electronic device according to claim 21, Among them, The plurality of signal lines further includes: a third signal line located on one side of the second signal line, with the first signal line located between the third signal line and the second signal line, and the third signal line includes a third detour portion that detours around the first side of the first hole; and a fourth signal line located on one side of the first signal line, with the second signal line located between the fourth signal line and the first signal line, and the fourth signal line includes a fourth detour portion that detours around the second side of the first hole, and Among them, the third detour portion of the third signal line and the fourth detour portion of the fourth signal line are asymmetric with respect to the first virtual line.

23. The electronic device according to claim 22, Among them, The first signal line includes an extension portion extending in the first direction and the first detour portion connected to the extension portion, Among them, the third signal line includes an extension portion extending in the first direction and the third detour portion connected to the extension portion, and Among them, the first connection point between the extension portion and the first detour portion of the first signal line and the second connection point between the extension portion and the third detour portion of the third signal line are arranged along a first virtual oblique line inclined with respect to the first direction.

24. The electronic device according to claim 21, wherein, The first virtual line is spaced apart from the first center line along the second direction.

25. The electronic device according to claim 21, Among them, The first virtual line and the first center line are the same line, and Among them, the width of one of the first detour portion and the second detour portion is greater than the width of the other of the first detour portion and the second detour portion, or the thickness of one of the first detour portion and the second detour portion is greater than the thickness of the other of the first detour portion and the second detour portion.

26. The electronic device according to claim 21, wherein, The at least one component includes an electronic component that emits or receives light through the first hole.

27. The electronic device according to claim 26, wherein, The electronic component includes a camera, a sensor for recognizing a part of the human body, or a lamp for outputting light.

28. The electronic device according to claim 21, Among them, The display panel further has a second hole spaced apart from the first hole, and Among them, the display panel further includes: An additional component corresponding to the second hole.

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