Energy harvesting circuit, corresponding system and operation method

Abstract

Various embodiments of the present disclosure relate to energy harvesting circuits, corresponding systems, and operating methods. A first RF to DC circuit receives an RF signal and generates a first converted signal that is transmitted to an energy storage circuit. The second RF to DC circuit is a down-scaled copy of the first RF to DC circuit, and it generates a second converted signal from an RF signal indicating an open circuit voltage of the first RF to DC circuit. The first RF to DC portion includes N sub-stages, wherein a subset of the sub-stages are selectively enabled. A window comparison of the second converted signal generates a first signal and a second signal, and the first signal and the second signal indicate whether the second converted signal is within a range of values ​​proportional to a voltage reference signal. When the performed window comparison has a first result and a second result, respectively, a subset of the sub-stages is selectively disabled or enabled, respectively.

Description

[0001] Priority declaration

[0002] This application claims the benefit of Italian Patent Application No. 102019000022950, ​​filed on December 4, 2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] This description relates to energy harvesting.

[0004] One or more embodiments may find use in various applications, such as in RF energy harvesting devices, such as ultra-low power (nanowatt) RF energy harvesting applications for battery-free systems (such as wireless battery chargers or wireless sensor platforms). Background Art

[0005] In energy harvesting (or, by other names, power harvesting or energy scavenging), energy from one or more sources (such as, solar panels, wind turbines, various types of thermal generators) is stored for possible use in a device (such as, a wireless portable device or a wireless sensor (for example, in a wireless sensing platform application)).

[0006] The ability to efficiently track available (electrical) power in systems could help meet the growing demand for, for example, wireless sensor networks (WSNs), platforms that collect, process and share data in wireless operations, often in locations that are difficult to reach and serve.

[0007] In particular, WSNs used to wirelessly collect and share data over Internet of Things (IoT) networks may include sensors located in locations that are difficult to reach and serve.

[0008] As a result, there is a growing demand for energy harvesting solutions that can facilitate the realization of battery-free and / or fire-and-forget sensor nodes, which in turn can facilitate the production of devices suitable for near-ubiquitous use and essentially maintenance-free, such as for IoT (Internet of Things) applications.

[0009] Wireless power transfer (WPT) involves dealing with very different power conditions. In fact, depending on the distance between the power transmitter (PTX) and the power receiver (PRX), the antenna orientation and the transmission channel, those systems can handle very low power or relatively high power and often have unpredictable variations in the available input power.

[0010] As in Figure 1As illustrated in , the RF to DC converter efficiency of the power harvester (e.g., operating at a frequency of 868 MHz, providing a maximum output voltage of approximately 2.3 V) can increase from zero to a maximum value within a first input power range of values ​​R1, remain approximately constant near the maximum value within a second range of values ​​R1, and decrease from the maximum value to zero within a third subsequent input power range of values ​​R2.

[0011] The main purpose of existing solutions is to maximize the circuit efficiency at a given input power level (e.g., within the range of R1), while ignoring the degradation of the power converter due to input power variation issues, which may reduce efficiency and output power levels.

[0012] Ignoring this effect can result in significant energy losses, which can be detrimental to the operation of applications based on energy harvesting circuits.

[0013] As disclosed by Scorcioni, S et al.: “A 868MHz CMOS RF-DC power converterwith-17dBminput power sensitivity and efficiency higher than 40%over 14dBinput power range”, 2012 Proceedings of the European Solid-State Circuits Conference (ESSCIRC), IEEE, 2012, pp. 109-112 (incorporated by reference), discusses a CMOS RF-DC converter circuit operating at 868MHz for RFID and remote powering applications, where the reconfigurable architecture of the converter facilitates the circuit to operate with very high efficiency over a very wide input power range.

[0014] However, this approach may have one or more of the following disadvantages: reconfiguration may be performed solely statically, for example, only during time periods when input power is constant; the architecture may not automatically adapt; and efficiency may be reduced during time periods when input power varies.

[0015] Regardless of the approach used, improving the efficiency of power transfer is a desirable goal to achieve under any operating conditions.

[0016] There is a need in the art to provide such improved solutions. Summary of the invention

[0017] One embodiment includes energy harvesting circuitry, and more particularly, includes adaptive maximum power transfer energy harvesting circuitry.

[0018] One or more embodiments may be directed to a corresponding system.

[0019] One or more embodiments may include a corresponding method.

[0020] One or more embodiments may include an RF to DC converter circuit configured to operate in an adaptive maximum power transfer method.

[0021] One or more embodiments may facilitate providing dynamically optimized energy efficiency over a wide range of input powers.

[0022] One or more embodiments may advantageously facilitate miniaturization, thereby providing a harvester circuit / device with reduced size. For example, the components used to perform dynamic efficiency improvement may occupy only 2% of the total chip area.

[0023] One or more embodiments may improve the flexibility of energy harvesting systems, such as improving circuit performance over a sufficient range of input power values.

[0024] Since the power consumption level is negligible, one or more embodiments may be applicable to battery-less systems.

[0025] One or more embodiments may facilitate increasing data update rates in wireless sensor networks powered via energy harvesting systems.

[0026] One or more embodiments may facilitate the use of (non-real-time) battery-free sensors to approximate real-time system performance, thereby facilitating increased data exchange rates, such as for Bluetooth Low Energy (BLE) radio applications.

[0027] One or more embodiments advantageously and innovatively facilitate continuous flow of energy from an energy harvester to an RF-to-DC converter, avoiding disconnection of the harvester to measure open circuit voltage (Voc).

[0028] One or more embodiments may facilitate ultra-low power energy harvesting in the context of wireless sensor networks and IoT.

[0029] In one or more embodiments, energy harvester circuits according to the present disclosure (and corresponding systems and methods) may provide built-in reference voltage sensing circuitry configured to perform dynamic efficiency improvements, for example, in ultra-low power applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0031] Figure 1 shows the RF to DC converter efficiency for the power harvester;

[0032] Figure 2is an exemplary architecture of an RF to DC converter circuit according to the present disclosure,

[0033] Figure 3 , 4 and 5 are diagrams showing the principle underlying the solution according to the present disclosure,

[0034] Figure 6 is an exemplary architecture of an RF to DC converter circuit that may be reconfigured according to the present disclosure,

[0035] Figure 7 is an exemplary diagram of a method according to the present disclosure,

[0036] Figure 8 is an exemplary diagram of possible voltage signals in one or more embodiments,

[0037] Fig. 9 is an exemplary diagram of possible power signals in one or more embodiments. DETAILED DESCRIPTION

[0038] In the following description, one or more specific details are shown to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0039] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to one embodiment or the same embodiment.

[0040] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0041] The references used herein are provided for convenience only and therefore do not define the extent of protection or the scope of the embodiments.

[0042] The drawings are in simplified form and not to exact scale. For simplicity, directional (upward / downward, etc.) or motion (forward / backward, etc.) terms may be used with respect to the drawings. The term "coupled" and similar terms do not necessarily indicate direct and direct connections, but also include connections through intermediate elements or devices.

[0043] One or more embodiments may utilize electromagnetic waves as a power source. For example, one or more embodiments may be applied to a radio frequency (RF) energy harvesting circuit.

[0044] The RF harvester as exemplified herein can rely on power extracted from RF radio waves emitted by a hub or base station, for example, due to a converter circuit. Thus, the energy harvester as exemplified herein can be used as a so-called radio frequency to direct current (RF to DC for short) converter.

[0045] The ability to operate at (very) low power levels can facilitate the use of RF energy harvesters to achieve high operating distances (r) from the power emitting source. The propagation of RF energy can be modeled by the Friis equation, which results in the power in free space increasing with r 2 The decrease is reduced by:

[0046]

[0047] Where P R is the available power at the input of the receiving antenna, P T is the output power of the transmitting antenna, G T and G R are the gains of the transmitting and receiving antennas respectively, and λ is the wavelength.

[0048] The lowest RF input power that allows the circuit to convert RF energy to DC is called sensitivity, and this is an advantage of such a circuit.

[0049] Another performance parameter is power conversion efficiency (PCE), or efficiency for short, which is the ratio of the RF input power P in Converted to DC output power P out The measure of , namely:

[0050] PCE=P out / P in

[0051] Therefore, designing an energy harvester may involve: improving sensitivity to increase the operating distance; and increasing PCE, which can increase the power consumption for the same input power P. in The output power P out .

[0052] In a power generation system (such as an RF energy harvester), the RF to DC (conversion) efficiency may reach an "optimal" energy transfer point, resulting in the highest (maximum) power generation point.

[0053] The ability to (quickly and accurately) adjust the electrical operating point of the system to maximize effective power generation may be of interest.

[0054] Circuit simplicity can be an advantageous feature of circuits for (ultra-) low power energy harvesting, so that the absorbed energy can be reduced to a sufficiently low level to achieve a positive balance between energy saved and energy consumed in a performance improvement function.

[0055] Throughout the drawings, Vin represents an input line of the energy harvesting circuit 10, which is adapted to receive an input voltage V from an energy source (not visible in the drawings). in (t). Such an energy source may be, for example, a radio frequency source, such as a radio frequency (RF) signal having a frequency of 868 MHz, which may be sensed via a receiving antenna RX.

[0056] Input voltage V in (t) can be expressed as:

[0057] V in (t) = V A sin(ωt)

[0058] Where V A is the amplitude of the ac input signal, ω is the angular frequency given by ω=2πf, and f is the operating frequency.

[0059] exist Figure 2 In one or more embodiments illustrated in , the matching network 11 may facilitate coupling the antenna RX to the energy harvesting circuit 10 , thereby facilitating providing a sensed signal Vin at an input node Vin of the energy harvester.

[0060] As in Figure 2 As illustrated in FIG. 1 , such an energy harvesting circuit 10 may include two circuit parts: a power converter 12 including a first radio frequency to direct current (RF to DC) circuit coupled to an input node Vin and configured to receive an input signal Vin therefrom and apply an RF to DC conversion process thereto to generate a converted signal at an output node Vout; and an energy storage circuit part C s , coupled to an output node Vout of the first RF-to-DC circuit and configured to provide a converted signal Vout therefrom, for example, a capacitor C s configured to store energy harvested by the energy harvesting circuit 10; and a sensing circuit 14, comprising a second RF to DC circuit, the second RF to DC circuit comprising a reduced-size copy of the first RF to DC circuit, wherein the second RF to DC circuit is configured to receive a first signal at an input node Vin and generate a scaled conversion signal at a sensing node Vocs indicating an open-circuit voltage of the first RF to DC circuit.

[0061] One or more embodiments of such an energy harvesting circuit 10 are discussed in U.S. Patent Application No. 16 / 849,370 (based on Italian Patent Application No. 102019000006086 filed on April 18, 2019), which is incorporated herein by reference.

[0062] In one or more embodiments, the Voc (open circuit voltage) sensing circuit 14 may correspond to a “miniaturized,” scaled-down copy of the power converter 12 and provide a measure proportional to the open circuit voltage Voc (eg, referred to as Vocs) at the corresponding output node Vocs.

[0063] In one or more embodiments, power converter 12 may occupy a high percentage of the volume / area of ​​overall device 10 and function as an energy generator.

[0064] For example, the sensing circuit 14 may be a scaled version of the power converter 12 , eg, with a reduced area, and is dedicated to measuring the open circuit voltage Voc.

[0065] One or more embodiments may use a second RF-to-DC circuit as a small "virtual" RF-to-DC unit that is configured to reproduce the behavior of a "main" RF-to-DC system, while the virtual unit is capable of providing, for example, a measurement of the open circuit voltage of the main system, which in turn can be used to perform dynamic system efficiency improvement functions.

[0066] Therefore, relative to the volume / area of ​​the power converter 12 , the volume / area of ​​the sensing circuit 14 can be smaller and almost negligible.

[0067] In the case where the power converter 12 is dimensioned to provide 1 μA, an area ratio of 1 / 10, ie a scaling factor equal to 10, may result.

[0068] In one or more embodiments, the ratio of the volume / area of ​​the sensing circuit 14 to the volume / area of ​​the power converter 12 will be the (only) source of power inefficiency for the arrangement.

[0069] For example, through proper design of the apparatus 10, this inefficiency can be reduced to a minimum, (well below) the inefficiency level of conventional solutions.

[0070] A further increase in energy efficiency may result from the continuous flow of energy from the device 10 to the converter, for example due to the possibility of avoiding disconnection to measure the Voc voltage.

[0071] Likewise, with respect to the overall system, the possibility of reducing the size of the system (system miniaturization) will have a synergistic effect, as long as the additional volume / area occupied by the sensing circuit 14 will be compensated (to a large extent) by the improvement in energy efficiency.

[0072] As a result, the volume / area ratio of the second RF-to-DC circuit may be much lower or better yet negligible relative to the volume / area ratio of the power converter 12 in one or more embodiments.

[0073] As in Figure 2 In one or more embodiments illustrated in the figures: a first RF to DC of the power converter 12 may include a first set of N (voltage) converter circuit sub-stages, such as a set of N multiplier stages, to provide a first (e.g., maximum) conversion factor N, such as N=4, wherein multiple stages N of the first converter circuit sub-stages N may be selectively enabled, for example, to provide a certain conversion factor, as discussed below; and a second RF to DC in the sensing circuit 14 may include a second set of M (voltage) converter circuit sub-stages, such as a set of M=N / 2 multiplier stages, to provide a second (e.g., scaled) conversion factor M, for example, when N=4, M=N / 2=2.

[0074] In one or more embodiments, the ratio between the first multiplication factor and the second multiplication factor may advantageously be one-half, thus providing a reference of half the open circuit voltage Voc, for example, Vocs=Voc / M=Voc / 2.

[0075] The power delivered by a radio frequency to direct current (RF to DC for short) energy converter to a typical load depends on its internal impedance. In particular, maximum power transfer occurs if there is a match between the internal resistance, Rs, of the RF to DC device and the load, Rs.

[0076] The RF to DC converter circuit converts the RF energy into DC electricity proportional to the (input) power received at the antenna. For example, the (output) power provided can be expressed as:

[0077] Pout=(-Vout 2 +Vout*Voc) / Rs

[0078] Where: Voc is the open circuit output voltage of the RF to DC circuit, and Rs is the RF to DC internal resistance. The output power provided by the RF to DC circuit is parabolic with respect to the output voltage, having a maximum value at the output voltage Vout = Voc / 2, which is again the same condition obtained by making Rs = RL.

[0079] This presents a relevant problem during the design phase. The RF to DC internal impedance Rs depends on the received power. Therefore, during the design phase, the power transfer may be optimized only for a single predefined received power and load condition.

[0080] Such conditions are difficult to match in real life: in practice, for a defined transmit power and frequency, in wireless power transfer the received power depends strongly on environmental conditions and the distance between the power receiver and the transmitter. In general, the received power at the input of the RF to DC circuit cannot be considered fixed, and load conditions vary greatly during power transfer.

[0081] Therefore, the system may lose efficiency when the relative distance between the power transmitter and the power receiver changes or if environmental conditions change, which often happens in practice.

[0082] Figure 3 Including as in Figure 2 Schematic diagram of the principle of an embodiment of an energy harvesting circuit 10 is illustrated in FIG.

[0083] In one or more embodiments, the open circuit voltage Voc of the first RF to DC circuit of the energy harvesting circuit 10 may vary in an almost linearly increasing manner relative to the input power Pin sensed via the at least one antenna RX, such as Figure 3 represented by the examples in part a).

[0084] For example, the trend of such a quasi-linear curve may be proportional to the N sub-stages in the first RF to DC circuit.

[0085] In this considered example: when the input power level Pin has a first power value P1, the open circuit voltage level Voc has a first voltage value Voc1, wherein these values ​​are as in Figure 3 The coordinate values ​​of such a first operating point of the first RF to DC circuit portion in the Voc-Pin diagram illustrated in part a) of FIG. 1 ; and when the input power level Pin has a second power value P2 higher than the first power value P1, the open circuit voltage level Voc has a second voltage value Voc2 higher than the first voltage value Voc1, wherein these values ​​are as follows Figure 3 The coordinate values ​​of such an operating point from the first RF to DC in the Voc-Pin diagram illustrated in part a).

[0086] As in Figure 3 In one or more embodiments illustrated in part b), the relationship between the output power Pout and the output voltage Vout presents a basic (inverted; concave, concave downward) parabolic trend with a peak value located at Vout = Voc / 2, where the operating voltage value Vop at which the energy harvesting circuit 10 is optimized to operate during the design stage is generally equal to such peak value Vout under the desired operating conditions, for example Vout = Voc1 / 2.

[0087] In the example considered, according to Figure 3 Based on the discussion of part a), we can conclude that Figure 3 As illustrated in part b) of : when the input power level Pin has a first power value P1, the peak output voltage value is equal to the operating voltage Vop, and the circuit has a first efficiency value η1; and when the input power level Pin has a second power value P2 higher than the first power value P1, the operating voltage value may be far away from the peak output voltage value, such as Figure 3 As illustrated in part b) of , resulting in the circuit having a second efficiency value η2 lower than the first efficiency value η1.

[0088] According to the solution of the present disclosure, a method is provided for reconfiguring the number Ns of conversion sub-stages that can be enabled to operate the RF to DC conversion in the first RF to DC circuit to solve the problem of efficiency loss. This can help avoid wasteful positive changes in input power, such as those that can be caused by reducing the distance between the RF energy source and the sensing antenna RX.

[0089] This suggests that, to help achieve optimal power transfer, it would be desirable to adjust the RF to DC unit to operate within a voltage range arranged around Voc / 2. It is therefore advantageous to measure the open circuit voltage value Voc.

[0090] Figure 4 Including as in Figure 2 Schematic diagram of the principle of an embodiment of an energy harvesting circuit 10 is illustrated in FIG.

[0091] Hereinafter, unless otherwise specified, like references may be used to refer to like elements.

[0092] As in Figure 4 In one or more embodiments illustrated in the drawings, it can be seen that the system efficiency can be improved by utilizing the dependence on the trend of the curve between the open circuit voltage Voc of the first RF to DC circuit of the energy harvesting circuit 10 and the input power Pin sensed from the number Ns of enabled sub-stages in the set of N sub-stages of the first RF to DC circuit of the energy harvesting circuit 10 via at least one antenna RX.

[0093] For example, consider the following scenario: until the input power has a first power value P1, all N sub-stages of the first RF-to-DC circuit of the energy harvesting circuit 10 convert the received signal Vin into a converted signal Vout, wherein the first RF-to-DC circuit with all N sub-stages enabled has a first open-circuit voltage Voc1 (detectable due to the second RF-to-DC circuit); and when the input power increases to reach a second power value P2 higher than the first power value P1, a reduced number Ns (e.g., Ns=N / 2) of sub-stages of all N sub-stages of the first RF-to-DC circuit are selectively enabled, wherein since the number of active sub-stages is Ns, the second open-circuit voltage Voc2 (detectable due to the second RF-to-DC circuit) can be equal to the first open-circuit voltage Voc1, as in Figure 4 exemplified in part a).

[0094] In this considered example: when the input power level Pin has a first power value P1, the open circuit voltage level Voc has a first voltage value Voc1, wherein these values ​​are as in Figure 4 The coordinate values ​​of such a first operating point of the first RF to DC circuit in the Voc-Pin diagram illustrated in part a) of FIG. 1 ; and when the input power level Pin has a second power value P2 higher than the first power value P1, the open circuit voltage level Voc has a second voltage value Voc2 equal to the first voltage value Voc1, wherein these values ​​are as follows Figure 4 The coordinate values ​​of this second operating point of the first RF to DC circuit in the Voc-Pin diagram illustrated in part a).

[0095] As in Figure 4 In one or more embodiments illustrated in part b), within the range of different input power values, the peak value at Vout=Voc / 2 remains constant, so that the operating voltage value Vop at which the energy harvesting circuit 10 is optimized to operate during the design stage remains one of the operating conditions expected by the design, for example, Vout=Voc1 / 2=Voc2 / 2=Vop.

[0096] In the example considered, according to Figure 4 Based on the discussion in part a), we can draw the following conclusions: Figure 4 As illustrated in part b) of FIG. 1 , when the input power level Pin has a first power value P1, the peak output voltage value is equal to the operating voltage Vop, and the circuit has the following characteristics: Figure 3 b) of the first efficiency value η1 illustrated in part; and when the input power level Pin has a second power value P2 higher than the first power value P1, the operating voltage value remains close to or equal to the peak output voltage value Vop.

[0097] As a result, energy harvesting circuit 10 operated in this manner exhibits improved performance, adjustability, and flexibility without loss of efficiency in energy conversion.

[0098] Figure 5 1 is a further exemplary diagram of the principles underlying an embodiment, wherein the number of active stages may be varied under a plurality of operating conditions, for example: until the input power has a first power value P1, all N sub-stages of the first RF to DC circuit of the energy harvesting circuit 10 convert the received signal Vin into a converted signal Vout, wherein the circuit portions in which all N sub-stages are enabled have a first open circuit voltage Voc1 (detectable due to the second RF to DC circuit); when the input power increases to a second power value P2 higher than the first power value P1, a reduced number Ns (e.g., Ns=N / 2) of sub-stages of all N sub-stages of the first RF to DC circuit are selected The first RF-to-DC circuit is selectively enabled, wherein since the number of active sub-stages is Ns, the second open circuit voltage Voc2 (detectable due to the second RF-to-DC circuit) can therefore be equal to the first open circuit voltage Voc1; and when the input power is further increased to reach a third power value P3 that is higher than both the first power value P1 and the second power value P2, a further reduced number (for example, N / 3) of sub-stages among all N sub-stages of the first RF-to-DC circuit are selectively enabled, wherein since the number of active sub-stages is reduced to N / 3, the third open circuit voltage Voc3=Voc1=Voc2 (detectable due to the second RF-to-DC circuit) can be equal to the first open circuit voltage Voc1.

[0099] As in Figure 6 In one or more embodiments illustrated in , a configurable energy harvesting circuit 100 according to the present disclosure may include: the energy harvesting circuit 10 as described above. The energy harvesting circuit 100 also includes a driver circuit device 20 coupled to the first RF to DC circuit and the second RF to DC circuit, the driver circuit device including a voltage reference (Vref) circuit portion 200, and configured to receive the sensing signal Vocs from the second RF to DC circuit, and selectively enable / disable Ns sub-stages in the set of sub-stages of the first RF to DC circuit. The load stage Z including the load impedance element L is coupled between a first RF to DC first voltage node Vout and a ground GND.

[0100] In one or more embodiments, the driver circuitry 20 may include: a voltage reference section 200, formed, for example, by a voltage reference generator (e.g., a low dropout (LDO) voltage regulator), the generator being configured to provide a voltage operating level (e.g., the voltage operating level at which the first RF-to-DC operation is designed to function optimally) at a corresponding voltage reference node Vop. The driver circuitry 20 also includes a window comparator stage configured to determine whether the open-circuit voltage Vocs sensed at a second RF-to-DC sensing node Vocs is above a reference voltage level threshold or below a voltage reference level threshold, wherein comparators 202, 204 are configured to output a first binary signal Up at a corresponding first node Up and a second binary signal Dn at a corresponding second node Dn, and if Vocs is greater than the threshold (e.g., Vocs > Vop), the first binary signal Up may have a first value (e.g., "logical high" or "1"), if Vocs is less than or equal to the threshold (e.g., Vocs ≤ Vop), the first binary signal Up may have a second value (e.g., "logical low" or "0"), if Vocs is less than the threshold (e.g., Vocs < Vop), the second binary signal Dn may have a first value (e.g., "logical high" or "1"), and if Vocs is greater than or equal to the threshold (e.g., Vocs ≥ Vop), the second binary signal Dn may have a second value (e.g., "logical low" or "0"). A finite state machine (FSM) stage, preferably an asynchronous FSM, is coupled to the window comparator and is configured to receive the first binary signal Up and the second binary signal Dn and perform FSM processing on these signals to generate a control signal cbs (e.g., a control bit sequence) that can be provided to a first RF-to-DC conversion stage, wherein the control signal cbs is configured to selectively enable / disable a set of sub-stages Ns among all N sub-stages of the first RF-to-DC circuit.

[0101] In one or more embodiments, relative to employing a synchronous FSM, employing an asynchronous FSM may facilitate reducing power consumption, and employing an asynchronous FSM advantageously avoids employing a power-consuming clock generator.

[0102] In one or more embodiments, as discussed below, the control signal cbs may be a two-bit (or n-bit) signal, the value of which may be a function of the operating state of the FSM stage and the binary signals Up, Dn input thereto, e.g., cbs may be calculated as the sum of the binary signals Up, Dn.

[0103] In one or more embodiments, the window comparator may include: i) a first "overvoltage" comparator circuit (e.g., a hysteresis comparator) having a first "positive" input node coupled to a sensing node Vocs of the second RF to DC circuit and configured to receive a (scaled) sensed open-circuit voltage level Vocs therefrom, the first hysteresis comparator 202 having a second "negative" input node coupled to a reference voltage node Vop and configured to receive a voltage reference level Vop therefrom; and ii) a second "undervoltage" comparator circuit (e.g., a hysteresis comparator) having a first "negative" input node coupled to a sensing node Vocs of the second RF to DC circuit and configured to receive a (scaled) sensed open-circuit voltage level Vocs therefrom, the first hysteresis comparator 202 having a second "positive" input node coupled to a reference voltage node Vop and configured to receive a voltage reference level Vop therefrom. Each of the first hysteresis comparator 202 and the second hysteresis comparator 204 detects the common input voltage Vocs with respect to the reference voltage ±Vocs as an upper limit and a lower limit.

[0104] In one or more embodiments, the driver circuit arrangement may include a power-on reset (POR) circuit portion 207 coupled to the FSM circuit 21 and configured to reset an operational state of the FSM, as discussed below.

[0105] One or more embodiments may optionally include a further comparator 208 having a first “positive” node coupled to the output node of the first RF to DC circuit and configured to receive the first output voltage Vout therefrom, and having a second “negative” input node coupled to the reference generator and configured to receive the voltage reference level Vop therefrom, the further comparator 208 being coupled to the load stage Z L and is configured to control the load Z L , for example, controlling the enabling state of the load according to an output voltage that is proportional to the operating voltage Vop.

[0106] In one or more embodiments, the further comparator 208 may include a simple (low cost) ultra-low power comparator that can adjust the stored C L The voltage at the position is adjusted so that its average value is close to the operating voltage value Vop voltage under various environmental conditions, as discussed below (for example, see Figure 8 ).

[0107] Figure 7 is an exemplary state diagram of possible functionality of FSM circuit 21 in one or more embodiments.

[0108] Consider an exemplary case where the first RF to DC circuit comprises N=6 sub-stages and where the second RF to DC circuit comprises M=N / 2=3 sub-stages, as in Figure 7 As illustrated in , for example: a POR signal may be sent from the POR stage to the FSM stage to initialize it to the start state 212 .

[0109] In the starting state 212, as long as the open circuit voltage Vocs sensed at the sensing node Vocs of the second RF to DC circuit is within the first interval ±Vop, which may indicate an input power level condition Pin=P1, the control signal cbs may have a starting value, e.g., cbs=“00”, which may selectively enable a maximum number Ns of sub-stages in the first RF to DC circuit, e.g., Ns=N=6.

[0110] The FSM circuit 21 may envisage a first transition from a starting state 212 to a first state 214, wherein the first transition may be triggered by an increase in the value of an open circuit voltage Vocs sensed at a sensing node Vocs of the second RF to DC circuit (e.g., Vocs=Voc2>Vop), wherein such an increase condition may be detected due to the comparator 202, 204 outputting a signal Up having a first value (e.g., when Up=“1”), which may indicate an input power level condition Pin=P2. In the first state 214, the control signal cbs may have a first value (e.g., cbs=“01”), and as a result, a reduced (e.g., halved) number of sub-stages may be enabled / disabled, e.g., Ns=N / 2=3.

[0111] The FSM circuit 21 may further have a second transition from the first state 214 to the second state 216, wherein the second transition may be triggered due to a further increase in the value of the open circuit voltage Vocs sensed at the sensing node Vocs of the second RF to DC circuit (e.g., Vocs=Voc3>Vop), wherein such an increase condition may be detected due to the comparator outputting a signal Up having a first value (e.g., when Up=“1”) when the system is in the first state 214, which may indicate an input power level condition Pin=P3. In the second state 216, the control signal cbs may have a second value (e.g., cbs=“10”), and as a result, a reduced number Ns of sub-stages (e.g., one third of the total number) may be enabled / disabled, e.g., Ns=N / 3=2.

[0112] The FSM circuit 21 may further transition from the second state 216 to a third state 218, where a further transition may be triggered due to another increase in the value of the open circuit voltage Vocs sensed at the sensing node Vocs of the second RF-to-DC circuit, where such an increase condition may be detected due to the comparator 202, 204 outputting a signal Up having a first value (e.g., when Up = "1") when the system is in the third state 218, which may indicate an input power level condition Pin>P3. In the third state 218, the control signal cbs may have a third value (e.g., cbs = "11"), and as a result, a reduced number Ns of sub-stages (e.g., one sixth of the total number) may be enabled / disabled, e.g., Ns = N / 6 = 1.

[0113] In one or more embodiments, when in any of states 212, 214, 216, 218, since the comparators 202, 204 output a signal Dn having a first value (for example, when Dn = "1"), the FSM circuit 21 can be conceived of an opposite transition in the opposite direction relative to that discussed above, causing the control signal value to change when the system is in any of states 212, 214, 216, 218, for example, from cbs = "11" to cbs = "10", which can indicate an input power level condition Pin <= P3.

[0114] As in Figure 8 In one or more embodiments illustrated in FIG. 1 , for example, in a steady-state condition, the voltage provided by the first RF to DC circuit and stored in the element C L The voltage Vout on the MOSFET can be switched between two voltages Vh and Vl.

[0115] For example, since Vout reaches the (upper limit) voltage Vh, it can be directed toward the load Z L (See Figure 6 ) enables a transfer mechanism for the energy stored at 16, which itself can be coupled to a load Z coupled to the output node 18c of the comparator 208. L The embodiments (e.g., IoT nodes) are different.

[0116] As in Figure 2 In one or more of the embodiments illustrated in FIG. 1 , for example, the current flowing toward the load Z may be achieved via a DC-DC converter (which may itself be of conventional, simplified design) controlled by a signal output by the comparator 208. L As energy is transferred to the load, the voltage Vout may be increased from the upper limit value Vh (see Figure 8 Schematic diagram of the embodiment of the present invention) drops to the lower limit value Vl, and the DC-DC converter is turned off (energy transmission is interrupted), thereby promoting the re-storage of energy until the upper limit value Vh is reached again.

[0117] As mentioned, in one or more embodiments, the voltage drop from Vh to Vl can be limited, for example, in a manner such that the average value of the voltage Vout can approach a "desired" operating voltage Vop, advantageously providing dynamically improved energy conversion efficiency.

[0118] like Figure 8 As illustrated in , the system can alternate between charging and discharging phases at a frequency proportional to the input power. For example, the higher the input power, the shorter the charging phase period, resulting in a higher switching frequency. In battery-free sensor applications (such as BLE radios), data is transmitted every time the discharge phase begins, and a higher switching frequency between the charging / discharging phases can advantageously increase the data transmission rate.

[0119] For a given amount of input power, one or more embodiments may advantageously increase the amount of data that can be transmitted by a sensor powered by a harvester according to the present disclosure, thereby facilitating near real-time system data rates.

[0120] For example, for a given energy harvesting circuit 10, Vh and Vl can be selected such that Vh = Voc / 2 + ΔV and Vl = Voc / 2 - ΔV, where (Vh + Vl) / 2 = Voc, where ΔV is selected in such a way that the power loss about the maximum value is kept within a desired range (e.g., 90%).

[0121] As in Figure 6 In one or more embodiments illustrated in , the FSM stage can be coupled to a voltage reference source 200 and can be configured to controllably vary its value in order to compensate for nonlinearities that may occur in the Pout-Vout curve of the energy harvesting circuit 10 with very high input power Pin.

[0122] Fig. 9 is an exemplary graph of this nonlinearity.

[0123] For example, when the input power Pin is much higher than P3, the value of Vop can be conveniently increased or decreased to facilitate the selection of conditions that can lead to maintaining the highest possible efficiency value. For example, if the input power Pin is the average value or much higher than P3, the first Vop' can be set to Ns'=6, Ns"=6, respectively, without changing the level of the reference voltage generator.

[0124] For example, when the input power Pin is much higher than P3, it may be convenient to further downscale the down-sized version 14 of the first RF-to-DC converter in order to facilitate the selection of conditions that may result in maintaining the highest possible efficiency value.

[0125] In one or more embodiments, a limited range of power values ​​may be set for the system to operate in. For example, the range may include an upper value and a lower value, where the lower value may be determined based on a maximum number N of sub-stages, which may help improve device sensitivity, while the upper value may be determined based on a "minimum" number of sub-stages that may be enabled at the same time.

[0126] In one or more embodiments, an electrically powered system, optionally a battery-free electrically powered system (e.g., a mobile RF terminal or wireless sensor including at least one RF sensing antenna RX) may include an energy harvesting circuit 10 as illustrated herein, for example as a source of power supply.

[0127] As illustrated herein, an energy harvester circuit (e.g., 100) may include: a first radio frequency to direct current (RF to DC) circuit portion (e.g., 12) configured to receive a first signal from at least one radio frequency sensing antenna (e.g., RX) at a first node (e.g., Vin) and generate a first converted signal at a second node (e.g., Vout); an energy storage circuit portion (e.g., C s), coupled to the first RF to DC portion and providing a converted signal therefrom; a second RF to DC circuit portion (e.g., 14), comprising a down-scaled copy of the first RF to DC portion and configured to receive the first converted signal at the input node and generate a second converted signal at a sense node (e.g., Vocs), the second converted signal indicating an open circuit voltage of the first RF to DC circuit portion; a driver circuit device (e.g., 20), comprising a voltage reference generator (e.g., 200), the voltage reference generator being configured to provide a voltage reference signal (e.g., Vop) and coupled to the first RF to DC converter circuit and the second RF to DC converter circuit (e.g., 12, 14); wherein the first RF to DC portion comprises N integer sub-stages, at least a subset of the integer sub-stages of the N integer sub-stages being selectively deactivatable / enabled (e.g., Ns). The driver circuit device is configured to: i) perform a comparison (e.g., 202, 204) between the second converted signal and the voltage reference signal, wherein the comparison generates a first signal (e.g., Up) and a second signal (e.g., Dn), the first signal (Up) having a first value when the second converted signal is higher than the voltage reference signal, and the second signal having a first value when the second converted signal is lower than the voltage reference signal, so as to check whether the second converted signal is within a range of values ​​proportional to the voltage reference signal (e.g., Up, Dn), and ii) selectively disable (e.g., 21, cbs) or enable a subset of an integer (e.g., Ns) number of sub-stages of the N integer number of sub-stages of the first RF to DC part, respectively, when the performed comparison has a first result and a second result, respectively.

[0128] As illustrated herein, the first RF to DC circuit portion may include a first voltage multiplier, the first voltage multiplier including a plurality of multiplication sub-stages (e.g., Ns), the first voltage multiplier having a minimum multiplication factor of 1 and a maximum multiplication factor of N, wherein the multiplication factor may be selectively varied based on an integer number of multiplication sub-stages enabled between 1 and N.

[0129] As illustrated herein, the down-scaled copy of the first RF to DC portion of the second RF to DC circuit portion may have a scaling factor equal to 2, thereby providing a half-scaled copy of the first RF to DC portion.

[0130] As illustrated herein, a driver circuit arrangement may include a window comparator (e.g., 202, 204) coupled to a voltage reference generator and a second RF to DC circuit portion, the window comparator being sensitive to a voltage reference signal received from the generator (200) and to a second signal from the second RF to DC circuit portion.

[0131] As illustrated herein, the comparator may include first (eg, 202 ) and second (eg, 204 ) hysteresis comparators configured to change states at upper and lower ends of a hysteresis interval around the voltage reference signal, respectively.

[0132] As illustrated herein, the driver circuit device may include a finite state machine (FSM) circuit (e.g., 21) configured to receive the first signal and the second signal, the FSM circuit configured to generate a control signal (e.g., cbs) and provide the control signal to the first RF to DC circuit, the control signal (e.g., cbs) being configured to selectively enable or disable the subset of the integer sub-stages of the N sub-stages of the first RF to DC part when the performed comparison has a first result and a second result, respectively, and the FSM circuit preferably includes an asynchronous FSM circuit.

[0133] As illustrated herein, the system may include: at least one RF antenna (e.g., RX) configured to sense an RF signal (e.g., Vin); at least one energy harvesting circuit (e.g., 100) as illustrated herein, the circuit having the first RF to DC circuit portion and the second RF to DC circuit portion coupled (e.g., 11) to the at least one RF antenna to receive the first signal therefrom; and an electrical load (e.g., Z L ), coupled to an output node (e.g., 10) of the circuit to be powered thereby.

[0134] As illustrated herein, a system may include a matching network (eg, 11) configured to adaptively couple at least one radio frequency antenna with the first RF to DC circuit portion and the second RF to DC circuit portion.

[0135] As exemplified herein, the electrical load may be an electrically powered sensor device.

[0136] As illustrated herein, a method (e.g., 21) of operating an energy harvesting circuit (100) includes: performing a comparison (e.g., 202, 204) between the second converted signal (e.g., Vocs) and the voltage reference signal (e.g., Vop), wherein the comparison generates a first signal (e.g., Up) and a second signal (e.g., Dn), the first signal having a first value when the second converted signal is higher than the voltage reference signal, and the second signal having a first value when the second converted signal is lower than the voltage reference signal, so as to check whether the second converted signal is within a range of values ​​(e.g., Up, Dn) proportional to the voltage reference signal; and selectively disabling (e.g., 21, cbs) or enabling a subset of an integer number (e.g., Ns) of the N integer number of sub-stages of the first RF to DC part when the performed comparison has a first result and a second result, respectively.

[0137] Otherwise it will be understood that the various individual implementation options illustrated throughout the drawings accompanying this specification are not necessarily intended to be employed in the same combination illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0138] The claims are an integral part of the technical guidance provided herein with reference to the examples.

[0139] Without prejudice to the underlying principles, the details and embodiments may vary (even significantly) with respect to what has been described purely by way of example, without departing from the scope of protection, which is defined by the accompanying claims.

Claims

1. A circuit comprising: a first RF to DC circuit configured to receive a first signal from at least one RF antenna at a first node and generate a first converted signal at a second node; an energy storage circuit coupled to the first RF-to-DC circuit and provided with the first converted signal; a second RF to DC circuit, wherein the second RF to DC circuit is a replica of the first RF to DC circuit scaled down by a scaling factor, the second RF to DC circuit being configured to receive the first signal at an input node and to produce a second converted signal at a sense node, the second converted signal being indicative of an open circuit voltage at the second node of the first RF to DC circuit; a driver circuit arrangement including a voltage reference generator configured to provide a voltage reference signal and coupled to the first RF-to-DC circuit and the second RF-to-DC circuit; wherein the first RF to DC circuit comprises an integer number N of sub-stages, at least a subset of the sub-stages among the N sub-stages being selectively deactivatable / activatable; wherein the driver circuit arrangement is configured as: i) performing a comparison between the second converted signal and the voltage reference signal, wherein the comparison generates a first signal and a second signal, the first signal having a first value when the second converted signal is higher than the voltage reference signal, and the second signal having a first value when the second converted signal is lower than the voltage reference signal, to check whether the second converted signal is within a range of values ​​proportional to the voltage reference signal; as well as ii) selectively disabling a subset of the N sub-stages of the first RF to DC circuit when the performed comparison has a first result, or selectively enabling the subset of an integer number of the N sub-stages of the first RF to DC circuit when the performed comparison has a second result.

2. The circuit of claim 1 , wherein the first RF to DC circuit comprises a first voltage multiplier, the first voltage multiplier comprising a plurality of multiplication sub-stages, the first voltage multiplier having a minimum multiplication factor of 1 and a maximum multiplication factor of N, wherein the multiplication factor is selectively variable based on an integer number of multiplication sub-stages enabled within a range between 1 and N. The circuit of claim 1 , wherein the scaling factor is equal to two.

4. The circuit of claim 1 , wherein the driver circuit arrangement comprises a window comparator coupled to the voltage reference generator and to the second RF to DC circuit, the window comparator being sensitive to the voltage reference signal received from the generator and to the second converted signal from the second RF to DC circuit.

5. The circuit of claim 4, wherein the window comparator comprises a first hysteresis comparator and a second hysteresis comparator, the first hysteresis comparator and the second hysteresis comparator being configured to change states at an upper end and a lower end of a hysteresis interval around the voltage reference signal, respectively.

6. The circuit of claim 1 , wherein the driver circuit device comprises a finite state machine (FSM) circuit configured to receive the first signal and the second signal, the FSM circuit configured to generate a control signal and provide the control signal to the first RF to DC circuit, the control signal being configured to selectively enable the subset of sub-stages among the N sub-stages when the performed comparison has the first result, or to selectively disable the subset of sub-stages among the N sub-stages when the performed comparison has the second result. The circuit according to claim 6 , wherein the FSM circuit is an asynchronous FSM circuit.

8. The circuit of claim 1 further comprising an electrical load coupled to the second node of the first RF to DC circuit.

9. The circuit of claim 8, wherein the electrical load is an electrically powered sensor device.

10. The circuit of claim 1, further comprising a matching network configured to adaptively couple the at least one radio frequency antenna to the first node of the first RF to DC circuit and to the input node of the second RF to DC circuit.

11. A circuit comprising: a first RF to DC circuit configured to receive a radio frequency signal at a first node and produce a first converted signal at a second node; an energy storage circuit coupled to receive the first converted signal from the second node; a second RF to DC circuit, wherein the second RF to DC circuit is a replica of the first RF to DC circuit scaled down by a scaling factor, the second RF to DC circuit being configured to receive the radio frequency signal at an input node and to generate a second converted signal at a sense node, the second converted signal being indicative of an open circuit voltage at the second node of the first RF to DC circuit; wherein the first RF to DC circuit comprises an integer number N of multiplication stages, and wherein at least a subset of the multiplication stages are selectively deactivatable; The control circuit is configured as follows: i) comparing the second converted signal to a reference voltage and asserting a control signal when the second converted signal is higher than the reference voltage; as well as ii) selectively disabling the subset of the multiplication stages in response to assertion of a control signal. The circuit of claim 11 , wherein the scaling factor is equal to 2.

13. The circuit of claim 11, further comprising an electrical load coupled to the second node of the first RF to DC circuit.

14. The circuit of claim 13, wherein the electrical load is an electrically powered sensor device.

15. The circuit of claim 11, further comprising a matching network configured to adaptively couple at least one radio frequency antenna to the first node of the first RF to DC circuit and to the input node of the second RF to DC circuit.

16. A circuit comprising: a first RF to DC circuit configured to receive a radio frequency signal at a first node and produce a first converted signal at a second node; an energy storage circuit coupled to receive the first converted signal from the second node; a second RF to DC circuit, wherein the second RF to DC circuit is a replica of the first RF to DC circuit scaled down by a scaling factor, the second RF to DC circuit being configured to receive the radio frequency signal at an input node and to generate a second converted signal at a sense node, the second converted signal being indicative of an open circuit voltage at the second node of the first RF to DC circuit; wherein said first RF to DC circuit comprises an integer number N of multiplication stages, and wherein at least a subset of said multiplication stages are selectively enabled; The control circuit is configured as follows: i) comparing the second converted signal to a reference voltage and asserting a control signal when the second converted signal is higher than the reference voltage; as well as ii) selectively enabling the subset of the multiplication stages in response to assertion of a control signal. The circuit of claim 16 , wherein the scaling factor is equal to 2.

18. The circuit of claim 16, further comprising an electrical load coupled to the second node of the first RF to DC circuit.

19. The circuit of claim 18, wherein the electrical load is an electrically powered sensor device.

20. The circuit of claim 16, further comprising a matching network configured to adaptively couple at least one radio frequency antenna to the first node of the first RF to DC circuit and to the input node of the second RF to DC circuit.

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