voltage controlled oscillator

Abstract

A voltage controlled oscillator is provided. The voltage controlled oscillator includes a first transistor, a second transistor, an inductive impedance element, a first variable capacitive impedance element, and a second variable capacitive impedance element. A source of the first transistor is coupled to a first power supply. A source of the second transistor is coupled to the first power supply. A drain of the second transistor is coupled to a gate of the first transistor. A gate of the second transistor is coupled to a drain of the first transistor. One end of the inductive impedance element is coupled to the drain of the first transistor and another end of the inductive impedance element is coupled to the drain of the second transistor. A first end of the first variable capacitive impedance element is coupled to the drain of the first transistor. A frequency control voltage is applied to a second end of the first variable capacitive impedance element.

Description

[0001] This application claims the benefit of Japanese Patent Application No. 2019-219023, filed on December 3, 2019, with the Japan Patent Office, and Korean Patent Application No. 10-2020-0101033, filed on August 12, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to an electronic circuit, and more specifically, to a voltage-controlled oscillator. Background Technology

[0003] A wireless communication network may include several base stations capable of supporting communication for several mobile stations. Mobile stations can communicate with base stations via uplink and downlink. Various wireless communication devices are used for wireless communication. Such wireless communication devices include smartphones, mobile phones, tablet computers, laptop computers, smart vehicles, wearable devices, etc.

[0004] One of the key components used in such wireless communication devices is the voltage-controlled oscillator (VCO). A VCO is a device used to generate a local oscillation signal in a wireless communication device, and the frequency of the local oscillation signal can be changed by voltage. Summary of the Invention

[0005] The present invention is provided in a simplified form to introduce the choice of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0006] In one general aspect, a voltage-controlled oscillator (VCO) includes a first transistor, a second transistor, an inductive impedance element, a first variable capacitive impedance element, and a second variable capacitive impedance element.

[0007] The source of the first transistor is coupled to a first power supply. The drain of the first transistor is coupled to a first node, and the gate of the first transistor is coupled to a second node. The source of the second transistor is coupled to the first power supply. The first power supply can provide a power supply voltage VDD.

[0008] The drain of the second transistor is connected to the second node. The gate of the second transistor is connected to the first node. The first terminal of the inductive impedance element is connected to the first node. The common terminal of the inductive impedance element is connected to the second power supply. The second power supply can provide ground voltage. The second terminal of the inductive impedance element is connected to the second node. The first terminal of the first variable capacitive impedance element is connected to the first node. The second terminal of the first variable capacitive impedance element is connected to the third node. The first terminal of the second variable capacitive impedance element is connected to the second node. The second terminal of the second variable capacitive impedance element is connected to the third node. A frequency control voltage VCTRL can be applied to the third node.

[0009] The VCO may also include a first resistor connected between the drain of the first transistor and the first node. The VCO may also include a second resistor connected between the drain of the second transistor and the second node.

[0010] The first variable capacitive impedance element includes a third transistor and a first capacitor. The first capacitor is coupled between the gate and drain of the third transistor. The second variable capacitive impedance element may include a fourth transistor and a third capacitor. The third capacitor is coupled between the gate and drain of the fourth transistor. The source of the third transistor and the source of the fourth transistor are coupled to a second power supply. The second power supply can provide a ground voltage.

[0011] The third and fourth transistors may have parasitic capacitance. For ease of description, the third and fourth transistors may be referred to as the first capacitive transistor and the second capacitive transistor, respectively.

[0012] The first variable capacitive impedance element may further include a second capacitor connected between the gate of the third transistor and the first node. The second variable capacitive impedance element may further include a fourth capacitor connected between the gate of the fourth transistor and the second node.

[0013] The first variable capacitive impedance element further includes a third resistor connected between the gate of the third transistor and the third node. The second variable capacitive impedance element further includes a fourth resistor connected between the gate of the fourth transistor and the third node.

[0014] The VCO also includes a first bias circuit configured to provide bias current to the drain of the third transistor. The VCO also includes a second bias circuit configured to provide bias current to the drain of the fourth transistor.

[0015] The first bias circuit may include a fifth transistor and a sixth transistor. The fifth transistor and the sixth transistor may be referred to as a first mirror transistor and a second mirror transistor, respectively. A bias voltage is applied to the source of the first mirror transistor. The gate of the first mirror transistor is coupled to the drain of the first mirror transistor. A bias voltage is applied to the source of the second mirror transistor. The gate of the second mirror transistor is coupled to the gate of the first mirror transistor. The drain of the second mirror transistor is coupled to the drain of the third transistor.

[0016] The second bias circuit may include a seventh transistor and an eighth transistor. The seventh and eighth transistors may be referred to as the third mirror transistor and the fourth mirror transistor, respectively. A bias voltage is applied to the source of the third mirror transistor. The gate of the third mirror transistor is coupled to the drain of the third mirror transistor. A bias voltage is applied to the source of the fourth mirror transistor. The gate of the fourth mirror transistor is coupled to the gate of the third mirror transistor. The drain of the fourth mirror transistor is coupled to the drain of the fourth transistor.

[0017] The first bias circuit may further include a fifth resistor connected between the drain of the first mirror transistor and the second power supply. This fifth resistor may be referred to as the first mirror resistor. The second bias circuit may further include a sixth resistor connected between the drain of the third mirror transistor and the second power supply. This sixth resistor may be referred to as the second mirror resistor. The second power supply can provide ground voltage.

[0018] The third and fourth transistors can be metal-oxide-semiconductor (MOS) transistors.

[0019] The second capacitor, the first capacitor, the fourth capacitor, and the third capacitor can be formed using inter-wire capacitance.

[0020] In another general aspect, a voltage-controlled oscillator (VCO) includes a first transistor, a second transistor, an inductive impedance element, a first variable capacitive impedance element, and a second variable capacitive impedance element. The source of the first transistor is coupled to a first power supply. The source of the second transistor is coupled to the first power supply, the drain of the second transistor is coupled to the gate of the first transistor, and the gate of the second transistor is coupled to the drain of the first transistor. One end of the inductive impedance element is coupled to the drain of the first transistor, and the other end of the inductive impedance element is coupled to the drain of the second transistor. A first end of the first variable capacitive impedance element is coupled to the drain of the first transistor, and a frequency control voltage is applied to a second end of the first variable capacitive impedance element. A first end of the second variable capacitive impedance element is coupled to the drain of the second transistor, and a frequency control voltage is applied to a second end of the second variable capacitive impedance element.

[0021] The first variable capacitive impedance element includes a third transistor, a second capacitor, and a first capacitor. The second capacitor is connected between the gate of the third transistor and a first terminal of the first variable capacitive impedance element. The first capacitor is connected between the gate and drain of the third transistor. The second variable capacitive impedance element includes a fourth transistor, a fourth capacitor, and a third capacitor. The fourth capacitor is connected between the gate of the fourth transistor and a first terminal of the second variable capacitive impedance element. The third capacitor is connected between the gate and drain of the fourth transistor.

[0022] The first variable capacitive impedance element may further include a third resistor connected between the gate of the third transistor and the second terminal of the first variable capacitive impedance element. The second variable capacitive impedance element may further include a fourth resistor connected between the gate of the fourth transistor and the second terminal of the second variable capacitive impedance element.

[0023] In another general aspect, a voltage-controlled oscillator (VCO) includes two cross-coupled transistors and capacitive impedance elements. Each of the capacitive impedance elements is coupled between each of the two cross-coupled transistors and a frequency control voltage.

[0024] Capacitive impedance elements may all include a transistor and a capacitor. The capacitor may be connected between the gate and drain of the transistor. Capacitive impedance elements may also include an additional capacitor. This additional capacitor may be connected between each of the two cross-coupled transistors and its gate. Capacitive impedance elements may also include a resistor connected between the gate of the transistor and a frequency control voltage.

[0025] The VCO may also include a bias circuit configured to provide bias current to a transistor in each of the capacitive impedance elements. The bias circuit may also be configured to provide bias current to the drain of the transistor in each of the capacitive impedance elements.

[0026] In another general aspect, a wireless communication device includes at least one of a receiver and a transmitter, the at least one of which includes a VCO as described herein. The wireless communication device includes: at least one antenna; and at least one of a receiver and a transmitter, the receiver being configured to receive radio frequency (RF) signals through the at least one antenna, and the transmitter being configured to transmit RF signals through the at least one antenna.

[0027] A VCO can expand the variable range of the output signal to accommodate the variable control voltage.

[0028] Other features and aspects will become clear from the following detailed description, the accompanying drawings, and the claims. Attached Figure Description

[0029] Figure 1 This is a circuit diagram illustrating an example of a voltage-controlled oscillator.

[0030] Figure 2 This is a circuit diagram illustrating an example of a voltage-controlled oscillator to describe a detailed circuit diagram of a variable capacitive impedance element.

[0031] Figure 3 This is an equivalent circuit diagram showing an example of a variable capacitive impedance element.

[0032] Figure 4A and Figure 4B This is a graph illustrating an example of the variable range of capacitance for a variable capacitive impedance element.

[0033] Figure 5A and Figure 5B This is a graph illustrating an example of the variable frequency range of a voltage-controlled oscillator.

[0034] Figure 6 This is a circuit diagram illustrating an example of a voltage-controlled oscillator to describe a detailed circuit diagram of a variable capacitive impedance element.

[0035] Figure 7 This is a block diagram illustrating an example of a user's wireless communication device (such as a mobile phone or smartphone).

[0036] Figure 8 This is a diagram showing an example of an access point.

[0037] Throughout the accompanying drawings and detailed embodiments, unless otherwise described or provided, the same reference numerals will be understood to denote the same elements, features, and structures. The drawings may not be drawn to scale, and for clarity, illustration, and convenience, the relative dimensions, scale, and depiction of elements in the drawings may be exaggerated. Detailed Implementation

[0038] The following structural or functional descriptions are exemplary and are intended to describe examples only; the scope of the examples is not limited to the descriptions provided in this specification.

[0039] The term “and / or” includes any one of the relevant listed items and any combination of two or more of the relevant listed items.

[0040] Components may be described herein using terms such as first, second, third, etc. Each of these terms is not intended to define the nature, order, or sequence of the corresponding component, but only to distinguish the corresponding component from another (other) component. For example, within the scope of the claims according to the concept of this disclosure, a "first" component may be referred to as a "second" component, or similarly, a "second" component may be referred to as a "first" component.

[0041] It should be noted that if a component is described as "connected," "joined," or "attached" to another component, a third component may also be "connected," "joined," or "attached" between the first and second components. However, the first component may be directly connected, directly joined, or directly attached to the second component. Conversely, it should be understood that if a component is described as "directly connected," "directly joined," or "directly attached" to another component, the third component may not exist. Expressions describing relationships between components (e.g., "between," "directly between," or "directly adjacent") should be interpreted similarly.

[0042] Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. It should also be understood that when the terms “comprising” and / or “having” are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, or combinations thereof, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0044] The examples will be described in detail below with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements.

[0045] Figure 1 This is a circuit diagram illustrating an example of a voltage-controlled oscillator. (Refer to...) Figure 1The voltage-controlled oscillator 1 includes a first transistor Tr1, a second transistor Tr2, a first variable capacitive impedance element Cv1, a second variable capacitive impedance element Cv2, and an inductive impedance element L1. The first transistor Tr1 and the second transistor Tr2 are cross-coupled. In addition to the aforementioned components, the voltage-controlled oscillator 1 may also include a first buffer circuit BUF1, a second buffer circuit BUF2, and a load resistor RL. In the voltage-controlled oscillator 1, the power supply voltage VDD is provided by a first power supply, and the ground voltage GND is provided by a second power supply. Furthermore, a frequency control voltage VCTRL is applied to control the frequency of the output signal Vout of the voltage-controlled oscillator 1.

[0046] The source of the first transistor Tr1 is connected to a first power supply. The first power supply provides a power supply voltage VDD. The drain of the first transistor Tr1 is connected to a first node N1. The gate of the first transistor Tr1 is connected to a second node N2. The source of the second transistor Tr2 is connected to the first power supply. The first power supply provides a power supply voltage VDD. The drain of the second transistor Tr2 is connected to a second node N2. The gate of the first transistor Tr1 is connected to the first node N1. Therefore, the drain of the first transistor Tr1 is connected to the gate of the second transistor Tr2, and the gate of the first transistor Tr1 is connected to the drain of the second transistor Tr2. The drain of the second transistor Tr2 is connected to the gate of the first transistor Tr1, and the gate of the second transistor Tr2 is connected to the drain of the first transistor Tr1.

[0047] like Figure 1As shown, the voltage-controlled oscillator 1 may further include: a first resistor R1 connected between the drain of the first transistor Tr1 and the first node N1, and a second resistor R2 connected between the drain of the second transistor Tr2 and the second node N2. The drain of the first transistor Tr1 is connected to one end of the first resistor R1, and the drain of the second transistor Tr2 is connected to one end of the second resistor R2. Furthermore, the gate of the first transistor Tr1 is connected to the other end of the second resistor R2, and the gate of the second transistor Tr2 is connected to the other end of the first resistor R1. The first resistor R1 and the second resistor R2 serve as load resistors for the first transistor Tr1 and the second transistor Tr2, respectively. In some examples, a circuit configuration without resistors R1 and R2 may also be used. Therefore, it will be apparent to those skilled in the art that if the drain of the first transistor Tr1 is described as being connected to the first node N1, the resistors may or may not be included between the drain of the first transistor Tr1 and the first node N1. Similarly, it will be apparent to those skilled in the art that if the drain of the second transistor Tr2 is described as being coupled to the second node N2, then the resistor may be included between the drain of the second transistor Tr2 and the second node N2, or may not be included between the drain of the second transistor Tr2 and the second node N2.

[0048] The first end of the inductive impedance element L1 is connected to the first node N1, and the second end of the inductive impedance element L1 is connected to the second node N2. For example, one end of the inductive impedance element L1 is connected to the drain of the first transistor Tr1, and the other end of the inductive impedance element L1 is connected to the drain of the second transistor Tr2.

[0049] In the example using resistors R1 and R2, the first end of the inductive impedance element L1 is connected to the drain of the first transistor Tr1 via the first resistor R1. Here, the first node N1, where the first end of the inductive impedance element L1 and one end of the first resistor R1 are connected, will be referred to as the first output node N1. The second end of the inductive impedance element L1 is connected to the drain of the second transistor Tr2 via the second resistor R2. Here, the second node N2, where the second end of the inductive impedance element L1 and one end of the second resistor R2 are connected, will be referred to as the second output node N2. In some examples, a circuit configuration without resistors R1 and R2 may also be used. Therefore, it will be apparent to those skilled in the art that if the first end of the inductive impedance element L1 is described as being connected to the drain of the first transistor Tr1, then the resistor may or may not be included between the first end of the inductive impedance element L1 and the drain of the first transistor Tr1. Similarly, it will be apparent to those skilled in the art that if the second end of the inductive impedance element L1 is described as being connected to the drain of the second transistor Tr2, then the resistor may be included between the second end of the inductive impedance element L1 and the drain of the second transistor Tr2, or may not be included between the second end of the inductive impedance element L1 and the drain of the second transistor Tr2.

[0050] The first terminal T11 of the first variable capacitive impedance element Cv1 is connected to the first node N1. The second terminal T12 of the first variable capacitive impedance element Cv1 is connected to the third node N3. A frequency control voltage VCTRL is applied to the third node N3. For example, the first terminal T11 of the first variable capacitive impedance element Cv1 is connected to the drain of the first transistor Tr1, and the frequency control voltage VCTRL is applied to the second terminal T12 of the first variable capacitive impedance element Cv1.

[0051] In the example employing the first resistor R1, one end of the first variable capacitive impedance element Cv1 is connected to the drain of the first transistor Tr1 via the first resistor R1, and a frequency control voltage VCTRL is applied to the other end of the first variable capacitive impedance element Cv1. In some examples, a circuit configuration without the first resistor R1 can also be used. Therefore, it will be apparent to those skilled in the art that if the first end T11 of the first variable capacitive impedance element Cv1 is described as being connected to the drain of the first transistor Tr1, then the resistor may or may not be included between the first end T11 of the first variable capacitive impedance element Cv1 and the drain of the first transistor Tr1.

[0052] The first terminal T21 of the second variable capacitive impedance element Cv2 is connected to the second node N2. The second terminal T22 of the second variable capacitive impedance element Cv2 is connected to the third node N3. A frequency control voltage VCTRL is applied to the third node N3. For example, the first terminal T21 of the second variable capacitive impedance element Cv2 is connected to the drain of the second transistor Tr2, and the frequency control voltage VCTRL is applied to the second terminal T22 of the second variable capacitive impedance element Cv2.

[0053] In the example employing the second resistor R2, one end of the second variable capacitive impedance element Cv2 is connected to the drain of the second transistor Tr2 via the second resistor R2, and the frequency control voltage VCTRL is applied to the other end of the second variable capacitive impedance element Cv2. In some examples, a circuit configuration without the second resistor R2 can also be used. Therefore, it will be apparent to those skilled in the art that if the first end T21 of the second variable capacitive impedance element Cv2 is described as being connected to the drain of the second transistor Tr2, then the resistor may or may not be included between the first end T21 of the second variable capacitive impedance element Cv2 and the drain of the second transistor Tr2.

[0054] The voltage-controlled oscillator 1 outputs an output signal Vout at the second output node N2 through the second buffer circuit BUF2. The second output node N2 connects one end of the inductive impedance element L1 and one end of the second resistor R2. The second buffer circuit BUF2 amplifies the transmitted signal generated by the voltage-controlled oscillator 1.

[0055] Furthermore, the voltage-controlled oscillator 1 drives the load resistor RL through a first buffer circuit BUF1 connected to the first output node N1. The first output node N1 is a node that connects one end of the inductive impedance element L1 and one end of the first resistor R1. The first buffer circuit BUF1 amplifies the transmitted signal generated by the voltage-controlled oscillator 1, while simultaneously balancing the impedance of the first output node N1 and the impedance of the second output node N2.

[0056] Figure 2 This is a circuit diagram illustrating an example of a voltage-controlled oscillator, including a detailed circuit diagram of variable capacitive impedance elements. An example configuration of the variable capacitive impedance elements Cv1 and Cv2 will be described in detail below.

[0057] like Figure 2 As shown, the first variable capacitive impedance element Cv1 and the second variable capacitive impedance element Cv2 can have the same configuration.

[0058] In detail, the first variable capacitive impedance element Cv1 may include a first capacitor C12, a second capacitor C11, and a third transistor Tr11.

[0059] The first capacitor C12 is coupled between the gate and drain of the third transistor Tr11. For example, the first terminal of the first capacitor C12 is coupled to the gate of the third transistor Tr11, and the second terminal of the first capacitor C12 is coupled to the drain of the third transistor Tr11. The first capacitor C12 can be formed using interwire capacitance. For example, the first capacitor C12 can be formed using interlayer capacitance formed between wiring layers using an interlayer insulating film and a metal wire having the interlayer insulating film therebetween.

[0060] The second capacitor C11 is coupled between the gate of the third transistor Tr11 and the first node N1. For example, the first terminal of the second capacitor C11 is coupled to the gate of the third transistor Tr11, and the second terminal of the second capacitor C11 serves as the first terminal T11 of the first variable capacitive impedance element Cv1 and is coupled to the first node N1. The second capacitor C11 can be formed using interlayer capacitance. For example, the second capacitor C11 can be formed using an interlayer capacitor that utilizes an interlayer insulating film formed between wiring layers and a metal wire having an interlayer insulating film therebetween.

[0061] The source of the third transistor Tr11 is connected to a second power supply. This second power supply can provide ground voltage. The drain of the third transistor Tr11 is connected to its gate through a first capacitor C12. For example, the gate of the third transistor Tr11 is connected to the first terminal of the first capacitor C12, and the drain of the third transistor Tr11 is connected to the second terminal of the first capacitor C12. The gate of the third transistor Tr11 is also connected to the second capacitor C11. The third transistor Tr11 can be a metal-oxide-semiconductor (MOS) transistor. For ease of description, the third transistor Tr11 can also be referred to as the first capacitive transistor Tr11. The first capacitive transistor Tr11 has parasitic capacitance.

[0062] The first variable capacitive impedance element Cv1 may further include a third resistor R11 connected between the gate of the third transistor Tr11 and the third node N3. For example, the first end of the third resistor R11 is connected to the gate of the third transistor Tr11, and the second end of the third resistor R11 serves as the second end T12 of the first variable capacitive impedance element Cv1 and is connected to the third node N3 to which a frequency control voltage VCTRL is applied. In some examples, a circuit configuration that does not use the third resistor R11 may also be employed.

[0063] The second variable capacitive impedance element Cv2 may include a third capacitor C21, a fourth capacitor C22, and a fourth transistor Tr21.

[0064] The third capacitor C21 is coupled between the gate and drain of the fourth transistor Tr21. For example, the first terminal of the third capacitor C21 is coupled to the gate of the fourth transistor Tr21, and the second terminal of the third capacitor C21 is coupled to the drain of the fourth transistor Tr21. The third capacitor C21 can be formed using interlayer capacitance. For example, the third capacitor C21 can be formed using an interlayer insulating film formed between wiring layers and metal wires having the interlayer insulating film therebetween.

[0065] A fourth capacitor C22 is coupled between the gate of the fourth transistor Tr21 and the second node N2. For example, the first terminal of the fourth capacitor C22 is coupled to the gate of the fourth transistor Tr21, and the second terminal of the fourth capacitor C22 serves as the first terminal T21 of the second variable capacitive impedance element Cv2 and is coupled to the second node N2. The fourth capacitor C22 can be formed using interlayer capacitance. For example, the fourth capacitor C22 can be formed using an interlayer insulating film formed between wiring layers and metal wires having the interlayer insulating film therebetween.

[0066] The source of the fourth transistor Tr21 is connected to a second power supply. This second power supply can provide ground voltage. The drain of the fourth transistor Tr21 is connected to its gate through a third capacitor C21. For example, the gate of the fourth transistor Tr21 is connected to the first terminal of the third capacitor C21, and the drain of the fourth transistor Tr21 is connected to the second terminal of the third capacitor C21. The gate of the fourth transistor Tr21 is also connected to a fourth capacitor C22. The fourth transistor Tr21 can be a MOS transistor. For ease of description, the fourth transistor Tr21 can also be referred to as a second capacitive transistor Tr21. The second capacitive transistor Tr21 has parasitic capacitance.

[0067] The second variable capacitive impedance element Cv2 may also include a fourth resistor R21 connected between the gate of the fourth transistor Tr21 and the third node N3. For example, the first end of the fourth resistor R21 is connected to the gate of the fourth transistor Tr21, and the second end of the fourth resistor R21 serves as the second end T22 of the second variable capacitive impedance element Cv2 and is connected to the third node N3 to which a frequency control voltage VCTRL is applied. In some examples, a circuit configuration that does not use the fourth resistor R21 may also be employed.

[0068] Here, the capacitance is variable, determined by the capacitive transistors Tr11 and Tr21 included in the variable capacitive impedance elements Cv1 and Cv2, and by the capacitors C12 and C21 connected between the drain and gate of the capacitive transistors Tr11 and Tr21.

[0069] The variable range of the capacitance is determined by adding the parasitic capacitances of capacitive transistors Tr11 and Tr21 to the capacitances of capacitors C12 and C21 connected between the gate and drain of capacitive transistors Tr11 and Tr21. Therefore, for a variable frequency control voltage VCTRL, the voltage-controlled oscillator has an expanded variable range of output frequency.

[0070] In the following text, the capacitance of the variable capacitive impedance element Cv1 will be described using an example of the equivalent circuit of the capacitive transistor Tr11 and the capacitor C12.

[0071] Figure 3 This is an equivalent circuit diagram illustrating an example of a variable capacitive impedance element. Figure 3 In the equivalent circuit diagram, the gate of the capacitive transistor Tr11 is represented as terminal G, the drain of the capacitive transistor Tr11 is represented as terminal D, and the source of the capacitive transistor Tr11 is represented as terminal S. In the equivalent circuit of the variable capacitive impedance element Cv1, the gate-source capacitance Cgs, which varies with the frequency control voltage VCTRL, is provided between terminals G and S. Furthermore, the source-drain resistance Rds, which also varies with the frequency control voltage VCTRL, is provided between terminals S and D. Additionally, capacitor C12 is connected between terminals G and D.

[0072] In use Figure 3 When calculating the admittance Y of the variable capacitive impedance element Cv1 using the equivalent circuit diagram, the admittance Y can be expressed by Equation 1. Here, in the following equation, capacitor C12 is assumed to have a capacitance of approximately 500 femtofarads (fF).

[0073] [Equation 1]

[0074]

[0075] In Equation 1, if the frequency control voltage VCTRL is 0 volts (V), then the source-drain resistance R ds Increase sufficiently, and 1 << ω 2 C 12 2 R ds 2 This is satisfied. Therefore, the admittance Y can be expressed by Equation 2. In Equation 2, C gs0This represents the gate-source capacitance when the frequency control voltage VCTRL is 0V.

[0076] [Equation 2]

[0077]

[0078] Therefore, if the frequency control voltage VCTRL is 0V, the effect of capacitor C12 will not be observed, and the admittance Y of the variable capacitive impedance element Cv1 will be the same as the admittance Y in the absence of capacitor C12.

[0079] Meanwhile, if the frequency control voltage VCTRL is 1V, then the source-drain resistance R ds It becomes zero, and 1 >> ω 2 C 12 2 R ds 2 This is satisfied. Therefore, the admittance Y can be expressed by Equation 3. In Equation 3, C gs1 This represents the gate-source capacitance when the frequency control voltage VCTRL is 1V.

[0080] [Equation 3]

[0081] Y=jω(C gs1 +C 12 )…(3)

[0082] Therefore, the capacitance of capacitor C12 is added to the capacitance of variable capacitive impedance element Cv1 as a parallel component, so that the capacitance of variable capacitive impedance element Cv1 is increased by the capacitance of capacitor C12.

[0083] If the frequency control voltage VCTRL is 0V, the variable capacitive impedance element has the same capacitance as the circuit without capacitor C12. If the frequency control voltage VCTRL is 1V, the variable capacitive impedance element has the same capacitance as the circuit without capacitor C12. gs The capacitance is obtained by adding the two components. Therefore, compared with a circuit without capacitor C12, the variable capacitive impedance element has a wider range of capacitance variation. Furthermore, the voltage-controlled oscillator 1 with variable capacitive impedance elements Cv1 and Cv2 has an expanded range of oscillation frequency variation.

[0084] The characteristics of the variable capacitive impedance elements Cv1 and Cv2, and the characteristics of the voltage-controlled oscillator 1 having the variable capacitive impedance elements Cv1 and Cv2, will be described below. In the following description, reference will be made to a voltage-controlled oscillator (Example 1) in which there is no capacitor between the gate and drain of the capacitive transistor with the variable capacitive impedance element, and a voltage-controlled oscillator (Example 2) in which a capacitor is included between the gate and drain of the capacitive transistor with the variable capacitive impedance element.

[0085] Figure 4A It is a graph describing the variable range of capacitance of the variable capacitive impedance element in the voltage-controlled oscillator (Example 1), which has no capacitor between the gate and drain of the capacitive transistor of the variable capacitive impedance element. Figure 4A The capacitance of the variable capacitive impedance element is shown in a voltage-controlled oscillator (Example 1) where there is no capacitor between the gate and drain of the capacitive transistor, and the capacitance changes according to the frequency control voltage VCTRL. Figure 4A As shown, if the frequency control voltage VCTRL changes from 0V to 1V, the capacitance of the variable capacitive impedance element changes from approximately 50fF to approximately 100fF. Therefore, it can be concluded that the variable range of the capacitance of the variable capacitive impedance element is from approximately 50fF to approximately 100fF.

[0086] Figure 4B It is a graph describing the variable range of capacitance of the variable capacitive impedance element in the voltage-controlled oscillator (Example 2), which includes a capacitor between the gate and drain of the capacitive transistor of the variable capacitive impedance element. Figure 4B The illustration shows the capacitance of a variable capacitive impedance element in a voltage-controlled oscillator (Example 2) where a capacitor is included between the gate and drain of a capacitive transistor, and the capacitance is varied according to the frequency-controlled voltage VCTRL. For example... Figure 4B As shown, if the frequency control voltage VCTRL changes from 0V to 1V, the capacitance of the variable capacitive impedance element changes from approximately 50fF to 600fF or greater. Therefore, it can be concluded that the variable range of the capacitance of the variable capacitive impedance element is from approximately 50fF to 600fF or greater.

[0087] Compared to the variable capacitive impedance element in a voltage-controlled oscillator (Example 1) that does not incorporate a capacitor between the gate and drain of a capacitive transistor, the variable capacitive impedance element in a voltage-controlled oscillator (Example 2) that includes a capacitor between the gate and drain of a capacitive transistor has a wider range of variable capacitance.

[0088] Figure 5AIt is a graph describing the variable range of frequencies of a voltage-controlled oscillator (Example 1) in which there is no capacitor between the gate and drain of a capacitive transistor with variable capacitive impedance elements. Figure 5A This illustrates the oscillation frequency of a voltage-controlled oscillator (VCO) (Example 1) in which there is no capacitor between the gate and drain of a capacitive transistor with variable capacitive impedance, and the frequency is controlled by varying the voltage VCTRL. Figure 5A As shown, if the frequency control voltage VCTRL changes from 0V to 1V, the oscillation frequency of the voltage-controlled oscillator changes from approximately 7.1GHz to approximately 6.5GHz. Therefore, it can be seen that the variable frequency range of the voltage-controlled oscillator in Example 1 is from approximately 7.1GHz to approximately 6.5GHz.

[0089] Figure 5B It is a graph describing the variable range of frequencies of a voltage-controlled oscillator (Example 2) that includes a capacitor between the gate and drain of a capacitive transistor with variable capacitive impedance elements. Figure 5B The diagram illustrates the oscillation frequency of a voltage-controlled oscillator (VCO) (Example 2) in which a capacitor is included between the gate and drain of a capacitive transistor with variable capacitive impedance. This frequency is controlled by a voltage VCTRL that varies according to frequency. Figure 5B As shown, if the frequency control voltage VCTRL changes from 0V to 1V, the oscillation frequency of the voltage-controlled oscillator changes from approximately 6.7GHz to approximately 4.0GHz. Therefore, it can be seen that the variable frequency range of the voltage-controlled oscillator in Example 2 is from approximately 6.7GHz to approximately 4.0GHz.

[0090] Compared to a voltage-controlled oscillator (VCO) without a capacitor between the gate and drain of a capacitive transistor (Example 1), a VCO with a capacitor between the gate and drain of a capacitive transistor (Example 2) has a wider frequency range. Thus, when the capacitor between the gate and drain of the capacitive transistor is included in the variable capacitive impedance element of the VCO, the variable range of the VCO's oscillation frequency is expanded.

[0091] Therefore, the voltage-controlled oscillator 1 can expand the variable range of capacitance of the variable capacitive impedance element by providing a capacitor between the gate and drain of the capacitive transistor in the variable capacitive impedance element. Furthermore, compared to a voltage-controlled oscillator with a variable capacitive impedance element that does not have a capacitor between the gate and drain of the capacitive transistor, the voltage-controlled oscillator 1 with such a variable capacitive impedance element can expand the variable range of the output signal frequency to a wider extent.

[0092] In the following text, reference will be made to Figure 6 Description as Figure 2The voltage-controlled oscillator has different types of variable capacitive impedance elements Cv1a and Cv2a, namely Cv1a and Cv2a. Here, with... Figure 2 Reference numbers that are the same as reference numbers in the reference numerals can be assigned to reference numbers that are the same as reference numbers in the reference numerals ... Figure 2 The components shown are the same as those in the diagram. Figure 6 The variable capacitive impedance elements Cv1a and Cv2a are coupled with a bias circuit that includes two transistors and a single resistor. Figure 2 The variable capacitive impedance elements Cv1 and Cv2 correspond to this. The bias circuit provides bias current to the drains of capacitive transistors Tr11 and Tr21.

[0093] Figure 6 This is a circuit diagram showing an example of a voltage-controlled oscillator, including a detailed circuit diagram of a variable capacitive impedance element.

[0094] The voltage-controlled oscillator 2 includes a first transistor Tr1, a second transistor Tr2, a first variable capacitive impedance element Cv1a, a second variable capacitive impedance element Cv2a, and an inductive impedance element L1. In addition to the aforementioned components, the voltage-controlled oscillator 2 may also include a first buffer circuit BUF1, a second buffer circuit BUF2, and a load resistor RL. The first transistor Tr1 and the second transistor Tr2 are cross-coupled. The source of the first transistor Tr1 is connected to a first power supply. The first power supply provides a power supply voltage VDD. The source of the second transistor Tr2 is connected to the first power supply, the drain of the second transistor Tr2 is connected to the gate of the first transistor Tr1, and the gate of the second transistor Tr2 is connected to the drain of the first transistor Tr1. One end of the inductive impedance element L1 is connected to the drain of the first transistor Tr1, and the other end of the inductive impedance element L1 is connected to the drain of the second transistor Tr2.

[0095] The first terminal of the first variable capacitive impedance element Cv1a is connected to the drain of the first transistor Tr1, and the frequency control voltage VCTRL is applied to the second terminal of the first variable capacitive impedance element Cv1a. The first terminal of the second variable capacitive impedance element Cv2a is connected to the drain of the second transistor Tr2, and the frequency control voltage VCTRL is applied to the second terminal of the second variable capacitive impedance element Cv2a.

[0096] The first variable capacitive impedance element Cv1a may include a first capacitor C12, a second capacitor C11, a third transistor Tr11, a third resistor R11, and a first bias circuit. The first capacitor C12 is coupled between the gate and drain of the third transistor Tr11. The second variable capacitive impedance element Cv2a may include a third capacitor C21, a fourth capacitor C22, a fourth transistor Tr21, a fourth resistor R21, and a second bias circuit. The third capacitor C21 is coupled between the gate and drain of the fourth transistor Tr21. The first capacitor C12 and the third capacitor C21 can be formed using interlayer capacitance. For example, the first capacitor C12 and the third capacitor C21 can be formed using an interlayer capacitance that utilizes an interlayer insulating film formed between wiring layers and metal wires having the interlayer insulating film therebetween.

[0097] The first bias circuit provides bias current to the drain of the third transistor Tr11. The first bias circuit includes a resistor and two transistors. (Example:) Figure 6 As shown, the first bias circuit includes a fifth transistor Tr31, a sixth transistor Tr32, and a resistor R31. In the following text, for ease of description, the fifth transistor Tr31, the sixth transistor Tr32, and the resistor R31 may also be referred to as the first mirror transistor Tr31, the second mirror transistor Tr32, and the first mirror resistor R31, respectively.

[0098] A bias voltage Vd is applied to the source of the first mirror transistor Tr31. The gate of the first mirror transistor Tr31 is coupled to the drain of the first mirror transistor Tr31.

[0099] A bias voltage Vd is applied to the source of the second mirror transistor Tr32. The gate of the second mirror transistor Tr32 is coupled to the gate of the first mirror transistor Tr31. The drain of the second mirror transistor Tr32 is coupled to the drain of the third transistor Tr11.

[0100] The first mirror resistor R31 is connected between the drain of the first mirror transistor Tr31 and the second power supply. For example, one end of the first mirror resistor R31 is connected to the drain of the first mirror transistor Tr31. This end of the first mirror resistor R31 is also connected to the gate of the first mirror transistor Tr31 and the gate of the second mirror transistor Tr32. The other end of the first mirror resistor R31 is connected to the second power supply. The second power supply is ground and provides the ground voltage GND.

[0101] The second variable capacitive impedance element Cv2a has a configuration substantially the same as that of the first variable capacitive impedance element Cv1a. For example, the second variable capacitive impedance element Cv2a has a configuration with an added second bias circuit. Figure 2The second variable capacitive impedance element Cv2 corresponds to the second bias circuit, which includes the seventh transistor Tr41, the eighth transistor Tr42, and the resistor R41.

[0102] The second bias circuit provides bias current to the drain of the fourth transistor Tr21. The second bias circuit includes a resistor and two transistors. (Example:) Figure 6 As shown, the second bias circuit includes a seventh transistor Tr41, an eighth transistor Tr42, and a resistor R41. In the following text, for ease of description, the seventh transistor Tr41, the eighth transistor Tr42, and the resistor R41 may also be referred to as the third mirror transistor Tr41, the fourth mirror transistor Tr42, and the second mirror resistor R41, respectively.

[0103] A bias voltage Vd is applied to the source of the third mirror transistor Tr41. The gate of the third mirror transistor Tr41 is coupled to the drain of the third mirror transistor Tr41.

[0104] A bias voltage Vd is applied to the source of the fourth mirror transistor Tr42. The gate of the fourth mirror transistor Tr42 is coupled to the gate of the third mirror transistor Tr41. The drain of the fourth mirror transistor Tr42 is coupled to the drain of the fourth transistor Tr21.

[0105] The second mirror resistor R41 is connected between the drain of the third mirror transistor Tr41 and the second power supply. For example, one end of the second mirror resistor R41 is connected to the drain of the third mirror transistor Tr41. This end of the second mirror resistor R41 is also connected to the gate of the third mirror transistor Tr41 and the gate of the fourth mirror transistor Tr42. The other end of the second mirror resistor R41 is connected to the second power supply. The second power supply is ground and provides the ground voltage GND.

[0106] exist Figure 6 In the variable capacitive impedance elements Cv1a and Cv2a of the voltage-controlled oscillator, a circuit can be implemented by appropriately setting the resistances of the mirror resistors R31 and R32 such that the value of the current flowing in the capacitive transistors Tr11 and Tr21 hardly changes in response to a change in the value of the bias voltage Vd.

[0107] The aforementioned voltage-controlled oscillator can be included in various types of electronic devices. For example, electronic devices may include personal computers (PCs), laptop computers, tablet computers, smartphones, televisions (TVs), smart electronic devices, smart vehicles, kiosks, wearable devices, communication devices, consumer electronic devices, medical electronic devices, industrial electronic devices, etc.

[0108] Figure 7 Examples of user wireless communication devices (such as mobile phones or smartphones) are shown. Figure 8 An example of a wireless communication device (such as an access point) is shown. Signals transmitted by a user equipment can be received by the access point, and signals transmitted by the access point can be received by the user equipment.

[0109] Figure 7 This is a block diagram illustrating an example of a user's wireless communication device (such as a mobile phone or smartphone).

[0110] User terminal 700 includes multiple antennas 711, 712...71n (where n is an integer greater than 1) and a transceiver 720. The transceiver 720 operates as either a transmitter or a receiver. In this example, the transmitter and receiver are implemented by being integrated into the transceiver 720. However, in some examples, the transmitter and receiver can be implemented independently. Hereinafter, for ease of description, the transceiver 720 may be referred to as either a transmitter or a receiver depending on its operation. In this case, the transmitter and receiver can be implemented as a transceiver, or they can be implemented independently. Furthermore, user terminal 700 may include both a transmitter and a receiver (including transceiver implementations), or it may include only one of the transmitter and receiver.

[0111] An example of a user terminal 700 receiving signals will be described. In user terminal 700, multiple antennas 711, 712...71n receive downlink signals. The downlink signals may be radio frequency (RF) signals. For processing, receiver 720 can select a signal received from one of the antennas 711, 712...71n. In some examples, signals from two or more selected from antennas 711, 712...71n can be combined. Receiver 720 generates a recovered downlink data symbol stream by performing processing corresponding to the operations performed by the transmitter at the access point. Receiver 720 provides the recovered downlink data symbol stream to RX data processor 730. RX data processor 730 processes the recovered downlink data symbol stream (e.g., demodulate, deinterleave, or decode) to obtain decoded data for user terminal 700. For data storage, the decoded data can be sent to data sink 740. RX data processor 730 can receive control data from controller 750.

[0112] An example of signal transmission by user terminal 700 will be described. In user terminal 700, TX data processor 770 receives traffic data from data source 780. TX data processor 770 may receive control data from controller 750. TX data processor 770 processes the traffic data (e.g., encoding, interleaving, or modulation) to generate an uplink data symbol stream. TX data processor 770 provides the uplink data symbol stream to transmitter 720. Transmitter 720 performs processing on the uplink data symbol stream (e.g., digital-to-analog conversion, amplification, filtering, or frequency up-conversion) to generate an uplink signal. Transmitter 720 provides the uplink signal to one or two or more of a plurality of antennas 711, 712...71n via an RF switch (not shown). Controller 750 may control antenna selection. Antennas 711, 712...71n transmit RF signals. In some examples, control data for the RX data processor 730 and the TX data processor 770 can be stored in memory 760.

[0113] Receiver 720, transmitter 720, or transceiver 720 includes a voltage-controlled oscillator (VCO) 725. A voltage-controlled oscillator is an electronic oscillator whose oscillation frequency is controlled by an input control voltage. Therefore, the oscillation frequency of the voltage-controlled oscillator is determined by the input control voltage. The voltage-controlled oscillator 725 can be used to perform frequency modulation or phase modulation by applying a modulation signal to a control signal.

[0114] Figure 8 This is a block diagram showing an example of an access point.

[0115] Access point 800 includes multiple antennas 811, 812...81m (where m is an integer greater than 1) and transceiver 820. Transceiver 820 operates as either a transmitter or a receiver. In this example, the transmitter and receiver are implemented by being integrated into the transceiver. However, in some examples, the transmitter and receiver can be implemented independently. Hereinafter, for ease of description, transceiver 820 may be referred to as either a transmitter or a receiver depending on its operation. In this case, the transmitter and receiver can be implemented as a transceiver, or they can be implemented independently. Furthermore, access point 800 may include both a transmitter and a receiver (including transceiver implementations), or it may include only one of the transmitter and receiver.

[0116] An example of signal transmission from access point 800 will be described. Access point 800 can transmit signals to user terminal 700. In access point 800, TX data processor 830 receives traffic data from data source 840. TX data processor 830 can receive control data from controller 850. TX data processor 830 processes the traffic data (e.g., encoding, interleaving, or modulation) to generate a downlink data symbol stream. TX data processor 830 provides the downlink data symbol stream to transmitter 820. Transmitter 820 performs processing on the downlink data symbol stream (e.g., digital-to-analog conversion, amplification, filtering, or frequency up-conversion) to generate a downlink signal. Transmitter 820 provides the downlink signal to one or two or more of multiple antennas 811, 812...81m via an RF switch (not shown). Controller 850 can control antenna selection. Antennas 811, 812...81m transmit RF signals.

[0117] An example of signal reception at access point 800 will be described. Access point 800 can receive uplink signals from user terminal 700. The uplink signals can be RF signals. In access point 800, multiple antennas 811, 812...81m receive uplink signals. For processing, receiver 820 can select a signal received from one of antennas 811, 812...81m. In some examples, signals from two or more antennas selected from antennas 811, 812...81m can be combined. Receiver 820 generates a recovered uplink data symbol stream by performing processing corresponding to the operations performed by the transmitter of the user terminal. Receiver 820 provides the recovered uplink data symbol stream to RX data processor 870. RX data processor 870 processes the recovered uplink data symbol stream (e.g., demodulation, deinterleaving, or decoding) to obtain decoded data for access point 800. For data storage, the decoded data can be sent to data sink 880. RX data processor 870 can receive control data from controller 850. In some examples, control data for the TX data processor 830 and the RX data processor 870 can be stored in memory 860.

[0118] The receiver 820, transmitter 820, or transceiver 820 includes a voltage-controlled oscillator (VCO) 825. The oscillation frequency of the VCO is controlled by an input control voltage.

[0119] Several examples have been described above. However, it should be understood that various modifications can be made to these examples. For example, suitable results can be achieved if the described techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents.

[0120] Therefore, other embodiments are within the scope of the appended claims.

Claims

1. A voltage-controlled oscillator, comprising: First transistor; Second transistor; Inductive impedance element; First variable capacitive impedance element; as well as Second variable capacitive impedance element, In this configuration, the source of the first transistor is coupled to the first power supply. The drain of the first transistor is coupled to the first node. The gate of the first transistor is coupled to the second node. The source of the second transistor is connected to the first power supply. The drain of the second transistor is coupled to the second node. The gate of the second transistor is coupled to the first node. The first end of the inductive impedance element is connected to the first node. The second end of the inductive impedance element is connected to the second node. The first end of the first variable capacitive impedance element is connected to the first node. The second end of the first variable capacitive impedance element is connected to the third node. The first end of the second variable capacitive impedance element is connected to the second node, and The second end of the second variable capacitive impedance element is connected to the third node. The first variable capacitive impedance element includes: Third transistor; A first capacitor is connected between the gate and drain of the third transistor; and The third resistor is connected between the gate of the third transistor and the third node.

2. The voltage-controlled oscillator according to claim 1, wherein, A frequency control voltage is applied to the third node.

3. The voltage-controlled oscillator according to claim 1 or 2, wherein, The second variable capacitive impedance element includes: The fourth transistor; and The third capacitor is connected between the gate and drain of the fourth transistor.

4. The voltage-controlled oscillator according to claim 3, wherein, The first variable capacitive impedance element also includes: The second capacitor is coupled between the gate of the third transistor and the first node, and The second variable capacitive impedance element also includes: The fourth capacitor is connected between the gate of the fourth transistor and the second node.

5. The voltage-controlled oscillator according to claim 3, wherein, The second variable capacitive impedance element also includes: The fourth resistor is connected between the gate of the fourth transistor and the third node.

6. The voltage-controlled oscillator according to claim 3, wherein, The source of the third transistor and the source of the fourth transistor are connected to the second power supply.

7. The voltage-controlled oscillator according to claim 1 or 2, wherein, The common connection terminal of the inductive impedance element is connected to the second power supply.

8. The voltage-controlled oscillator according to claim 3, further comprising: The first bias circuit is configured to provide a first bias current to the drain of the third transistor; as well as The second bias circuit is configured to provide a second bias current to the drain of the fourth transistor.

9. The voltage-controlled oscillator according to claim 8, wherein, The first bias circuit includes: The fifth transistor; and The sixth transistor, In this process, a bias voltage is applied to the source of the fifth transistor. The gate of the fifth transistor is coupled to the drain of the fifth transistor. A bias voltage is applied to the source of the sixth transistor. The gate of the sixth transistor is coupled to the gate of the fifth transistor, and The drain of the sixth transistor is coupled to the drain of the third transistor, and The second bias circuit includes: The seventh transistor; and The eighth transistor, In this process, a bias voltage is applied to the source of the seventh transistor. The gate of the seventh transistor is coupled to the drain of the seventh transistor. A bias voltage is applied to the source of the eighth transistor. The gate of the eighth transistor is coupled to the gate of the seventh transistor, and The drain of the eighth transistor is coupled to the drain of the fourth transistor.

10. The voltage-controlled oscillator according to claim 9, wherein, The first bias circuit also includes: The first mirror resistor is connected between the drain of the fifth transistor and the second power supply, and The second bias circuit also includes: The second mirror resistor is connected between the drain of the seventh transistor and the second power supply.

11. The voltage-controlled oscillator according to claim 1 or 2, further comprising: A first resistor is connected between the drain of the first transistor and the first node; as well as The second resistor is connected between the drain of the second transistor and the second node.

12. The voltage-controlled oscillator according to claim 3, wherein, The third and fourth transistors are metal-oxide-semiconductor transistors.

13. The voltage-controlled oscillator according to claim 4, wherein, The second capacitor, the first capacitor, the fourth capacitor, and the third capacitor are formed using inter-wire capacitance.

14. A voltage-controlled oscillator, comprising: Two cross-coupled transistors; as well as Capacitive impedance elements are respectively connected between the two cross-coupled transistors and the frequency control voltage. Among them, capacitive impedance elements all include: First transistor; A capacitor is connected between the gate and drain of the first transistor; A resistor is connected between the gate of the first transistor and the frequency control voltage.

15. The voltage-controlled oscillator according to claim 14, wherein, Capacitive impedance elements also include: An additional capacitor is attached between the gate of each of the two cross-coupled transistors and the gate of the first transistor.

16. The voltage-controlled oscillator according to any one of claims 14 to 15, wherein, Capacitive impedance elements also include: The bias circuit is configured to provide bias current to a first transistor included in a corresponding capacitive impedance element.

17. The voltage-controlled oscillator according to claim 16, wherein, The bias circuit is also configured to provide bias current to the drain of the first transistor included in the corresponding capacitive impedance element.

18. A wireless communication device, comprising: At least one antenna; as well as At least one of a receiver and a transmitter, wherein the receiver is configured to receive radio frequency signals through the at least one antenna, and the transmitter is configured to transmit radio frequency signals through the at least one antenna; Wherein, at least one of the receiver and the transmitter includes: The voltage-controlled oscillator according to any one of claims 1 to 17.

19. An electronic device comprising a voltage-controlled oscillator according to any one of claims 1 to 17.

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